Semiconductor device

Abstract

To suppress controllability in switching operation from decreasing.SOLUTION: A semiconductor comprises semiconductor chips 20a, 20b which comprise control electrode on top surfaces, and top-surface wiring layers 33c, 33a which are striped in plan view and each have one end part opposed and electrically connected to the control electrode. At this time, the top-surface wiring layers 33c, 33a extend with their other-end parts in the opposite directions and the top-surface wiring layers 33c, 33a are equal in extension-directional length to each other. Consequently, the top-surface wiring layers 33a, 33c become substantially equal in inductance and electric resistance, and delay of control in switching operation, etc., are prevented to prevent controllability from decreasing.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device includes a power semiconductor chip and functions as a power conversion device. The power semiconductor chip includes a switching element and a diode element. The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Further, the semiconductor device includes a printed circuit board or a connection unit that is connected by pin-shaped post electrodes for each control electrode of a plurality of semiconductor chips. Such a printed circuit board or connection unit includes an external terminal to which a control signal is input from the outside and a connection terminal connected to the control electrode of the semiconductor chip. Therefore, in the semiconductor device, control signals are respectively input to the control electrodes of the semiconductor chips via the printed circuit board or the connection unit (see, for example, Patent Documents 1 and 2). Further, a plurality of lead frames arranged in one direction and the control electrodes of the semiconductor chips are connected by a control wiring layer, and a control signal is input (see, for example, Patent Document 3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a control signal is input to the control electrodes of a plurality of semiconductor chips via a printed circuit board, depending on the wiring pattern (wiring layer) included in the printed circuit board, the wiring lengths from the external terminals to the control electrodes of the respective semiconductor chips may be different. In this case, when a switching operation is performed, there is a risk that a difference in control timing will occur due to the different wiring lengths, resulting in a decrease in controllability during the switching operation. As a result, the reliability of the operation of the semiconductor device may decrease.

[0005] The present invention has been made in view of such points, and an object thereof is to provide a semiconductor device in which a decrease in controllability during a switching operation is suppressed.

Means for Solving the Problems

[0006] According to one aspect of the present invention, a first semiconductor chip having a first control electrode and a first main electrode provided on a front surface, a second semiconductor chip having a second control electrode and a second main electrode provided on a front surface, a first control wiring layer that is stripe-shaped in plan view and has one end facing and electrically connected to the first control electrode, and a second control wiring layer that is stripe-shaped in plan view and has one end facing and mainly electrically connected to the second control electrode, an insulating layer in which the first control wiring layer and the second control wiring layer are formed on a first main surface, and a first detection wiring layer formed on a second main surface opposite to the first main surface of the insulating layer, the first detection wiring layer being stripe-shaped in plan view and having one end facing and electrically connected to the first main electrode, and a second detection wiring layer formed on the second main surface, the second detection wiring layer being stripe-shaped in plan view and having one end facing and electrically connected to the second main electrode, a printed circuit board facing the first semiconductor chip and the second semiconductor chip, a first control terminal formed at the other end of the first control wiring layer, a second control terminal formed at the other end of the second control wiring layer, a first sense terminal formed at the other end of the first detection wiring layer, and a second sense terminal formed at the other end of the second detection wiring layer are provided, and the first control wiring layer and the second control wiring layer extend with their other ends facing in opposite directions, and the lengths of the first control wiring layer and the second control wiring layer in the extending direction are equal to each other < , The other ends of the first detection wiring layer and the second detection wiring layer extend in opposite directions, the lengths of the first detection wiring layer and the second detection wiring layer in the extending direction are equal to each other, the lengths of the first detection wiring layer and the second detection wiring layer in the extending direction are the same as the lengths of the first control wiring layer and the second control wiring layer in the extending direction, the first detection wiring layer and the second detection wiring layer are formed on the second main surface of the insulating layer facing the first control wiring layer and the second control wiring layer, and the length between the portion of the first control wiring layer electrically connected to the first control electrode and the portion where the first control terminal is formed is equal to the length between the portion of the first detection wiring layer electrically connected to the first main electrode and the portion where the first sense terminal is formed, and the length between the portion of the second control wiring layer electrically connected to the second control electrode and the portion where the second control terminal is formed is equal to the length between the portion of the second detection wiring layer electrically connected to the second main electrode and the portion where the second sense terminal is formed a semiconductor device is provided.

Effects of the Invention

[0007] According to the disclosed technology, it is possible to suppress a decrease in controllability during a switching operation and prevent a decrease in the reliability of a semiconductor device.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Modes for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the "front surface" and the "upper surface" represent the X-Y plane facing upward (+Z direction) in the semiconductor device of the figure. Similarly, "up" represents the upward (+Z direction) in the semiconductor device of the figure. The "back surface" and the "lower surface" represent the X-Y plane facing downward (-Z direction) in the semiconductor device of the figure. Similarly, "down" represents the downward (-Z direction) in the semiconductor device of the figure. The same directionality is meant in other drawings as necessary. The "front surface", "upper surface", "up", "back surface", "lower surface", "down", and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the direction of gravity. Further, in the following description, "main component" means the case where it contains 80 vol% or more.

[0010] [First Embodiment] The semiconductor device of the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the semiconductor device of the first embodiment, and FIG. 2 is a side cross-sectional view of the semiconductor device of the first embodiment. Note that FIG. 2 is a cross-sectional view taken along the dashed-dotted line X-X in FIG. 1. The dashed-dotted line X-X is also a center line passing through the center of the short side of the semiconductor device 1 and parallel to the long side of the semiconductor device 1.

[0011] The semiconductor device 1 includes a rectangular parallelepiped sealing main body portion 2, and external connection terminals 3, 4, 5, control terminals 6a, 6b, and sense terminals 7a, 7b extend vertically upward (+Z direction) from the front surface 2e of the sealing main body portion 2 with respect to the front surface 2e.

[0012] In a plan view, the sealing body portion 2 has its four sides of the substantially rectangular front surface 2e surrounded by side wall portions 2a to 2d. Further, the side wall portions 2a and 2c correspond to the longitudinal direction (long side) of the sealing body portion 2, and the side wall portions 2b and 2d correspond to the short side direction (short side) of the sealing body portion 2, respectively. Note that the connection portions at the four corners of the side wall portions 2a to 2d do not necessarily have to be right angles, and may form an R shape or may be chamfered. The joints between the front surface 2e and the side wall portions 2a to 2d do not necessarily have to be right angles, and may form an R shape or may be chamfered.

[0013] The external connection terminals 3, 4, 5, the control terminals 6a, 6b, and the sense terminals 7a, 7b are in a cylindrical or prismatic shape. That is, they are in a so-called pin shape. The external connection terminals 3, 4, 5, the control terminals 6a, 6b, and the sense terminals 7a, 7b are made of a material with excellent conductivity. Such a material is constituted by, for example, silver, copper, nickel, or an alloy containing at least one of these.

[0014] The external connection terminals 3, 4, 5 extend one by one symmetrically with respect to the dash-dotted line X-X and vertically upward (+Z direction) with respect to the front surface 2e, sandwiching the dash-dotted line X-X. Note that the case where the external connection terminals 3, 4, 5 extend one by one sandwiching the dash-dotted line X-X is described. Not limited to this case, the external connection terminals 3, 4, 5 may extend two or more at a time sandwiching the dash-dotted line X-X. Further, the upper end portions of the external connection terminals 3, 4, 5 extend from the front surfaces of the terminal blocks 2f to 2h integrally formed on the front surface 2e. The lower end portions of the external connection terminals 3, 4, 5 extend in the -Z direction inside the sealing body portion 2.

[0015] The control terminals 6a, 6b are on the dash-dotted line X-X, on the side of the side wall portions 2b, 2d, and extend vertically upward with respect to the front surface 2e, respectively. Further, the upper end portions of the control terminals 6a, 6b extend from the front surfaces of the terminal blocks 2i, 2j integrally formed on the front surface 2e. The lower end portions of the control terminals 6a, 6b extend vertically downward (-Z direction) inside the sealing body portion 2.

[0016] The sense terminals 7a and 7b are on the dash-dotted line X-X, further on the side of the side wall parts 2b and 2d than the control terminals 6a and 6b, and extend vertically upward (+Z direction) with respect to the front surface 2e. Also, the upper end parts of the sense terminals 7a and 7b extend from the front surface of the terminal blocks 2i and 2j integrally formed on the front surface 2e. The lower end parts of the sense terminals 7a and 7b extend vertically downward (-Z direction) inside the sealing main body part 2.

[0017] Also, the external connection terminals 3, 4, and 5 are the main terminals through which the main current is input and output. The external connection terminal 3 is an input terminal (P terminal) connected to the positive electrode of an external power source. The external connection terminal 3 is electrically connected to the main electrode (collector electrode) of a semiconductor chip 20b described later.

[0018] The external connection terminal 4 is an input terminal (N terminal) connected to the negative electrode of an external power source. The external connection terminal 4 is electrically connected to the main electrode (emitter electrode) of a semiconductor chip 20a described later. The external connection terminal 5 is an output terminal (O terminal) through which the output current flows. The external connection terminal 5 is electrically connected to the main electrode (emitter electrode) of the semiconductor chip 20b and the main electrode (collector electrode) of the semiconductor chip 20a.

[0019] The control terminals 6a and 6b (G1 and G2 terminals) are electrically connected to the control electrodes of the semiconductor chips 20b and 20a via a printed circuit board 30 described later. The sense terminals 7a and 7b (E1s and E2s terminals) are electrically connected to the emitter electrodes of the semiconductor chips 20b and 20a via the printed circuit board 30.

[0020] The sealing main body part 2 in which the external connection terminals 3, 4, and 5, the control terminals 6a and 6b, and the sense terminals 7a and 7b are integrally formed is configured by encapsulating semiconductor chips 20a, 20b, etc. described later with resin in a predetermined mold. Such resin is mainly composed of a thermoplastic resin. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyimide resin, or acrylonitrile-butadiene-styrene resin.

[0021] In such a semiconductor device 1, an insulating circuit board 10a, 10b, semiconductor chips 20a, 20b, and a printed circuit board 30 are encapsulated by an encapsulation main body 2. The insulating circuit boards 10a, 10b include insulating plates 11a, 11b, metal plates 12a, 12b provided on the back surfaces of the insulating plates 11a, 11b, and circuit patterns 13a1, 13a2, 13b provided on the front surfaces of the insulating plates 11a, 11b. The insulating plates 11a, 11b and the metal plates 12a, 12b are rectangular in plan view. Further, the corners of the insulating plates 11a, 11b and the metal plates 12a, 12b may be chamfered into an R shape or a C shape. The sizes of the metal plates 12a, 12b are smaller than the sizes of the insulating plates 11a, 11b in plan view and are formed inside the insulating plates 11a, 11b. The insulating plates 11a, 11b are made of a material having insulation properties and excellent thermal conductivity. Such insulating plates 11a, 11b are made of ceramics or an insulating resin. The ceramics are, for example, aluminum oxide, aluminum nitride, or silicon nitride. The insulating resin is, for example, a paper phenolic substrate, a paper epoxy substrate, a glass composite substrate, or a glass epoxy substrate. The thickness of the insulating plates 11a, 11b is 0.2 mm or more and 2.5 mm or less.

[0022] The metal plates 12a, 12b are smaller in area than the insulating plates 11a, 11b and larger in area than the area of the region where the circuit patterns 13a1, 13a2, 13b are formed, and have a rectangular shape similar to that of the insulating plates 11a, 11b. Further, the corners may be chamfered into an R shape or a C shape. The metal plates 12a, 12b are smaller than the sizes of the insulating plates 11a, 11b and are formed on the entire surface of the insulating plates 11a, 11b except for the edges. The metal plates 12a, 12b are mainly composed of a metal having excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. Also, the thickness of the metal plates 12a, 12b is 0.1 mm or more and 2.5 mm or less. In order to improve the corrosion resistance of the metal plates 12a, 12b, plating treatment may be performed. At this time, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0023] The circuit patterns 13a1, 13a2, and 13b are made of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy having at least one of these as a main component. Also, the thickness of the circuit patterns 13a1, 13a2, and 13b is 0.1 mm or more and 2.0 mm or less. A plating process may be performed on the surface of the circuit patterns 13a1, 13a2, and 13b to improve corrosion resistance. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy. Note that the circuit patterns 13a1, 13a2, and 13b shown in FIG. 2 are an example. The number, shape, size, etc. of the circuit patterns 13a1, 13a2, and 13b may be appropriately selected as needed. The insulated circuit boards 10a and 10b having such a configuration include, for example, a DCB (Direct Copper Bonding) board, an AMB (Active Metal Brazed) board, and a resin insulated board.

[0024] In the semiconductor device 1, the back surfaces of the metal plates 12a and 12b of the insulated circuit boards 10a and 10b are exposed. A cooling unit may be attached to the back surface of such a semiconductor device 1 via a joining member.

[0025] The joining member used herein is solder, brazing material, or a metal sintered body. For the solder, lead-free solder is used. The lead-free solder mainly consists of an alloy containing at least two of, for example, tin, silver, copper, zinc, antimony, indium, and bismuth. Further, the solder may contain additives. The additives are, for example, nickel, germanium, cobalt, or silicon. By including the additives, the solder can improve wettability, gloss, and bonding strength, thereby improving reliability. The brazing material mainly consists of, for example, at least one of aluminum alloy, titanium alloy, magnesium alloy, zirconium alloy, and silicon alloy. The insulating circuit boards 10a and 10b can be joined by brazing using such a joining member. The metal sintered body mainly consists of, for example, silver and silver alloy. Alternatively, the joining member may be a thermal interface material. The thermal interface material is, for example, an adhesive material including an elastomer sheet, RTV (Room Temperature Vulcanization) rubber, gel, and phase change material. By attaching to the cooling unit via such a brazing material or thermal interface material, the heat dissipation performance of the semiconductor device 1 can be improved.

[0026] The cooling unit may apply, for example, a heat sink composed of a plurality of fins and a cooling device that cools with a refrigerant. The heat sink mainly consists of a material with excellent thermal conductivity. Such materials include aluminum, iron, silver, copper, or an alloy containing at least one of these. And, in order to improve corrosion resistance, a plating treatment may be performed on the surface of the heat sink. In this case, the plating materials used are, for example, nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0027] The semiconductor chips 20a and 20b include power device elements made of silicon or silicon carbide. Also, the thickness of the semiconductor chips 20a and 20b is, for example, 40 μm or more and 250 μm or less. The power device element combines the functions of a switching element and a diode element. Such a power device element may be an RC (Reverse-Conducting)-IGBT, an IGBT, or a power MOSFET. However, the IGBT and the power MOSFET include parasitic diodes. When the semiconductor chips 20a and 20b are RC-IGBTs or IGBTs, they are provided with a collector electrode as a main electrode on the back surface, and a gate electrode as a control electrode and an emitter electrode as a main electrode on the front surface, respectively. When the semiconductor chips 20a and 20b are power MOSFETs, they are provided with a drain electrode as a main electrode on the back surface, and a gate electrode as a control electrode and a source electrode as a main electrode on the front surface, respectively. Details of the semiconductor chips 20a and 20b will be described later.

[0028] The back surfaces of such semiconductor chips 20a and 20b are mechanically and electrically joined to the circuit patterns 13a1 and 13b by a joining member. The joining member used here is solder or a metal sintered body. For the solder, lead-free solder is used. The lead-free solder is mainly composed of an alloy containing at least two of, for example, tin, silver, copper, zinc, antimony, indium, and bismuth. Further, the solder may contain an additive. The additive is, for example, nickel, germanium, cobalt, or silicon. By including the additive, the solder can improve wettability, gloss, and bonding strength, and thus improve reliability. The metal used for the metal sintered body is, for example, silver and silver alloys.

[0029] The printed circuit board 30 includes an insulating layer 31, a bottom surface wiring layer 32 formed on the back surface of the insulating layer 31, and a top surface wiring layer 33 formed on the front surface of the insulating layer 31. The insulating layer 31 includes a base material and a resin impregnated in the base material. The base material is, for example, paper or glass cloth, or those containing these. The resin is, for example, a phenolic resin, an epoxy resin, or a polyimide resin. Specific examples include paper phenolic substrates, paper epoxy substrates, glass epoxy substrates, composite base material epoxy substrates, and glass polyimide substrates.

[0030] The bottom surface wiring layer 32 and the top surface wiring layer 33 are composed of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy mainly composed of at least one of these. Such a printed circuit board 30 is disposed opposite the front surfaces of the insulating circuit boards 10a and 10b at a predetermined interval. Note that the bottom surface wiring layer 32 and the top surface wiring layer 33 each include a plurality. When not distinguishing them, they are referred to as the bottom surface wiring layer 32 and the top surface wiring layer 33. Details of the bottom surface wiring layer 32 and the top surface wiring layer 33 will be described later.

[0031] Also, the semiconductor device 1 further includes main current post electrodes 8a to 8d, control post electrodes 9a and 9b, and detection post electrodes 9c and 9d (see FIG. 3). The main current post electrodes 8a to 8d, the control post electrodes 9a and 9b, and the detection post electrodes 9c and 9d are, for example, in the shape of cylindrical or prismatic posts. The main current post electrodes 8a to 8d, the control post electrodes 9a and 9b, and the detection post electrodes 9c and 9d are composed of a material with excellent conductivity. Such a material is, for example, composed of silver, copper, nickel, or an alloy containing at least one of these.

[0032] The main current post electrodes 8a to 8d mechanically and electrically connect between the printed circuit board 30, the main electrodes of the semiconductor chips 20a and 20b, and the insulating circuit boards 10a and 10b. The control post electrodes 9a and 9b mechanically and electrically connect between the printed circuit board 30 and the control electrodes of the semiconductor chips 20a and 20b. The detection post electrodes 9c and 9d mechanically and electrically connect between the printed circuit board 30 and the main electrodes of the semiconductor chips 20a and 20b.

[0033] Next, the details of the semiconductor chips 20a and 20b, the insulating circuit boards 10a and 10b, and the printed circuit board 30 will be described. First, the semiconductor chips 20a and 20b and the insulating circuit boards 10a and 10b will be described with reference to FIG. 3. FIG. 3 is a plan view of the inside of the semiconductor device according to the first embodiment. Note that FIG. 3 is a plan view of the insulating circuit boards 10a and 10b to which the semiconductor chips 20a and 20b are joined in the semiconductor device 1. The positions of the sealing main body portion 2, the main current post electrodes 8a to 8d, the control post electrodes 9a and 9b, and the detection post electrodes 9c and 9d of the semiconductor device 1 are indicated by broken lines.

[0034] As shown in FIG. 3, the semiconductor chips 20a and 20b are provided with control electrodes 21a and 21b at the central portions of the front side edges (the first and second side edges). The regions of the front surfaces of the semiconductor chips 20a and 20b excluding the control electrodes 21a and 21b are provided with main electrodes 22a and 22b.

[0035] In a plan view, the semiconductor chips 20a and 20b are arranged such that the sides on which the control electrodes 21a and 21b are formed are parallel to the circuit patterns 13a1 and 13b. In the case of FIG. 3, in a plan view, the semiconductor chips 20a and 20b are arranged such that the sides on which the control electrodes 21a and 21b are formed are in the same plane with respect to the circuit patterns 13a1 and 13b. In other words, the semiconductor chips 20a and 20b are arranged such that the control electrodes 21a and 21b face the side wall portion 2a of the sealing main body portion 2. That is, the control electrodes 21a and 21b face the same direction.

[0036] Also, the semiconductor chip 20a is disposed substantially at the center of the circuit pattern 13a1. The semiconductor chip 20b is disposed at the center in the X direction of the circuit pattern 13b and on the sidewall portion 2b side in the Y direction.

[0037] Control post electrodes 9b and 9a are electrically and mechanically connected to the control electrodes 21a and 21b of the semiconductor chips 20a and 20b, respectively, and main current post electrodes 8d and 8a are electrically and mechanically connected to the main electrodes 22a and 22b, respectively. Further, detection post electrodes 9d and 9c are electrically and mechanically connected to the regions of the main electrodes 22a and 22b adjacent to the control electrodes 21a and 21b of the semiconductor chips 20a and 20b, respectively. Note that the detection post electrode 9d is provided adjacent to the control electrode 21a on the sidewall portion 2d side, and the detection post electrode 9c is provided adjacent to the control electrode 21b on the sidewall portion 2d side.

[0038] The insulating circuit board 10a has circuit patterns 13a1 and 13a2 formed on the front surface of the insulating board 11a. Both of the circuit patterns 13a1 and 13a2 are rectangular in plan view. The circuit patterns 13a1 and 13a2 are formed across the width of the insulating board 11a in the X direction. The circuit pattern 13a1 occupies about two-thirds of the width of the insulating board 11a in the Y direction on the front surface and is formed on the sidewall portion 2d side with respect to the front surface of the insulating board 11a. As described above, the semiconductor chip 20a is disposed at the center of the circuit pattern 13a1. A plurality of main current post electrodes 8c are electrically and mechanically connected along the X direction on the sidewall portion 2b side of the semiconductor chip 20a in the circuit pattern 13a1 and slightly on the sidewall portion 2c side. Further, external connection terminals 5 are electrically and mechanically connected to the corner portions on the sidewall portion 2d side of the circuit pattern 13a1, respectively.

[0039] The circuit pattern 13a2 occupies about one-third of the width of the front surface of the insulating board 11a in the Y direction and is formed on the side of the side wall portion 2b with respect to the front surface of the insulating board 11a. On the side of the side wall portion 2d of the circuit pattern 13a2, a plurality of main current post electrodes 8b are electrically and mechanically connected along the X direction facing the main current post electrode 8c. Also, the external connection terminals 4 are electrically and mechanically connected to the corner portions on the side of the side wall portion 2b of the circuit pattern 13a2, respectively.

[0040] The circuit pattern 13b is formed on the entire front surface of the insulating board 11b. As described above, the semiconductor chip 20b is disposed at the center of the side wall portion 2b side of the circuit pattern 13b. The external connection terminals 3 are electrically and mechanically connected between the side wall portions 2a and 2c of the circuit pattern 13b and the side edges on the side of the side wall portion 2d of the circuit pattern 13b, respectively.

[0041] Next, the printed circuit board 30 will be described with reference to FIGS. 4 and 5. FIG. 4 is a plan view of the front surface of the printed circuit board included in the semiconductor device of the first embodiment, and FIG. 5 is a plan view of the back surface of the printed circuit board included in the semiconductor device of the first embodiment. FIG. 4 shows the case when the upper wiring layer 33 is viewed from the front surface of the printed circuit board 30, and FIG. 5 shows the case when the lower wiring layer 32 is viewed from the front surface of the printed circuit board 30. Also, FIGS. 4 and 5 show the components included in the sealing main body portion 2, the semiconductor chips 20a and 20b, and the insulating circuit boards 10a and 10b by broken lines.

[0042] As shown in FIG. 4, the printed circuit board 30 includes an insulating layer 31 and upper surface wiring layers 33a, 33b, 33c formed on the front surface of the insulating layer 31. The insulating layer 31 has a rectangular shape in plan view. The length (long side) of the insulating layer 31 in the Y direction is the length at which the formation of the upper surface wiring layer 33 and the lower surface wiring layer 32 is allowed, and is shorter than the long side of the sealing main body portion 2. Further, the width (short side) of the insulating layer 31 in the X direction may be shorter than the interval in the X direction of the external connection terminals 3, 4, 5 formed on the insulating circuit boards 10a, 10b. When the width of the insulating layer 31 in the X direction is equal to or longer than the width of the insulating circuit boards 10a, 10b in the same direction, an opening (through hole) through which the external connection terminals 3, 4, 5 are inserted may be formed in the insulating layer 31 (printed circuit board 30). However, the external connection terminals 3, 4, 5 passing through the through holes need to be electrically insulated from the upper surface wiring layer 33 and the lower surface wiring layer 32.

[0043] The upper surface wiring layer 33a (first control wiring layer) has a stripe shape (strip shape) with a length of length L2 in plan view. The width (short side) of the upper surface wiring layer 33a in the X direction only needs to be such that through holes through which at least the detection post electrode 9c and the sense terminal 7a penetrate can be formed. One end portion (left end portion in the figure) of the upper surface wiring layer 33a is electrically and mechanically connected to the control post electrode 9a. Therefore, one end portion of the upper surface wiring layer 33a faces the control electrode 21b of the semiconductor chip 20b and is electrically connected via the control post electrode 9a. Further, with respect to one end portion of the upper surface wiring layer 33a, the detection post electrode 9c penetrates through the side wall portion 2b side of the control post electrode 9a without being electrically connected.

[0044] The other end portion (right end portion in the figure) of the upper surface wiring layer 33a extends along the side wall portions 2a, 2c to the side wall portion 2b. The other end portion of the upper surface wiring layer 33a is electrically and mechanically connected to the control terminal 6a. Further, with respect to the other end portion of the upper surface wiring layer 33a, the sense terminal 7a penetrates through the side wall portion 2b side of the control terminal 6a without being electrically connected. At this time, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same length.

[0045] The upper wiring layer 33b forms a stripe shape in plan view. The width (short side) of the upper wiring layer 33b in the X direction may be at least about the length obtained by combining the diameters of at least three main current post electrodes 8c. One end portion (the left end portion in the figure) of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8c. In addition, one end portion of the upper wiring layer 33b may extend to the front of the main current post electrode 8d. In FIG. 4, one end portion of the upper wiring layer 33b extends to the front of the semiconductor chip 20a in the Y direction in plan view.

[0046] The other end portion (the right end portion in the figure) of the upper wiring layer 33b extends along the side wall portions 2a and 2c to the side wall portion 2b. In addition, the other end portion of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8a. Therefore, the upper wiring layer 33b faces the main electrode 22b of the semiconductor chip 20b and is electrically connected via the main current post electrode 8a. The other end portion of the upper wiring layer 33b extends to such an extent that it does not exceed the semiconductor chip 20b. In addition, the main current post electrode 8b penetrates through the side wall portion 2b side of the main current post electrode 8c of the upper wiring layer 33b without being electrically connected.

[0047] The upper wiring layer 33c (second control wiring layer) forms a stripe shape with a length of length L1 in plan view. Also, the length L1 and the length L2 are the same length. The width of the upper wiring layer 33c in the X direction may be at least such that a through hole through which at least the detection post electrode 9d and the sense terminal 7b penetrate can be formed. One end portion (the right end portion in the figure) of the upper wiring layer 33c is electrically and mechanically connected to the control post electrode 9b. Therefore, one end portion of the upper wiring layer 33c faces the control electrode 21a of the semiconductor chip 20a and is electrically connected via the control post electrode 9b. In addition, the detection post electrode 9d penetrates through the side wall portion 2d side of the control post electrode 9b without being electrically connected to one end portion of the upper wiring layer 33c.

[0048] The other end (left end in the figure) of the upper wiring layer 33c extends along the side wall portions 2a and 2c to the side wall portion 2d. Further, the other end of the upper wiring layer 33c is electrically and mechanically connected to the control terminal 6b. The sense terminal 7b penetrates through the side wall portion 2d side of the control terminal 6b without being electrically connected to the other end of the upper wiring layer 33c. At this time, the length Lc1 from the control post electrode 9b to the control terminal 6b is the same as the length Ls1 from the detection post electrode 9d to the sense terminal 7b.

[0049] Furthermore, as shown in FIG. 5, the printed circuit board 30 includes lower wiring layers 32a, 32b, and 32c formed on the back surface of the insulating layer 31. The lower wiring layer 32a has a stripe shape with a length L4 in a plan view. The length L4 is substantially the same as the length L2 of the upper wiring layer 33a. The width of the lower wiring layer 32a in the X direction only needs to be such that through holes through which at least the control post electrode 9a and the control terminal 6a penetrate can be formed. That is, the lower wiring layer 32a has the same shape and size as the upper wiring layer 33a. Also, the lower wiring layer 32a is formed on the back surface at the same position as the upper wiring layer 33a with the insulating layer 31 interposed therebetween.

[0050] One end (left end in the figure) of the lower wiring layer 32a is electrically and mechanically connected to the detection post electrode 9c. Therefore, one end of the lower wiring layer 32a faces the region of the main electrode 22b adjacent to the control electrode 21b of the semiconductor chip 20b and is electrically connected via the detection post electrode 9c. Also, the control post electrode 9a penetrates through the side wall portion 2d side of the detection post electrode 9c without being electrically connected to one end of the lower wiring layer 32a.

[0051] The other end portion (right end portion in the figure) of the lower wiring layer 32a extends along the side wall portions 2a and 2c to the side wall portion 2b. Further, the other end portion of the lower wiring layer 32a is electrically and mechanically connected to the sense terminal 7a. Further, the control terminal 6a penetrates through the other end portion of the lower wiring layer 32a without being electrically connected to the side wall portion 2d side of the sense terminal 7a. At this time, as described for the upper wiring layer 33a, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same length.

[0052] The lower wiring layer 32b forms a stripe shape in plan view. Note that the width of the lower wiring layer 32b in the X direction may be at least about the length obtained by combining the diameters of at least three main current post electrodes 8c. One end portion (left end portion in the figure) of the lower wiring layer 32b is electrically and mechanically connected to the main current post electrode 8d. Therefore, one end portion of the lower wiring layer 32b faces the main electrode 22a of the semiconductor chip 20a and is electrically connected via the main current post electrode 8d.

[0053] The other end portion (right end portion in the figure) of the lower wiring layer 32b extends along the side wall portions 2a and 2c to the side wall portion 2b up to the main current post electrode 8b. The other end portion of the lower wiring layer 32b is electrically and mechanically connected to the main current post electrode 8b. Further, the main current post electrode 8c penetrates through the lower wiring layer 32b between one end portion and the other end portion without being electrically connected. Further, the lower wiring layer 32b is formed on the back surface of the upper wiring layer 33b so as to be in a line with the upper wiring layer 33b with the insulating layer 31 interposed therebetween. Further, a part of the lower wiring layer 32b overlaps with the upper wiring layer 33b.

[0054] The lower wiring layer 32c forms a stripe shape with a length of L3 in a plan view. Note that the length L3 is substantially the same as the length L1 of the upper wiring layer 33c. The width of the lower wiring layer 32c in the X direction only needs to be such that through holes through which at least the control post electrode 9b and the control terminal 6b penetrate can be formed. That is, the lower wiring layer 32c has the same shape and size as the upper wiring layer 33c. Also, the lower wiring layer 32c is formed on the back surface at the same position as the upper wiring layer 33c with the insulating layer 31 interposed therebetween.

[0055] One end portion (the right end portion in the figure) of the lower wiring layer 32c is electrically and mechanically connected to the detection post electrode 9d. Therefore, one end portion of the lower wiring layer 32c faces the region of the main electrode 22a adjacent to the control electrode 21a and is electrically connected via the detection post electrode 9d. With respect to one end portion of the lower wiring layer 32c, the control post electrode 9b penetrates through to the side wall portion 2b side of the detection post electrode 9d without being electrically connected.

[0056] The other end portion (the left end portion in the figure) of the lower wiring layer 32c extends along the side wall portions 2a, 2c to the side wall portion 2d. Also, the other end portion of the lower wiring layer 32c is electrically and mechanically connected to the sense terminal 7b. With respect to the other end portion of the lower wiring layer 32c, the control terminal 6b penetrates through to the side wall portion 2b side of the sense terminal 7b without being electrically connected. At this time, as described for the upper wiring layer 33c, the length Lc1 from the control post electrode 9b to the control terminal 6b and the length Ls1 from the detection post electrode 9d to the sense terminal 7b are the same length.

[0057] Therefore, the control electrodes 21a, 21b of the semiconductor chips 20a, 20b are electrically connected to the control terminals 6b, 6a via the control post electrodes 9b, 9a and the upper wiring layers 33c, 33a.

[0058] The main electrode 22b of the semiconductor chip 20b is electrically connected to the external connection terminal 5 via the main current post electrode 8a, the upper wiring layer 33b, the main current post electrode 8c, and the circuit pattern 13a1.

[0059] Also, the main electrode 22a of the semiconductor chip 20a is electrically connected to the external connection terminal 4 via the main current post electrode 8d, the lower surface wiring layer 32b, the main current post electrode 8b, and the circuit pattern 13a2.

[0060] Also, the main electrode (rear surface) of the semiconductor chip 20a is electrically connected to the main electrode 22b of the semiconductor chip 20b via the circuit pattern 13a1, the main current post electrode 8c, the upper surface wiring layer 33b, and the main current post electrode 8a.

[0061] The main electrodes 22a and 22b of the semiconductor chips 20a and 20b are electrically connected to the sense terminals 7b and 7a via the detection post electrodes 9c and 9d and the lower surface wiring layers 32c and 32a.

[0062] Next, the operation of such a semiconductor device 1 will be described. Hereinafter, the semiconductor chips 20a and 20b are RC-IGBTs. The positive electrode of an external power supply is connected to the external connection terminal 3 of the semiconductor device 1, and the negative electrode of the external power supply is connected to the external connection terminal 4. Control signals are input to the control terminals 6a and 6b at a predetermined timing.

[0063] First, an input current is input to the main electrode (collector electrode) on the rear surface of the semiconductor chip 20b via the circuit pattern 13b from the external connection terminal 3. At this time, when the control signal is on for the control terminal 6a and off for the control terminal 6b, the control signal is input from the control terminal 6a to the control electrode 21b of the semiconductor chip 20b via the upper surface wiring layer 33a and the control post electrode 9a. Then, the main electrode 22b (emitter electrode) on the front surface of the semiconductor chip 20b outputs an output current. The output current is input from the main current post electrode 8a to the main current post electrode 8c via the upper surface wiring layer 33b. The output current is output from the external connection terminal 5 via the circuit pattern 13a1 from the main current post electrode 8c. Also, the output current output from the main electrode 22b (emitter electrode) of the semiconductor chip 20b is output from the sense terminal 7a via the lower surface wiring layer 32a from the detection post electrode 9c.

[0064] Also, after a control signal for the control terminal 6a turns off and a control signal for the control signal 6b turns on and a certain period of time has passed, current is input from the external connection terminal 5 to the main electrode (collector electrode) on the back surface of the semiconductor chip 20a via the circuit pattern 13a1. Then, the main electrode 22a (emitter electrode) on the front surface of the semiconductor chip 20a outputs an output current. The output current is input from the main current post electrode 8d to the main current post electrode 8bc via the lower surface wiring layer 32b. The output current is output from the external connection terminal 4 via the circuit pattern 13a2 from the main current post electrode 8b. Also, the output current output from the main electrode 22a (emitter electrode) of the semiconductor chip 20a is output from the sense terminal 7b via the lower surface wiring layer 32c from the detection post electrode 9d.

[0065] In this way, in the semiconductor device 1, by inputting control signals to the control terminals 6a and 6b at a predetermined timing, an output current with a predetermined waveform can be obtained from the external connection terminal 5. At this time, the distance Lc2 from the control terminal 6a to the control electrode 21b of the semiconductor chip 20b and the distance Lc1 from the control terminal 6b to the control electrode 21a of the semiconductor chip 20a are substantially equal. For this reason, the inductances and electrical resistances of the upper surface wiring layers 33a and 33c become substantially equal, and control delays during the switching operation and the like are prevented, and a decrease in controllability can be prevented.

[0066] Also, the distance between the distance Ls2 from the sense terminal 7a to the main electrode 22b of the semiconductor chip 20b and the distance Ls1 from the sense terminal 7b to the main electrode 22a of the semiconductor chip 20a is substantially equal. The lower surface wiring layers 32a and 32c through which the sense current flows have the same length as the upper surface wiring layers 33a and 33c through which the control signal flows. The lower surface wiring layers 32a and 32c are formed to coincide with the back surface of the upper surface wiring layers 33a and 33c with the insulating layer 31 interposed therebetween. And the energization direction of the sense current with respect to the lower surface wiring layers 32a and 32c and the energization direction of the control signal with respect to the upper surface wiring layers 33a and 33c are opposite directions. For this reason, the mutual inductance generated by the control signal and the sense current is canceled out. Therefore, the electrical influence on the vicinity of the upper surface wiring layers 33a and 33c can be suppressed.

[0067] The semiconductor device 1 described above includes semiconductor chips 20a and 20b having control electrodes 21a and 21b on the front surface, and upper surface wiring layers 33c and 33a that are stripe-shaped in plan view, with one end facing and electrically connected to the control electrodes 21a and 21b. At this time, the upper surface wiring layers 33c and 33a extend with their other ends facing in opposite directions, and the lengths of the upper surface wiring layers 33c and 33a in the extending direction are equal to each other. For this reason, the inductances and electrical resistances of the upper surface wiring layers 33a and 33c become substantially equal, preventing delays in control during the switching operation and the like, and preventing a decrease in controllability.

[0068] [Second Embodiment] In the second embodiment, in the first embodiment, the semiconductor chips 20a and 20b are rotated and arranged with respect to the insulating circuit boards 10a and 10b. The semiconductor device of the second embodiment will be described with reference to FIGS. 6 and 7. In the second embodiment, the description will focus on the parts modified from the semiconductor device of the first embodiment.

[0069] FIG. 6 is a plan view of the semiconductor device of the second embodiment, and FIG. 7 is a side cross-sectional view of the semiconductor device of the second embodiment. Note that FIG. 7 is a cross-sectional view taken along the dashed-dotted line X-X in FIG. 6. The dashed-dotted line X-X is also a center line passing through the center of the short side of the semiconductor device 1a and parallel to the long side.

[0070] The semiconductor device 1a includes a rectangular parallelepiped-shaped sealing main body portion 2, and external connection terminals 3, 4, 5, control terminals 6a, 6b, and sense terminals 7a, 7b extend vertically upward (+Z direction) from the front surface 2e of the sealing main body portion 2 with respect to the front surface 2e.

[0071] In the semiconductor device 1a, in the semiconductor device 1, the control terminals 6a, 6b and the sense terminals 7a, 7b are provided symmetrically with respect to the center line and are displaced toward the side wall portion 2c. The control terminals 6a, 6b are provided on the side wall portion 2a side, and the sense terminals 7a, 7b are provided on the side wall portion 2c side, respectively. Along with this, the terminal blocks 2i, 2j are also integrally formed on the front surface 2e so as to be displaced toward the side wall portion 2c side with respect to the center line and be line-symmetric. Therefore, the upper ends of the control terminals 6a, 6b and the sense terminals 7a, 7b extend from the front surface of the terminal blocks 2i, 2j. The lower ends of the control terminals 6a, 6b and the sense terminals 7a, 7b extend vertically downward (-Z direction) inside the sealing main body portion 2.

[0072] Next, the details of the semiconductor chips 20a, 20b, the insulating circuit boards 10a, 10b, and the printed circuit board 30 will be described. First, the semiconductor chips 20a, 20b and the insulating circuit boards 10a, 10b will be described with reference to FIG. 8. FIG. 8 is a plan view of the inside of the semiconductor device according to the second embodiment. Note that FIG. 8 is a plan view of the insulating circuit boards 10a, 10b to which the semiconductor chips 20a, 20b are joined in the semiconductor device 1a. The positions of the sealing main body portion 2, the main current post electrodes 8a to 8d, the control post electrodes 9a, 9b, and the detection post electrodes 9c, 9d of the semiconductor device 1a are shown by broken lines.

[0073] In the semiconductor chips 20a, 20b, the control electrodes 21a, 21b are arranged so as to face in opposite directions with respect to the circuit patterns 13a1, 13b. That is, the sides of the semiconductor chips 20a, 20b on which the control electrodes 21a, 21b are provided are arranged so as to be close to each other at the opposite ends in the longitudinal direction of the sealing main body portion 2. More specifically, in the semiconductor chips 20a, 20b, the control electrodes 21a, 21b are arranged facing the side wall portions 2d, 2b of the sealing main body portion 2, respectively. Along with such an arrangement of the semiconductor chips 20a, 20b, the main current post electrodes 8c, 8b are also arranged linearly with respect to the semiconductor chips 20a, 20b.

[0074] Next, the printed circuit board 30 will be described with reference to FIGS. 9 and 10. FIG. 9 is a plan view of the front surface of the printed circuit board included in the semiconductor device of the second embodiment, and FIG. 10 is a plan view of the back surface of the printed circuit board included in the semiconductor device of the second embodiment. Note that FIG. 9 shows the upper surface wiring layer 33 of the printed circuit board 30 as viewed from the front surface of the printed circuit board 30, and FIG. 10 shows the lower surface wiring layer 32 of the printed circuit board 30 as viewed from the front surface of the printed circuit board 30. Also, FIGS. 9 and 10 show the components included in the sealing main body portion 2, the semiconductor chips 20a and 20b, and the insulating circuit boards 10a and 10b with broken lines.

[0075] As shown in FIG. 9, the printed circuit board 30 includes an insulating layer 31 and upper surface wiring layers 33a, 33b, and 33c formed on the front surface of the insulating layer 31. The upper surface wiring layer 33a has a stripe shape (strip shape) with a length of length L2 in a plan view. Note that the width of the upper surface wiring layer 33a in the X direction only needs to be such that at least the through hole through which the detection post electrode 9c (or the sense terminal 7a) penetrates and the control post electrode 9a (or the control terminal 6a) can be formed along the X direction.

[0076] One end portion (the left end portion in the figure) of the upper surface wiring layer 33a is electrically and mechanically connected to the control post electrode 9a. Therefore, one end portion of the upper surface wiring layer 33a faces the control electrode 21b of the semiconductor chip 20b and is electrically connected via the control post electrode 9a. Also, with respect to one end portion of the upper surface wiring layer 33a, the detection post electrode 9c penetrates without being electrically connected to the side wall portion 2c side of the control post electrode 9a.

[0077] The other end portion (right end portion in the figure) of the upper wiring layer 33a extends along the side wall portions 2a and 2c to the side wall portion 2b. Further, the other end portion of the upper wiring layer 33a is electrically and mechanically connected to the control terminal 6a. The control terminal 6a is arranged so as to be linear with respect to the control post electrode 9a. Further, a sense terminal 7a penetrates through the other end portion of the upper wiring layer 33a without being electrically connected to the side wall portion 2c side of the control terminal 6a. At this time, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same length.

[0078] The upper wiring layer 33b is in a stripe shape in a plan view. The width of the upper wiring layer 33b in the X direction may be about the length obtained by combining the diameters of at least three main current post electrodes 8c. One end portion (left end portion in the figure) of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8c. Note that one end portion of the upper wiring layer 33b may extend up to in front of the main current post electrode 8d. In FIG. 9, one end portion of the upper wiring layer 33b extends up to in front of the semiconductor chip 20a in a plan view.

[0079] The other end portion (right end portion in the figure) of the upper wiring layer 33b extends along the side wall portions 2a and 2c to the side wall portion 2b. Further, the other end portion of the upper wiring layer 33b is electrically and mechanically connected to the main current post electrode 8a. Therefore, the upper wiring layer 33b faces the main electrode 22b of the semiconductor chip 20b and is electrically connected via the main current post electrode 8a. The other end portion of the upper wiring layer 33b extends up to in front of the control electrode 21b of the semiconductor chip 20b. Further, a main current post electrode 8b penetrates through the side wall portion 2b side of the main current post electrode 8c of the upper wiring layer 33b without being electrically connected.

[0080] The upper wiring layer 33c forms a stripe shape with a length of L1 in a plan view. Also, the length L1 and the length L2 are the same length. Note that the width of the upper wiring layer 33c in the X direction only needs to be such that at least the through-hole through which the detection post electrode 9d (or the sense terminal 7b) penetrates and the control post electrode 9b (or the control terminal 6b) can be formed along the X direction.

[0081] One end portion (the right end portion in the figure) of the upper wiring layer 33c is electrically and mechanically connected to the control post electrode 9b. Therefore, one end portion of the upper wiring layer 33c faces the control electrode 21a of the semiconductor chip 20a and is electrically connected via the control post electrode 9b. Also, with respect to one end portion of the upper wiring layer 33c, the detection post electrode 9d penetrates through the side wall portion 2c side of the control post electrode 9b without being electrically connected.

[0082] The other end portion (the left end portion in the figure) of the upper wiring layer 33c extends along the side wall portions 2a and 2c to the side wall portion 2d. Also, the other end portion of the upper wiring layer 33c is electrically and mechanically connected to the control terminal 6b. With respect to the other end portion of the upper wiring layer 33c, the sense terminal 7b penetrates through the side wall portion 2c side of the control terminal 6b without being electrically connected. At this time, the length Lc1 from the control post electrode 9b to the control terminal 6b and the length Ls1 from the detection post electrode 9d to the sense terminal 7b are the same length.

[0083] Furthermore, as shown in FIG. 10, the printed circuit board 30 includes lower wiring layers 32a, 32b, and 32c formed on the back surface of the insulating layer 31. The lower wiring layer 32a forms a stripe shape with a length of L4 in a plan view. Note that the length L4 is substantially the same length as the length L2 of the upper wiring layer 33a. The width of the lower wiring layer 32a in the X direction only needs to be such that at least the through-hole through which the control post electrode 9a (or the control terminal 6a) penetrates and the detection post electrode 9c (or the sense terminal 7a) can be formed along the X direction. That is, the lower wiring layer 32a has the same shape and size as the upper wiring layer 33a. Also, the lower wiring layer 32a is formed on the back surface at the same position as the upper wiring layer 33a with the insulating layer 31 interposed therebetween.

[0084] One end portion (left end portion in the figure) of the lower wiring layer 32a is electrically and mechanically connected to the detection post electrode 9c. Therefore, one end portion of the lower wiring layer 32a faces the region of the main electrode 22b adjacent to the control electrode 21b of the semiconductor chip 20b and is electrically connected via the detection post electrode 9c. Further, with respect to one end portion of the lower wiring layer 32a, the control post electrode 9a penetrates without being electrically connected to the side wall portion 2a side of the detection post electrode 9c.

[0085] The other end portion (right end portion in the figure) of the lower wiring layer 32a extends along the side wall portions 2a and 2c to the side wall portion 2b. Further, the other end portion of the lower wiring layer 32a is electrically and mechanically connected to the sense terminal 7a. Further, with respect to the other end portion of the lower wiring layer 32a, the control terminal 6a penetrates without being electrically connected to the side wall portion 2d side of the sense terminal 7a. At this time, as described for the upper wiring layer 33a, the length Lc2 from the control post electrode 9a to the control terminal 6a and the length Ls2 from the detection post electrode 9c to the sense terminal 7a are the same length.

[0086] The lower wiring layer 32b forms a stripe shape in plan view. Note that the width of the lower wiring layer 32b in the X direction may be about the length obtained by combining the diameters of at least three main current post electrodes 8d. One end portion (left end portion in the figure) of the lower wiring layer 32b is electrically and mechanically connected to the main current post electrode 8d. Therefore, one end portion of the lower wiring layer 32b faces the main electrode 22a of the semiconductor chip 20a and is electrically connected via the main current post electrode 8d.

[0087] The other end portion (the right end portion in the figure) of the lower wiring layer 32b extends along the side wall portions 2a and 2c to the side wall portion 2b up to the main current post electrode 8b. The other end portion of the lower wiring layer 32b is electrically and mechanically connected to the main current post electrode 8b. Further, the main current post electrode 8c penetrates between one end portion and the other end portion of the lower wiring layer 32b without electrical connection. Also, the lower wiring layer 32b is formed on the back surface of the upper wiring layer 33b so as to be in a line with the upper wiring layer 33b with the insulating layer 31 interposed therebetween. Further, a part of the lower wiring layer 32b overlaps with the upper wiring layer 33b.

[0088] The lower wiring layer 32c forms a stripe shape with a length of L3 in a plan view. Note that the length L3 is substantially the same as the length L1 of the upper wiring layer 33c. Also, the length L3 and the length L4 are the same length. Note that the width of the lower wiring layer 32c in the X direction only needs to be such that at least the through hole through which the control post electrode 9b (or the control terminal 6b) penetrates and the detection post electrode 9d (or the sense terminal 7b) can be formed along the X direction. That is, the lower wiring layer 32c has the same shape and size as the upper wiring layer 33c. Also, the lower wiring layer 32c is formed on the back surface at the same position as the upper wiring layer 33c with the insulating layer 31 interposed therebetween.

[0089] One end portion (the right end portion in the figure) of the lower wiring layer 32c is electrically and mechanically connected to the detection post electrode 9d. Therefore, one end portion of the lower wiring layer 32c faces the region of the main electrode 22a adjacent to the control electrode 21a and is electrically connected via the detection post electrode 9d. With respect to one end portion of the lower wiring layer 32c, the control post electrode 9b penetrates through the side wall portion 2a side of the detection post electrode 9d without electrical connection.

[0090] The other end (left end in the figure) of the lower wiring layer 32c extends along the side wall portions 2a and 2c to the side wall portion 2d. Further, the other end of the lower wiring layer 32c is electrically and mechanically connected to the sense terminal 7b. Further, the control terminal 6b penetrates through the side wall portion 2a side of the sense terminal 7b without being electrically connected to the other end of the lower wiring layer 32c. At this time, as described for the upper wiring layer 33c, the length Lc1 from the control post electrode 9b to the control terminal 6b and the length Ls1 from the detection post electrode 9d to the sense terminal 7b are the same length.

[0091] Therefore, the control electrodes 21a and 21b of the semiconductor chips 20a and 20b are electrically connected to the control terminals 6b and 6a via the control post electrodes 9b and 9a and the upper wiring layers 33c and 33a.

[0092] Even in such a semiconductor device 1a, by inputting a control signal to the control terminals 6a and 6b at a predetermined timing, an output current having a predetermined waveform can be obtained from the external connection terminal 5. At this time, the distance Lc2 from the control terminal 6a to the control electrode 21b of the semiconductor chip 20b and the distance Lc1 from the control terminal 6b to the control electrode 21a of the semiconductor chip 20a are substantially equal. For this reason, the inductances and electrical resistances of the upper wiring layers 33a and 33c become substantially equal, and control delay during the switching operation and the like are prevented, and a decrease in controllability can be prevented.

[0093] Also, the distance Ls2 from the sense terminal 7a to the main electrode 22b of the semiconductor chip 20b and the distance Ls1 from the sense terminal 7b to the main electrode 22a of the semiconductor chip 20a are substantially equal. The lower surface wiring layers 32a and 32c through which the sense current flows have the same length as the upper surface wiring layers 33a and 33c through which the control signal flows. The lower surface wiring layers 32a and 32c are formed to coincide with the back surface of the upper surface wiring layers 33a and 33c with the insulating layer 31 interposed therebetween. And the energization direction of the sense current with respect to the lower surface wiring layers 32a and 32c is opposite to the energization direction of the control signal with respect to the upper surface wiring layers 33a and 33c. For this reason, the mutual inductance generated by the control signal and the sense current is canceled out. Therefore, the electrical influence on the vicinity of the upper surface wiring layers 33a and 33c can be suppressed.

[0094] Also, in the semiconductor device 1a, the lengths of the upper surface wiring layers 33a and 33b and the lower surface wiring layers 32a and 32c can be shortened. Also, in the case of the semiconductor device 1, for example, there is an overlapping region on the semiconductor chip 20b in a side view between the upper surface wiring layer 33a and the upper surface wiring layer 33b. For this reason, there is a limit to reducing the width of the semiconductor device 1 in the X direction. In the semiconductor device 1a, since the upper surface wiring layer 33 and the lower surface wiring layer 32 are arranged linearly, the width in the X direction can be reduced. For this reason, the semiconductor device 1a can be made smaller than the semiconductor device 1.

[0095] Note that, in the semiconductor device 1a, the case where the control terminals 6a and 6b are arranged on the center line (dashed-dotted line X-X) and the sense terminals 7a and 7b are provided with a displacement from the center line toward the side wall portion 2c is described. Not limited to this case, the sense terminals 7a and 7b may be provided with a displacement with respect to the control terminals 6a and 6b toward the side wall portion 2a. In this case, with respect to FIGS. 9 and 10, the sense terminals 7a and 7b are provided on the side wall portion 2a side with respect to the control terminals 6a and 6b, and the detection post electrodes 9c and 9d are provided on the side wall portion 2a side with respect to the control post electrodes 9a and 9b.

[0096] Further, the control terminals 6a and 6b and the sense terminals 7a and 7b may be arranged symmetrically with respect to the center line (dashed-dotted line X-X) with respect to the front surface 2e of the semiconductor device 1a. In this case, for example, the semiconductor chips 20a and 20b in FIGS. 8 to 10 are displaced toward the side wall portion 2a.

[0097] [Third Embodiment] In the third embodiment, a power conversion device including a plurality of semiconductor devices 1 of the first embodiment will be described with reference to FIGS. 11, 1, and 2. FIG. 11 is a diagram showing the power conversion device of the third embodiment. Note that FIG. 11(A) shows a plan view of the power conversion device. FIG. 11(B) represents a cross-sectional view taken along the dashed-dotted line X-X in FIG. 11(A). The power conversion device 40 includes the semiconductor device 1 of the first embodiment. Note that the reference numeral of the semiconductor device 1 is omitted. The configuration of the semiconductor device 1 can be referred to FIGS. 1 and 2. Note that the power conversion device 40 is not limited to the semiconductor device 1 of the first embodiment, and the semiconductor device 1a of the second embodiment may be similarly used.

[0098] The power conversion device 40 includes a plurality of semiconductor devices 1 and conduction substrates 41 to 44, 45a, 45b, 45c that are electrically connected to the plurality of semiconductor devices 1. The plurality of semiconductor devices 1 are arranged in the X direction such that the short side wall portions 2d and 2b are in the same plane (parallel) and the long side wall portions 2a and 2c face each other. FIG. 11 shows a case where the semiconductor devices 1 are arranged in three rows.

[0099] The conduction substrates 41 to 44, 45a, 45b, 45c are plates including a conductor. The conduction substrates 41 to 44, 45a, 45b, 45c are, for example, bus bars or printed circuit boards. The conduction substrates 41 to 44, 45a, 45b, 45c can electrically connect a driver circuit, external devices such as a power supply and output equipment to the external connection terminals 3, 4, 5, the control terminals 6a, 6b, and the sense terminals 7a, 7b of the semiconductor device 1, and can control each semiconductor device 1 and perform input / output of voltages and the like to the semiconductor device 1.

[0100] The conduction substrates 41 and 42 are electrically and mechanically connected to the control terminals 6a and 6b and the sense terminals 7a and 7b of the semiconductor device 1. A control signal is input to the control terminals 6a and 6b at a predetermined timing by the conduction substrates 41 and 42. Also, a sense current is input from the sense terminals 7a and 7b to the conduction substrates 41 and 42.

[0101] The conduction substrates 43 and 44 are electrically and mechanically connected to the external connection terminals 3 and 4 of the semiconductor device 1. External power supplies of the positive electrode and the negative electrode are connected to the conduction substrates 43 and 44, respectively.

[0102] The conduction substrates 45a, 45b, and 45c are electrically and mechanically connected to the external connection terminals 5 of a plurality of semiconductor devices 1, respectively. The conduction substrates 45a, 45b, and 45c input the output current output from the external connection terminals 5 of the plurality of semiconductor devices 1 to a load.

[0103] In the semiconductor device 1, the upper surface wiring layers 33a and 33c are arranged facing in opposite directions. Therefore, in the power conversion device 40, such semiconductor devices 1 can be arranged in a required number and array so that the short side side wall portions 2d and 2b are parallel and the long side side wall portions 2a and 2c face each other.

Explanation of Signs

[0104] 1, 1a Semiconductor device 2 Sealing main body portion 2a~2d Side wall portions 2e Front surface 2f~2j Terminal blocks 3~5 External connection terminals 6a, 6b Control terminals 7a, 7b Sense terminals 8a~8d Main current post electrodes 9a, 9b Control post electrodes 9c, 9d Detection post electrodes 10a, 10b Insulating circuit boards 11a, 11b Insulating plates 12a, 12b Metal plates 13a1, 13a2, 13b Circuit patterns 20a and 20b semiconductor chips 21a and 21b control electrodes 22a and 22b main electrodes 30 printed circuit board 31 insulating layer 32 and 32a - 32c bottom wiring layers 33 and 33a - 33c top wiring layers 40 power conversion device 41 - 44, 45a, 45b, 45c conduction substrates

Claims

【Claim 1】 a first semiconductor chip having a first control electrode and a first main electrode on a front surface; a second semiconductor chip having a second control electrode and a second main electrode on a front surface; a first control wiring layer that is stripe-shaped in plan view, one end of which faces and is electrically connected to the first control electrode, a second control wiring layer that is stripe-shaped in plan view, one end of which faces and is mainly electrically connected to the second control electrode, an insulating layer on which the first control wiring layer and the second control wiring layer are formed on a first main surface, and a first detection wiring layer that is stripe-shaped in plan view and is formed on a second main surface opposite to the first main surface of the insulating layer, one end of which faces and is electrically connected to the first main electrode, and a second detection wiring layer that is stripe-shaped in plan view and is formed on the second main surface, one end of which faces and is electrically connected to the second main electrode, and a printed circuit board facing the first semiconductor chip and the second semiconductor chip; a first control terminal formed at the other end of the first control wiring layer; a second control terminal formed at the other end of the second control wiring layer; a first sense terminal formed at the other end of the first detection wiring layer; a second sense terminal formed at the other end of the second detection wiring layer; comprising the first control wiring layer and the second control wiring layer extend with their other ends facing in opposite directions, and the lengths of the first control wiring layer and the second control wiring layer in the extending direction are equal to each other; the first detection wiring layer and the second detection wiring layer extend with their other ends facing in opposite directions, and the lengths of the first detection wiring layer and the second detection wiring layer in the extending direction are equal to each other; the lengths of the first detection wiring layer and the second detection wiring layer in the extending direction are the same as the lengths of the first control wiring layer and the second control wiring layer in the extending direction; the first detection wiring layer and the second detection wiring layer are formed on the second main surface of the insulating layer facing the first control wiring layer and the second control wiring layer; the length between the portion of the first control wiring layer electrically connected to the first control electrode and the portion where the first control terminal is formed is equal to the length between the portion of the first detection wiring layer electrically connected to the first main electrode and the portion where the first sense terminal is formed; The length between the portion electrically connected to the second control electrode of the second control wiring layer and the portion where the second control terminal is formed is equal to the length between the portion electrically connected to the second main electrode of the second detection wiring layer and the portion where the second sense terminal is formed. Semiconductor device. **Claim 2** The first control electrode is provided on the first side of the front surface of the first semiconductor chip. The second control electrode is provided on the second side of the front surface of the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are arranged such that the first side and the second side are parallel to each other. The semiconductor device according to claim 1. **Claim 3** The first side of the first semiconductor chip is arranged in series on the extension line of the second side of the second semiconductor chip. The semiconductor device according to claim 2. **Claim 4** The first side of the first semiconductor chip and the second side of the second semiconductor chip are arranged close to each other at each end in the longitudinal direction of the semiconductor device. The semiconductor device according to claim 2. **Claim 5** A first insulating circuit board on which the first semiconductor chip is mounted; A second insulating circuit board on which the second semiconductor chip is mounted; further comprising: The first insulating circuit board includes a first insulating plate and a first circuit pattern formed on the front surface of the first insulating plate to which the first semiconductor chip is joined. The second insulating circuit board includes a second insulating plate and a second circuit pattern formed on the front surface of the second insulating plate to which the second semiconductor chip is joined. The semiconductor device according to any one of claims 1 to 4.

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