Compound Semiconductor Device and Method for Manufacturing Compound Semiconductor Device

Abstract

To provide a compound semiconductor device and a method for manufacturing the compound semiconductor device that can suppress decrease in 2DEG density.SOLUTION: A compound semiconductor device has a carrier supply layer, a channel layer provided on the carrier supply layer and containing InGaAs, and an etching stopper layer provided on the channel layer, the etching stopper layer has a first layer provided on the channel layer and containing Inx1Ga1-x1 P( 0<x1≤1) and a second layer provided on the first layer and containing Inx2Ga1-x2 P(0≤x2<1) and a value of x1 is larger than a value of x2.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present disclosure relates to a compound semiconductor device and a method for manufacturing a compound semiconductor device.

Background Art

[0002] Application of InP-based high electron mobility transistors (HEMTs) to high-capacity high-speed wireless communication in the millimeter-wave band and terahertz band is expected. InP-based HEMTs have high-speed and low-noise device characteristics. In order to apply an InP-HEMT to a wireless transceiver system in the 300 GHz band, a maximum oscillation frequency (fmax) of 600 GHz or higher is desired for a single InP-HEMT device. In addition to reducing parasitic capacitance by shortening the gate length, reducing the drain conductance (gd) is effective for improving the maximum oscillation frequency.

[0003] To reduce the drain conductance, suppressing impact ionization by electric field relaxation in the channel is effective. For electric field relaxation, a structure in which a carrier supply layer is on the substrate side rather than the channel layer has been proposed. A HEMT having this structure is sometimes called an inverse HEMT.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a conventional inverse HEMT, a two-dimensional electron gas (2DEG) density decreases due to the influence of an etching stopper containing InGaP formed on a channel layer containing InGaAs.

[0006] An object of the present disclosure is to provide a compound semiconductor device and a method for manufacturing a compound semiconductor device capable of suppressing a decrease in the density of 2DEG.

Means for Solving the Problems

[0007] According to one embodiment of the present disclosure, there are provided a carrier supply layer, a channel layer provided on the carrier supply layer and containing InGaAs, and an etching stopper layer provided on the channel layer. The etching stopper layer is provided on the channel layer and has a first layer containing In x1 Ga 1-x1 P(0 < x1 ≦ 1) and a second layer provided on the first layer and containing In x2 Ga 1-x2 P(0 ≦ x2 < 1), and a compound semiconductor device is provided in which the value of x1 is larger than the value of x2.

Advantages of the Invention

[0008] According to the present disclosure, a decrease in the density of 2DEG can be suppressed.

Brief Description of the Drawings

[0009]

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Modes for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant descriptions may be omitted.

[0011] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a compound semiconductor device including an InP-based HEMT. FIG. 1 is a cross-sectional view showing the compound semiconductor device according to the first embodiment.

[0012] As shown in FIG. 1, the compound semiconductor device 100 according to the first embodiment includes a carrier supply layer 103, a channel layer 104, an etching stopper layer 105, a cap layer 106, an insulating layer 112, a source electrode 11, a drain electrode 12, and a gate electrode 13.

[0013] The channel layer 104 is provided on the carrier supply layer 103. The channel layer 104 contains InGaAs. The etching stopper layer 105 is provided on the channel layer 104. The etching stopper layer 105 has a first layer 105A and a second layer 105B. The first layer 105A is provided on the channel layer 104. The first layer 105A contains In x1 Ga 1-x1 P (0 < x1 ≤ 1). The second layer 105B is provided on the first layer 105A. The second layer 105B contains In x2 Ga 1-x2It includes P(0≦x2<1). The value of x1, which is the In composition of the first layer 105A, is larger than the value of x2, which is the In composition of the second layer 105B. The difference in lattice constant between the first layer 105A and the channel layer 104 is smaller than the difference in lattice constant between the second layer 105B and the channel layer 104.

[0014] The cap layer 106 is provided on the etching stopper layer 105. A recess 111 reaching the etching stopper layer 105 is formed in the cap layer 106. The source electrode 11 and the drain electrode 12 are provided on the cap layer 106 with the recess 111 therebetween in a plan view. The insulating layer 112 is provided on the etching stopper layer 105 inside the recess 111. The gate electrode 13 is provided on the insulating layer 112.

[0015] In the first embodiment, a two-dimensional electron gas (2DEG) is generated in the vicinity of the interface between the carrier supply layer 103 of the channel layer 104.

[0016] Next, a method for manufacturing the compound semiconductor device 100 according to the first embodiment will be described. FIGS. 2 to 6 are cross-sectional views showing the method for manufacturing the compound semiconductor device 100 according to the first embodiment.

[0017] First, as shown in FIG. 2, a channel layer 104 is formed on the carrier supply layer 103, a first layer 105A is formed on the channel layer 104, a second layer 105B is formed on the first layer 105A, and a cap layer 106 is formed on the second layer 105B.

[0018] Next, as shown in FIG. 3, a source electrode 11 and a drain electrode 12 are formed on the cap layer 106.

[0019] Thereafter, as shown in FIG. 4, a recess 111 for the gate electrode 13 is formed in the cap layer 106 between the source electrode 11 and the drain electrode 12 in a plan view. The recess 111 is formed so as to reach the etching stopper layer 105.

[0020] Subsequently, as shown in FIG. 5, an insulating layer 112 is formed on the etching stopper layer 105 inside the recess 111.

[0021] Next, as shown in FIG. 6, a gate electrode 13 is formed on the insulating layer 112.

[0022] In the first embodiment, the etching stopper layer 105 has a first layer 105A and a second layer 105B. Also, the value of x1 which is the In composition of the first layer 105A is larger than the value of x2 which is the In composition of the second layer 105B, and the difference in lattice constant between the lattice constant of the first layer 105A and the channel layer 104 is smaller than the difference in lattice constant between the lattice constant of the second layer 105B and the channel layer 104. Therefore, compared with the case where the etching stopper layer 105 is composed of only the second layer 105B, the lattice mismatch between the channel layer 104 and the etching stopper layer 105 can be alleviated, and a decrease in the density of 2DEG due to the lattice mismatch can be suppressed. Also, compared with the case where the etching stopper layer 105 is composed of only the first layer 105A, a larger bandgap of the etching stopper layer 105 can be ensured, and leakage current can be suppressed.

[0023] Furthermore, since the etching of the cap layer 106 for forming the recess 111 can be stopped at the upper surface of the etching stopper layer 105, high-precision manufacturing is possible.

[0024] (Second Embodiment) Next, the second embodiment will be described. The second embodiment relates to a compound semiconductor device including an InP-based HEMT. FIG. 7 is a cross-sectional view showing the compound semiconductor device according to the second embodiment.

[0025] As shown in FIG. 7, the compound semiconductor device 200 according to the second embodiment includes a substrate 201, a buffer layer 202, a carrier supply layer 203, a channel layer 204, an etching stopper layer 205, a cap layer 206, an insulating layer 212, a source electrode 11, a drain electrode 12, and a gate electrode 13.

[0026] The substrate 201 is, for example, a semi-insulating InP substrate. The buffer layer 202 is provided on the substrate 201. The buffer layer 202 is, for example, an InAlAs layer (i-InAlAs layer) with a thickness of about 300 nm in which no intentional impurity introduction is performed. The carrier supply layer 203 is formed, for example, by introducing impurities such as delta doping (atomic layer doping) onto the surface of the buffer layer 202. As the impurity, for example, Si, Sn, Se, or any combination thereof is used. The channel layer 204 is provided on the carrier supply layer 203. The channel layer 204 is, for example, an InGaAs layer (i-InGaAs layer) with a thickness of about 10 nm in which no intentional impurity introduction is performed.

[0027] The etching stopper layer 205 is provided on the channel layer 204. The etching stopper layer 205 has a first layer 205A and a second layer 205B. The first layer 205A is provided on the channel layer 204. The first layer 205A is, for example, an n-type InP layer (n-InP layer) with a thickness of about 1 nm to 4 nm. The second layer 205B is provided on the first layer 205A. The second layer 205B is, for example, an n-type InGaP layer (n-InGaP layer) with a thickness of about 1 nm to 4 nm. The range of the In composition of the InGaP layer constituting the second layer 205B (atomic composition of the two elements In and Ga) is, for example, 50% to 95%. The difference in lattice constant between the first layer 205A and the channel layer 204 is smaller than the difference in lattice constant between the second layer 205B and the channel layer 204. The cap layer 206 is provided on the etching stopper layer 205. The cap layer 206 is an n-type InGaAs layer (n-InGaAs layer) with a thickness of about 50 nm.

[0028] An element isolation region 220 is formed in the buffer layer 202, the carrier supply layer 203, the channel layer 204, the etching stopper layer 205, and the cap layer 206. In the element region partitioned by the element isolation region 220, a recess 211 reaching the etching stopper layer 205 is formed in the cap layer 206.

[0029] The source electrode 11 and the drain electrode 12 are provided on the cap layer 206 with the recess 211 therebetween in a plan view. The source electrode 11 and the drain electrode 12 include, for example, a Ti film with a thickness of about 10 nm, a Pt film with a thickness of about 30 nm, and an Au film with a thickness of about 300 nm. The Pt film is provided on the Ti film, and the Au film is provided on the Pt film.

[0030] The insulating layer 212 is provided on the etching stopper layer 205 inside the recess 211. The insulating layer 212 may also be formed on the inner wall surface of the recess 211 and on the upper surface of the cap layer 206. The insulating layer 212 is, for example, an aluminum oxide layer with a thickness of about 2 nm. The gate electrode 13 is provided on a portion of the insulating layer 212 inside the recess 211. The gate electrode 13 includes, for example, a Ti film with a thickness of about 10 nm, a Pt film with a thickness of about 30 nm, and an Au film with a thickness of about 300 nm. The Pt film is provided on the Ti film, and the Au film is provided on the Pt film. The cross-sectional shape of the gate electrode 13 may be T-shaped. The compound semiconductor device 200 has a MOS (metal-oxide-semiconductor) type gate.

[0031] In the second embodiment, a two-dimensional electron gas (2DEG) is generated near the interface between the carrier supply layer 203 of the channel layer 204.

[0032] Next, a method for manufacturing the compound semiconductor device 200 according to the second embodiment will be described. FIGS. 8 to 13 are cross-sectional views showing the method for manufacturing the compound semiconductor device 200 according to the second embodiment.

[0033] First, as shown in FIG. 8, a buffer layer 202 is formed on the substrate 201. The buffer layer 202 can be formed by a crystal growth method such as a metal-organic chemical vapor deposition (MOCVD) method.

[0034] Next, as also shown in FIG. 8, a carrier supply layer 203 is formed on the surface of the buffer layer 202. The carrier supply layer 203 can be formed, for example, by introducing impurities such as delta doping (atomic layer doping). As the impurity, for example, silicon is doped to about 12 cm -2 . The impurity is doped into the buffer layer 202 in a sheet shape, and the peak of the impurity profile is set to a depth of about 3 nm to about 5 nm from the surface of the buffer layer 202. The portion on the surface side of this peak can also be regarded as a spacer layer.

[0035] Thereafter, as also shown in FIG. 8, a channel layer 204 is formed on the carrier supply layer 203, a first layer 205A is formed on the channel layer 204, a second layer 205B is formed on the first layer 205A, and a cap layer 206 is formed on the second layer 205B. The channel layer 204, the first layer 205A, the second layer 205B, and the cap layer 206 can be formed, for example, by a crystal growth method such as the MOCVD method.

[0036] Subsequently, as shown in FIG. 9, an element isolation region 220 is formed in the buffer layer 202, the carrier supply layer 203, the channel layer 204, the etching stopper layer 205, and the cap layer 206. The element isolation region 220 is formed, for example, as follows. First, a region where the element isolation region 220 is to be formed is exposed, and a photoresist mask covering other regions is formed on the cap layer 206, and the cap layer 206 is etched, for example, with a mixed solution of phosphoric acid and hydrogen peroxide water. This etching stops at the surface of the etching stopper layer 205. Next, the etching stopper layer 205 is etched, for example, with hydrochloric acid. This etching stops at the surface of the channel layer 204. Thereafter, the channel layer 204, the carrier supply layer 203, and the buffer layer 202 are etched, for example, with a mixed solution of phosphoric acid and hydrogen peroxide water. In this way, the element isolation region 220 can be formed. After the formation of the element isolation region 220, the photoresist mask is removed.

[0037] Next, as shown in FIG. 10, within the device region partitioned by the device isolation region 220, source electrode 11 and drain electrode 12 are formed on the cap layer 206. In forming the source electrode 11 and the drain electrode 12, a photoresist mask is formed on the cap layer 206 to expose the regions where the source electrode 11 is to be formed and the regions where the drain electrode 12 is to be formed, and to cover other regions. Then, a Ti film, a Pt film, and an Au film are formed by vapor deposition, and the photoresist mask is removed together with the Ti film, the Pt film, and the Au film thereon. In this way, the source electrode 11 and the drain electrode 12 can be formed by the lift-off method.

[0038] Thereafter, as shown in FIG. 11, a recess 211 for the gate electrode 13 is formed in the cap layer 206 between the source electrode 11 and the drain electrode 12 in plan view. The recess 211 can be formed by electron beam lithography by forming a mask on the cap layer 206 to expose the region where the recess 211 is to be formed and to cover other regions, and then etching the cap layer 206 with, for example, a mixed solution of phosphoric acid and hydrogen peroxide water. This etching stops at the surface of the etching stopper layer 205.

[0039] Subsequently, as shown in FIG. 12, an insulating layer 212 is formed to cover the upper surface and the side surfaces of the etching stopper layer 205 within the recess 211 and the upper surface of the cap layer 206. The insulating layer 212 can be formed by, for example, atomic layer deposition (ALD) method.

[0040] Next, as shown in FIG. 13, a gate electrode 13 is formed on the insulating layer 212 within the recess 211. In forming the gate electrode 13, for example, by electron beam lithography, a mask, such as a multilayer mask, is formed on the insulating layer 212 to expose the region where the gate electrode 13 is to be formed and to cover other regions, a Ti film, a Pt film, and an Au film are formed by vapor deposition, and the mask is removed together with the Ti film, the Pt film, and the Au film thereon. In this way, the gate electrode 13 can be formed by the lift-off method.

[0041] Then, if necessary, a passivation film, wiring, etc. are formed to complete the compound semiconductor device 200.

[0042] In the second embodiment, the etching stopper layer 205 has a first layer 205A and a second layer 205B. Further, since the first layer 205A is an InP layer and the second layer 205B is an InGaP layer, the In composition of the first layer 205A is larger than that of the second layer 205B, and the difference in lattice constant between the first layer 205A and the channel layer 204 is smaller than the difference in lattice constant between the second layer 205B and the channel layer 204. Therefore, compared with the case where the etching stopper layer 205 is composed of only an InGaP layer, the lattice mismatch between the channel layer 204 and the etching stopper layer 205 can be alleviated, and a decrease in the density of 2DEG due to the lattice mismatch can be suppressed. Further, compared with the case where the etching stopper layer 205 is composed of only an InP layer, a larger bandgap of the etching stopper layer 205 can be ensured, and leakage current can be suppressed.

[0043] Furthermore, since the etching of the cap layer 206 for forming the recess 211 can be stopped on the upper surface of the etching stopper layer 205, high-precision manufacturing is possible.

[0044] Note that the insulating layer 212 is not limited to an aluminum oxide layer. The insulating layer 212 may include an oxide layer, a nitride layer, or an oxynitride layer of aluminum, hafnium, titanium, or silicon, or any combination thereof. Further, the thickness of the insulating layer 212 may be, for example, 0.5 nm to 10 nm.

[0045] (Third Embodiment) Next, the third embodiment will be described. The third embodiment also relates to a compound semiconductor device including an InP-based HEMT. The third embodiment is mainly different from the second embodiment in that an oxide layer is provided between the cap layer 206 and the insulating layer 212. FIG. 14 is a cross-sectional view showing the compound semiconductor device according to the third embodiment.

[0046] As shown in FIG. 14, the compound semiconductor device 300 according to the third embodiment has an oxide layer 310 between an etching stopper layer 205 and an insulating layer 212 inside a recess 211. The oxide layer 310 contains gallium oxide (GaO x ). The main component of the oxide layer 310 may be gallium oxide, and the oxide layer 310 may be a gallium oxide layer. The thickness of the oxide layer 310 is, for example, 0.5 nm or more.

[0047] Next, a method for manufacturing the compound semiconductor device 300 according to the third embodiment will be described. FIGS. 15 to 17 are cross-sectional views showing the method for manufacturing the compound semiconductor device 300 according to the third embodiment.

[0048] First, as in the second embodiment, processing up to the formation of the recess 211 is performed (see FIG. 11). Next, a steam treatment is performed on the surface of the etching stopper layer 205 exposed from the recess 211. The temperature of the steam treatment is set to about 200°C to 300°C. Before the steam treatment, a natural oxide film containing indium gallium oxide exists on the surface of the etching stopper layer 205 exposed from the recess 211. When the steam treatment is performed, indium in the indium gallium oxide becomes indium oxide and volatilizes, the natural oxide film is removed, and gallium oxide remains. Therefore, an oxide layer 310 containing gallium oxide is formed by the steam treatment as shown in FIG. 15.

[0049] Thereafter, as shown in FIG. 16, an insulating layer 212 that covers the upper surface of the oxide layer 310 and the upper surface and side surfaces of the cap layer 206 is formed. Subsequently, as shown in FIG. 17, a gate electrode 13 is formed on the insulating layer 212 within the recess 211.

[0050] Then, a passivation film, wiring, etc. are formed as necessary to complete the compound semiconductor device 300.

[0051] The third embodiment can also obtain the same effects as the second embodiment.

[0052] In addition, when a natural oxide film containing indium gallium oxide exists on the surface exposed from the recess 211 of the etching stopper layer 205, due to the influence of interface levels contained in the natural oxide film, it is difficult to control the drain current with the gate voltage, and pinch-off failure may occur. On the other hand, in the third embodiment, since the natural oxide film containing indium gallium oxide is removed and the oxide layer 310 containing gallium oxide is formed, pinch-off failure can be suppressed.

[0053] Here, the pinch-off characteristics of the second and third embodiments will be described while comparing with a reference example. The reference example corresponds to a structure in which, except for the first layer 205A from the second embodiment, the etching stopper layer 205 is composed of only the second layer 205B of InGaP.

[0054] For the reference example, the second embodiment, and the third embodiment, the relationship between the drain voltage Vd and the drain current Id when the gate voltage is changed was measured. FIG. 18 is a diagram showing the relationship between the drain voltage Vd and the drain current Id in the reference example. FIG. 19 is a diagram showing the relationship between the drain voltage Vd and the drain current Id in the second embodiment. FIG. 20 is a diagram showing the relationship between the drain voltage Vd and the drain current Id in the third embodiment.

[0055] As shown in FIGS. 18 to 20, in the second and third embodiments, a larger drain current can be obtained than in the reference example. Further, according to the third embodiment, pinch-off failure is more suppressed than in the second embodiment.

[0056] (Fourth Embodiment) Next, the fourth embodiment will be described. The fourth embodiment relates to a discrete package of a HEMT. FIG. 21 is a diagram showing the discrete package according to the fourth embodiment.

[0057] In the fourth embodiment, as shown in FIG. 21, the back surface of the semiconductor device 1210 having the same structure as any of the first to third embodiments is fixed to the land (die pad) 1233 using a die attach agent 1234 such as solder. Also, a wire 1235d such as an Al wire is connected to the drain pad 1226d to which the drain electrode 12 is connected, and the other end of the wire 1235d is connected to the drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to the source pad 1226s to which the source electrode 11 is connected, and the other end of the wire 1235s is connected to the source lead 1232s independent of the land 1233. A wire 1235g such as an Al wire is connected to the gate pad 1226g to which the gate electrode 13 is connected, and the other end of the wire 1235g is connected to the gate lead 1232g independent of the land 1233. Then, a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude, and the land 1233 and the semiconductor device 1210 etc. are packaged with the mold resin 1231.

[0058] Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attach agent 1234 such as solder. Next, by bonding using the wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. Then, sealing is performed using the mold resin 1231 by the transfer molding method. Subsequently, the lead frame is separated.

[0059] (Fifth Embodiment) Next, the fifth embodiment will be described. The fifth embodiment relates to a PFC (Power Factor Correction) circuit including a HEMT. FIG. 22 is a connection diagram showing the PFC circuit according to the fifth embodiment.

[0060] The PFC circuit 1250 is provided with a switching element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switching element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switching element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switching element 1251. AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. A DC power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, a semiconductor device having the same structure as any of the first to third embodiments is used for the switching element 1251.

[0061] When manufacturing the PFC circuit 1250, for example, the switching element 1251 is connected to the diode 1252, the choke coil 1253, etc. using solder or the like.

[0062] (Sixth Embodiment) Next, the sixth embodiment will be described. The sixth embodiment relates to a power supply device including a HEMT, which is suitable for a server power supply. FIG. 23 is a wiring diagram showing the power supply device according to the sixth embodiment.

[0063] The power supply device is provided with a high-voltage primary side circuit 1261, a low-voltage secondary side circuit 1262, and a transformer 1263 disposed between the primary side circuit 1261 and the secondary side circuit 1262.

[0064] The primary circuit 1261 is provided with a PFC circuit 1250 according to the fifth embodiment and an inverter circuit, for example, a full-bridge inverter circuit 1260, connected between both terminals of the capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 is provided with a plurality (here, four) of switch elements 1264a, 1264b, 1264c, and 1264d.

[0065] The secondary circuit 1262 is provided with a plurality (here, three) of switch elements 1265a, 1265b, and 1265c.

[0066] In this embodiment, semiconductor devices having the same structure as any of the first to third embodiments are used for the switch element 1251 of the PFC circuit 1250 constituting the primary circuit 1261 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full-bridge inverter circuit 1260. On the other hand, ordinary MIS-type FETs (metal-insulator-semiconductor field-effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary circuit 1262.

[0067] (Seventh Embodiment) Next, the seventh embodiment will be described. The sixth embodiment relates to an amplifier provided with a HEMT. FIG. 24 is a connection diagram showing the amplifier according to the seventh embodiment.

[0068] The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

[0069] The digital predistortion circuit 1271 compensates for the non-linear distortion of the input signal. The mixer 1272a mixes the input signal with the non-linear distortion compensated and the AC signal. The power amplifier 1273 includes a semiconductor device having the same structure as any of the first to third embodiments, and amplifies the input signal mixed with the AC signal. In this embodiment, for example, by switching the switch, the output signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-output amplifier. The high-frequency amplifier can be used, for example, in a transceiver for a mobile phone base station, a radar device, and a microwave generator.

[0070] (Eighth Embodiment) Next, the eighth embodiment will be described. The eighth embodiment relates to a receiving monolithic microwave integrated circuit (MMIC). FIG. 25 is a diagram showing the receiving MMIC according to the eighth embodiment.

[0071] The receiving MMIC 1300 according to the eighth embodiment includes, as shown in FIG. 25, a low noise amplifier (LNA) 1301, a detector 1302, and an inductor 1303. The LNA 1301, the detector 1302, and the inductor 1303 are integrated on one InP substrate. The LNA 1301 includes an InP-based HEMT (compound semiconductor device) according to any of the first to third embodiments.

[0072] In the eighth embodiment, for example, the source electrode 11 of the InP-based HEMT included in the LNA 1301 and the cathode electrode of the detector 1302 are grounded, and the drain electrode 12 of the InP-based HEMT and the anode electrode of the detector 1302 are connected to one end of the inductor 1303. Then, an antenna 1305 for receiving radio waves in the millimeter wave band or the terahertz band is connected to the gate electrode 13 of the InP-based HEMT, and the detection signal V det is output from the other end of the inductor 1303. The detection signal V detFor example, a potential difference ΔV of several hundred mV is output.

[0073] According to the receiving MMIC 1304 according to the eighth embodiment, since the InP-based HEMT (compound semiconductor device) according to any one of the first to third embodiments is included, excellent characteristics can be obtained.

[0074] Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

[0075] Hereinafter, aspects of the present disclosure will be collectively described as appendices.

[0076] (Appendix 1) A carrier supply layer, A channel layer provided on the carrier supply layer and containing InGaAs, An etching stopper layer provided on the channel layer, having, The etching stopper layer is provided on the channel layer, In x1 Ga 1-x1 P (0 < x1 ≤ 1) containing the first layer, A second layer provided on the first layer and containing In x2 Ga 1-x2 P (0 ≤ x2 < 1), having, A compound semiconductor device characterized in that the value of x1 is larger than the value of x2. (Appendix 2) The compound semiconductor device according to Appendix 1, characterized in that the difference between the lattice constant of the first layer and the lattice constant of the channel layer is smaller than the difference between the lattice constant of the second layer and the lattice constant of the channel layer. (Appendix 3) having a cap layer provided on the etching stopper layer, a recess reaching the etching stopper layer is formed in the cap layer, The compound semiconductor device according to appended claim 1 or 2, characterized in that an oxide layer containing gallium oxide is provided on the etching stopper layer inside the recess. (Appended claim 4) The compound semiconductor device according to appended claim 3, characterized in that the thickness of the oxide layer is 0.5 nm or more. (Appended claim 5) The compound semiconductor device according to appended claim 3 or 4, characterized in that a gate electrode is provided on the oxide layer. (Appended claim 6) The compound semiconductor device according to appended claim 5, characterized in that an insulating layer is provided between the oxide layer and the gate electrode. (Appended claim 7) The compound semiconductor device according to appended claim 6, characterized in that the insulating layer includes an oxide layer, a nitride layer or an oxynitride layer of aluminum, hafnium, titanium or silicon, or any combination thereof. (Appended claim 8) The compound semiconductor device according to appended claim 6 or 7, characterized in that the thickness of the insulating layer is 0.5 nm to 10 nm. (Appended claim 9) The compound semiconductor device according to any one of appended claims 3 to 8, characterized in that source electrodes and drain electrodes are provided on the cap layer with the recess therebetween. (Appended claim 10) An amplifier characterized by having the compound semiconductor device according to any one of appended claims 1 to 9. (Appended claim 11) A power supply device characterized by having the compound semiconductor device according to any one of appended claims 1 to 9. (Appended claim 12) A step of forming a channel layer containing InGaAs on a carrier supply layer, A step of forming an etching stopper layer on the channel layer, and having The step of forming the etching stopper layer is a step of forming a first layer containing In x1 Ga 1-x1 P (0 <x1 ≦ 1) on the channel layer. In on top of the first layer x2 Ga 1-x2 A step of forming a second layer containing P(0 ≦ x2 < 1), having A method for manufacturing a compound semiconductor device, characterized in that the value of x1 is larger than the value of x2. (Appendix 13) The method for manufacturing a compound semiconductor device according to Appendix 12, characterized in that the difference in lattice constant between the first layer and the channel layer is smaller than the difference in lattice constant between the second layer and the channel layer. (Appendix 14) A step of forming a cap layer on the etching stopper layer, A step of forming a recess reaching the etching stopper layer in the cap layer, A method for manufacturing a compound semiconductor device according to Appendix 12 or 13, characterized by having a step of performing a steam treatment on the surface of the etching stopper layer exposed from the recess at a temperature of 250°C to 300°C to form an oxide layer containing gallium oxide on the second layer inside the recess. (Appendix 15) The method for manufacturing a compound semiconductor device according to Appendix 14, characterized in that the thickness of the oxide layer is 0.5 nm or more. (Appendix 16) A method for manufacturing a compound semiconductor device according to Appendix 14 or 15, characterized by having a step of forming a gate electrode on the oxide layer. (Appendix 17) A method for manufacturing a compound semiconductor device according to Appendix 16, characterized by having a step of forming an insulating layer between the oxide layer and the gate electrode. (Appendix 18) The method for manufacturing a compound semiconductor device according to Appendix 17, characterized in that the insulating layer includes an oxide layer, a nitride layer, or an oxynitride layer of aluminum, hafnium, titanium, or silicon, or any combination thereof. (Appendix 19) The method for manufacturing a compound semiconductor device according to Appendix 17 or 18, characterized in that the thickness of the insulating layer is 0.5 nm to 10 nm. (Supplementary Note 20) A method for manufacturing a compound semiconductor device according to any one of claims 14 to 19, comprising a step of forming a source electrode and a drain electrode on the cap layer with the recess therebetween.

Explanation of Reference Numerals

[0077] 100, 200, 300: Compound semiconductor device 103, 203: Carrier supply layer 104, 204: Channel layer 105, 205: Etching stopper layer 105A, 205A: First layer 105B, 205B: Second layer 106, 206: Cap layer 111, 211: Recess 112, 212: Insulating layer 310: Oxide layer

Claims

1. A carrier supply layer, a channel layer provided on the carrier supply layer and containing InGaAs, an etching stopper layer provided on the channel layer, having, the etching stopper layer, Provided on the channel layer, In ｘ１ Ga １－ｘ１ A first layer containing P (0 < x1 ≤ 1), and Provided on the first layer, In ｘ２ Ga １－ｘ２ A second layer containing P(0 ≦ x2 < 1), and having, a compound semiconductor device characterized in that the value of x1 is greater than the value of x2.

2. The compound semiconductor device according to claim 1, characterized in that the difference in lattice constant between the lattice constant of the first layer and the channel layer is smaller than the difference in lattice constant between the lattice constant of the second layer and the channel layer.

3. having a cap layer provided on the etching stopper layer, a recess reaching the etching stopper layer is formed in the cap layer, The compound semiconductor device according to claim 1 or 2, characterized in that an oxide layer containing gallium oxide is provided on the etching stopper layer inside the recess.

4. The compound semiconductor device according to claim 3, characterized in that it has a gate electrode provided on the oxide layer.

5. The compound semiconductor device according to claim 4, characterized in that it has an insulating layer provided between the oxide layer and the gate electrode.

6. The compound semiconductor device according to any one of claims 3 to 5, characterized in that it has a source electrode and a drain electrode provided on the cap layer with the recess therebetween.

7. A step of forming a channel layer containing InGaAs on a carrier supply layer, a step of forming an etching stopper layer on the channel layer, having, the step of forming the etching stopper layer, On the channel layer, In ｘ１ Ga １－ｘ１ forming a first layer containing P (0 < x1 ≤ 1); On top of the first layer, In ｘ２ Ga １－ｘ２ forming a second layer containing P (0 ≦ x2 < 1); having, A method for manufacturing a compound semiconductor device characterized in that the value of x1 is greater than the value of x2.

8. The method for manufacturing a compound semiconductor device according to claim 7, characterized in that the difference in lattice constant between the lattice constant of the first layer and the channel layer is smaller than the difference in lattice constant between the lattice constant of the second layer and the channel layer.

9. A step of forming a cap layer on the etching stopper layer, a step of forming a recess reaching the etching stopper layer in the cap layer, The method for manufacturing a compound semiconductor device according to claim 7 or 8, characterized by having a step of performing a steam treatment on the surface of the etching stopper layer exposed from the recess at a temperature of 200°C to 300°C to form an oxide layer containing gallium oxide on the second layer inside the recess.

10. The method for manufacturing a compound semiconductor device according to claim 9, comprising a step of forming a gate electrode on the oxide layer.

11. A step of forming an insulating layer on the oxide layer, A step of forming a gate electrode on the insulating layer, The method for manufacturing a compound semiconductor device according to claim 9, characterized by comprising these steps.

12. The method for manufacturing a compound semiconductor device according to any one of claims 9 to 11, comprising a step of forming a source electrode and a drain electrode on the cap layer with the recess therebetween.

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