Vapor deposition mask and method for manufacturing an electronic device

Abstract

Provided are a vapor deposition mask with which it is possible to form a vapor deposition film having exceptional pattern dimensions, and a method for manufacturing an electronic device using the vapor deposition mask. A vapor deposition mask according to the present invention comprises a semiconductor substrate having a first surface and a second surface on the side opposite from the first surface, a plurality of openings penetrating between the first surface and the second surface being formed in the semiconductor substrate, wherein the vapor deposition mask is characterized in that the side wall surfaces of the openings are formed in a relief shape, the opening width is less than 30 μm, and the relief ratio (average value of relief height difference / opening width) is 0.0001-0.0420.

Description

Technical Field

[0001] The present invention relates to a vapor deposition mask and a method for manufacturing an electronic device.

Background Art

[0002] For example, a vapor deposition mask used for coating three colors of RGB in the production of an organic EL display is known. Patent Documents 1 and 2 describe that the side wall surfaces of the openings of the vapor deposition mask have an uneven shape. Also, the surface roughness of the unevenness is defined.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Due to the uneven shape of the side wall surfaces of the openings, a problem occurs in that the vapor deposition material accumulates on the side wall surfaces, deteriorating the pattern dimensions of the vapor deposition film.

[0005] An object of the present invention is to provide a vapor deposition mask capable of forming a vapor deposition film having excellent pattern dimensions and a method for manufacturing an electronic device using the vapor deposition mask.

Means for Solving the Problems

[0006] ThisThe vapor deposition mask of the embodiment has a first surface and a second surface opposite to the first surface, and is a vapor deposition mask in which a plurality of openings penetrating between the first surface and the second surface are formed. The side wall surface of the opening is formed in an uneven shape, the opening width is 30 μm or less, and the uneven ratio (average value of the uneven height difference / opening width) is 0.0001 or more and 0.0420 or less. The vapor deposition mask is composed of an SOI substrate, and a SiN layer is formed on the surface side where the opening is formed, or the back surface side, or both the surface side and the back surface side.

Advantages of the Invention

[0007] According to the present invention, by controlling the size of the unevenness formed on the side wall surface of the opening of the vapor deposition mask by the ratio to the opening width, a vapor deposition film having excellent pattern dimensions can be stably formed. In addition, the cleaning frequency of the vapor deposition mask can be reduced, and the quality control of the vapor deposition mask can be easily performed. Further, the occurrence of clogging of the opening can be reduced, and the long life of the vapor deposition mask can be achieved.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and dimensions, ratios, etc. of each drawing are not necessarily the same as those in reality. Also, even when the same part is represented between the drawings, the dimensional relationships and ratios may be represented differently from each other. In particular, the embodiments shown below are examples of structures for embodying the technical idea of the present invention, and do not specify the technical idea of the present invention. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant descriptions are omitted. Also, the lower limit value and the upper limit value of the numerical range include the error range.

[0010] <Background Leading to the Present Invention> Virtual reality / augmented reality (VR / AR) technology and the VR / AR-related market are growing rapidly. And with the progress of the growth, miniaturization of display panels suitable for the VR / AR field, high pixelization of the screen resolution (PPI: Pixels Per Inch), high-speed response, and high color gamut are progressing. In advancing the technology, the spread of silicon-based organic light-emitting diode (OLED) microdisplay panels has become remarkable.

[0011] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. In order to effectively prepare for AR and VR as high-value-added industries, for example, it is expected to implement displays with ultra-high resolutions of 1000 ppi or more. In response to this, the need for evaporation masks for RGB painting used in the manufacturing process of OLED microdisplays is increasing.

[0012] The evaporation mask has a plurality of openings corresponding to the evaporation film, and the opening accuracy of the evaporation mask is important in order to improve the pattern dimensions of the evaporation film.

[0013] The evaporation mask is disposed between the substrate to be evaporated and the evaporation source, and the evaporation material reaches the surface of the substrate to be evaporated from the evaporation source through the openings of the evaporation mask. At this time, if the evaporation material accumulates on the side wall surface of the opening, the opening width becomes narrower than the actual width, making it difficult to form an evaporation film with excellent pattern dimensions.

[0014] In Patent Document 1, the problem is that the deposition of the evaporation material on the side wall surface becomes foreign matter and falls off, resulting in pixel defects, and the purpose is to form an opening for stabilizing the deposition of the evaporation material. In Patent Document 1, for example, the opening width is defined to be 100 μm (0.1 mm) or more.

[0015] On the other hand, as the opening width is made smaller (specifically, 30 μm or less), assuming that, for example, the magnitude of the unevenness on the side wall surface of the opening is constant, the smaller the opening width, the greater the influence of the deposition of the evaporation material, and the pattern dimensions of the evaporation film decrease. From this, it was not possible to obtain excellent pattern dimensions only by adjusting the magnitude of the unevenness, and it was necessary to obtain a range in which an evaporation film with excellent pattern dimensions could be formed in consideration of the relationship with the opening width.

[0016] Therefore, as a result of intensive research by the inventors, they focused on the ratio of the height difference of the unevenness on the side wall surface to the opening width, and developed an evaporation mask capable of increasing the pattern dimensions of the evaporation film.

[0017] <Overview of the vapor deposition mask 1 in this embodiment> FIG. 1 is a cross-sectional view of the vapor deposition mask 1 in this embodiment. FIG. 2 is an enlarged cross-sectional view showing a part of the vapor deposition mask shown in FIG. 1. FIG. 3 is a partially enlarged cross-sectional view showing an enlarged part of the opening of the vapor deposition mask of this embodiment. FIG. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the vapor deposition mask of this embodiment.

[0018] The vapor deposition mask 1 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably composed of a SOI (Silicon on Insulator) substrate 9.

[0019] The semiconductor layer 2 is preferably a single crystal silicon layer, and is also called an active layer, a membrane, or the like. The thickness of the semiconductor layer 2 is not limited, but is about 1 μm to 300 μm.

[0020] As shown in FIG. 1, the vapor deposition mask 1 has a plurality of opening regions 15 and a peripheral region 16 located around the opening regions 15. In the peripheral region 16, the semiconductor layer 2, the insulating layer 3, and the support substrate 4 are laminated. On the other hand, only the semiconductor layer 2 is disposed in the opening region 15, that is, the insulating layer 3 and the support substrate 4 are removed, and a plurality of minute openings 5 are formed in each opening region 15.

[0021] FIG. 2 shows an enlarged view of the vicinity of one opening region 15 shown in FIG. 1. As shown in FIG. 2, the semiconductor layer 2 includes a first surface 2a and a second surface 2b facing each other in the thickness direction. The insulating layer 3 and the support substrate 4 are provided on the second surface 2b side. As shown in FIG. 4, the first surface 2a is a surface facing the substrate to be vapor-deposited 10, and the second surface 2b is a back surface facing the vapor deposition source 11.

[0022] As shown in FIG. 2, a plurality of openings 5 penetrating between the first surface 2a and the second surface 2b are formed in the semiconductor layer 2. As shown in FIG. 2, the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a. Therefore, the side wall surface 6 of the opening 5 is inclined. Also, in FIG. 2, the opening width W1 is defined as the width dimension in the plane direction along the first surface 2a. Thus, in FIG. 2, the opening width W1 is illustrated at the location where the width dimension is the narrowest. In FIG. 2, although the reference signs of the opening width W1 and the side wall surface 6 are shown only for one opening 5, they are similarly applied to the other openings 5. Note that the shape of the side wall surface 6 of the opening 5 will be described in detail later.

[0023] The planar pattern of the opening 5 (the shape seen from directly above the semiconductor layer 2 toward the first surface 2a) is not to be limited, but examples thereof include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. Also, all the openings 5 may have the same planar pattern, or some of them may be different. Also, the openings 5 may be regularly arranged, or may have an irregular arrangement, or a combination of a regular arrangement and an irregular arrangement. Although the interval between adjacent openings 5 is not limited, when viewed from the first surface 2a side, the interval is about 1 μm to 20 μm.

[0024] The outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer. Although the diameter (in the case of a rectangle, the length of one side) is not limited, it is preferably about 100 mm to 500 mm. Thus, even when the diameter of the semiconductor layer 2 increases, each opening 5 can be formed uniformly.

[0025] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer, and specifically, is preferably a silicon oxide (SiO2) layer. The insulating layer 3 is also called a BOX layer (Buried Oxide Layer). Although the thickness of the insulating layer 3 is not limited, it is, for example, about 100 nm to 20 μm.

[0026] The insulating layer 3 shown in Fig. 2 is not provided in the opening region facing the opening 5 of the semiconductor layer 2 and is removed, and remains only in the peripheral region of the opening region on the second surface 2b of the semiconductor layer 2. The insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and having the insulating layer 3 enables stable processing.

[0027] The support substrate 4 shown in Fig. 2 is a semiconductor substrate, for example, a silicon substrate. Although the thickness of the support substrate 4 is not limited, it is, for example, about 100 μm to 1000 μm.

[0028] As shown in Fig. 1, the support substrate 4 can function as a columnar portion 16a and an outer peripheral frame 16b that surround the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be maintained in a stretched state by the support substrate 4, eliminating the need for a stretching process, and the vapor deposition mask 1 of the present embodiment can be brought into close contact with the substrate to be vapor-deposited 10 using an electrostatic chuck that utilizes electrostatic force. As shown in Fig. 1, the columnar portion 16a is located inside the outer peripheral frame 16b, and they all have the same length (height). However, for example, the height of the columnar portion 16a may be made lower than that of the outer peripheral frame. However, keeping the heights the same can maintain greater strength.

[0029] Also, although not shown in Figs. 1 and 2, alignment marks for alignment can be formed in the outer peripheral region on the first surface 2a side of the semiconductor layer 2. The alignment marks can be formed, for example, in a concave shape on the first surface 2a and can be formed to a depth that reaches the insulating layer 3.

[0030] <Detailed description of the opening 5 of the vapor deposition mask 1 in the present embodiment> Fig. 3 is a partial enlarged cross-sectional view showing an enlarged view of one opening 5 formed in the vapor deposition mask 1, extracting the middle portion in the height direction (thickness direction of the semiconductor layer 2) of the opening 5. Note that the reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side of the drawing, but the cross-sectional shape is symmetric about the vertical axis, and the side wall surface 6 on the right side of the drawing has the same configuration.

[0031] As shown in FIG. 3, the side wall surface 6 of the opening 5 is formed in an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding in the inner direction of the opening 5 and concave portions 8 located between the convex portions 7 are continuously and repeatedly formed along the height direction of the opening 5. In the present embodiment, the uneven height difference and the like of the opening 5 are calculated as follows.

[0032] [Calculation method of uneven height difference] First, an SEM (scanning electron microscope) image of the cross section of the opening 5 was obtained. Although the SEM is not limited, for example, Regulus 8220 manufactured by Hitachi High-Tech was used.

[0033] At an intermediate position located exactly at the center of the thickness between the first surface 2a and the second surface 2b of the opening 5, taking adjacent unevenness as one pitch, the length of 5 pitches was measured with an SEM. Note that it is not limited to 5 pitches, but if the number of pitches is too small, the parameter noise will increase, and if the number of pitches is too large, depending on the thickness, it may not be possible to secure that number of pitches, and also, it takes time to calculate the parameters and becomes complicated. Therefore, it is preferable to set it to about several pitches to within 10 pitches. In the present embodiment, basically, it is measured at 5 pitches, but if it is difficult, the number of pitches can be appropriately set and changed.

[0034] Also, instead of the above-mentioned pitch concept, at the center of the thickness by the SEM image, for example, 5 locations where the height can be confirmed may be measured. In this case, a location with a height can be regarded as a convex portion, and the space between them can be regarded as a concave portion.

[0035] In FIG. 3, only two pitches will be illustrated and described. In FIG. 3, reference numerals 7a and 7b are given to distinguish the two convex portions 7. When viewed from each of the convex portions 7a and 7b, a recess 8 located on the first surface 2a side (the upper side in the figure) is combined with a half pitch. Also, reference numerals 8a and 8b are given to distinguish the two recesses 8. Let the convex portion 7a and the recess 8a be the first half pitch P1, and the convex portion 7b and the recess 8b be the second half pitch P2. Note that the pitch refers to the distance between convex portions or the distance between recesses, and half of that distance is defined as the half pitch.

[0036] As shown in FIG. 3, an approximate straight line T1 connecting the lowest positions (bottom A) of each of the recesses 8a and 8b within the measurement range was drawn. The bottom A is, for example, the position farthest from the center line O in the width direction of the opening 5. The approximate straight line T1 can be obtained by the least squares method. In the case where irregular recesses 8 are formed within the measurement range (for example, when the bottom A is extremely lower than the top B), the approximate straight line T1 can be drawn excluding that recess 8.

[0037] Next, as shown in FIG. 3, at the first half pitch P1, the highest position (top) B of the convex portion 7a was obtained. The top B is the position closest to the center line O in the width direction of the opening 5. Then, as shown in FIG. 3, a straight line S1 orthogonal to the approximate straight line T1 was drawn so as to intersect the top B. The length of the straight line S1 from the approximate straight line T1 to the top B was obtained. The length of this straight line S1 was defined as the unevenness height difference D1 of the first half pitch P1.

[0038] For the second half pitch P2 and other half pitches, the unevenness height difference can be obtained in the same manner as that obtained for the first half pitch P1. That is, a straight line orthogonal to the approximate straight line T1 was drawn to obtain the straight line length to the top B of each convex portion, and this straight line length was defined as the unevenness height difference of each pitch. Incidentally, in FIG. 3, the unevenness height difference D2 of the second half pitch P2 is shown.

[0039] As described above, a plurality of uneven height differences can be obtained. When measuring for five pitches, five uneven height differences Dn (n = 1 to 5) are calculated. Then, the average value Ave of these uneven height differences Dn is obtained.

[0040] Note that there may be fine unevenness formed on the surfaces of the respective concave portions 8a and 8b (or it can also be said to be the bottom portions of the convex portions 7a and 7b), but these fine unevenness can be ignored. For example, fine unevenness with a wavelength in the order of several nm or smaller can be cut off to create a wavy curve and obtain the uneven height difference.

[0041] [Calculation method of opening width W1] As shown in FIG. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. Therefore, as shown in FIG. 2, the opening width W1 is obtained as the dimension in the surface direction along the first surface 2a where it is the narrowest. Note that the opening width W1 can be obtained from a SEM image obtained using an eCD-2 manufactured by KLA-Tencor.

[0042] [Calculation method of uneven ratio R] The uneven ratio R is obtained based on the average value Ave of the uneven height differences Dn measured above and the opening width W1. That is, the uneven ratio R is obtained as (average value Ave of the uneven height differences Dn / opening width W1). A small uneven ratio R means that if the average value Ave of the uneven height differences Dn is constant, the opening width W1 is large, or if the opening width W1 is constant, the average value Ave of the uneven height differences Dn is small. On the other hand, a large uneven ratio R means that if the average value Ave of the uneven height differences Dn is constant, the opening width W1 is small, or if the opening width W1 is constant, the average value Ave of the uneven height differences Dn is large. Thus, in this embodiment, by adjusting one or both of the average value Ave of the uneven height differences Dn and the opening width W1, it is possible to control so that the uneven ratio R falls within a predetermined range.

[0043] [Calculation method of taper angle θ1 of opening 5 and inclination angle θ4 of side wall surface 6] In this embodiment, the taper angle θ1 of the opening 5 is obtained as follows. That is, as shown in FIG. 2, the end of the opening width W1 in the plane direction along the first surface 2a and the end of the opening width W2 in the plane direction along the second surface 2b are connected by a straight line, and the inclination angle between this straight line and the first surface 2a can be set as the taper angle θ1 of the opening 5. The taper angle θ1 was obtained by length measurement from an SEM image obtained using Regulus 8220 manufactured by Hitachi High-Tech.

[0044] Also, as shown in FIG. 3, the inclination angle θ4 of the side wall surface 6 can be obtained from the inclination angle between the approximate straight line T1 shown in FIG. 3 and the first surface 2a.

[0045] The taper angle θ1 and the inclination angle θ4 are the same or approximate. However, for example, depending on the state of the uneven shape of the side wall surface 6 and the way of taking the pitch, the inclination of the approximate straight line T1 may change, and the taper angle θ1 and the inclination angle θ4 may be separated. Therefore, the inclination of the side wall surface 6 was determined by measuring the taper angle θ1 of the opening 5.

[0046] [Calculation method of uneven angles θ2 and θ3] As shown in FIG. 3, the uneven angle θ2 can be obtained as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest (the farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8a located on the substrate 10 side (the upper side in the figure) as viewed from the convex portion 7a and the approximate straight line T1. Also, as shown in FIG. 3, the uneven angle θ3 can be obtained as the angle between a straight line L2 connecting the top B of the convex portion 7a and the lowest (the farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8b located on the evaporation source 11 side (the lower side in the figure, see FIG. 4) as viewed from the convex portion 7a and the approximate straight line T1.

[0047] The fact that the uneven angles θ2 and θ3 are small means that the height of the convex portion 7 is low (the depth of the concave portion 8 is shallow) and the undulation of the side wall surface 6 is small.

[0048] [Regarding the characteristic configuration of the opening parameters in this embodiment] The evaporation mask 1 in this embodiment is (1) The opening width W1 is 30 μm or less. (2) The concavo-convex ratio R (average value Ave of the concavo-convex height difference Dn / opening width W1) is 0.0001 or more and 0.0420 or less, which is characterized.

[0049] In the present embodiment, the opening width W1 is in the range of 30 μm or less. The needs required for the vapor deposition mask 1 provided with the semiconductor layer 2 can be ensured. In particular, as a vapor deposition mask for RGB painting used in the manufacturing process of an OLED microdisplay, it is necessary to further reduce the opening width W1. In the present embodiment, the opening width W1 is preferably 20 μm or less, and more preferably 10 μm or less. Also, the opening width W1 is preferably 1 μm or more, more preferably 2 μm or more, and still more preferably 3 μm or more.

[0050] Alternatively, the opening width W1 is preferably 1 μm or more and 30 μm or less, more preferably 2 μm or more and 20 μm or less, and still more preferably 3 μm or more and 10 μm or less.

[0051] The opening width W1 is preferably set as the width dimension in the plane direction along the first surface 2a facing the substrate 10 to be vapor-deposited.

[0052] In the present embodiment, the concavo-convex ratio R is 0.0001 or more and 0.0420 or less. By adjusting the concavo-convex ratio R within this range, it becomes possible to make the pattern width of the vapor-deposited film formed using the vapor deposition mask 1 80% or more of the opening width W1 of the vapor deposition mask 1.

[0053] FIG. 4 is a cross-sectional view showing the vapor deposition mask 1 of the present embodiment disposed between the substrate 10 to be vapor-deposited and the vapor deposition source 11, and shows one step of a method for manufacturing an electronic device.

[0054] As shown in Fig. 4, the deposition material (deposition particles) 12 from the evaporation source 11 passes through the opening 5 of the evaporation mask 1 and reaches the surface 10a of the substrate 10 to be deposited, and the deposited film 13 is formed. When the pattern width W3 of the deposited film 13 is measured and the ratio to the opening width W1 is calculated, if the pattern width ratio ((pattern width W3 / opening width W1)×100 (%)) is the unevenness ratio R of 80% or more, it is regarded as this embodiment, and the unevenness ratio R of less than 80% is regarded as a comparative example.

[0055] The lower limit value 0.0001 of the unevenness ratio R has almost reached the manufacturing limit, so it is set to 0.0001 or more. Also, when the unevenness ratio R exceeds the upper limit value 0.0420, it is known that the unevenness ratio R with respect to the opening width W1 increases exponentially. In particular, when the unevenness ratio R exceeds 0.0425, the exponential increase becomes remarkable, and the influence during evaporation becomes extremely large. That is, for example, even if the average value Ave of the unevenness height difference Dn is the same size, in the range where the unevenness ratio R exceeds 0.0420, just a slight deviation in the direction of decreasing the opening width W1 will cause the unevenness ratio R to fluctuate in the direction of becoming very large, and the pattern width ratio of the deposited film 13 will deteriorate. Therefore, the unevenness ratio R is set to 0.0420 or less so that a pattern width ratio of 80% or more can be stably obtained. Here, the reason for setting the required pattern width ratio to 80% or more is that if it is less than 80%, the deviation from the desired pattern width W3 of the deposited film 13 is too large, leading to a decrease in yield, and it also leads to a decrease in the area to be lit at the design position such as coordinate position accuracy, resulting in a decrease in the luminance of the light-emitting element itself, or it is a numerical value required for product quality assurance. To increase the production efficiency, the pattern width ratio is set to 85% or more, preferably 90% or more, more preferably 95% or more.

[0056] Also, in this embodiment, it is preferable that the unevenness ratio R is 0.0380 or less, more preferably 0.0350 or less, and even more preferably 0.0300 or less.

[0057] In this embodiment, the lower limit value of the unevenness ratio R can be set to about 0.0003 or 0.0005. Alternatively, the unevenness ratio R can be set to 0.0015 or more, or 0.0020 or more.

[0058] Also, the average value Ave of the unevenness height difference Dn is preferably 0.200 μm or less, more preferably 0.180 μm or less, still more preferably 0.175 or less, and most preferably 0.170 μm or less. Also, the average value Ave of the unevenness height difference Dn is preferably 0.003 μm or more, more preferably 0.005 μm or more, and still more preferably 0.008 μm or more. By adjusting the average value Ave of the unevenness height difference Dn within the above range, it is easy to appropriately control the unevenness ratio R within the range of 0.0001 or more and 0.0420 or less, and further within the range of the preferable unevenness ratio R. Also, it has effects such as reducing the deposition of the deposition material 12 on the side wall surface 6 of the opening 5 and reducing the number of cleaning times of the deposition mask 1.

[0059] For example, when the opening width is 5 μm or less, the average value Ave of the unevenness height difference Dn is preferably about 0.003 μm or more and 0.165 μm or less, more preferably 0.160 μm or less, still more preferably 0.155 μm or less, even more preferably 0.150 μm or less, even more preferably 0.130 μm or less, and most preferably 0.100 μm or less.

[0060] Also, for example, when the opening width is greater than 5 μm and about 20 μm or less, the average value Ave of the unevenness height difference Dn is preferably about 0.003 μm or more and 0.200 μm or less, more preferably about 0.003 μm or more and 0.180 μm or less, and still more preferably about 0.003 μm or more and 0.175 μm or less.

[0061] Also, the maximum value of the uneven height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, still more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.300 μm or less. The smaller the opening width W1, the smaller the maximum value of the uneven height difference Dn is preferably. For example, when the opening width W1 is 5 μm or less, the maximum value of the uneven height difference Dn is preferably 0.300 μm or less, more preferably 0.250 μm or less, still more preferably 0.200 μm or less, and most preferably 0.100 μm or less. Note that the lower limit value of the maximum value of the uneven height difference Dn is not limited, but the maximum value of the uneven height difference Dn is about 0.005 μm or more.

[0062] Also, the uneven angles θ2 and θ3 described in FIG. 3 are in the range of about 0.5° to 50°, preferably 45° or less, more preferably 40° or less, still more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less. By reducing the uneven angles θ2 and θ3, the protruding height of the convex portion 7 can be reduced, or the interval between adjacent convex portions 7 can be widened (the range of the concave portion 8 can be widened), and the deposition of the vapor deposition material 12 on the side surface of the convex portion 7 can be suppressed. Note that the most preferable range of the uneven angles θ2 and θ3 is about 0.5° to 2°. Also, the uneven angle θ3 shown in FIG. 3 is preferably smaller than the uneven angle θ2. Thereby, the deposition of the vapor deposition material 12 on the side wall surface 6 can be suppressed.

[0063] In addition, in the present embodiment, the opening width of the opening 5 gradually narrows from the second surface 2b side toward the first surface 2a side. That is, as shown in FIG. 4, in the vapor deposition mask 1, the opening width W1 on the side facing the substrate 10 to be vapor-deposited is narrow, and the side wall surface 6 of the opening 5 is formed as an inclined surface. This makes it easier to stably form a vapor-deposited film 13 having a desired pattern width W3. Further, when the vapor-deposited material 12 deposited on the side wall surface 6 peels off from the side wall surface 6, it can be made less likely to fly toward the substrate 10 to be vapor-deposited. Also, from the perspective of manufacturing, by inclining the side wall surface 6 of the opening 5, it becomes easier to form the side wall surface 6. Although not limited, the taper angle θ1 of the opening 5 is preferably 60° or more, more preferably 70° or more. Also, the taper angle θ1 is preferably less than 90°, more preferably 85° or less, and even more preferably 80° or less. Therefore, the taper angle θ1 is most preferably 70° or more and 80° or less. When the taper angle θ1 is less than 60°, the amount of the vapor-deposited material 12 deposited on the side wall surface 6 increases, and the pattern width ratio of the vapor-deposited film is likely to be less than 80%. Also, although the taper angle θ1 can be made up to about 90°, that is, the side wall surface 6 can be formed substantially vertically, in that case, it is considered that the influence of the uneven height difference Dn of the side wall surface 6 during vapor deposition becomes large. In particular, the smaller the opening width W1, the more necessary it is to minimize the average value Ave and the maximum value of the uneven height difference Dn. There is also a relationship with the thickness of the semiconductor layer 2. That is, as the thickness of the semiconductor layer 2 increases, it becomes difficult to form the side wall surface 6 as a vertical surface. Therefore, in the present embodiment, the taper angle θ1 is controlled to be less than 90°, preferably 85° or less, and more preferably 80° or less.

[0064] <Regarding the manufacturing method of the vapor deposition mask 1 in the present embodiment> FIG. 5 is a process diagram showing a first manufacturing method of the vapor deposition mask 1 of the present embodiment. Here, the vapor deposition mask 1 in the manufacturing process shown in FIG. 5 and FIG. 6 described later shows only the vicinity of a certain opening region 15, similar to FIG. 2. Actually, a plurality of opening regions 15 shown in FIG. 1 are simultaneously formed. In FIG. 5(a), an SOI substrate 9 is prepared. The SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. Since the materials and thicknesses of each layer were described in FIG. 1, please refer to that.

[0065] Note that in the case of the SOI substrate 9, although the diameter is not limited, in the present embodiment, it can correspond up to about 500 mm.

[0066] In FIG. 5(b), a mask layer 14 is pattern-formed on the surface of the semiconductor layer 2. The mask layer 14 is preferably a resist and can be pattern-formed by exposure and development. A plurality of through-holes 14a are formed in the mask layer 14. This through-hole 14a is an opening pattern for forming the opening 5 in the semiconductor layer 2, and the width dimension W4 of the through-hole 14a is formed with a small dimension of 30 μm or less.

[0067] Next, in FIG. 5(c), the semiconductor layer 2 exposed from the through-hole 14a of the mask layer 14 is dry-etched. In the present embodiment, the semiconductor layer 2 is deep-etched. For example, in a so-called Bosch process, a method of repeating etching of Si with SF6 and generation of a polymer film with C4F8 to deeply dig silicon and alternately advancing sidewall protection and bottom etching is preferably used. By the Bosch process, the sidewall surface 6 of the opening 5 formed in the semiconductor layer 2 has an uneven shape.

[0068] At this time, as shown in FIG. 5(c), the composition, flow rate, internal pressure of the etching chamber, power of the high-frequency power supply, etc. of the etching gas are appropriately adjusted so as to form an inverse taper surface. Further, by these adjustments, the inclination angle of the inverse taper surface (taper angle θ1 of the opening 5) and the control of the uneven height difference Dn can be performed.

[0069] For example, in a dry etching apparatus, a Bosch process was carried out using SF6 gas and C4F8 gas alternately. By applying a bias to the substrate to be etched using the same gas as in the mode of performing isotropic dry etching using fluorine radicals using SF6 gas, anisotropic dry etching using fluorine ions was carried out. The processing conditions were as follows: SF6 gas was 0 to 500 sccm, C4F8 gas was 0 to 300 sccm, Platen LF was 0 to 1500 W, Coil RF was 300 to 1500 W, and the chamber pressure was 1 to 10 Pa, and various conditions were adjusted.

[0070] By the above-described Bosch process, a plurality of openings 5 can be formed with deep trenches in the semiconductor layer 2, and at this time, the taper angle θ1 and the uneven height difference of the opening 5 can be appropriately adjusted.

[0071] In the present embodiment, in order to reduce the uneven height difference Dn, in addition to adjusting the conditions in the above-described etching process, for example, after performing deep trench etching of silicon, a smoothing process (a process for reducing the uneven height difference) can be achieved by performing laser hydrogen annealing treatment. Next, in the process shown in FIG. 5(d), the mask layer 14 is removed. Thereby, the SOI substrate 9 in which a plurality of openings 5 are formed in the semiconductor layer 2 is completed.

[0072] Next, in the process shown in FIG. 5(e), a protective layer 20 is formed on the surface of the semiconductor layer 2. Thereby, the entire surface of the semiconductor layer 2 can be appropriately protected. Although not limited, the protective layer 20 is, for example, a resist film.

[0073] Next, in the process shown in FIG. 5(f), a mask layer 21 is formed on the surface of the support substrate 4 corresponding to the back surface of the SOI substrate 9. Although not limited, the mask layer 21 is a resist pattern. As shown in FIG. 5(f), the mask layer 21 is not formed in the opening region 15 that is opposed to the opening 5 formed in the semiconductor layer 2 in the thickness direction, and is provided only in the peripheral region 16 (see also FIG. 1). Note that the mask layer 21 may be formed together with the mask layer 14 in the process of FIG. 5(b).

[0074] Then, in the process shown in FIG. 5(g), the support substrate 4 not covered by the mask layer 21 is removed by dry etching, and in the process shown in FIG. 4(h), the insulating layer 3 exposed by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains a form having a plurality of openings 5. Then, in the process shown in FIG. 5(i), the protective layer 20 and the mask layer 21 are removed. Thereby, the vapor deposition mask 1 is completed.

[0075] FIG. 6 is a process diagram showing a second manufacturing method of the vapor deposition mask 1 according to the present embodiment. In FIG. 6(a), an SOI substrate 9 is prepared. The SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. Since the materials and thicknesses of each layer are described in FIG. 1, please refer to that.

[0076] Note that in the case of the SOI substrate 9, the diameter is not limited, but in the present embodiment, it can correspond to about 500 mm.

[0077] Next, in the process shown in FIG. 6(b), a mask layer 21 is formed on the surface of the support substrate 4 corresponding to the back surface of the SOI substrate 9. Although not limited, the mask layer 21 is a resist pattern. Similar to FIG. 5(f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0078] Next, in the process shown in FIG. 6(c), the support substrate 4 not covered by the mask layer 21 is removed by dry etching, and in the process shown in FIG. 6(d), the insulating layer 3 exposed by removing the support substrate 4 is removed by wet etching.

[0079] Next, in the process of FIG. 6(e), a mask layer 22 is formed on the back surface of the semiconductor layer 2. Although not limited, the mask layer 22 can be formed as a resist pattern. As shown in FIG. 6(e), a plurality of openings 22a are formed in the mask layer 22 by exposure and development.

[0080] Next, in the step of FIG. 6(f), the semiconductor layer 2 exposed from the opening 22a is etched. This etching process is dry etching, and although not limited thereto, it is preferable to use an etching gas containing a fluorine compound and oxygen, and further optionally a rare gas.

[0081] As the fluorine compound, for example, one or more can be selected from CF4, SF6, NF3, BF3, PF5, and F2, and as the rare gas, one or more can be selected from helium and argon.

[0082] For example, dry etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus. The processing conditions were as follows: CF4 gas at 10 to 100 sccm, O2 gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.

[0083] In the step of FIG. 6(f), an opening 5 with a gradually decreasing width dimension can be formed in the semiconductor layer 2 as it moves away from the mask layer 22 side (toward the first surface 2a of the semiconductor layer 2). Thereby, the side wall surface 6 of the opening 5 can be formed as an inclined surface. Then, in the step of FIG. 6(g), the mask layer 22 is removed. Thereby, the vapor deposition mask 1 is completed.

[0084] In both the manufacturing method shown in FIG. 5 and the manufacturing method shown in FIG. 6, a plurality of openings 5 can be formed in the semiconductor layer 2, and the side wall surface 6 of the opening 5 can be formed as an inclined surface such that the opening width gradually narrows from the back surface (second surface 2b) of the semiconductor layer 2 facing the vapor deposition source 11 side toward the surface (first surface 2a) facing the substrate 10 to be vapor-deposited.

[0085] In the present embodiment, although not limited thereto, the opening width W1 and the taper angle θ1 can be adjusted by various gas flow rates, chamber pressure, power of the plasma generation source, etc.

[0086] In the Bosch process described with reference to FIG. 5, in the method of forming the opening 5 by deeply etching the semiconductor layer 2, the uneven height difference Dn of the side wall surface 6 becomes larger than that in the dry etching process described with reference to FIG. 6. Although not limiting, in the manufacturing process shown in FIG. 5, the uneven height difference Dn of the opening 5 formed in the semiconductor layer 2 is about 0.040 μm to 0.300 μm. On the other hand, in the manufacturing process shown in FIG. 6, the uneven height difference Dn of the opening 5 formed in the semiconductor layer 2 is about 0.003 μm to 0.020 μm. Therefore, as the opening width W1 becomes narrower (for example, when the opening width W1 is 5 μm or less), it is preferable to apply the manufacturing method of FIG. 6, and when the opening width W1 is 5 μm or more, it is preferable to apply the manufacturing method shown in FIG. 5. However, even when the manufacturing method shown in FIG. 5 is applied, as described above, it is possible to reduce the uneven height difference by laser hydrogen annealing treatment or the like.

[0087] <Method for manufacturing an electronic device according to the present embodiment> In the present embodiment, as shown in FIG. 4, the vapor deposition mask 1 is disposed between the substrate 10 to be vapor-deposited and the vapor deposition source 11. At this time, the first surface 2a side of the semiconductor layer 2 of the vapor deposition mask 1 is directed toward the substrate 10 to be vapor-deposited, and the second surface 2b side of the semiconductor layer 2 is directed toward the vapor deposition source 11 side. A plurality of openings 5 are formed in the semiconductor layer 2, and the opening width is narrower on the first surface side than on the second surface side.

[0088] The vapor deposition mask 1 is installed on a holder (not shown) of a vapor deposition apparatus, and at this time, the vapor deposition mask 1 and the substrate 10 to be vapor-deposited can be fixed by an electrostatic chuck. The vapor deposition mask 1 and the substrate 10 to be vapor-deposited are rotated with the axis center of the holder as the rotation axis.

[0089] The vapor deposition material (vapor deposition particles) 12 reaches the surface 10a of the substrate 10 to be vapor-deposited through the opening 5 of the vapor deposition mask 1 from the vapor deposition source 11, and the vapor deposition film 13 is formed.

[0090] In the present embodiment, examples of the electronic device include an OLED microdisplay panel, a liquid crystal panel, a solar cell, etc. In particular, it is suitable for the manufacturing method of an OLED microdisplay panel as an organic electronic device.

[0091] By using the vapor deposition mask 1 of the present embodiment, the pattern width W3 of the vapor deposition film 13 can be ensured to be 80% or more, preferably 85% or more, more preferably 90% or more with respect to the opening width W1. Thus, the vapor deposition film 13 excellent in pattern dimensions can be formed.

[0092] <Regarding the effect of using the vapor deposition mask 1 of the present embodiment> In the present embodiment, by defining the unevenness ratio R (= average value Ave of the unevenness height difference Dn / opening width W1) in the opening 5 of the vapor deposition mask 1, a high pattern dimension of the vapor deposition film 13 can be obtained.

[0093] In the present embodiment, by setting the opening width W1 in the range of 30 μm or less and setting the unevenness ratio R in the range of 0.0001 or more and 0.0420 or less, the vapor deposition film 13 having excellent pattern dimensions can be stably formed.

[0094] Conventionally, the unevenness on the side wall surface of the opening was uniformly defined by a roughness where the vapor deposition material was difficult to deposit. However, the allowable size of the unevenness changes depending on the opening width. Therefore, with the conventional control method, the vapor deposition film 13 having a high pattern dimension cannot be stably formed regardless of the opening width.

[0095] On the other hand, in the present embodiment, a new factor of the unevenness ratio R is introduced. If the opening width W1 is in the range of 30 μm or less, by adjusting the average value Ave of the unevenness height difference Dn so as to satisfy the unevenness ratio R of 0.0001 or more and 0.0420 or less regardless of the size of the opening width W1, the vapor deposition film 13 having a pattern width W3 with a pattern width ratio of 80% or more can be stably formed.

[0096] Further, by adjusting the average value Ave of the unevenness height difference Dn, the deposition of the vapor deposition material 12 can be suppressed, the cleaning frequency of the vapor deposition mask can be reduced, and the quality control of the vapor deposition mask can be easily performed. In addition, the occurrence of clogging of the opening can be reduced, and the long life of the vapor deposition mask can be achieved. In addition, although the embodiments and modifications have been described, as other embodiments, those obtained by wholly or partially combining the above-described embodiments and modifications may be used.

[0097] Further, the present invention is not limited to the above-described embodiments and modifications, and various changes, substitutions, and modifications may be made without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in another way by technological progress or another derived technology, the method may be used for implementation. Therefore, the claims cover all embodiments that can be included within the scope of the technical idea.

[0098] An embodiment having a layer structure different from that of the vapor deposition mask 1 shown in FIG. 1 will be described. For example, as shown in FIG. 7, a membrane 31 made of SiN, SiO2, or the like is formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 are formed in the membrane 31 in the central region where the silicon substrate 30 has been removed, or it may be configured with a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (a silicon substrate is preferable). The membrane is formed by CVD, but SiN is preferably used from the viewpoint of easy stress control.

[0099] In another embodiment shown in FIGS. 8 to 10, an SOI substrate 9 is used as in FIG. 1. In FIG. 8, an SiN layer 33 is formed on the back surface side of the SOI substrate 9 (the support substrate 4 side, the side facing the vapor deposition source 11). In FIG. 9, an SiN layer 33 is formed on the front surface side of the SOI substrate 9 (the semiconductor layer 2 side, the side facing the substrate to be vapor-deposited 10). In FIG. 10, SiN layers 33 are formed on both the back surface side and the front surface side of the SOI substrate 9. In a configuration in which the SiN layer 33 is formed on the front surface side (the semiconductor layer 2 side) of the SOI substrate 9, as shown in FIGS. 9 and 10, an opening 5 is formed continuously with the semiconductor layer 2.

[0100] By providing the SiN layer 33, it is easy to control the stress of the vapor deposition mask and suppress distortion and the like. Further, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is preferably thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9. Although not limited, the film thickness of the SiN layer 33 formed on the front surface side of the SOI substrate 9 is about 0.05 μm to 0.5 μm, and the film thickness of the SiN layer 33 formed on the back surface side of the SOI substrate 9 is about 0.05 μm to 3 μm. Since the semiconductor layer 2 is thinner than the support substrate 4 and a large number of openings 5 are also formed in the semiconductor layer 2, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9 in order to control stress well in a balanced manner between the front surface side and the back surface side.

Example

[0101] Hereinafter, the effects of the present invention will be described with reference to examples and comparative examples of the present invention. Note that the present invention is not limited by the following examples at all.

[0102] <SOI substrate> For the SOI substrate, a support substrate (625 μm) / insulating layer (0.5 μm) / semiconductor layer (15 μm or 5 μm) was used. The parentheses indicate the thickness. The support substrate was a Si substrate, the semiconductor layer was a Si layer, and the insulating layer was a SiO2 layer. The outer diameter of the SOI substrate was 200 mm. In the experiment, two types of SOI substrates with semiconductor layer thicknesses of 15 μm and 5 μm were prepared.

[0103] <Original master used> In the steps shown in (b) of FIG. 5 and (e) of FIG. 6, an opening pattern is formed in the mask layer (resist layer) by i-line exposure, and the opening width of the original master used when forming this opening pattern was adjusted within the range of 2.0 μm to 30 μm.

[0104] <Method for manufacturing vapor deposition mask> The vapor deposition mask 1 was formed using the manufacturing methods shown in FIGS. 5 and 6. In the experiment, the opening width W1 was changed using the above-described original plate for use. Also, the opening width W1 and the taper angle θ1 formed in the semiconductor layer 2 were adjusted by various gas flow rates, chamber pressure, power of the plasma generation source, and the like. For example, in the dry etching of FIG. 5(c), anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as in the mode of performing isotropic dry etching using fluorine radicals using SF6 gas. The processing conditions were set as follows: SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.

[0105] Also, in the dry etching shown in FIG. 6(f), CF4 gas was set at 10 to 100 sccm, O2 gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.

[0106] <Regarding the dimensions of the opening 5 formed in the vapor deposition mask 1> In the experiment, the opening width W1, the average value Ave of the uneven height difference Dn, the maximum value of the uneven height difference Dn, and the taper angle θ1 were obtained. As shown in FIG. 1, the opening width W1 was the width dimension in the plane direction along the first surface 2a of the semiconductor layer 2. The opening width W1 can be obtained from the SEM image obtained using eCD-2 manufactured by KLA-Tencor.

[0107] The uneven height difference Dn and the taper angle θ1 were determined by the method described in Fig. 2 from the SEM images obtained using Regulus 8220 manufactured by Hitachi High-Tech. As described in Fig. 2, at the middle position of the opening height, five pitches at the center of the thickness of the uneven shape formed on the side wall surface 6 were observed and determined. For the detailed method of determining the uneven height difference Dn and the taper angle θ1, refer to the explanatory parts in Figs. 1 and 2. Note that the experimental examples determined as pitches are limited to those with odd numbers in Tables 1 and 2. On the other hand, for the even-numbered experimental examples, five high points were determined at the center of the thickness, and the space between them was regarded as a concave part to determine the uneven height difference Dn and the like. The odd-numbered experimental examples were formed by the manufacturing method shown in Fig. 5. Since the unevenness is relatively large, it is easy to measure as a pitch. However, the even-numbered experimental examples were formed by the manufacturing method shown in Fig. 6, and the unevenness is small, making it difficult to recognize as a pitch. Therefore, for the even-numbered experimental examples, five positions that can be recognized as height were measured and applied to the measurement method in Fig. 3 to measure various parameters.

[0108] Then, from the average value Ave of the uneven height difference Dn and the opening width W1, the uneven ratio R (= average value Ave of the uneven height difference Dn / opening width W1) was calculated.

[0109] <Regarding the determination of the evaporation pattern dimensions> Using the plurality of evaporation masks formed above, the green light-emitting material Alq3 (tris(8-hydroxyquinoline)aluminum) was deposited on the glass surface through the evaporation mask by the vacuum resistance heating evaporation method to form an evaporation film pattern for evaluation.

[0110] Then, the pattern width W3 of the evaporation film was measured with a laser microscope (model number VK-X210 (manufactured by Keyence)), and the pattern width ratio of the evaporation film to the opening width W1 of the evaporation mask ((W3 / W1) × 100 (%)) was determined. For the experimental examples where the pattern width ratio is less than 70%, it is marked as ×; for the experimental examples where the pattern width ratio is 70% - 80%, it is marked as △; for the experimental examples where the pattern width ratio is 80% - 90%, it is marked as ○; for the experimental examples where the pattern width ratio is more than 90%, it is marked as ◎.

[0111] The experimental results are shown in the "Vapor Deposition Pattern Dimension Judgment" columns of Table 1 and Table 2 below. Table 1 shows the experimental results with a semiconductor layer thickness of 15 μm, and Table 2 shows the experimental results with a semiconductor layer thickness of 5 μm.

[0112] Note that the "Taper Angle" shown in Tables 1 and 2 is described in units of 10°, but this is a representative value, and it was confirmed that all experimental examples fall within the range of ±3° from each representative value.

[0113]

Table 1

[0114]

Table 2

[0115] As shown in Tables 1 and 2, there are experimental examples from No. 1 to No. 46, and the opening width W1 was set within the range of 3 μm to 20 μm. In experimental examples No. 1, 3, 5, 31, and 33, the vapor deposition result is ×, and in experimental examples No. 7 and 35, the vapor deposition result is △. These are all comparative examples. The remaining experimental examples have vapor deposition results of ○ or ◎, and all correspond to examples.

[0116] From this experiment, it was found that by adjusting the unevenness ratio R within the range of 0.0001 to 0.0420 regardless of the opening width W1, the deposition of the vapor deposition material 12 on the side wall surface 6 of the opening 5 can be suppressed, and a vapor deposition film with a pattern width W3 of 80% or more, preferably more than 90%, with respect to the opening width W1 can be stably formed. In this example, the needs required for the vapor deposition mask 1 provided with the semiconductor layer 2 can be ensured. In particular, for preferably applying as a vapor deposition mask for RGB coating used in the manufacturing process of an OLED microdisplay, the opening width W1 was set to 30 μm or less, preferably 20 μm or less. Also, based on the experimental examples, the opening width W1 is more preferably in the range of 3 μm or more and 20 μm.

[0117] Also, in order to stably obtain a pattern width ratio exceeding 90%, the unevenness ratio R was preferably set to 0.0400 or less, more preferably 0.0380 or less.

[0118] Also, the average value Ave of the unevenness height difference Dn was preferably 0.200 μm or less, more preferably 0.18 μm or less, and even more preferably 0.170 μm or less. Also, the lower limit value of the average value Ave of the unevenness height difference Dn was set to 0.001 μm or more, or 0.003 μm or more.

[0119] Also, the maximum value of the unevenness height difference Dn was preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.300 μm or less.

[0120] Also, according to the experimental results, the taper angle was preferably 60° or more, more preferably 70° or more. Also, the lower limit value of the taper angle can be less than 90°, or 85° or less, or 80° or less. According to the experimental examples, the taper angle can be set in the range of 60° or more and 80° or less. Regarding the taper angle, an error of about ±3° is allowed.

[0121] Also, the unevenness angles θ2 and θ3 described in FIG. 2 were approximately 11° to 41° in the odd-numbered experimental examples. Also, the unevenness angles θ2 and θ3 were approximately 1.0° to 1.5° in the even-numbered experimental examples.

[0122] The smaller the concave-convex angles θ2 and θ3 are, the smaller the protrusion height of the convex portion 7 (see Fig. 3) can be, and thus the deposition of the vapor deposition material 12 can be suppressed, which is preferable. From experimental examples, the concave-convex angles θ2 and θ3 can be set within a range of about 0.5° to 50°. When the opening width W1 is 5 μm or less, it is desirable to make the concave-convex angles θ2 and θ3 as small as possible, set them to 10° or less, and the most preferable range is about 0.5° to 2°. Also, the concave-convex angle θ3 is smaller than the concave-convex angle θ2, and thus it has been found that the deposition of the vapor deposition material can be suppressed in this form.

[0123] Fig. 11(a) is an image diagram showing the deposition of the vapor deposition material 19 when the thickness of the semiconductor layer 2 is about 3 to 5 μm, and Fig. 11(b) is an image diagram showing the deposition of the vapor deposition material 19 when the thickness of the semiconductor layer is about 15 to 20 μm. Figs. 11(a) and (b) show the state of the vapor deposition material 19 depositing below the side wall of the opening 5 from the upper figure to the lower figure. As shown in Figs. 11(a) and (b), even if the thickness of the semiconductor layer 2 is different, the range where the vapor deposition material 19 is deposited on the side wall surface 6 of the opening 5 is almost the same, and it is considered that the vapor deposition results are almost unchanged. Therefore, it is considered that the vapor deposition results do not change much within the range where the thickness of the semiconductor layer 2 is 2 to 20 μm. Therefore, in the above, the experimental examples were when the thickness of the semiconductor layer was 15 μm and 5 μm, but even for other thicknesses, it can be estimated that by adjusting the concavity-convex ratio R within the range of 0.0001 or more and 0.0420 or less, the pattern width ratio can be made 80% or more.

[0124] Note that before the vapor deposition material is deposited on the side wall surface of the opening, when the thickness of the semiconductor layer is about 3 to 5 μm, a pattern width ratio of more than 90% can be surely obtained.

[0125] This application is based on Japanese Patent Application No. 2023-130554 filed on August 10, 2023. All of its contents are incorporated herein.

Claims

1. A vapor deposition mask having a first surface and a second surface opposite to the first surface, and a plurality of openings penetrating between the first surface and the second surface, wherein the side wall surfaces of the openings are formed in an uneven shape, the opening width is 30 μm or less, the uneven ratio (average value of the uneven height difference / opening width) is 0.0001 or more and 0.0420 or less, the vapor deposition mask is composed of a SOI substrate, and a SiN layer is formed on the surface side or the back side where the openings are formed, or on both the surface side and the back side. A vapor deposition mask characterized by the above.

2. The uneven ratio is 0.0380 or less. The vapor deposition mask according to Claim 1, characterized by the above.

3. When the substrate to be vapor deposited side is the first surface and the vapor deposition source side is the second surface, the opening width is defined by the opening width on the first surface side. The vapor deposition mask according to Claim 1, characterized by the above.

4. The opening width becomes narrower from the second surface to the first surface. The vapor deposition mask according to Claim 3, characterized by the above.

5. The average value of the uneven height difference is 0.200 μm or less. The vapor deposition mask according to Claim 1, characterized by the above.

6. The opening width is 1 μm or more and 30 μm or less. The vapor deposition mask according to Claim 1, characterized by the above.

7. The maximum value of the uneven height difference is 0.500 μm or less. The vapor deposition mask according to Claim 1, characterized by the above.

Images