Evaporation mask and method for manufacturing an electronic device

Abstract

The purpose of the present invention is to provide: a vapor deposition mask capable of forming a vapor deposition film that has excellent pattern dimensions and suppressing mutual influence between adjacent pixels; and a method for manufacturing an electronic device using the vapor deposition mask. A vapor deposition mask according to the present invention is disposed between a vapor deposition source and a substrate to be subjected to vapor deposition, in order to deposit, through openings therein, a vapor deposition material from the vapor deposition source onto a surface of the substrate to be subjected to vapor deposition, and is characterized in that: the vapor deposition mask has a first surface that faces the substrate to be subjected to vapor deposition and a second surface that is located opposite to the first surface and that faces the vapor deposition source; a plurality of openings penetrating the vapor deposition mask between the first surface and the second surface are formed; the lateral wall surface of each of the openings is inclined such that the opening width becomes narrower from the second surface side to the first surface side; and the opening width defined on the first surface side is more than 3 µm but less than 15 µm.

Description

Technical Field

[0001] The present invention relates to a vapor deposition mask and a method for manufacturing an electronic device.

Background Art

[0002] For example, a vapor deposition mask used for coating three colors of RGB in the production of an organic EL display is known.

[0003] As shown in Patent Documents 1 and 2, a plurality of openings are provided in the vapor deposition mask, and a vapor deposition material is formed on a substrate to be vapor-deposited through the openings.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Due to variations in the opening width of the vapor deposition mask, in the vapor deposition film formed on the substrate to be vapor-deposited, there may be an interaction between adjacent pixels, for example, the risk of color mixing may increase. Therefore, there is a need for a vapor deposition mask that can improve the pattern dimensions of the vapor deposition film and suppress the interaction between adjacent pixels.

[0006] An object of the present invention is to provide a vapor deposition mask capable of forming a vapor deposition film having excellent pattern dimensions and suppressing the interaction between adjacent pixels, and a method for manufacturing an electronic device using the vapor deposition mask.

Means for Solving the Problems

[0007] The vapor deposition mask of the present embodiment is disposed between a substrate to be vapor-deposited and a vapor deposition source, and through the opening, a vapor deposition material from the vapor deposition source is deposited on the by vapor deposition mask for depositing on the surface of the vapor deposition substrate, having a first surface facing the substrate to be vapor-deposited and a second surface located on the opposite side of the first surface and facing the vapor deposition source side, and a plurality of openings penetrating between the first surface and the second surface are formed, and side wall surfaces of the openings are inclined so that an opening width becomes narrower from the second surface side toward the first surface side, the opening width defined on the first surface side is larger than 3 μm and smaller than 15 μm, the vapor deposition mask is composed of an SOI substrate, and a SiN layer is formed on a side facing the substrate to be vapor-deposited, or a side facing the vapor deposition source, or both a side facing the substrate to be vapor-deposited and a side facing the vapor deposition source.

Advantages of the Invention

[0008] According to the present invention, by controlling the opening width and the variation σ, a vapor deposition film having excellent pattern dimensions and suppressing risks such as color mixing between adjacent pixels can be stably formed.

Brief Description of the Drawings

[0009]

Figure 1

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Figure 11

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions, ratios, etc. of each drawing are not necessarily the same as the actual ones. Also, even when representing the same part between the drawings, the dimensional relationships and ratios between them may be represented differently. In particular, the embodiments shown below are examples of structures for embodying the technical idea of the present invention, and do not specify the technical idea of the present invention. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and overlapping descriptions are omitted. Also, the lower limit value and the upper limit value of the numerical range include the error range.

[0011] <Background of the Present Invention> Virtual reality / augmented reality (VR / AR) technologies and VR / AR-related markets are growing rapidly. Along with the progress of growth, the miniaturization, high pixelization of the screen resolution (PPI: Pixels Per Inch), high-speed response, and high color gamut of display panels suitable for the VR / AR field are advancing. In order to advance the technology, the spread of silicon-based organic light-emitting diode (OLED) microdisplay panels has become remarkable.

[0012] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. In order to effectively prepare for AR and VR as high-value-added industries, for example, it is expected to realize a display with an ultra-high resolution of 1000 ppi or more. In response to this, the need for a vapor deposition mask for RGB painting used in the manufacturing process of OLED microdisplays is increasing.

[0013] The vapor deposition mask is provided with a plurality of openings corresponding to the vapor deposition film, and the opening accuracy of the vapor deposition mask is important in order to improve the pattern dimensions of the vapor deposition film.

[0014] The vapor deposition mask is disposed between the substrate to be vapor-deposited and the vapor deposition source, and the vapor deposition material reaches the surface of the substrate to be vapor-deposited from the vapor deposition source through the openings of the vapor deposition mask. The opening width of the vapor deposition mask in the present embodiment is being narrowed in order to meet the needs of the above-described OLED microdisplay, but if it is too small, the influence of the deposition of the vapor deposition material on the side wall surface of the opening becomes large, the opening width becomes narrower than the actual width, and it becomes difficult to form a vapor deposition film with excellent pattern dimensions.

[0015] On the other hand, when the opening width becomes wider, the variation in the opening width tends to increase. The vapor deposition film formed on the substrate to be vapor-deposited has a small variation in the emission area, but the risk of color mixing with adjacent pixels increases. Since the color mixing risk is determined by the absolute value of the variation σ of the opening width, it is necessary to reduce the variation σ.

[0016] Therefore, as a result of intensive research, the present inventors focused on the opening width and the variation σ, and developed a vapor deposition mask that can suppress the mutual influence (for example, color mixing risk) between adjacent pixels while having excellent pattern dimensions.

[0017] <Overview of the vapor deposition mask 1 in the present embodiment> FIG. 1 is a cross-sectional view of the vapor deposition mask 1 in the present embodiment. FIG. 2 is a cross-sectional view showing an enlarged part of the vapor deposition mask shown in FIG. 1. FIG. 3 is a partial enlarged cross-sectional view showing an enlarged part of an opening of the vapor deposition mask of the present embodiment. FIG. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the vapor deposition mask of the present embodiment.

[0018] The vapor deposition mask 1 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably composed of a SOI (Silicon on Insulator) substrate 9.

[0019] The semiconductor layer 2 is preferably a single crystal silicon layer, and is also called an active layer or a membrane. Although the thickness of the semiconductor layer 2 is not limited, it is about 1 μm to 300 μm.

[0020] As shown in FIG. 1, the vapor deposition mask 1 has a plurality of opening regions 15 and a peripheral region 16 located around the opening regions 15. In the peripheral region 16, the semiconductor layer 2, the insulating layer 3, and the support substrate 4 are laminated. On the other hand, only the semiconductor layer 2 is disposed in the opening region 15, that is, the insulating layer 3 and the support substrate 4 are removed, and a plurality of minute openings 5 are formed in each opening region 15.

[0021] FIG. 2 shows an enlarged view of the vicinity of one opening region 15 shown in FIG. 1. As shown in FIG. 2, the semiconductor layer 2 includes a first surface 2a and a second surface 2b facing each other in the thickness direction. The insulating layer 3 and the support substrate 4 are provided on the second surface 2b side. As shown in FIG. 4, the first surface 2a is a surface facing the substrate to be vapor-deposited 10, and the second surface 2b is a back surface facing the vapor deposition source 11.

[0022] As shown in FIG. 2, a plurality of openings 5 penetrating between the first surface 2a and the second surface 2b are formed in the semiconductor layer 2. As shown in FIG. 2, the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a. Therefore, the side wall surface 6 of the opening 5 is inclined. In FIG. 2, the opening width W1 is defined as the width dimension in the plane direction along the first surface 2a. Thus, in FIG. 2, the opening width W1 is illustrated at the location where the width dimension is the narrowest. In FIG. 2, although the reference signs of the opening width W1 and the side wall surface 6 are illustrated only for one opening 5, they are similarly applied to the other openings 5. The shape of the side wall surface 6 of the opening 5 will be described in detail later.

[0023] The planar pattern of the opening 5 (the shape seen from directly above the semiconductor layer 2 toward the first surface 2a) is not to be limited, but examples include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. Also, all the openings 5 may have the same planar pattern, or some may be different. Also, the openings 5 may be regularly arranged, or may be irregularly arranged, or a combination of regular and irregular arrangements may be mixed. Although the interval between adjacent openings 5 is not limited, when viewed from the first surface 2a side, the interval is about 1 μm to 20 μm.

[0024] The outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer. Although the diameter (in the case of a rectangle, the length of one side) is not limited, it is preferably about 100 mm to 500 mm. Thus, even if the diameter of the semiconductor layer 2 increases, each opening 5 can be formed uniformly.

[0025] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer, and specifically, is preferably a silicon oxide (SiO2) layer. The insulating layer 3 is also called a BOX layer (Buried Oxide Layer). Although the thickness of the insulating layer 3 is not limited, for example, it is about 100 nm to 20 μm.

[0026] The insulating layer 3 shown in FIG. 2 is not provided in the opening region facing the opening 5 of the semiconductor layer 2 and has been removed, and remains only in the peripheral region of the opening region on the second surface 2b of the semiconductor layer 2. The insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and having the insulating layer 3 enables stable processing.

[0027] The support substrate 4 shown in FIG. 2 is a semiconductor substrate, for example, a silicon substrate. Although the thickness of the support substrate 4 is not limited, it is, for example, about 100 μm to 1000 μm.

[0028] As shown in FIG. 1, the support substrate 4 can function as a columnar portion 16a and an outer peripheral frame 16b that surround the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be maintained in a stretched state by the support substrate 4, eliminating the need for a stretching process, and the vapor deposition mask 1 of the present embodiment can be brought into close contact with the substrate to be vapor deposited 10 using an electrostatic chuck that utilizes electrostatic force. As shown in FIG. 1, the columnar portion 16a is located inside the outer peripheral frame 16b, and they all have the same length (height). However, for example, the height of the columnar portion 16a may be made lower than that of the outer peripheral frame. However, keeping the heights the same can maintain greater strength.

[0029] Also, although not shown in FIGS. 1 and 2, alignment marks for alignment can be formed in the outer peripheral region on the first surface 2a side of the semiconductor layer 2. The alignment marks can be formed, for example, in a concave shape on the first surface 2a and can be formed to a depth that reaches the insulating layer 3.

[0030] <Detailed description of the opening 5 of the vapor deposition mask 1 in the present embodiment> [Method for calculating the opening width W1] As shown in FIG. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. Therefore, as shown in FIG. 2, the opening width W1 was determined as the dimension in the plane direction along the first surface 2a where it is the narrowest. For example, the opening width W1 can be obtained from the SEM image obtained using eCD-2 manufactured by KLA-Tencor.

[0031] [Calculation method for the variation σ of the opening width W1] In the present embodiment, the variation σ of the opening width W1 of the vapor deposition mask 1 is defined. A predetermined range is defined within the plane of the vapor deposition mask 1 shown in FIG. 1, the opening widths W1 of a plurality of openings 5 located within the predetermined range are measured, and the standard deviation σ is obtained. Then, this standard deviation σ is defined as the variation σ of the opening width W1.

[0032] Although not limiting, the "predetermined range" can be defined as the central region of the vapor deposition mask 1. At this time, the central region preferably has a size that includes at least 100 or more openings 5.

[0033] A predetermined number of adjacent openings 5 included in the central region are selected, the opening widths W1 of these openings 5 are measured, and the variation σ is obtained. Although not limiting the "predetermined number", it is about several tens to several hundreds, and specifically, it may be about 50 to 150. In the present embodiment, 100 adjacent openings 5 are selected to obtain the variation σ.

[0034] Also, "adjacent openings" can be defined as openings included within the contour of a rectangle, square, circle, ellipse, polygon, or openings arranged in a row. Preferably, a plurality of openings existing within the contour of a square or rectangle are picked up. For example, when selecting 100 openings 5, 100 arranged in a 10×10 matrix in the vertical and horizontal directions can be selected.

[0035] FIG. 3 is a partial enlarged cross-sectional view showing an enlarged view of one opening 5 formed in the vapor deposition mask 1, and shows an extraction of an intermediate portion in the height direction (thickness direction of the semiconductor layer 2) of the opening 5. Although the reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side of the drawing, the cross-sectional shape is symmetric about the vertical axis, and the side wall surface 6 on the right side of the drawing has the same configuration.

[0036] As shown in Fig. 3, the side wall surface 6 of the opening 5 is formed in an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding in the inner direction of the opening 5 and recesses 8 located between the convex portions 7 are continuously and repeatedly formed along the height direction of the opening 5. In the present embodiment, the uneven height difference and the like of the opening 5 are calculated as follows.

[0037] [Calculation method of uneven height difference] First, an SEM (scanning electron microscope) image of the cross section of the opening 5 was obtained. Although the SEM is not limited, for example, Regulus 8220 manufactured by Hitachi High-Tech was used.

[0038] At an intermediate position exactly at the center of the thickness between the first surface 2a and the second surface 2b of the opening 5, the length of five pitches of the uneven shape was measured by SEM. Note that the number of pitches is not limited to five. If the number of pitches is too small, parameter noise will increase. If the number of pitches is too large, depending on the thickness, it may not be possible to secure that number of pitches. Also, since it takes time and becomes complicated to calculate the parameters, it is preferably about several pitches to within ten pitches. In the present embodiment, basically, it is measured at five pitches, but if it is difficult, the number of pitches can be appropriately set and changed.

[0039] Also, instead of the above-mentioned concept of pitch, five locations where the height can be confirmed at the center of the thickness may be measured by the SEM image, for example. In this case, the locations with height can be regarded as convex portions, and the spaces between them can be regarded as recesses.

[0040] In Fig. 3, only two pitches are shown and described. In Fig. 3, reference numerals 7a and 7b are attached to distinguish the two convex portions 7. When viewed from each of the convex portions 7a and 7b, a half pitch is formed with the recess 8 located on the first surface 2a side (the upper side in the drawing). Also, reference numerals 8a and 8b are attached to distinguish the two recesses 8. Let the convex portion 7a and the recess 8a be the first half pitch P1, and the convex portion 7b and the recess 8b be the second half pitch P2. Note that the pitch refers to the distance between convex portions or the distance between recesses, and half of that distance is defined as the half pitch.

[0041] As shown in FIG. 3, an approximate straight line T1 connecting the lowest positions (bottom A) of the respective recesses 8a and 8b within the measurement range was drawn. The bottom A is, for example, the position farthest from the center line O in the width direction of the opening 5. The approximate straight line T1 can be obtained by the least squares method. When an irregular recess 8 is formed within the measurement range (for example, when the bottom A is extremely low), the approximate straight line T1 can be drawn excluding that recess 8.

[0042] Next, as shown in FIG. 3, at the first half pitch P1, the highest position (top) B of the convex portion 7a was determined. The top B is the position closest to the center line O in the width direction of the opening 5. Then, as shown in FIG. 3, a straight line S1 orthogonal to the approximate straight line T1 was drawn so as to intersect the top B. The length of the straight line S1 from the approximate straight line T1 to the top B was determined. The length of this straight line S1 was defined as the unevenness height difference D1 of the first half pitch P1.

[0043] For the second half pitch P2 and other half pitches, the unevenness height difference can be obtained in the same manner as that determined for the first half pitch P1. That is, a straight line orthogonal to the approximate straight line T1 was drawn, and the straight line length to the top B of each convex portion was determined, and this straight line length was defined as the unevenness height difference of each pitch. Incidentally, in FIG. 3, the unevenness height difference D2 of the second half pitch P2 is shown.

[0044] As described above, a plurality of unevenness height differences can be obtained. When measuring for five pitches, five unevenness height differences Dn (n = 1 to 5) are calculated. Then, the average value Ave of these unevenness height differences Dn was determined.

[0045] Note that there may be fine unevenness formed on the surfaces of the respective recesses 8a and 8b (or it can also be said to be the bottom portions of the convex portions 7a and 7b), but these fine unevenness can be ignored. For example, fine unevenness with a wavelength in the order of several nm or smaller can be cut off, and a wavy curve can be created to obtain the unevenness height difference.

[0046] [Method for calculating the taper angle θ1] In the present embodiment, the taper angle θ1 of the opening 5 is obtained as follows. That is, as shown in FIG. 3, the end of the opening width W1 in the plane direction along the first surface 2a and the end of the opening width W2 in the plane direction along the second surface 2b are connected by a straight line, and the inclination angle between this straight line and the first surface 2a can be set as the taper angle θ1 of the opening 5. The taper angle θ1 was obtained by measuring the length from the SEM image obtained using Regulus8220 manufactured by Hitachi High-Tech.

[0047] [Method for calculating the uneven angles θ2 and θ3] As shown in FIG. 3, the uneven angle θ2 can be obtained as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest (the farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8a located on the vapor deposition substrate 10 side (the upper side in the figure) as viewed from the convex portion 7a, and an approximate straight line T1. Further, as shown in FIG. 3, the uneven angle θ3 can be obtained as the angle between a straight line L2 connecting the top B of the convex portion 7a and the lowest (the farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8b located on the vapor deposition source 11 side (the lower side in the figure, see FIG. 4) as viewed from the convex portion 7a, and the approximate straight line T1.

[0048] The fact that the uneven angles θ2 and θ3 are small means that the height of the convex portion 7 is low (the depth of the concave portion 8 is shallow) and the undulation of the side wall surface 6 is small.

[0049] [Regarding the characteristic configuration of the opening parameters in the present embodiment] The vapor deposition mask 1 in the present embodiment (1) The side wall surface 6 of the opening 5 is inclined so as to narrow from the second surface 2b side to the first surface 2a side, (2) The opening width W1 is greater than 3 μm and less than 15 μm,

[0050] Thus, in this embodiment, the opening width W1 is set in a range greater than 3 μm and less than 15 μm. The needs required for the deposition mask 1 provided with the semiconductor layer 2 can be ensured. In particular, as a deposition mask for RGB painting used in the manufacturing process of an OLED microdisplay, it is necessary to further reduce the opening width W1. In this embodiment, the opening width W1 is preferably 4 μm or more and 10 μm or less.

[0051] The opening width W1 is preferably set as the width dimension in the plane direction along the first surface 2a facing the substrate 10 to be deposited.

[0052] FIG. 4 is a cross-sectional view showing the deposition mask 1 of this embodiment disposed between the substrate 10 to be deposited and the deposition source 11, and shows one step of the method for manufacturing an electronic device.

[0053] As shown in FIG. 4, the deposition material (deposition particles) 12 from the deposition source 11 passes through the opening 5 of the deposition mask 1 and reaches the surface 10a of the substrate 10 to be deposited, and the deposition film 13 is formed. When the pattern width W3 of the deposition film 13 is measured and the ratio to the opening width W1 is calculated, if the pattern width ratio ((pattern width W3 / opening width W1) × 100 (%)) is 80% or more, it is taken as this example, and the opening width W1 less than 80% is taken as the comparative example.

[0054] In this embodiment, by setting the opening width W1 in a range greater than 3 μm and less than 15 μm, preferably 4 μm or more and 10 μm or less, the pattern width ratio can be made 80% or more, and the variation σ of the opening width W1 can be reduced. Here, the reason for setting the pattern width ratio to 80% or more is that if it is less than 80%, the deviation from the desired pattern width W3 of the deposition film 13 is too large, leading to a decrease in yield, and it also leads to a decrease in the area to emit light at the design position such as coordinate position accuracy, resulting in a decrease in the luminance of the light-emitting element itself, or it is a numerical value required for product quality assurance. To increase the production efficiency, the pattern width ratio is set to 85% or more, preferably 90% or more, more preferably 95% or more.

[0055] When the opening width W1 becomes 3 μm or less, the reason why the pattern width ratio is likely to fall below 80% is that the influence of the deposition material 12 deposited on the side wall surface 6 becomes greater as the opening width W1 becomes narrower. As shown in FIG. 3, since the side wall surface 6 is formed in an uneven shape, the deposition material 12 is likely to adhere to the side surface of the convex portion 7 located on the substrate side to be deposited (the upper side in FIG. 3) when viewed from the concave portion 8. Therefore, in the present embodiment, it is preferable to control the average value Ave of the uneven height difference Dn together with the setting of the opening width W1. That is, in the present embodiment, the average value Ave of the uneven height difference Dn is preferably 0.200 μm or less, more preferably 0.195 μm or less, further preferably 0.190 or less, still further preferably 0.180 μm or less, and most preferably 0.175 μm or less. Also, although the lower limit value of the average value Ave of the uneven height difference Dn is not limited, the average value Ave of the uneven height difference Dn can be defined as 0.003 μm or more, or 0.005 μm or more, or 0.008 μm or more. In the present embodiment, by adjusting the average value Ave of the uneven height difference Dn as described above, the deposition of the deposition material 12 on the side wall surface 6 of the opening 5 can be reduced, and there is also an effect such as reducing the number of cleaning times of the deposition mask 1.

[0056] In the present embodiment, the variation σ of the opening width W1 is preferably less than 0.09 μm. As described above, the variation σ can be obtained, for example, by the standard deviation σ of the opening widths W1 of 100 adjacent openings 5.

[0057] When the opening width W1 is 15 μm or more, the variation σ becomes 0.09 μm or more, and furthermore, it tends to be as large as 0.10 μm or more. FIG. 5 is an image diagram in which RGB pixels 23 are arranged in a matrix in a vapor deposition film 13 formed on the surface of a substrate to be vapor-deposited using the vapor deposition mask 1. When the opening width W1 of the vapor deposition mask 1 increases, although it becomes difficult to receive the influence of the variation σ in the light-emitting area of each pixel 23, for example, the risk of color mixing with adjacent pixels 23 shown in FIG. 5 increases. The color mixing risk is determined by the absolute value of the variation σ, and the larger the variation σ, the higher the color mixing risk. Therefore, in the present embodiment, the variation σ is defined in a range smaller than 0.09 μm, and preferably, the variation σ is set to be 0.01 μm or more and 0.08 μm or less.

[0058] In the present embodiment, an opening 5 is formed in the semiconductor layer 2 by dry etching. At this time, for example, compared with the width dimension W4 of the through hole 14a shown in FIG. 6, the etching enters slightly excessively, so that the opening widths W1 do not all become the same, and variations are likely to occur. At this time, if the opening width W1 is increased, it is likely to be formed by overetching, and as a result, it is considered that the variation σ increases. Therefore, in the present embodiment, it has been found that by setting the opening width W1 in a range larger than 3 μm and smaller than 15 μm, the variation σ can be suppressed to be smaller.

[0059] In addition, the uneven angles θ2 and θ3 described with reference to FIG. 3 are in the range of about 0.5° to 50°, preferably 45° or less, more preferably 40° or less, still more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less. By being able to reduce the uneven angles θ2 and θ3, the protrusion height of the convex portion 7 can be reduced, or the interval between adjacent convex portions 7 can be widened (the range of the concave portion 8 can be widened), and the deposition of the vapor deposition material 12 on the side surface of the convex portion 7 can be suppressed. The most preferable range of the uneven angles θ2 and θ3 is about 0.5° to 2°. In addition, the uneven angle θ3 shown in FIG. 3 is preferably smaller than the uneven angle θ2. Thereby, the deposition of the vapor deposition material 12 on the side wall surface 6 can be suppressed.

[0060] In this embodiment, the opening width of the opening 5 gradually decreases from the second surface 2b side toward the first surface 2a side. That is, as shown in FIG. 4, in the vapor deposition mask 1, the opening width W1 on the side facing the substrate 10 to be vapor-deposited is narrow, and the side wall surface 6 of the opening 5 is formed as an inclined surface. Thereby, it becomes easier to stably form the vapor-deposited film 13 having the desired pattern width W3. Further, when the vapor deposition material 12 deposited on the side wall surface 6 peels off from the side wall surface 6, it can be made less likely to fly toward the substrate 10 to be vapor-deposited. Also, from the viewpoint of manufacturing, by inclining the side wall surface 6 of the opening 5, it becomes easier to form the side wall surface 6. Although not limited, the taper angle θ1 of the side wall surface 6 is preferably 60° or more, more preferably 70° or more, and even more preferably 80° or more. Also, the taper angle θ1 is preferably less than 90°, and more preferably 88° or less. When the taper angle θ1 is less than 60°, the amount of the vapor deposition material 12 deposited on the side wall surface 6 increases, and the pattern width ratio of the vapor-deposited film is likely to be less than 80%. Also, although the taper angle θ1 can be made up to about 90°, that is, the side wall surface 6 can be formed substantially vertically, in that case, it is considered that the influence of the uneven height difference Dn of the side wall surface 6 during vapor deposition becomes large. In particular, the smaller the opening width W1, the more necessary it is to minimize the average value Ave of the uneven height difference Dn. There is also a relationship with the thickness of the semiconductor layer 2. That is, as the thickness of the semiconductor layer 2 increases, it becomes difficult to form the side wall surface 6 as a vertical surface. Therefore, in this embodiment, the taper angle θ1 of the side wall surface 6 is controlled to be less than 90°, preferably 88° or less.

[0061] <Regarding the manufacturing method of the vapor deposition mask 1 in the present embodiment> FIG. 6 is a process diagram showing a first manufacturing method of the vapor deposition mask 1 of the present embodiment. Here, the vapor deposition mask 1 in the manufacturing process shown in FIG. 6 and FIG. 7 to be described later shows only the vicinity of a certain opening region 15, similar to FIG. 2. Actually, a plurality of opening regions 15 shown in FIG. 1 are formed simultaneously. In FIG. 6(a), an SOI substrate 9 is prepared. The SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. Since the materials and thicknesses of each layer were described in FIG. 1, please refer to that for details.

[0062] Note that in the case of the SOI substrate 9, although the diameter is not limited, in the present embodiment, it can support up to about 500 mm.

[0063] In FIG. 6(b), a mask layer 14 is patterned on the surface of the semiconductor layer 2. The mask layer 14 is preferably a resist and can be patterned by exposure and development. A plurality of through holes 14a are formed in the mask layer 14. These through holes 14a are opening patterns for forming the opening 5 in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed to be larger than 3 μm and smaller than 15 μm.

[0064] Next, in FIG. 6(c), the semiconductor layer 2 exposed from the through holes 14a of the mask layer 14 is dry-etched. In the present embodiment, the semiconductor layer 2 is etched deeply. In a so-called Bosch process, for example, it is preferable to use a method of repeating the etching of Si with SF6 and the formation of a polymer film with C4F8 to deeply dig silicon and alternately progress sidewall protection and bottom etching. By the Bosch process, the side wall surface 6 of the opening 5 formed in the semiconductor layer 2 becomes an uneven shape.

[0065] At this time, as shown in FIG. 6(c), the composition, flow rate, internal pressure of the etching chamber, power of the high-frequency power supply, etc. of the etching gas are appropriately adjusted so as to form an inverse taper surface. Also, by these adjustments, the taper angle θ1 of the inverse taper surface and the uneven height difference Dn can be controlled.

[0066] For example, in a dry etching apparatus, a Bosch process was carried out using SF6 gas and C4F8 gas alternately. By applying a bias to the substrate to be etched using the same gas as in the mode of performing isotropic dry etching using fluorine radicals with SF6 gas, anisotropic dry etching using fluorine ions was carried out. For example, the processing conditions were set as follows: SF6 gas from 0 to 500 sccm, C4F8 gas from 0 to 300 sccm, Platen LF from 0 to 1500 W, Coil RF from 300 to 1500 W, and chamber pressure from 1 to 10 Pa, and various conditions were adjusted.

[0067] By the above-described Bosch process, a plurality of openings 5 can be deeply formed in the semiconductor layer 2, and at this time, the taper angle θ1 and the uneven height difference of the side wall surface 6 of the opening 5 can be appropriately adjusted.

[0068] In the present embodiment, in addition to adjusting the conditions in the above-described etching process, in order to reduce the uneven height difference Dn, for example, after deeply etching silicon, a smoothing process (a process for reducing the uneven height difference) can also be achieved by performing laser hydrogen annealing treatment.

[0069] Next, in the process shown in FIG. 6(d), the mask layer 14 is removed. Thereby, the SOI substrate 9 in which a plurality of openings 5 are formed in the semiconductor layer 2 is completed.

[0070] Next, in the process shown in FIG. 6(e), a protective layer 20 is formed on the surface of the semiconductor layer 2. Thereby, the entire surface of the semiconductor layer 2 can be appropriately protected. Although not limited, the protective layer 20 is, for example, a resist film.

[0071] Next, in the process shown in FIG. 6(f), a mask layer 21 is formed on the surface of the support substrate 4 corresponding to the back surface of the SOI substrate 9. Although not limited, the mask layer 21 is a resist pattern. As shown in FIG. 6(f), the mask layer 21 is not formed in the opening region 15 that is opposed to the opening 5 formed in the semiconductor layer 2 in the thickness direction, and is provided only in the peripheral region 16 (see also FIG. 1). Note that the mask layer 21 may be formed together with the mask layer 14 during the process of FIG. 6(b).

[0072] Then, in the process shown in FIG. 6(g), the support substrate 4 not covered with the mask layer 21 is removed by dry etching, and in the process shown in FIG. 6(h), the insulating layer 3 that appears by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains a form having a plurality of openings 5. Then, in the process shown in FIG. 6(i), the protective layer 20 and the mask layer 21 are removed. Thereby, the vapor deposition mask 1 is completed.

[0073] FIG. 7 is a process diagram showing a second manufacturing method of the vapor deposition mask 1 of the present embodiment. In FIG. 7(a), an SOI substrate 9 is prepared. The SOI substrate 9 has a stacked structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. Since the materials and thicknesses of each layer are described in FIG. 1, please refer to that figure.

[0074] Note that in the case of the SOI substrate 9, although the diameter is not limited, in the present embodiment, it can correspond up to about 500 mm.

[0075] Next, in the process shown in FIG. 7(b), a mask layer 21 is formed on the surface of the support substrate 4 corresponding to the back surface of the SOI substrate 9. Although not limited, the mask layer 21 is a resist pattern. Similar to FIG. 6(f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0076] Next, in the process shown in FIG. 7(c), the support substrate 4 not covered with the mask layer 21 is removed by dry etching, and in the process shown in FIG. 7(d), the insulating layer 3 that appears by removing the support substrate 4 is removed by wet etching.

[0077] Next, in the step of FIG. 7(e), a mask layer 22 is formed on the back surface of the semiconductor layer 2. Although not limited, the mask layer 22 can be formed of a resist pattern. As shown in FIG. 7(e), a plurality of openings 22a are patterned in the mask layer 22 by exposure and development.

[0078] Next, in the step of FIG. 7(f), the semiconductor layer 2 exposed from the openings 22a is etched. This etching process is dry etching. Although not limited, it is preferable to use an etching gas containing a fluorine compound and oxygen, and further optionally a rare gas.

[0079] As the fluorine compound, for example, one or more can be selected from CF4, SF6, NF3, BF3, PF5, and F2, and as the rare gas, one or more can be selected from helium and argon.

[0080] For example, dry etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus. The processing conditions were 10 to 100 sccm of CF4 gas, 0 to 100 sccm of O2 gas, 0 to 200 sccm of Ar gas, IPC power of 200 to 1000 W, RIE power of 0 to 1000 W, and chamber pressure of 1 to 10 Pa, and various conditions were adjusted.

[0081] In the step of FIG. 7(f), an opening 5 with a gradually decreasing width dimension can be formed in the semiconductor layer 2 as it moves away from the mask layer 22 side (toward the first surface 2a of the semiconductor layer 2). Thereby, the side wall surface 6 of the opening 5 can be formed as an inclined surface. Then, in the step of FIG. 7(g), the mask layer 22 is removed. Thereby, the vapor deposition mask 1 is completed.

[0082] In both the manufacturing method shown in FIG. 6 and the manufacturing method shown in FIG. 7, a plurality of openings 5 can be formed in the semiconductor layer 2, and the side wall surface 6 of the opening 5 can be formed as an inclined surface such that the opening width gradually narrows from the back surface (second surface 2b) of the semiconductor layer 2 facing the vapor deposition source 11 side toward the surface (first surface 2a) facing the substrate 10 to be vapor-deposited.

[0083] In this embodiment, although not limited thereto, the opening width W1, the variation σ of the opening, and the taper angle θ1 can be adjusted by various gas flow rates, chamber pressures, the power of the plasma generation source, and the like.

[0084] <Manufacturing method of the electronic device in this embodiment> In this embodiment, as shown in FIG. 4, the vapor deposition mask 1 is disposed between the substrate 10 to be vapor-deposited and the vapor deposition source 11. At this time, the first surface 2a side of the semiconductor layer 2 of the vapor deposition mask 1 is directed toward the substrate 10 to be vapor-deposited, and the second surface 2b side of the semiconductor layer 2 is directed toward the vapor deposition source 11 side. A plurality of openings 5 are formed in the semiconductor layer 2, and the opening width is narrower on the first surface side than on the second surface side.

[0085] The vapor deposition mask 1 is installed on a holder (not shown) of the vapor deposition apparatus, and at this time, the vapor deposition mask 1 and the substrate 10 to be vapor-deposited can be fixed by an electrostatic chuck. The vapor deposition mask 1 and the substrate 10 to be vapor-deposited are rotated with the axis center of the holder as the rotation axis.

[0086] The vapor deposition material (vapor deposition particles) 12 reaches the surface 10a of the substrate 10 to be vapor-deposited through the opening 5 of the vapor deposition mask 1 from the vapor deposition source 11, and the vapor deposition film 13 is formed.

[0087] In this embodiment, examples of the electronic device include an OLED microdisplay panel, a liquid crystal panel, a solar cell, etc. In particular, it is suitable for the manufacturing method of an OLED microdisplay panel as an organic electronic device.

[0088] By using the vapor deposition mask 1 of this embodiment, the pattern width W3 of the vapor deposition film 13 can be ensured to be 80% or more with respect to the opening width W1, preferably 85% or more, more preferably 90% or more. Thus, the vapor deposition film 13 excellent in pattern dimensions can be formed.

[0089] <Regarding the effect of using the vapor deposition mask 1 of this embodiment> In this embodiment, by setting the aperture width W1 of the opening 5 of the vapor deposition mask 1 to be greater than 3 μm and less than 15 μm, a vapor deposition film with excellent pattern dimensions and suppressed mutual influence between adjacent pixels can be stably formed.

[0090] Conventionally, the aperture width W1 has not been set from the viewpoints of pattern dimensions and mutual influence (e.g., color mixing risk) between adjacent pixels. In particular, the variation σ of the aperture width W1 has not been considered. Therefore, with the conventional control method, a vapor deposition film 13 having high pattern dimensions and low color mixing risk could not be stably formed.

[0091] In contrast, in this embodiment, by adjusting the aperture width W1 to be in the range greater than 3 μm and less than 15 μm, a vapor deposition film 13 having a pattern width W3 with a pattern width ratio of 80% or more and reduced mutual influence between adjacent pixels can be stably formed.

[0092] In this embodiment, the variation σ of the aperture width W1 can be made less than 0.09 μm, preferably in the range of 0.01 μm or more and 0.08 μm or less. Thereby, the mutual influence between adjacent pixels can be effectively reduced.

[0093] Also, in this embodiment, by adjusting the average value Ave of the uneven height difference Dn, the deposition of the vapor deposition material 12 can be suppressed, the cleaning frequency of the vapor deposition mask can be reduced, and the quality control of the vapor deposition mask can be easily performed. Also, the occurrence of clogging of the opening can be reduced, and the long life of the vapor deposition mask can be achieved. Although the embodiments and modification examples have been described, as other embodiments, those obtained by wholly or partially combining the above-described embodiments and modification examples may be used.

[0094] Furthermore, the present invention is not limited to the above-described embodiments and modifications, and may be variously changed, replaced, or modified without departing from the gist of the technical idea. Moreover, if the technical idea can be realized in another way by technological progress or another derived technology, it may be implemented using that method. Therefore, the scope of the claims covers all embodiments that can be included within the scope of the technical idea.

[0095] An embodiment with a layer structure different from the vapor deposition mask 1 shown in FIG. 1 will be described. For example, as shown in FIG. 8, a membrane 31 such as SiN or SiO2 is formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 are formed in the membrane 31 in the central region where the silicon substrate 30 has been removed, or it may be configured with a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (a silicon substrate is preferred). The membrane is formed by CVD, but it is preferable to use SiN from the viewpoint of easy stress control.

[0096] In another embodiment shown in FIGS. 9 to 11, an SOI substrate 9 is used as in FIG. 1. In FIG. 9, an SiN layer 33 is formed on the back side of the SOI substrate 9 (the side facing the support substrate 4 and the vapor deposition source 11). In FIG. 10, an SiN layer 33 is formed on the front side of the SOI substrate 9 (the side facing the semiconductor layer 2 and the substrate to be vapor-deposited 10). In FIG. 11, SiN layers 33 are formed on both the back side and the front side of the SOI substrate 9. In the configuration where the SiN layer 33 is formed on the front side (the semiconductor layer 2 side) of the SOI substrate 9, as shown in FIGS. 10 and 11, an opening 5 is formed continuously with the semiconductor layer 2.

[0097] By providing the SiN layer 33, it is easy to control the stress of the vapor deposition mask and suppress distortion and the like. Also, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is preferably thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9. Although not limited, the film thickness of the SiN layer 33 formed on the front surface side of the SOI substrate 9 is about 0.05 μm to 0.5 μm, and the film thickness of the SiN layer 33 formed on the back surface side of the SOI substrate 9 is about 0.05 μm to 3 μm. Since the semiconductor layer 2 is thinner than the support substrate 4 and a large number of openings 5 are also formed in the semiconductor layer 2, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9 in order to control stress well in balance between the front surface side and the back surface side.

Example

[0098] Hereinafter, the effects of the present invention will be described with reference to the examples and comparative examples of the present invention. Note that the present invention is not limited by the following examples.

[0099] <SOI Substrate> For the SOI substrate, a support substrate (625 μm) / insulating layer (0.5 μm) / semiconductor layer (15 μm or 5 μm) was used. The parentheses indicate the thickness. The support substrate was a Si substrate, the semiconductor layer was a Si layer, and the insulating layer was a SiO2 layer. The outer diameter of the SOI substrate was 200 mm. In the experiment, two types of SOI substrates with semiconductor layer thicknesses of 15 μm and 5 μm were prepared.

[0100] <Original Master Used> In the step (b) shown in FIG. 6, an opening pattern was formed in the mask layer (resist layer) by i-line exposure, and the opening width of the original master used when forming this opening pattern was adjusted within the range of 2.0 μm to 30 μm.

[0101] <Method for Manufacturing Evaporation Mask> The vapor deposition mask 1 was formed using the manufacturing method shown in FIG. 6. In the experiment, the opening width W1 was changed using the above-described master plate. Further, the opening width W1 and the taper angle formed in the semiconductor layer 2 were adjusted by various gas flow rates, chamber pressure, power of the plasma generation source, and the like. For example, in the dry etching shown in FIG. 6(c), anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as the mode in which isotropic dry etching using fluorine radicals was performed using SF6 gas. The processing conditions were set such that the SF6 gas was 0 to 500 sccm, the C4F8 gas was 0 to 300 sccm, the Platen LF was 0 to 1500 W, the Coil RF was 300 to 1500 W, and the chamber pressure was 1 to 10 Pa, and various conditions were adjusted.

[0102] <Regarding the dimensions of the opening 5 formed in the vapor deposition mask 1> In the experiment, the opening width W1, the variation σ, the average value Ave of the uneven height difference Dn, and the taper angle were obtained. As shown in FIG. 1, the opening width W1 was the width dimension in the plane direction along the first surface 2a of the semiconductor layer 2.

[0103] The variation σ of the opening width W1 was obtained by calculating the standard deviation σ from the opening widths W1 of 10×10 (100) adjacent openings in the vertical and horizontal directions in the central region of the vapor deposition mask 1. The opening width W1 was obtained from the SEM image obtained using the eCD-2 manufactured by KLA-Tencor.

[0104] Further, the average value Ave of the uneven height difference Dn and the taper angle were obtained from the SEM image obtained using the Regulus8220 manufactured by Hitachi High-Tech.

[0105] <Regarding the determination of the vapor deposition pattern dimensions> Using the plurality of vapor deposition masks formed above, a vapor deposition film was pattern-formed on the glass surface through the vapor deposition mask by vacuum resistance heating vapor deposition of the green light-emitting material Alq3 (tris(8-hydroxyquinoline)aluminum).

[0106] Then, the pattern width W3 of the vapor-deposited film was measured, and the pattern width ratio of the vapor-deposited film to the opening width W1 of the vapor-deposition mask ((W3 / W1)×100(%)) was determined. For experimental examples where the pattern width ratio was less than 80%, it was marked as ×; for those where the pattern width ratio was between 80% and 90%, it was marked as ○; and for those where the pattern width ratio exceeded 90%, it was marked as ◎.

[0107] <Regarding the opening variation determination> Regarding the opening variation determination, for experimental examples where the variation (standard deviation) σ of the opening width W1 was 0.08 μm or less, it was marked as ○; for those within the range of 0.09 μm to 0.10 μm, it was marked as △; and for those exceeding 0.10 μm, it was marked as ×.

[0108] Note that the descriptions of the "taper angle" shown in Tables 1 to 6 are representative values, and it was confirmed that all experimental examples were within the range of ±3° from each representative value. Tables 1 to 3 show the experimental results with a semiconductor layer thickness of 15 μm, and Tables 4 to 6 show the experimental results with a semiconductor layer thickness of 5 μm.

[0109]

Table 1

[0110]

Table 2

[0111]

Table 3

[0112]

Table 4

[0113]

Table 5

[0114]

Table 6

[0115] As shown in Tables 1 to 6, there are Experimental Examples No. 1 to No. 36, and the opening width W1 was in the range of 3 μm to 20 μm. In Experimental Examples No. 1, 7, 13, 19, 25, and 31, the determination of the vapor deposition pattern size was × or △, and all of these are comparative examples. Also, in Experimental Examples No. 5, 6, 11, 12, 18, 23, 24, 29, 30, 35, and 36, the determination of the opening variation was △ or ×, and all of these are comparative examples. The remaining experimental examples have a vapor deposition pattern size determination of ○ or ◎ and an opening variation determination of ○, and all correspond to the examples.

[0116] From this experiment, it was found that by making the opening width W1 greater than 3 μm and less than 15 μm, the deposition of the vapor deposition material 12 on the side wall surface 6 of the opening 5 can be suppressed, and a vapor deposition film with a pattern width W3 relative to the opening width W1 of 80% or more, preferably more than 90%, can be stably formed. In addition, it was found that the variation σ of the opening width W1 can be reduced, specifically, the variation σ can be set to 0.09 μm or less. In this example, it is preferable that the variation σ is 0.01 μm or more and 0.08 μm or less. Also, in this example, the needs required for the vapor deposition mask 1 provided with the semiconductor layer 2 can be ensured, and in particular, it can be preferably applied as a vapor deposition mask for RGB coating used in the manufacturing process of an OLED microdisplay.

[0117] Also, the average value Ave of the uneven height difference Dn is preferably 0.200 μm or less, more preferably 0.180 μm or less, and even more preferably 0.170 μm or less.

[0118] Also, according to the experimental results, the taper angle is preferably 60° or more, and more preferably 70° or more. Also, the lower limit value of the taper angle (tilt angle) can be less than 90°, or 88° or less. Note that for the taper angle, an error of about ±3° is allowed.

[0119] Also, it was found that the uneven angles θ2 and θ3 described in FIG. 3 can be set within a range of about 0.5° to 50°. Preferably, it is set to 10° or less, and a more preferable range is about 0.5° to 2°. Also, the uneven angle θ3 is smaller than the uneven angle θ2, and it was found that this is a form in which deposition of the vapor deposition material can be suppressed.

[0120] This application is based on Japanese Patent Application No. 2023-130556 filed on August 10, 2023. All of its contents are incorporated herein.

Claims

1. A vapor deposition mask disposed between a substrate to be vapor-deposited and a vapor deposition source, and through which a vapor deposition material from the vapor deposition source is vapor-deposited on the surface of the substrate to be vapor-deposited, having a first surface facing the substrate to be vapor-deposited and a second surface located on the side opposite to the first surface and facing the vapor deposition source, and a plurality of openings penetrating between the first surface and the second surface are formed, wherein side wall surfaces of the openings are inclined such that an opening width becomes narrower from the second surface side toward the first surface side, the opening width defined on the first surface side is greater than 3 μm and less than 15 μm, the vapor deposition mask is composed of a SOI substrate, and a SiN layer is formed on a side facing the substrate to be vapor-deposited, or a side facing the vapor deposition source, or both a side facing the substrate to be vapor-deposited and a side facing the vapor deposition source, characterized in that it is a vapor deposition mask.

2. The opening width is 4 μm or more and 10 μm or less, characterized in that it is the vapor deposition mask according to Claim 1.

3. Variation σ of the opening width is less than 0.09 μm, characterized in that it is the vapor deposition mask according to Claim 1.

4. Variation σ of the opening width is 0.01 μm or more and 0.08 μm or less, characterized in that it is the vapor deposition mask according to Claim 3.

5. The vapor deposition mask according to Claim 1 is disposed between a substrate to be vapor-deposited and a vapor deposition source such that the first surface faces the substrate to be vapor-deposited and the second surface faces the vapor deposition source, and a vapor deposition material is vapor-deposited on the surface of the substrate to be vapor-deposited through the opening, characterized in that it is a method for manufacturing an electronic device.

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