Vapor deposition mask and method for manufacturing an electronic device

Abstract

Provided are: a vapor deposition mask capable of forming a vapor deposition film having excellent pattern dimensions; and an electronic device manufacturing method that utilizes the vapor deposition mask. This vapor deposition mask is a vapor deposition mask for depositing a vapor deposition material from a vapor deposition source onto a surface of a vapor deposition substrate through an opening, the vapor deposition mask being disposed between the vapor deposition substrate and the vapor deposition source. The vapor deposition mask is characterized: by having a first surface facing the vapor deposition substrate side and a second surface positioned on the opposite side from the first surface and facing the vapor deposition source side; in that a plurality of openings penetrating the vapor deposition mask between the first surface and the second surface are formed; in that the width of each opening is greater than 3 μm and equal to or less than 5 μm; in that the side wall surface of the opening is inclined so that the opening width decreases from the second surface side toward the first surface side; and in that the taper angle of the opening is greater than 50°.

Description

Technical Field

[0001] The present invention relates to a vapor deposition mask and a method for manufacturing an electronic device.

Background Art

[0002] For example, a vapor deposition mask used for coating three colors of RGB in the production of an organic EL display is known.

[0003] Patent Document 1 discloses a configuration in which when forming a plurality of openings in a vapor deposition mask, the openings are formed by dividing them into a first part and a second part, and the first part is inclined. However, the taper angle is not disclosed.

[0004] Patent Document 2 discloses a vapor deposition mask in which the side wall surface of a grid thin film layer formed of silicon nitride is formed as an inclined surface.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] Due to the inclination of the side wall surface of the opening formed in the semiconductor layer, a problem occurs in that the vapor deposition material accumulates on the side wall surface and the pattern dimension of the vapor deposition film deteriorates.

[0007] An object of the present invention is to provide a vapor deposition mask capable of forming a vapor deposition film having excellent pattern dimensions and a method for manufacturing an electronic device using the vapor deposition mask.

Means for Solving the Problems

[0008] The vapor deposition mask of the present embodiment is disposed between a substrate to be vapor deposited and a vapor deposition source, and through the opening, the vapor deposition material from the vapor deposition source is deposited on the by vapor deposition mask for depositing on the surface of the vapor deposition substrate, It has a first surface facing the substrate to be vapor deposited and a second surface located on the opposite side of the first surface and facing the vapor deposition source side, and a plurality of openings penetrating between the first surface and the second surface are formed. The opening width is greater than 3 μm and 5 μm or less. The side wall surface of the opening is inclined so that the opening width becomes narrower from the second surface side toward the first surface side. The taper angle of the opening is greater than 50°. The vapor deposition mask is composed of an SOI substrate, and a SiN layer is formed on the side facing the substrate to be vapor deposited, or on the side facing the vapor deposition source, or on both the side facing the substrate to be vapor deposited and the side facing the vapor deposition source. This is the feature.

Advantages of the Invention

[0009] According to the present invention, by controlling the opening width of the vapor deposition mask and the taper angle of the opening, a vapor deposition film having excellent pattern dimensions can be stably formed. In addition, the cleaning frequency of the vapor deposition mask can be reduced, and the quality control of the vapor deposition mask can be easily performed. Further, the occurrence of clogging of the opening can be reduced, and the long life of the vapor deposition mask can be achieved.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and dimensions, ratios, etc. in each drawing are not necessarily the same as the actual ones. Also, even when representing the same part between the drawings, the dimensional relationships and ratios may be represented differently. In particular, the embodiments shown below are examples of structures for embodying the technical idea of the present invention, and do not specify the technical idea of the present invention. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant descriptions are omitted. Also, the lower limit value and upper limit value of the numerical range include the error range.

[0012] <Background of the Present Invention> Virtual reality / augmented reality (VR / AR) technology and the VR / AR-related market are growing rapidly. And with the progress of the growth, miniaturization of display panels suitable for the VR / AR field, high pixelization of the screen resolution (PPI: Pixels Per Inch), high-speed response, and high color gamut have advanced. In promoting the technology, the spread of silicon-based organic light-emitting diode (OLED) microdisplay panels has become remarkable.

[0013] Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. In order to effectively prepare for AR and VR as high-value-added industries, for example, it is expected to realize a display with an ultra-high resolution of 1000 ppi or more. In response to this, the need for evaporation masks for RGB coating used in the manufacturing process of OLED microdisplays is increasing.

[0014] The evaporation mask has a plurality of openings corresponding to the evaporated film, and in order to improve the pattern dimensions of the evaporated film, the opening accuracy of the evaporation mask is considered important.

[0015] The evaporation mask is disposed between the substrate to be evaporated and the evaporation source, and the evaporation material reaches the surface of the substrate to be evaporated from the evaporation source through the openings of the evaporation mask. At this time, if the evaporation material accumulates on the side wall surface of the opening, the opening width becomes narrower than the actual width, and it becomes difficult to form an evaporated film with excellent pattern dimensions.

[0016] In Patent Document 1, each opening is formed of a first portion in which the opening width gradually decreases and a second portion in which the opening width is substantially constant. It is said that such a shape can suppress the evaporation material from blocking the opening. However, Patent Document 1 does not mention the relationship between the taper angle and the deposition of the evaporation material. Further, in Patent Document 1, for example, the opening width is quite wide at 100 μm (0.1 mm) or more, and the deposition of the evaporation material at a narrow opening width in the order of several μm is not considered.

[0017] Patent Document 2 also does not describe or suggest the relationship between the opening width and taper angle and the pattern dimensions.

[0018] Therefore, as a result of intensive research by the present inventors, focusing on the opening width and taper angle, they have developed an evaporation mask capable of increasing the pattern dimensions of the evaporated film.

[0019] <Overview of the evaporation mask 1 in the present embodiment> FIG. 1 is a cross-sectional view of the vapor deposition mask 1 in the present embodiment. FIG. 2 is an enlarged cross-sectional view showing a part of the vapor deposition mask shown in FIG. 1. FIG. 3 is a partial enlarged cross-sectional view showing a part of the opening of the vapor deposition mask of the present embodiment in an enlarged manner. FIG. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the vapor deposition mask of the present embodiment.

[0020] The vapor deposition mask 1 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably composed of a SOI (Silicon on Insulator) substrate 9.

[0021] The semiconductor layer 2 is preferably a single crystal silicon layer, and is also called an active layer, a membrane, or the like. Although the thickness of the semiconductor layer 2 is not limited, it is about 1 μm to 300 μm.

[0022] As shown in FIG. 1, the vapor deposition mask 1 has a plurality of opening regions 15 and a peripheral region 16 located around the opening regions 15. In the peripheral region 16, the semiconductor layer 2, the insulating layer 3, and the support substrate 4 are laminated. On the other hand, only the semiconductor layer 2 is disposed in the opening region 15, that is, the insulating layer 3 and the support substrate 4 are removed, and a plurality of minute openings 5 are formed in each opening region 15.

[0023] FIG. 2 is an enlarged view showing the vicinity of one opening region 15 shown in FIG. 1. As shown in FIG. 2, the semiconductor layer 2 includes a first surface 2a and a second surface 2b facing each other in the thickness direction. The insulating layer 3 and the support substrate 4 are provided on the second surface 2b side.

[0024] As shown in FIG. 4, the first surface 2a is a surface facing the substrate to be vapor-deposited 10, and the second surface 2b is a back surface facing the vapor deposition source 11.

[0025] As shown in Fig. 2, a plurality of openings 5 penetrating between the first surface 2a and the second surface 2b are formed in the semiconductor layer 2. As shown in Fig. 2, the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a. Therefore, the side wall surface 6 of the opening 5 is inclined.

[0026] The planar pattern of the opening 5 (the shape seen from directly above the semiconductor layer 2 toward the first surface 2a) is not to be limited, but examples thereof include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. Also, all the openings 5 may have the same planar pattern, or some of them may be different. Further, the openings 5 may be regularly arranged, or may be irregularly arranged, or a combination of regular and irregular arrangements may be mixed.

[0027] Although the interval between adjacent openings 5 is not limited, when viewed from the first surface 2a side, the interval is about 1 μm to 20 μm.

[0028] The outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer. Although the diameter (in the case of a rectangle, the length of one side) is not limited, it is preferably about 100 mm to 500 mm. In this way, even if the diameter of the semiconductor layer 2 increases, each opening 5 can be formed uniformly.

[0029] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer, and specifically, is preferably a silicon oxide (SiO2) layer. The insulating layer 3 is also called a BOX layer (Buried Oxide Layer). Although the thickness of the insulating layer 3 is not limited, it is, for example, about 100 nm to 20 μm.

[0030] The insulating layer 3 shown in Fig. 1 is not provided in the opening region facing the opening 5 of the semiconductor layer 2 and is removed, and remains only in the peripheral region of the opening region on the second surface 2b of the semiconductor layer 2. The insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and having the insulating layer 3 enables stable processing.

[0031] The support substrate 4 shown in FIG. 1 is a semiconductor substrate, for example, a silicon substrate. Although the thickness of the support substrate 4 is not limited, it is, for example, about 100 μm to 1000 μm.

[0032] As shown in FIG. 1, the support substrate 4 can function as a columnar portion 16a and an outer peripheral frame 16b that surround the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be maintained in a stretched state by the support substrate 4, eliminating the need for a stretching process, and the vapor deposition mask 1 of the present embodiment can be adhered to the substrate to be vapor-deposited 10 using an electrostatic chuck that utilizes electrostatic force. As shown in FIG. 1, the columnar portion 16a is located inside the outer peripheral frame 16b, and they all have the same length (height). However, for example, the height of the columnar portion 16a may be made lower than that of the outer peripheral frame. However, keeping the heights the same can maintain greater strength.

[0033] Also, although not shown in FIGS. 1 and 2, alignment marks for alignment can be formed in the outer peripheral region on the first surface 2a side of the semiconductor layer 2. The alignment marks can be formed, for example, in a concave shape on the first surface 2a and can be formed to a depth that penetrates to the insulating layer 3.

[0034] <Detailed description of the opening 5 of the vapor deposition mask 1 in the present embodiment> In the present embodiment, the opening width W1 of the opening 5 and the taper angle θ1 of the opening 5 are defined. [Method for calculating the opening width W1] As shown in FIG. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. Therefore, as shown in FIG. 2, the opening width W1 is obtained as the dimension in the plane direction along the first surface 2a where it is the narrowest. Note that the opening width W1 can be obtained from an SEM image obtained using an eCD-2 manufactured by KLA-Tencor.

[0035] [Method for calculating the taper angle θ1 of the opening 5] In this embodiment, the taper angle θ1 of the opening 5 is obtained as follows. That is, as shown in FIG. 2, the end of the opening width W1 in the plane direction along the first surface 2a and the end of the opening width W2 in the plane direction along the second surface 2b are connected by a straight line, and the inclination angle between the straight line and the first surface 2a can be set as the taper angle θ1 of the opening 5. The taper angle θ1 was obtained by length measurement from the SEM image obtained using Regulus 8220 manufactured by Hitachi High-Tech.

[0036] FIG. 3 is a partially enlarged cross-sectional view showing an enlarged view of one opening 5 formed in the vapor deposition mask 1, and shows an extracted intermediate portion in the height direction (thickness direction of the semiconductor layer 2) of the opening 5. Although the reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side of the drawing, the cross-sectional shape is symmetric about the vertical axis, and the side wall surface 6 on the right side of the drawing has the same configuration.

[0037] As shown in FIG. 3, the side wall surface 6 of the opening 5 is formed in an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding in the inner direction of the opening 5 and recesses 8 located between the convex portions 7 are continuously and repeatedly formed along the height direction of the opening 5.

[0038] In FIG. 3, only two pitches are shown and described. In FIG. 3, reference numerals 7a and 7b are attached to distinguish the two convex portions 7. When viewed from each of the convex portions 7a and 7b, the recess 8 located on the first surface 2a side (upper side in the drawing) is combined with the half pitch. Further, reference numerals 8a and 8b are attached to distinguish the two recesses 8. Let the convex portion 7a and the recess 8a be the first half pitch P1, and the convex portion 7b and the recess 8b be the second half pitch P2. Note that the pitch refers to the distance between convex portions or the distance between recesses, and half of that distance is defined as the half pitch.

[0039] As shown in FIG. 3, an approximate straight line T1 connecting the lowest positions (bottom A) of the respective recesses 8a and 8b within the measurement range was drawn. The bottom A is, for example, the position farthest when viewed from the center line O in the width direction of the opening 5. The approximate straight line T1 can be obtained by the least squares method. When an irregular recess 8 is formed within the measurement range (for example, when the bottom A is extremely low), the approximate straight line T1 can be drawn excluding that recess 8.

[0040] As shown in FIG. 3, the inclination angle θ4 of the side wall surface 6 can be obtained from the inclination angle between the approximate straight line T1 shown in FIG. 3 and the first surface 2a.

[0041] The above-described taper angle θ1 and inclination angle θ4 are the same or approximate, but for example, depending on the state of the uneven shape of the side wall surface 6 and the way of taking the pitch, the inclination of the approximate straight line T1 changes, and there is a possibility that the taper angle θ1 and the inclination angle θ4 deviate. Therefore, the inclination of the side wall surface 6 was determined by measuring the taper angle θ1 of the opening 5.

[0042] [Calculation method of uneven height difference] In the present embodiment, in addition to the above-described opening width W1 and taper angle θ1, the uneven height difference can be obtained. The uneven height difference can be obtained as follows.

[0043] As shown in FIG. 3, at the first half pitch P1, the highest position (top) B of the convex portion 7a was obtained. The top B is the position closest when viewed from the center line O in the width direction of the opening 5. Then, as shown in FIG. 3, a straight line S1 orthogonal to the approximate straight line T1 was drawn so as to intersect the top B. The length of the straight line S1 from the approximate straight line T1 to the top B was obtained. The length of this straight line S1 was defined as the uneven height difference D1 at the first half pitch P1.

[0044] For the second half pitch P2 and other half pitches, the uneven height difference can be obtained in the same manner as that determined for the first half pitch P1. That is, a straight line perpendicular to the approximate straight line T1 is drawn, and the straight-line length to the top B of each convex portion is obtained, and this straight-line length is regarded as the uneven height difference for each pitch. Incidentally, Fig. 3 shows the uneven height difference D2 of the second half pitch P2.

[0045] As described above, a plurality of uneven height differences can be obtained. When measuring for five pitches, five uneven height differences Dn (n = 1 to 5) are calculated. Then, the average value Ave of these uneven height differences Dn is obtained.

[0046] Although not limited, at an intermediate location exactly at the center of the thickness between the first surface 2a and the second surface 2b of the opening 5, the uneven shape for five pitches was measured in length by SEM. Note that although not limited to five pitches, if the number of pitches is too small, parameter noise becomes large, and if the number of pitches is too large, depending on the thickness, it may not be possible to secure that number of pitches. Also, since it takes time to calculate the parameters and becomes complicated, it is preferably about several pitches to within ten pitches. In this embodiment, basically, it is measured at five pitches, but if that is difficult, the number of pitches can be appropriately set and changed.

[0047] Also, instead of the above-described concept of pitch, for example, five locations where the height can be confirmed at the center of the thickness may be measured in length by SEM images. In this case, portions with height can be regarded as convex portions, and the spaces therebetween can be regarded as concave portions.

[0048] Note that fine unevenness may be formed on the surfaces of the respective concave portions 8a, 8b (or the bottom portions of the convex portions 7a, 7b). However, these fine unevenness can be ignored. For example, fine unevenness with a wavelength in the order of several nm or smaller can be cut off, a wavy curve can be created, and a tangent line and the uneven height difference can be obtained.

[0049] [Calculation method of uneven angles θ2, θ3] In this embodiment, when limiting the concavo-convex shape of the side wall surface 6, the concavo-convex angle θ2 can be obtained together with the above-described concavo-convex height difference.

[0050] As shown in FIG. 3, the concavo-convex angle θ2 can be obtained as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest (the farthest when viewed from the center line O in the width direction of the opening 5) bottom A of the concave portion 8a located on the side of the substrate 10 to be vapor-deposited (the upper side in the drawing) as viewed from the convex portion 7a, and an approximate straight line T1. Further, as shown in FIG. 3, the concavo-convex angle θ3 can be obtained as the angle between a straight line L2 connecting the top B of the convex portion 7a and the lowest (the farthest when viewed from the center line O in the width direction of the opening 5) bottom A of the concave portion 8b located on the side of the vapor deposition source 11 (the lower side in the drawing, see FIG. 4) as viewed from the convex portion 7a, and the approximate straight line T1.

[0051] That the concavo-convex angles θ2 and θ3 are small means that the height of the convex portion 7 is low (the depth of the concave portion 8 is shallow) and the undulation of the side wall surface 6 is small.

[0052] <Regarding the characteristic configuration of the opening parameters in this embodiment> The vapor deposition mask 1 in this embodiment (1) The opening width W1 is greater than 3 μm and less than or equal to 5 μm, (2) The side wall surface 6 of the opening 5 is inclined so that the opening width becomes narrower from the second surface 2b facing the vapor deposition source 11 side to the first surface 2a facing the substrate 10 to be vapor-deposited, and the taper angle θ1 of the opening 5 is greater than 50°, which is characterized.

[0053] Thus, in this embodiment, the opening width W1 is set in the range greater than 3 μm and less than or equal to 5 μm. The opening width W1 is preferably 4 μm or more and 5 μm or less, and more preferably in the range of 4.5 μm or more and 5 μm or less. Thereby, the needs required for the vapor deposition mask 1 provided with the semiconductor layer 2 can be ensured, and in particular, it can be preferably applied as a vapor deposition mask for RGB coating used in the manufacturing process of an OLED microdisplay.

[0054] In the present embodiment, the side wall surface 6 of the opening is inclined so that the opening width becomes narrower from the second surface 2b to the first surface 2a. Thereby, the vapor deposition film 13 having a desired pattern width W3 can be stably formed. That is, the size control of the vapor deposition film 13 can be facilitated. Further, when the vapor deposition material 12 deposited on the side wall surface 6 is peeled off from the side wall surface 6, it can be made difficult to fly toward the vapor deposition substrate 10 side. Further, from the viewpoint of manufacturing, by inclining the side wall surface 6 of the opening 5, a plurality of openings 5 can be efficiently formed in the semiconductor layer 2 by deep etching.

[0055] On the other hand, when the taper angle θ1 is up to about 90°, that is, when the side wall surface 6 is formed substantially vertically, it is considered that the influence of the uneven height difference Dn of the side wall surface 6 during vapor deposition becomes large. In particular, in the present embodiment, since the opening width W1 is extremely narrow at several μm, it is necessary to minimize the average value Ave and the maximum value of the uneven height difference Dn as much as possible. There is also a relationship with the thickness of the semiconductor layer 2. That is, as the thickness of the semiconductor layer 2 increases, it becomes difficult to form the side wall surface 6 as a vertical surface.

[0056] In the present embodiment, in order to obtain excellent vapor deposition results without being affected by the uneven shape of the side wall surface 6, the side wall surface 6 is inclined, and at this time, the taper angle θ1 of the opening 5 is set to be greater than 50°. The upper limit value of the taper angle θ1 is less than 90°, preferably 88° or less, and more preferably 85° or less. The taper angle θ1 includes an error of about ±3°.

[0057] In this way, by defining both the opening width W1 and the taper angle θ1, it becomes possible to make the pattern width of the vapor deposition film formed using the vapor deposition mask 1 80% or more of the opening width W1 of the vapor deposition mask 1.

[0058] FIG. 4 is a cross-sectional view showing the vapor deposition mask 1 of the present embodiment disposed between the vapor deposition substrate 10 and the vapor deposition source 11, and shows one step of a method for manufacturing an electronic device.

[0059] As shown in FIG. 4, the vapor deposition material (vapor deposition particles) 12 from the vapor deposition source 11 passes through the opening 5 of the vapor deposition mask 1 and reaches the surface 10a of the substrate 10 to be vapor deposited, and the vapor deposition film 13 is formed. When the pattern width W3 of the vapor deposition film 13 is measured and the ratio to the opening width W1 is calculated, if the combination of the opening width W1 and the taper angle θ1 is such that the pattern width ratio ((pattern width W3 / opening width W1)×100(%)) is 80% or more, it is an example of this embodiment, and when it is less than 80%, the combination of the opening width W1 and the taper angle θ1 is taken as a comparative example.

[0060] The vapor deposition mask 1 of this embodiment can form the side wall surface 6 as an inclined surface by the manufacturing method described later. At this time, when the taper angle θ1 becomes small, the vapor deposition material 12 is likely to deposit on the side wall surface 6, but by defining the taper angle θ1 according to the opening width W1, a range having a pattern width ratio of 80% or more was found. Here, the reason for setting the required pattern ratio to 80% or more is that if it is less than 80%, the deviation from the pattern width W3 of the desired vapor deposition film 13 is too large, leading to a decrease in yield, and it also leads to a decrease in the area to emit light at the design position such as the coordinate position accuracy, resulting in a decrease in the luminance of the light emitting element itself, or it is a numerical value required for product quality assurance. To increase the production efficiency, the pattern width ratio is set to 85% or more, preferably 90% or more, more preferably 95% or more.

[0061] In this embodiment, it is preferable that the opening width W1 is 4 μm or more and 5 μm or less, and the taper angle θ1 is 60° or more. Thereby, the pattern width ratio can be effectively made 80% or more. Also, it is preferable that the opening width W1 is 4 μm or more and 5 μm or less, and the taper angle θ1 is 70° or more. Thereby, it becomes possible to obtain an embodiment in which the pattern width ratio exceeds 90%.

[0062] Conventionally, there has been no mention of the combination of both the taper angle θ1 and the opening width W1 of the opening 5 that can improve the pattern width ratio when the opening width W1 is narrowed to several μm.

[0063] Next, regarding the concavo-convex shape of the side wall surface 6 of the opening 5, in the present embodiment, although not particularly limited, as an example, it can be adjusted as follows.

[0064] That is, the average value Ave of the concavo-convex height difference Dn is preferably 0.200 μm or less, more preferably 0.180 μm or less, and even more preferably 0.170 μm or less. Also, although not limiting the lower limit value of the average value Ave of the concavo-convex height difference Dn, for example, it can be set to about 0.003 μm.

[0065] By adjusting the average value Ave of the concavo-convex height difference Dn within the above range, the deposition of the vapor deposition material 12 on the side wall surface 6 of the opening 5 can be minimized as much as possible, and more effectively, the number of cleaning times of the vapor deposition mask 1 can be reduced, and the life of the vapor deposition mask 1 can be extended.

[0066] Also, the maximum value of the concavo-convex height difference Dn is preferably 0.300 μm or less, more preferably 0.250 μm or less, even more preferably 0.200 μm or less, and most preferably 0.100 μm or less. The maximum value of the concavo-convex height difference Dn is the maximum concavo-convex height difference obtained when the concavo-convex height difference Dn is obtained for the plurality of pitches described in FIG. 3.

[0067] Also, the concavo-convex angles θ2 and θ3 described in FIG. 3 are in the range of about 0.5° to 50°, preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less. By being able to reduce the concavo-convex angles θ2 and θ3, the protruding height of the convex portion 7 can be reduced, or the interval between adjacent convex portions 7 can be widened (the range of the concave portion 8 can be widened), and the deposition of the vapor deposition material 12 on the side surface of the convex portion 7 can be suppressed. Note that the most preferable range of the concavo-convex angles θ2 and θ3 is about 0.5° to 2°. Also, the concavo-convex angle θ3 shown in FIG. 3 is preferably smaller than the concavo-convex angle θ2. Thereby, the deposition of the vapor deposition material 12 on the side wall surface 6 can be suppressed.

[0068] <Manufacturing Method of Evaporation Mask 1 in this Embodiment> FIG. 5 is a process diagram showing a first manufacturing method of the evaporation mask 1 of this embodiment. Here, the evaporation mask 1 in the manufacturing process shown in FIG. 5 and FIG. 6 described later shows only the vicinity of one opening region 15, similar to FIG. 2. Actually, a plurality of opening regions 15 shown in FIG. 1 are formed simultaneously. In FIG. 5(a), an SOI substrate 9 is prepared. The SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. Since the materials and thicknesses of each layer were described in FIG. 1, please refer to that for details.

[0069] In the case of the SOI substrate 9, although the diameter is not limited, in this embodiment, it can support up to about 500 mm.

[0070] In FIG. 5(b), a mask layer 14 is patterned on the surface of the semiconductor layer 2. The mask layer 14 is preferably a resist and can be patterned by exposure and development. A plurality of through holes 14a are formed in the mask layer 14. These through holes 14a are opening patterns for forming the opening 5 in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed with a dimension of about 2 μm to 6 μm.

[0071] Next, in FIG. 5(c), the semiconductor layer 2 exposed from the through holes 14a of the mask layer 14 is dry-etched. In this embodiment, the semiconductor layer 2 is deep-etched. In a so-called Bosch process, for example, it is preferable to use a method of repeatedly etching Si with SF6 and generating a polymer film with C4F8 to deeply dig silicon and alternately progress sidewall protection and bottom etching. By the Bosch process, the side wall surface 6 of the opening 5 formed in the semiconductor layer 2 has an uneven shape.

[0072] At this time, as shown in FIG. 5(c), the composition, flow rate, internal pressure of the etching chamber, power of the high-frequency power supply, etc. of the etching gas are appropriately adjusted so as to form an inverse taper surface. Further, by these adjustments, the inclination angle of the inverse taper surface (taper angle θ1 of the opening 5) and the control of the uneven height difference Dn can be performed.

[0073] For example, in a dry etching apparatus, a Bosch process was performed using SF6 gas and C4F8 gas alternately. By applying a bias to the substrate to be etched using the same gas as in the mode of performing isotropic dry etching using fluorine radicals with SF6 gas, anisotropic dry etching using fluorine ions was performed. The processing conditions were as follows: SF6 gas at 0 - 500 sccm, C4F8 gas at 0 - 300 sccm, Platen LF at 0 - 1500 W, Coil RF at 300 - 1500 W, and chamber pressure at 1 - 10 Pa, and various conditions were adjusted.

[0074] By the above-described Bosch process, a plurality of openings 5 can be formed with deep trenches in the semiconductor layer 2, and at this time, the taper angle θ1 and the uneven height difference of the side wall surface 6 of the opening 5 can be appropriately adjusted.

[0075] In the present embodiment, to reduce the uneven height difference Dn, in addition to adjusting the conditions in the above-described etching process, for example, after deep trench etching of silicon, it can also be achieved by performing a smoothing process (a process for reducing the uneven height difference) by laser hydrogen annealing treatment.

[0076] Next, in the process shown in FIG. 5(d), the mask layer 14 is removed. As a result, the SOI substrate 9 in which a plurality of openings 5 are formed in the semiconductor layer 2 is completed.

[0077] Next, in the process shown in FIG. 5(e), a protective layer 20 is formed on the surface of the semiconductor layer 2. As a result, the entire surface of the semiconductor layer 2 can be appropriately protected. Although not limited, the protective layer 20 is, for example, a resist film.

[0078] Next, in the process shown in FIG. 5(f), a mask layer 21 is formed on the surface of the support substrate 4 corresponding to the back surface of the SOI substrate 9. Although not limited, the mask layer 21 is a resist pattern. As shown in FIG. 5(f), the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the semiconductor layer 2 in the thickness direction, and is provided only in the peripheral region 16 (see also FIG. 1). Note that the mask layer 21 may be formed together with the mask layer 14 during the process of FIG. 5(b).

[0079] Then, in the process shown in FIG. 5(g), the support substrate 4 not covered by the mask layer 21 is removed by dry etching, and in the process shown in FIG. 5(h), the insulating layer 3 exposed by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains a form having a plurality of openings 5.

[0080] Then, in the process shown in FIG. 5(i), the protective layer 20 and the mask layer 21 are removed. Thereby, the vapor deposition mask 1 is completed.

[0081] FIG. 6 is a process diagram showing a second manufacturing method of the vapor deposition mask 1 according to the present embodiment. In FIG. 6(a), an SOI substrate 9 is prepared. The SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. Since the materials and thicknesses of each layer are described in FIG. 1, please refer to that.

[0082] In the case of the SOI substrate 9, although not limited to the diameter, in the present embodiment, it can correspond up to about 500 mm.

[0083] Next, in the process shown in FIG. 6(b), a mask layer 21 is formed on the surface of the support substrate 4 corresponding to the back surface of the SOI substrate 9. Although not limited, the mask layer 21 is a resist pattern. Similar to FIG. 5(f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0084] Next, in the process shown in FIG. 6(c), the support substrate 4 not covered by the mask layer 21 is removed by dry etching, and in the process shown in FIG. 6(d), the insulating layer 3 exposed by removing the support substrate 4 is removed by wet etching.

[0085] Next, in the process of FIG. 6(e), a mask layer 22 is formed on the back surface of the semiconductor layer 2. Although not limited thereto, the mask layer 22 can be formed of a resist pattern. As shown in FIG. 6(e), a plurality of openings 22a are formed in the mask layer 22 by exposure and development.

[0086] Next, in the process of FIG. 6(f), the semiconductor layer 2 exposed from the opening 22a is etched. This etching process is dry etching, and although not limited thereto, it is preferable to use an etching gas containing a fluorine compound and oxygen, and further optionally a rare gas.

[0087] The fluorine compound can be selected from one or more of, for example, CF4, SF6, NF3, BF3, PF5, and F2, and the rare gas can be selected from one or more of helium and argon.

[0088] For example, dry etching was performed using a dry etching apparatus with CF4 gas, O2 gas, and Ar gas. The processing conditions were 10 - 100 sccm for CF4 gas, 0 - 100 sccm for O2 gas, 0 - 200 sccm for Ar gas, 200 - 1000 W for IPC power, 0 - 1000 W for RIE power, and 1 - 10 Pa for chamber pressure, and various conditions were adjusted.

[0089] In the process of FIG. 6(f), an opening 5 whose width dimension gradually decreases can be formed in the semiconductor layer 2 as it moves away from the mask layer 22 (toward the first surface 2a of the semiconductor layer 2). Thereby, the side wall surface 6 of the opening 5 can be formed as an inclined surface. Then, in the process of FIG. 6(g), the mask layer 22 is removed. Thereby, the vapor deposition mask 1 is completed.

[0090] In any of the manufacturing methods shown in FIG. 5 and the manufacturing method shown in FIG. 6, a plurality of openings 5 can be formed in the semiconductor layer 2, and the side wall surface 6 of the opening 5 can be formed as an inclined surface such that the opening width gradually becomes narrower from the back surface (second surface 2b) of the semiconductor layer 2 facing the vapor deposition source 11 side toward the surface (first surface 2a) facing the substrate 10 to be vapor-deposited.

[0091] In the present embodiment, although not limited thereto, the opening width W1 and the taper angle θ1 can be adjusted by various gas flow rates, chamber pressure, and power of the plasma generation source, etc.

[0092] <Manufacturing Method of Electronic Device in the Present Embodiment> In the present embodiment, as shown in FIG. 4, the vapor deposition mask 1 is disposed between the substrate 10 to be vapor-deposited and the vapor deposition source 11. At this time, the first surface 2a side of the semiconductor layer 2 of the vapor deposition mask 1 faces the substrate 10 to be vapor-deposited, and the second surface 2b side of the semiconductor layer 2 faces the vapor deposition source 11 side. A plurality of openings 5 are formed in the semiconductor layer 2, and the opening width is narrower on the first surface 2a side than on the second surface 2b side.

[0093] The vapor deposition mask 1 is installed on a holder (not shown) of the vapor deposition apparatus, and at this time, the vapor deposition mask 1 and the substrate 10 to be vapor-deposited can be fixed by an electrostatic chuck. The vapor deposition mask 1 and the substrate 10 to be vapor-deposited are rotated with the axis center of the holder as the rotation axis.

[0094] The vapor deposition material (vapor deposition particles) 12 reaches the surface 10a of the substrate 10 to be vapor-deposited through the opening 5 of the vapor deposition mask 1 from the vapor deposition source 11, and the vapor deposition film 13 is formed.

[0095] In the present embodiment, examples of the electronic device include an OLED microdisplay panel, a liquid crystal panel, a solar cell, etc. In particular, it is suitable for the manufacturing method of an OLED microdisplay panel as an organic electronic device.

[0096] By using the vapor deposition mask 1 of the present embodiment, the pattern width W3 of the vapor deposition film 13 can be ensured to be 80% or more, preferably 90% or more, more preferably 95% or more, with respect to the opening width W1. Thus, a vapor deposition film 13 with excellent pattern dimensions can be formed.

[0097] <Regarding the effect of using the vapor deposition mask 1 of the present embodiment> In the present embodiment, by setting the opening width W1 of the opening 5 of the vapor deposition mask 1 to be greater than 3 μm and less than or equal to 5 μm, and making the taper angle θ1 of the opening 5 greater than 50°, a high pattern dimension of the vapor deposition film 13 can be obtained.

[0098] In the present embodiment, by setting the opening width W1 to be 4 μm or more and 5 μm or less, and making the taper angle θ1 of the opening 5 60° or more, a vapor deposition film 13 having a pattern width ratio of 80% or more can be stably formed.

[0099] Conventionally, the unevenness formed on the side wall surface 6 of the opening 5 was uniformly defined by roughness or the like where the vapor deposition material was difficult to deposit, but the taper angle θ1 was not adjusted. However, it has been found that with a narrow opening width W1 in the order of several μm, the pattern width ratio varies greatly due to the change in the taper angle θ1. Therefore, with the conventional control method, a vapor deposition film 13 having a high pattern dimension cannot be stably formed for a narrow opening width in the order of several μm.

[0100] In contrast, in the present embodiment, by combining the two factors of the opening width W1 and the taper angle θ1, as described above, a vapor deposition film 13 having a pattern width W3 with a pattern width ratio of 80% or more can be stably formed.

[0101] According to the vapor deposition mask 1 of the present embodiment, the deposition of the vapor deposition material 12 can be suppressed, the cleaning frequency of the vapor deposition mask can be reduced, and the quality control of the vapor deposition mask can be easily performed. In addition, the occurrence of clogging of the opening can be reduced, and the long life of the vapor deposition mask can be achieved.

[0102] Although the embodiments and modifications have been described, as another embodiment, those obtained by wholly or partially combining the above-described embodiments and modifications may be used.

[0103] Further, the present invention is not limited to the above-described embodiments and modifications, and various changes, substitutions, and modifications may be made without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in another way by technological progress or another derived technology, the method may be used for implementation. Therefore, the scope of the claims covers all embodiments that can be included within the scope of the technical idea.

[0104] An embodiment having a layer structure different from that of the vapor deposition mask 1 shown in FIG. 1 will be described. For example, as shown in FIG. 7, a membrane 31 made of SiN, SiO2, or the like is formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 are formed in the membrane 31 in the central region from which the silicon substrate 30 has been removed, or a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (preferably a silicon substrate) may be used. The membrane is formed by CVD, but SiN is preferably used from the viewpoint of easy stress control.

[0105] In another embodiment shown in FIGS. 8 to 10, an SOI substrate 9 is used as in FIG. 1. In FIG. 8, a SiN layer 33 is formed on the back surface side of the SOI substrate 9 (the support substrate 4 side, the side facing the vapor deposition source 11), in FIG. 9, a SiN layer 33 is formed on the front surface side of the SOI substrate 9 (the semiconductor layer 2 side, the side facing the substrate to be vapor-deposited 10), and in FIG. 10, SiN layers 33 are formed on both the back surface side and the front surface side of the SOI substrate 9. In the configuration in which the SiN layer 33 is formed on the front surface side (semiconductor layer 2 side) of the SOI substrate 9, as shown in FIGS. 9 and 10, the opening 5 is formed continuously with the semiconductor layer 2.

[0106] By providing the SiN layer 33, it is easy to control the stress of the vapor deposition mask and suppress distortion and the like. Also, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is preferably thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9. Although not limited, the film thickness of the SiN layer 33 formed on the front surface side of the SOI substrate 9 is about 0.05 μm to 0.5 μm, and the film thickness of the SiN layer 33 formed on the back surface side of the SOI substrate 9 is about 0.05 μm to 3 μm. Since the semiconductor layer 2 is thinner than the support substrate 4 and a large number of openings 5 are also formed in the semiconductor layer 2, the SiN layer 33 formed on the front surface side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back surface side of the SOI substrate 9 in order to control stress well in a balanced manner between the front surface side and the back surface side.

Example

[0107] Hereinafter, the effects of the present invention will be described with reference to examples and comparative examples of the present invention. Note that the present invention is not limited by the following examples.

[0108] <SOI substrate> For the SOI substrate, a support substrate (625 μm) / insulating layer (0.5 μm) / semiconductor layer (15 μm or 5 μm) was used. The parentheses indicate the thickness. The support substrate was a Si substrate, the semiconductor layer was a Si layer, and the insulating layer was a SiO2 layer. The outer diameter of the SOI substrate was 200 mm. In the experiment, two types of SOI substrates with semiconductor layer thicknesses of 15 μm and 5 μm were prepared.

[0109] <Original master used> In the steps (b) shown in FIG. 5 and the step (e) shown in FIG. 6, an opening pattern is formed in the mask layer (resist layer) by i-line exposure. The opening width of the original master used when forming this opening pattern was adjusted within the range of 2.0 μm to 6.0 μm.

[0110] <Method for manufacturing evaporation mask> The vapor deposition mask 1 was formed using the manufacturing method shown in FIGS. 5 and 6. In the experiment, the opening width W1 was changed using the above-described original plate for use. Also, the opening width W1 formed in the semiconductor layer 2 and the taper angle θ1 of the side wall surface 6 were adjusted by the switching conditions of SF6 and C4F8, the gas flow rate under non-switching conditions, the chamber pressure, and the power of the plasma generation source. For example, in the dry etching of FIG. 5(c), anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as in the mode of performing isotropic dry etching using fluorine radicals using SF6 gas. The processing conditions were SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.

[0111] Also, in the dry etching shown in FIG. 6(f), CF4 gas was 10 to 100 sccm, O2 gas was 0 to 100 sccm, Ar gas was 0 to 200 sccm, IPC power was 200 to 1000 W, RIE power was 0 to 1000 W, and chamber pressure was 1 to 10 Pa, and various conditions were adjusted.

[0112] <Regarding the dimensions of the opening 5 formed in the vapor deposition mask 1> In the experiment, the opening width W1, the taper angle θ1 of the side wall surface 6, the average value Ave of the uneven height difference Dn, and the maximum value of the uneven height difference Dn were obtained. As shown in FIG. 2, the opening width W1 was the width dimension in the plane direction along the first surface 2a of the semiconductor layer 2. The opening width W1 can be obtained from the SEM image obtained using the eCD-2 manufactured by KLA-Tencor.

[0113] The uneven height difference Dn and the taper angle θ1 were obtained by the method described in FIGS. 2 and 3 from the SEM image obtained using the Regulus8220 manufactured by Hitachi High-Tech. As described in FIG. 3, at the middle part of the height of the opening, five pitches at the center of the thickness of the uneven shape formed on the side wall surface 6 were observed and obtained. For the detailed method of obtaining the uneven height difference Dn and the taper angle θ1, refer to the description parts of FIGS. 2 and 3.

[0114] <Regarding the determination of the vapor deposition pattern dimensions> Using the plurality of vapor deposition masks formed above, the green light-emitting material Alq3 (tris(8-hydroxyquinoline)aluminum) was vapor-deposited on the glass surface through the vapor deposition mask by the vacuum resistance heating vapor deposition method to form a vapor deposition film pattern.

[0115] Then, the pattern width W3 of the vapor deposition film was measured, and the length was measured with a laser microscope (model number VK-X210 (manufactured by Keyence)), and the pattern width ratio of the vapor deposition film to the opening width W1 of the vapor deposition mask ((W3 / W1)×100(%)) was obtained. For the experimental examples where the pattern width ratio is less than 70%, it is marked as ×; for the experimental examples where the pattern width ratio is 70% - 80%, it is marked as △; for the experimental examples where the pattern width ratio is 80% - 90%, it is marked as ○; for the experimental examples where the pattern width ratio is more than 90%, it is marked as ◎. The experimental results are shown in Table 1 and Table 2 below. Note that the "taper angle" shown in Table 1 and Table 2 is described in units of 10°, but this is a representative value, and it was confirmed that all experimental examples are within the range of ±3° from each representative value. Table 1 shows the experimental results when the thickness of the semiconductor layer is 15μm, and Table 2 shows the experimental results when the thickness of the semiconductor layer is 5μm.

[0116]

Table 1

[0117]

Table 2

[0118] As shown in Table 1 and Table 2, there are Experimental Examples No. 1 to No. 24, and the opening width W1 was in the range of 3 μm to 5 μm. In Experimental Examples No. 1, 5, 13, and 17 where the opening width W1 was 3 μm or 4 μm and the taper angle θ1 was 50°, the pattern width ratio was less than 70%, and the evaluation was ×. Also, in Experimental Examples 2 to 4, 14 to 16 where the opening width W1 was 3 μm and the taper angle θ1 was 60° to 80°, and in Experimental Examples 9 and 21 where the opening width W1 was 5 μm and the taper angle θ1 was 50°, the pattern width ratio was 70% to 80% in all cases, and the evaluation was △. Thus, the experimental examples where the evaluation of the pattern width ratio is × or △ are comparative examples. On the other hand, Experimental Examples No. 6 to No. 8, No. 10 to No. 12, No. 18 to No. 20, and No. 22 to No. 24 correspond to the examples, as the evaluation of the pattern width ratio is ○ or ◎.

[0119] From this experiment, it was found that by setting the opening width W1 to be greater than 3 μm and less than or equal to 5 μm, and by setting the taper angle θ1 to be greater than 50°, the deposition of the vapor deposition material 12 on the side wall surface 6 of the opening 5 can be suppressed, and a vapor deposition film with a pattern width W3 of 80% or more with respect to the opening width W1 can be formed. In this example, the needs required for the vapor deposition mask 1 provided with the semiconductor layer 2 can be ensured. In particular, to preferably apply it as a vapor deposition mask for RGB painting used in the manufacturing process of an OLED microdisplay, the opening width W1 was set to be 4 μm or more and 5 μm or less, and the taper angle θ1 was set to be 60° or more. Thereby, a vapor deposition film with a stable pattern width ratio of 80% or more can be formed. Also, by setting the opening width W1 to be 4.5 μm or more and 5 μm or less, and by setting the taper angle θ1 to be 70° or more, a vapor deposition film with a pattern width ratio exceeding 90% can be stably formed.

[0120] Also, the average value Ave of the uneven height difference Dn is preferably 0.200 μm or less, more preferably 0.180 μm or less, and even more preferably 0.170 μm or less. Also, the lower limit value of the average value Ave of the uneven height difference Dn is 0.100 μm or more and 0.130 μm or more.

[0121] Further, the maximum value of the uneven height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, still more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.300 μm or less. Also, the uneven angle θ2 described in FIG. 3 was 11° to 41°.

[0122] This application is based on Japanese Patent Application No. 2023-130555 filed on August 10, 2023. All of its contents are incorporated herein by reference.

Claims

1. A vapor deposition mask disposed between a substrate to be vapor-deposited and a vapor deposition source, for vapor-depositing a vapor deposition material from the vapor deposition source onto the surface of the substrate to be vapor-deposited through an opening, having a first surface facing the substrate to be vapor-deposited and a second surface located on the opposite side of the first surface and facing the vapor deposition source side, and a plurality of openings penetrating between the first surface and the second surface are formed, the opening width is greater than 3 μm and not more than 5 μm, the side wall surface of the opening is inclined so that the opening width becomes narrower from the second surface side toward the first surface side, the taper angle of the opening is greater than 50°, the vapor deposition mask is composed of an SOI substrate, and a SiN layer is formed on the side facing the substrate to be vapor-deposited, or on the side facing the vapor deposition source, or on both the side facing the substrate to be vapor-deposited and the side facing the vapor deposition source, characterized in that it is a vapor deposition mask.

2. The taper angle is 60° or more, characterized in that it is the vapor deposition mask according to Claim 1.

3. The taper angle is 70° or more, characterized in that it is the vapor deposition mask according to Claim 1.

4. The opening width is 4 μm or more and 5 μm or less, characterized in that it is the vapor deposition mask according to Claim 1.

5. The opening width is defined by the opening width on the first surface side, characterized in that it is the vapor deposition mask according to Claim 1.

6. Dispose the vapor deposition mask according to Claim 1 between the substrate to be vapor-deposited and the vapor deposition source, and vapor-deposit the vapor deposition material onto the surface of the substrate to be vapor-deposited through the opening, characterized in that it is a method for manufacturing an electronic device.

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