Meta-Table Avoidance Synchronization Circuit

Abstract

To output incorrect data, which is a mixture of old and new data in multiple bits, as post-synchronization data.SOLUTION: A metastable avoidance synchronization circuit includes: a phase synchronization unit that generates a 2n multiplied clock by multiplying a clock by 2n (n: positive integer); a shift register that sequentially takes in input data consisting of multiple bits in synchronization with the 2n multiplied clock; an invalid data removal EN generation circuit that detects the occurrence of invalid data in the process in which the input data taken into the shift register is sequentially shifted and generates an enable signal that becomes active during periods other than the period in which the invalid data is output from the shift register; and a final stage flip-flop that latches and outputs the multiple bits of data output from the shift register in synchronization with the clock on the condition that the enable signal is active.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a metastable state avoidance type synchronization circuit, a metastable state avoidance type synchronization method, and a program.

Background Art

[0002] Communication devices used in the field of electric and electronic communications may be configured using different clocks by dividing them into different logic circuit modules for each function in order to realize various functions. In such a communication device, in order to transfer asynchronous signals between logic circuit modules, a synchronization circuit for synchronizing the asynchronous signals is required.

[0003] However, if the rising and falling timings of the signal input to the synchronization circuit and the clock are close to each other, a metastable state may occur in which the signal level continues at an intermediate voltage between the thresholds of "L" and "H", and the output signal may become unstable. Therefore, for asynchronous inputs, even if a metastable state occurs, measures are required so as not to affect the circuit operation.

[0004] As a metastable state avoidance type synchronization circuit having a synchronization function that avoids the metastable state, when performing asynchronous transfer between clocks of different frequencies between logic circuit modules, a flip-flop (hereinafter referred to as FF) operating with the receiving side clock having a two-stage configuration has been proposed (for example, paragraph 0004 of Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the synchronization circuit with the FF two-stage configuration described above, when the input signal is composed of multiple bits, a state occurs in which old and new data are mixed in multiple bits after the metastable state stabilizes, and such incorrect output data may be output as the synchronized data.

[0007] An object of the present invention is to provide a metastable state avoidance type synchronization circuit that solves the above-described problems, that is, the problem that incorrect data in which old and new data are mixed in multiple bits may be output as synchronized data.

Means for Solving the Problems

[0008] A metastable state avoidance type synchronization circuit according to an aspect of the present invention includes: A phase synchronization unit that generates a multiplied clock (n: a positive integer) by multiplying a clock by 2; n A shift register that sequentially captures input data composed of multiple bits in synchronization with the multiplied clock by 2; n An illegal data removal EN generation circuit that detects the generation of illegal data in the process of sequentially shifting the input data captured by the shift register and generates an enable signal that becomes active during a period other than the period in which the illegal data is output from the shift register; A final stage flip-flop that latches and outputs the multiple-bit data output from the shift register in synchronization with the clock on the condition that the enable signal is active; n A final stage flip-flop that latches and outputs the multiple-bit data output from the shift register in synchronization with the clock on the condition that the enable signal is active; An illegal data removal EN generation circuit that detects the generation of illegal data in the process of sequentially shifting the input data captured by the shift register and generates an enable signal that becomes active during a period other than the period in which the illegal data is output from the shift register; A final stage flip-flop that latches and outputs the multiple-bit data output from the shift register in synchronization with the clock on the condition that the enable signal is active; It is configured to include.

[0009] Further, a metastable state avoidance type synchronization method according to another aspect of the present invention includes: Generating a multiplied clock (n: a positive integer) by multiplying a clock by 2; n Sequentially shifting input data composed of multiple bits in synchronization with the multiplied clock by 2; n Generating a multiplied clock (n: a positive integer) by multiplying a clock by 2; Sequentially shifting input data composed of multiple bits in synchronization with the multiplied clock by 2; n Sequentially shifting input data composed of multiple bits in synchronization with the multiplied clock by 2; Detecting the generation of illegal data in the process of sequentially shifting the input data, and generating an enable signal that becomes active during a period other than the period when the illegal data is output; Latching and outputting the multi-bit data obtained by sequentially shifting the input data in synchronization with the clock on the condition that the enable signal is active; It is configured to include.

[0010] Also, a program according to another aspect of the present invention, To a computer of a metastable state avoidance type synchronization circuit, Doubling (n: positive integer) the clock to generate a doubled clock; n Doubling the clock by a factor of 2 n Generating a doubled clock; Sequentially shifting input data composed of multiple bits in synchronization with the doubled clock; n Detecting the generation of illegal data in the process of sequentially shifting the input data, and generating an enable signal that becomes active during a period other than the period when the illegal data is output; Latching and outputting the multi-bit data obtained by sequentially shifting the input data in synchronization with the clock on the condition that the enable signal is active; Causing it to execute. It is configured to cause the above to be executed.

Advantages of the Invention

[0011] By having the configuration as described above, the present invention can prevent illegal data in which old and new data are mixed in multiple bits from being output as synchronized data.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

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Figure 6

[0013] [First Embodiment] Next, the first embodiment of the present invention will be described in detail with reference to the drawings. In the first embodiment of the present invention, the synchronization of output DATA_OUT controlled by an output side clock having a higher frequency than the input side clock is described for multi-bit input DATA_IN controlled by an input side clock of a certain frequency. For the sake of convenience of explanation, in the block diagram, it is described as an n + 1-bit signal, and in the timing diagram, it is described as a 2-bit signal of [1:0].

[0014] [Explanation of Configuration] FIG. 1 is a block diagram showing an example of a metastable state avoidance type synchronization circuit according to the first embodiment of the present invention. The metastable state avoidance type synchronization circuit according to the present embodiment includes a PLL (Phase Locked Loop) 110, a shift register 120, an illegal data removal enable signal generation circuit (hereinafter referred to as an illegal data removal EN generation circuit) 140, and a final stage FF 170.

[0015] Based on the clock CLK1, the PLL 110 generates an x1 clock 111 with the same frequency as the clock CLK1 and an 8-fold clock 112 with a frequency eight times that of the clock CLK1. The x1 clock 111 generated by the PLL 110 is output to the final-stage FF 170. The 8-fold clock 112 generated by the PLL 110 is output to the shift register 120 and the invalid data removal EN generation circuit 140. The PLL 110 is also referred to as a phase-locked section.

[0016] The shift register 120 is a three-stage shift register that sequentially captures a multi-bit input signal, the DATA_IN[n:0] signal, in synchronization with the 8-fold clock 112. Among the signals inside the shift register 120, 121 is the synchronization FF first-stage passing signal of DATA_IN[0], 122 is the synchronization FF second-stage passing signal of DATA_IN[0], 123 is the synchronization FF third-stage passing signal of DATA_IN[0], 131 is the synchronization FF first-stage passing signal of DATA_IN[n], 132 is the synchronization FF second-stage passing signal of DATA_IN[n], and 133 is the synchronization FF third-stage passing signal of DATA_IN[n]. In FIG. 1, only the FFs corresponding to the least significant bit and the most significant bit of the DATA_IN[n:0] signal and their outputs among the FFs of each stage constituting the shift register 120 are illustrated. Also, the second-stage signal 162 of the shift register 120 is the synchronization FF second-stage passing signals 122, ···, 132 of DATA_IN[n:0] and is output to the invalid data removal EN generation circuit 140. Also, the third-stage (final stage) signal 163 of the shift register 120 is the synchronization FF second-stage passing signals 123, ···, 133 of DATA_IN[n:0] and is output to the invalid data removal EN generation circuit 140 and the final-stage FF 170.

[0017] The invalid data removal EN generation circuit 140 operates in synchronization with the 8-fold clock 112, and based on the second-stage signal 162 and the third-stage signal 163 of the shift register 120, generates an enable signal 155 for removing invalid data caused by the presence or absence of a metastable state for each bit and outputs it to the final-stage FF 170.

[0018] The final stage FF170 is an FF for converting the DATA_IN[n:0] signal to the timing synchronized with the finally required clock CLK1. Each FF constituting the final stage FF170 has a clock input terminal, an enable terminal (hereinafter referred to as an EN terminal), an input terminal, and an output terminal. The x1 clock 111 is input to the clock input terminal, the enable signal 155 output from the invalid data removal EN generation circuit 155 is input to the EN terminal, and the output signal 163 of the shift register 120 is input to the input terminal. Also, the DATA_OUT[n:0] signal synchronized with the clock CLK1 is output from the output terminal of each FF constituting the final stage FF170.

[0019] Figure 2 is a block diagram showing an example of the invalid data removal EN generation circuit 140. The invalid data removal EN generation circuit 140 in this example includes a comparator 141 and an enable signal generation circuit (hereinafter referred to as an EN generation circuit) 142.

[0020] The comparator 141 inputs the second-stage signal 162 and the third-stage signal 163 from the shift register 120, and is configured to determine whether the value of any bit of the DATA_IN[n:0] signal has changed between the second stage and the third stage of the shift register 120. The comparator 141 includes an EXOR circuit that takes the exclusive logical sum of the second-stage signal and the third-stage signal for each bit of the DATA_IN[n:0] signal, and an AND circuit that takes the logical product of the outputs 151,..., 152 of all the EXOR circuits. The output 153 of the AND circuit is output to the EN generation circuit 142 as the output of the comparator 141.

[0021] The EN generation circuit 142 inputs the output 153 of the comparator 141, and generates and outputs a signal 155 for removing invalid data by detecting that a plurality of bits of the DATA_IN[n:0] signal have changed at different timings. The EN generation circuit 142 includes an FF that generates a signal 154 obtained by shifting the output 153 of the comparator 141 by one clock of the 8-fold clock 112, and an OR gate that takes the logical sum of this signal 154 and the output 153 of the comparator 141.

[0022] Next, before explaining the operation of the metastable state avoidance type synchronization circuit according to the present embodiment, the operation of the two-stage configuration synchronization circuit mentioned in the background art will be explained.

[0023] FIG. 3 is a timing diagram of synchronization of multi-bit data by a two-stage configuration synchronization circuit. For convenience of explanation, the DATA_IN[n:0] signal is assumed to be a 2-bit wide DATA_IN[1:0] signal. Also, the case where the DATA_IN[1:0] signal switches from 00 (LL) to 11 (HH) is taken as an example.

[0024] Referring to FIG. 3, when the DATA_IN[1:0] signal is taken into the first-stage FF by the clock CLK1 at the timing of T10, a metastable state is generated by the asynchronous clock-to-clock signal. Bit [0] stabilizes on the "H" side, and bit [1] stabilizes on the "L" side. As a result, at the timing of T20, the output of the second-stage FF that is latched has bit [0] stabilizing on the new data side and bit [1] stabilizing on the old data side, resulting in incorrect data with a one-clock difference between the two. Referring to FIG. 3, the correct DATA_OUT signal after synchronization can be obtained from the second-stage FF after the timing of T30. The period from the timing of T20 to the timing of T30 is a period in which new and old data are mixed.

[0025] Thus, in a two-stage configuration synchronization circuit, in order to prevent the capture of incorrect data, it is necessary to capture the DATA_OUT signal after a sufficient time has elapsed, and the delay amount increases.

[0026] Next, the operation of the metastable state avoidance type synchronization circuit according to the present embodiment will be explained.

[0027] In FIG. 1, first, based on the clock CLK1, the PLL110 generates a x1 clock 111 and an 8-fold clock 112.

[0028] The input signal, the DATA_IN signal, is sequentially captured into the three-stage shift register 120 in synchronization with the 8-fold clock 112.

[0029] From the shift register 120, for example, in the case of bit [0], the second-stage signal 122 and the third-stage signal 123 of the shift register are sent to the illegal data removal EN generation circuit 140. Also, in the case of bit [n], the second-stage signal 132 and the third-stage signal 133 of the shift register are sent to the illegal data removal EN generation circuit 140. The same applies to the remaining other bits.

[0030] The illegal data removal EN generation circuit 140 generates an illegal data removal EN signal 155 synchronized with the 8-fold clock 112. The operation at this time will be described later.

[0031] The final-stage FF 170 replaces the data at a timing synchronized with the finally required clock CLK1. By setting the data update condition of this final-stage FF 170 to the illegal data removal EN signal 155 = "L", the outflow of illegal data to the subsequent stage is prevented. Since the final-stage FF 170 is in a synchronous relationship with the illegal data removal EN signal 155, it is a single-stage FF.

[0032] Referring to FIG. 2, the operation of the illegal data removal EN generation circuit 140 will be described. The second-stage signal 122 and the third-stage signal 123 of bit [0] of the shift register 120 are input to the corresponding EXOR gate of the comparator 141. Then, the output 151 of the EXOR gate becomes "L" only when the second-stage signal 122 is "H" and the third-stage signal 123 is "L", or when the second-stage signal 122 is "L" and the third-stage signal 123 is "H". That is, the output 151 becomes "L" when bit [0] changes from "L" to "H" or from "H" to "L", and becomes "H" when there is no such change.

[0033] Also, the second-stage signal 132 and the third-stage signal 133 of bit [n] of the shift register 120 are input to the corresponding EXOR gates of the comparator 141. Then, the output 152 of the EXOR gate becomes "L" only when the second-stage signal 132 is "H" and the third-stage signal 133 is "L", or when the second-stage signal 132 is "L" and the third-stage signal 133 is "H". That is, the output 152 becomes "L" when bit [n] changes from "L" to "H" or from "H" to "L", and becomes "H" when there is no such change.

[0034] For the remaining bits other than bit [0] and [n] of the shift register 120, signals that become "L" only when they change in the same way as the outputs 151 and 152 are generated by the corresponding EXOR gates.

[0035] The signals 151, ···, 152 that become "L" when there is a change generated for each bit are input to the AND gate of the comparator 141, and the logical product signal 153 of all bits is generated there. This logical product signal 153 is a signal that becomes "L" when there is a change in any bit. Next, by taking the logical sum of this signal 153 and the signal 154 obtained by shifting this signal by 1T with the 8-fold clock 112 using an OR gate, a signal 155 that becomes "L" when there is a change in any bit for 2T continuously is generated. Then, this signal 155 is used as the illegal data removal EN signal.

[0036] The multi-bit data when there is a change in any bit for 2T continuously indicates that it switches as old value → data with a mixture of old and new for each bit due to the influence of the metastable state (illegal data) → new value. The "illegal data removal EN signal" generated above becomes a signal that is "L" (inactive) only during this illegal data period. In other words, the "illegal data removal EN signal" is a signal that is "H" (active) during periods other than the illegal data period.

[0037] FIG. 4 is an example of a timing diagram of the metastable state avoidance type synchronization circuit according to the present embodiment. In FIG. 4, similar to FIG. 3, the case where the 2-bit wide data DATA_IN[1:0] switches from 00 to 11 is taken as an example.

[0038] Referring to FIG. 4, at the timing of T10, when the DATA_IN[1:0] signal is captured by the clock 112, a metastable state due to the asynchronous clock interval signal occurs, and the output 121 of the first stage of the shift register of bit [0] stabilizes to "H", and the output 131 of the first stage of the shift register of bit [1] stabilizes to "L".

[0039] The signal 121 that stabilizes to "H" of bit [0] becomes signals 122 and 123 by the subsequent two-stage shift register.

[0040] The signal 151 becomes "L" between T11 - T12 where the values of the signals 122 and 123 are different according to the logic of the comparator 141 in FIG. 2.

[0041] Similarly, the signal 131 that stabilizes to "L" of bit [1] becomes signals 132 and 133 by the subsequent two-stage shift register.

[0042] The signal 152 becomes "L" between T12 - T13 where the values of the signals 132 and 133 are different according to the logic of the comparator 141 in FIG. 2.

[0043] The signal 153 is a signal obtained by ANDing the signals 151 and 152, and is a signal that becomes "L" between T11 - T13.

[0044] The EN generation circuit 142 in FIG. 2 takes the OR of the signal 153 and the signal 154 shifted by one clock to generate the signal 155. Therefore, the signal 155 is a signal that becomes "L" for only 1T when different bits change at different timings.

[0045] In Figure 4, signal 161 is the signal of the first stage of the shift register for DATA_IN[1:0], signal 162 is the signal of the second stage of the shift register for DATA_IN[1:0], and signal 163 is the signal of the third stage of the shift register for DATA_IN[1:0]. The period from T12 to T13 when the value of signal 163 becomes "01" becomes incorrect data in which old and new data are mixed, and at this timing and the same timing, signal 155 becomes "L".

[0046] The DATA_OUT[1:0] signal is the output of the final stage FF170 in Figure 1, and is generated by latching signal 163 on the condition that signal 155 = "H" at the timing of T20 which is the rising timing of clock CLK1. As a result, the clock transfer from the DATA_IN signal to the DATA_OUT signal synchronized with clock CLK1 is completed.

[0047] Figures 5 and 6 are timing diagrams of different timings of the switching of DATA_IN[1:0]. Among them, Figure 5 is a timing diagram when the switching of DATA_IN[1:0] occurs at the timing of T15 which is 5T slower than the timing of T10 in Figure 4 by clock 122. When incorrect data due to the influence of the metastable state is detected at the timing as shown in Figure 5, since the timing of T20 becomes incorrect data, data update is not performed at the timing of T20, and new data is updated at the timing of T30.

[0048] Figure 6 is a timing diagram when the switching of DATA_IN[1:0] occurs at the timing of T14 which is 4T slower than the timing of T10 in Figure 4 by clock 122. Even when incorrect data due to the influence of the metastable state is detected at the timing as shown in Figure 6, since new data is determined at the timing of T20, data update is performed at the timing of T20.

[0049] That is, as described with reference to FIG. 3, in the synchronization circuit with a two-stage flip-flop configuration, it takes a time of 2T with the clock CLK1 from T10 to T30 until synchronization is completed. However, in the synchronization circuit according to the present embodiment, synchronization can be completed in a time of 0.5T with the clock CLK1 from the shortest T14 to T20.

[0050] [Other Embodiments of the Invention] As described above, the present invention has been described with reference to the embodiments of the present invention. However, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

[0051] For example, in the above embodiment, the shift register 120 and the illegal data removal EN generation circuit 140 were operated in synchronization with the 8-fold clock of the clock CLK1. However, the shift register 120 and the illegal data removal EN generation circuit 140 may generally be operated in synchronization with the 2 n -fold clock (n is a positive integer) of the clock CLK1. For example, by further increasing the multiplication factor more than the 8-fold clock (n = 3), such as the 16-fold clock (n = 4), it is possible to shorten the time until synchronization is completed compared to the above embodiment.

[0052] Also, the shift register 120 is not limited to a three-stage configuration and may have four or more stages.

[0053] Also, the metastability avoidance type synchronization circuit may have a computer system inside. And the above-described processing process is stored in a computer-readable recording medium in the form of a program, and by the computer reading and executing this program, the above processing by the metastability avoidance type synchronization circuit may be performed. The computer can be composed of, for example, a CPU (Central Processing Unit), main memory, storage, and interface, but is not limited thereto.

[0054] Alternatively, instead of the CPU described above, a GPU (Graphic Processing Unit), DSP (Digital Signal Processor), MPU (Micro Processing Unit), FPU (Floating number Processing Unit), PPU (Physics Processing Unit), TPU (Tensor Processing Unit), quantum processor, microcontroller, or a combination thereof can be used.

Industrial Applicability

[0055] It can be used for synchronization circuits in general to avoid the influence of metastability that may occur during asynchronous transfer between logic circuit modules operating at different clock frequencies.

Explanation of Signs

[0056] 110 PLL 111 Clock with the same frequency as clock CLK1 112 Clock that is 8 times the frequency of clock CLK1 120 Shift register 121 Signal after passing through the first stage of synchronization FF for DATA_IN[0] 122 Signal after passing through the second stage of synchronization FF for DATA_IN[0] 123 Signal after passing through the third stage of synchronization FF for DATA_IN[0] 131 Signal after passing through the first stage of synchronization FF for DATA_IN[n] 132 Signal after passing through the second stage of synchronization FF for DATA_IN[n] 133 Signal after passing through the third stage of synchronization FF for DATA_IN[n] 140 Illegal data removal EN generation circuit 155 Illegal data removal EN signal 170 Final stage FF

Claims

1. 2 times the output clock with a higher frequency compared to the input clock n multiplied by 2 (n: positive integer) n a phase synchronization unit that generates a multiplied clock, Input data composed of a plurality of bits synchronized with the input-side clock to the 2 n A three-stage shift register that sequentially captures in synchronization with the multiplication clock Detect the occurrence of illegal data during the process in which the input data captured by the shift register is sequentially shifted, and generate an enable signal that becomes active during a period other than the period in which the illegal data is output from the shift register, an illegal data removal EN generation circuit; A one-stage final-stage flip-flop that latches and outputs the multi-bit data output from the shift register in synchronization with the output-side clock on the condition that the enable signal is active; Comprising: The illegal data removal EN generation circuit: A comparator that detects whether or not the value of any bit has changed between the second-stage signal and the third-stage signal of the shift register; An EN generation circuit that generates the enable signal as a logical sum signal of the output of the comparator and a signal obtained by shifting the output of the comparator by one clock with the 2n multiplication clock; A metastable state avoidance type synchronization circuit comprising:

2. Wherein n is 3; The metastable state avoidance type synchronization circuit according to Claim 1. **Claim 3**: Doubling (n: positive integer) an output clock having a higher frequency compared to the input clock to generate a doubled clock. n Doubling (n: positive integer) n to generate a doubled clock, Input data composed of a plurality of bits synchronized with the input-side clock is sequentially shifted into a three-stage shift register synchronized with the multiplication clock, and n sequentially shifted into a three-stage shift register synchronized with the multiplication clock. Detect the occurrence of illegal data during the process in which the input data is sequentially shifted into the shift register, and generate an enable signal that becomes active during a period other than the period in which the illegal data is output from the shift register; Latch and output the multi-bit data output from the shift register to a one-stage final-stage flip-flop in synchronization with the output-side clock on the condition that the enable signal is active; Including: In the generation of the enable signal: Detect whether or not the value of any bit has changed between the second-stage signal and the third-stage signal of the shift register; A metastable state avoidance type synchronization method including generating, as the enable signal, a logical sum signal of the detection output of whether or not the change has occurred and a signal obtained by shifting the detection output of whether or not the change has occurred by one clock with the 2n multiplication clock.

4. On a computer of a metastable state avoidance type synchronization circuit, Output clock having a higher frequency than the input clock is doubled by 2 n doubled by n (n: positive integer) by 2 n generate a multiplied clock, and Input data composed of a plurality of bits synchronized with the input-side clock is sequentially shifted into a three-stage shift register synchronized with the multiplication clock. n ​ Detect the occurrence of illegal data during the process in which the input data is sequentially shifted into the shift register, and generate an enable signal that becomes active during a period other than the period in which the illegal data is output from the shift register; Latch and output the multi-bit data output from the shift register to the final-stage flip-flop of one stage in synchronization with the output-side clock on the condition that the enable signal is active. Cause to execute In the generation of the enable signal, Detect whether or not the value of any bit has changed between the second-stage signal and the third-stage signal of the shift register. A program that causes to execute generating the enable signal as a logical sum signal of the detection output of whether or not the change has occurred and a signal obtained by shifting the detection output of whether or not the change has occurred by one clock with the 2n multiplication clock.

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