Process for creating a composite structure comprising a thin layer of single crystal SiC on a carrier substrate of crystalline SiC

Abstract

The present invention relates to a process for producing a composite structure (1) comprising a thin layer (10) of monocrystalline silicon carbide on a silicon carbide carrier substrate (20). The process comprises the steps of: a) providing an initial substrate (11) of monocrystalline silicon carbide; b) epitaxially growing a donor layer (110) of monocrystalline silicon carbide on the initial substrate (11) to form a donor substrate (111); c) forming a buried brittle plane (12) in the donor layer (110); d) forming a silicon carbide carrier substrate (20) on the free surface of the donor layer (110), comprising deposition at temperatures between 400°C and 1100°C; e) separating along the buried brittle plane (12) to form a composite structure (1) on the one hand and a donor substrate remnant (111') on the other hand; and f) mechanically and / or chemically processing the composite structure (1).

Description

Technical Field

[0001] The present invention relates to the field of semiconductor materials for microelectronic components. More particularly, the present invention relates to a process for creating a composite structure comprising a thin layer of single-crystalline silicon carbide on a carrier substrate of crystalline, and in particular polycrystalline, silicon carbide.

Background Art

[0002] Interest in silicon carbide (SiC) has increased considerably over the last few years. This is because this semiconductor material can increase the ability to process energy. SiC is increasingly used extensively for the creation of innovative power devices, in particular to meet the requirements of emerging fields of electronic devices such as electric vehicles.

[0003] Power devices and integrated power supply systems based on single-crystalline silicon carbide can manage much higher power densities compared to their traditional silicon counterparts and can do so using smaller active area dimensions. To further limit the dimensions of SiC power devices, it is advantageous to create vertical rather than lateral components. For this to be the case, vertical electrical conduction must be permitted by the SiC structure between an electrode arranged on the front face of the SiC structure and an electrode arranged on the back face.

[0004] However, single-crystalline SiC substrates intended for the microelectronics industry remain expensive and difficult to supply in large sizes. Therefore, it is advantageous to utilize thin-layer transfer solutions to create composite structures typically comprising a thin layer of single-crystalline SiC on a non-expensive carrier substrate. A well-known thin-layer transfer solution is the Smart Cut™ process, which is based on the implantation of light ions and structuring by direct bonding. This type of process enables, for example, the creation of a composite structure comprising a thin layer of c-SiC taken from a single-crystalline SiC (c-SiC) donor substrate in direct contact with a carrier substrate of polycrystalline SiC (p-SiC), the composite structure enabling vertical electrical conduction. However, it remains difficult to achieve high-quality direct bonding by molecular adhesion between the two substrates of c-SiC and p-SiC. The reason is that the management of the roughness and surface state of the substrates is complex.

[0005] Various methods resulting from this process are also known from the prior art. For example, F. Mu et al. (ECS Transactions, 86(5)3-21, 2018) perform direct bonding after activating the surface to be joined by irradiation with argon ("surface-activated bonding" or SAB): such treatment prior to bonding generates a very high density of dangling bonds, which promote the formation of covalent bonds at the structured interface and thus a high bonding energy. However, this method has the drawback of generating an amorphous layer on the surface of the single-crystalline SiC donor substrate, which has an adverse effect on the vertical electrical conduction between the thin layer of c-SiC and the carrier substrate of p-SiC.

[0006] A solution to this problem has been proposed in more detail in the document, European Patent No. 3168862, which uses the implantation of dopant species into the amorphous layer to restore the electrical properties of the amorphous layer. The main drawback of this approach is its complexity and thus its cost.

[0007] The document, U.S. Patent No. 8,436,363, is also known. U.S. Patent No. 8,436,363 describes a process for creating a composite structure comprising a thin layer of c-SiC disposed on a metallic carrier substrate, where the coefficient of thermal expansion of the metallic carrier substrate matches that of the thin layer. This creation process involves forming an embedded brittle plane within the c-SiC donor substrate, where the embedded brittle plane defines the boundary of the thin layer between the embedded brittle plane and the front surface of the donor substrate, depositing a layer of metal, such as tungsten or molybdenum, on the front surface of the donor substrate to form a carrier substrate having a thickness sufficient to serve as a stiffener, separating along the embedded brittle plane to form, on the one hand, a composite structure comprising a metallic carrier substrate and a thin layer of c-SiC, and on the other hand, a residue of the c-SiC donor substrate and includes.

[0008] However, this type of creation process is incompatible when the material for forming the carrier substrate is p-SiC and requires deposition at temperatures higher than 1200 °C (the normal temperature for p-SiC creation). More specifically, at these high temperatures, the growth rate of the cavities present within the embedded brittle plane is faster than the growth rate of the p-SiC layer, and before blistering begins, it does not reach the thickness required for the stiffening effect, which is related to the deformation of the layers aligned perpendicular to the cavities.

[0009] Regardless of the layer transfer technique used, a further problem that arises is that of providing a composite structure comprising a very high-quality thin c-SiC layer, and more specifically, one having no extended defects (or having such defects with a very low density), as extended defects tend to have an adverse effect on the performance and reliability of the power devices created on said thin layer. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] The present invention relates to an alternative solution to the prior art solutions and aims to overcome the above disadvantages, wholly or in part. More particularly, the present invention relates to a process for creating a composite structure comprising a high-quality thin c-SiC layer disposed on a crystalline SiC carrier substrate.

Means for Solving the Problems

[0011] The present invention relates to a process for creating a composite structure comprising a thin layer of single-crystalline silicon carbide disposed on a carrier substrate of silicon carbide. The process comprises a) providing an initial substrate of single-crystalline silicon carbide; b) epitaxially growing a donor layer of single-crystalline silicon carbide on the initial substrate to form a donor substrate, the donor layer having a lower crystal defect density than the initial substrate; c) ion implanting a light species into the donor layer to form an embedded brittle plane, the embedded brittle plane defining a boundary of a thin layer between the embedded brittle plane and the free surface of the donor layer; d) forming a carrier substrate of silicon carbide on the free surface of the donor layer, including deposition at a temperature between 400 °C and 1100 °C and defining a non-insulating interface between the donor layer and the carrier substrate; e) separating along the embedded brittle plane to form, on the one hand, the composite structure and, on the other hand, the residue of the donor substrate; f) mechanically and / or chemically treating the composite structure to smooth the free surface of the thin layer and correct the film thickness uniformity of the composite structure. and includes.

[0012] According to other advantageous and non-limiting features of the present invention, adopted singly or in any technically feasible combination, The deposition of step d) is carried out at a temperature between 600 °C and 900 °C, and more preferably between 700 °C and 800 °C, based on a chemical vapor deposition technique or a sintering technique or a liquid phase deposition technique using a solution of ceramic powder; The deposition of step d) is a chemical vapor deposition assisted by direct liquid injection. The deposition of step d) is a plasma enhanced or low pressure chemical vapor deposition; The deposition of step d) is carried out at a rate faster than 10 microns / hour, and more preferably faster than 50 microns / hour; At the end of the deposition of step d), the carrier substrate has a thickness of 50 microns or more, and further a thickness of 100 microns or more; Step a) includes the formation of a single crystal conversion layer on the initial substrate in order to convert the basal plane dislocation defects of the initial substrate into through-edge transition defects; The epitaxial growth step b) is carried out at a temperature higher than 1200 °C, preferably between 1500 °C and 1650 °C; The light species implanted during step c) are selected from hydrogen and / or helium; The separation step e) acts at a temperature higher than the temperature of the deposition of step d); The separation step e) acts by applying mechanical stress to a laminate comprising a carrier substrate joined to a donor substrate; Step f) includes chemical-mechanical simultaneous polishing of the front and back surfaces of the composite structure; The process includes a step of heat treatment at a temperature between 1000 °C and 1800 °C, before or after step f); The process includes a second step g) of epitaxially growing additional single crystal silicon carbide on a thin layer of the composite structure; The process includes a step of readjusting the residue of the donor substrate in order to reuse the residue of the donor substrate as the initial substrate or as the donor substrate; The residue of the donor substrate is reused at least twice as a new donor substrate.

[0013] Other features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2a

Figure 2b

Figure 2c

Figure 2d

Figure 2e

Figure 2f

Figure 2g

Figure 3a

Figure 3b

Best Mode for Carrying Out the Invention

[0015] In this description, the same reference numerals in the figures may be used for the same type of elements. The figures are schematic representations not drawn to a fixed scale for ease of reading. More specifically, the thickness of the layers along the z-axis does not follow a fixed scale with respect to the lateral dimensions along the x-axis and y-axis, and the relative thicknesses of the layers with respect to each other are not necessarily respected in the figures.

[0016] The present invention relates to a process for creating a composite structure 1 comprising a thin layer 10 of single crystal silicon carbide disposed on a carrier substrate 20 of silicon carbide (Figure 1). The carrier substrate 20 is crystalline and preferably polycrystalline (hereinafter "p-SiC" is used to refer to polycrystalline SiC).

[0017] The process initially includes a step a) of providing an initial substrate 11 of single crystal silicon carbide (Figure 2a). Throughout the remainder of the description, "c-SiC" is used to refer to single crystal silicon carbide.

[0018] The initial substrate 11 preferably takes the form of a wafer having a diameter of 100 mm or 150 mm, or even 200 mm, and a thickness typically between 300 microns and 800 microns. The initial substrate 11 has a front surface 11a and a back surface 11b. The surface roughness selected for the front surface 11a is advantageously less than 1 nm Ra, the average roughness measured by atomic force microscopy (AFM) for a 20 micron × 20 micron scan.

[0019] The process then includes a step b) of epitaxially growing a single crystal silicon carbide donor layer 110 on the initial substrate 11 to form a donor substrate 111 (Figure 2b). The epitaxial growth step is carried out such that the donor layer 110 has a lower crystal defect density than the initial substrate 11.

[0020] The initial substrate 11 of c-SiC is typically of the 4H or 6H polytype, with an orientation reduction ("offcut") of less than 4.0° with respect to the <11-20> crystal axis by ±0.5°, and a threading dislocation ("micro-pipe") density of 5 / cm 2 or less, or even 1 / cm 2 or less. When doped with N (nitrogen), the initial substrate 11 preferably exhibits a resistivity between 0.015 ohm.cm and 0.030 ohm.cm. The initial substrate 11 selected typically has 3000 / cm 2It may have the following low basal plane dislocation (BPD) defect density: 1500 / cm 2 c-SiC substrates with a BPD density on the order of 2 are reasonably available, making it easier to supply them.

[0021] At the end of the process of the present invention, for a vertical component intended to have a donor layer 110 on which a c-SiC thin layer 10 of the composite structure 1 will be formed therefrom to meet the required specifications, it is desirable to have a crystal quality higher than that of the initial substrate 11. Various types of extended defects are present in the c-SiC layer or substrate. These extended defects may have an adverse effect on the performance and reliability of the component. More specifically, BPD defects are fatal for bipolar components: The reason is that when the recombination energy of electron-hole pairs is available, Shockley stacking faults (SSF) expand from the dislocations. The expansion of SSF stacking defects within the active region of the component results in an increase in the resistance of the component in the on state.

[0022] Therefore, the c-SiC donor layer 110 is created to have a BPD defect density of 2 below.

[0023] For this reason, the epitaxial growth step b) is carried out at a temperature higher than 1200 °C, preferably between 1500 °C and 1650 °C. The precursor used is monosilane (SiH4), propane (C3H8), or ethylene (C2H4); the carrier gas may be argon or hydrogen with or without argon.

[0024] The low BPD defect rate in the donor layer 110 is obtained by promoting the conversion of the BPD defects existing in the initial substrate 11 into through-thickness edge dislocations, i.e., TEDs.

[0025] According to one specific embodiment, step a) preferably includes the formation of a single crystal conversion layer 13 of c-SiC (FIG. 3a) in order to maximize the conversion of BPD defects in the initial substrate 11 into TED defects. For this purpose, for the initial substrate 11 of c-SiC, a low off-cut angle of approximately 4° is selected, its in-situ etching realized before epitaxial growth is increased, a high growth rate (typically higher than 5 μm / hour) is targeted, and finally, it is advantageous to select the growth conditions of the single crystal conversion layer 13 having a C / Si ratio in a precursor flow of approximately 1.

[0026] Step b) then involves performing epitaxial growth of the donor layer 110 on the conversion layer 13 (FIG. 3b). According to this specific embodiment, 1 / cm 2 less than or even 0.1 / cm 2 It is also possible to obtain a donor layer 110 of c-SiC having a smaller BPD defect density. Furthermore, at the end of the process according to the present invention, the probability of bipolar degradation (the probability that holes reach below the BPD / TED conversion point) is negligible (<0.1%). The reason is that the single crystal conversion layer 13 is not intended for transfer into the composite structure 1. Prior art having the goal of reducing bipolar degradation includes integrating a recombination layer (doped with more than 1 E 18 at / cm 3 nitrogen) between the conversion layer and the active layer. At the expense of a thickness of 10 μm and a concentration higher than 5 E 18 / cm 3 This recombination layer can reduce the probability of the presence of holes to 0.1% with respect to the base structure not including this recombination layer. In the present invention, since the single crystal conversion layer 13 cannot be transferred, the probability that holes reach the nucleation point of bipolar degradation (the BPD-TED conversion point or any BPD point) is at least less than 0.1%, or even approximately 0%.

[0027] The conventional sequence of cleaning or etching the initial substrate 11, aimed at removing possibly present particulate matter, metals or organic contaminants, or part or all of the native oxide layer on the front 11a, may be implemented prior to the epitaxial growth step b).

[0028] The fabrication process according to the invention further comprises a step c) of ion implantation of light species into the donor layer 110, up to a predetermined depth indicative of the desired thickness of the thin layer 10, without reaching in any case the initial substrate 11 (and / or the conversion layer 13, when present). This implantation generates an embedded brittle plane 12 within the donor layer 110, which defines the boundary of the thin layer 10 between the embedded brittle plane 12 and the free surface 11a of the donor layer 110 (Figure 2c).

[0029] The light species to be implanted are preferably hydrogen, helium, or these two species co-implanted. As is well known with respect to the Smart Cut™ process, these light species will form microcavities distributed within a thin layer parallel to the free surface 11a of the donor layer 110, i.e., parallel to the plane of the figure (x,y), around a given depth. This thin layer is, for the sake of simplicity, called the embedded brittle plane 12.

[0030] The implantation energy of the light species is selected to reach a defined depth within the donor layer 110.

[0031] Typically, hydrogen ions are implanted at an energy between 10 keV and 250 keV and at a dose between 5 E 16 / cm 2 and 1 E 17 / cm 2 to define the boundary of the thin layer 10 having a thickness on the order of 100 nm to 1500 nm.

[0032] The protective layer can be deposited on the free surface of the donor layer 110 prior to the ion implantation step. This protective layer may be made of a material such as silicon oxide or silicon nitride, for example.

[0033] The process according to the invention then comprises step d) of forming a carrier substrate 20 of crystalline silicon carbide on the free surface of the donor layer 110 (Figure 2d). This step d) includes deposition at a temperature between 400 °C and 1100 °C. The deposition of step d) is advantageously carried out at a temperature between 600 °C and 900 °C, and preferably between 700 °C and 800 °C.

[0034] Furthermore, step d) defines a non-insulating interface between the donor layer 110 and the carrier substrate 20. In other words, step d) is carried out such that the interface between the donor layer 110 and the carrier substrate 20 is electrically conductive: the objective is typically a specific resistance of less than 1 mohm.cm 2 or even less than 0.1 mohm.cm 2 for the intrinsic resistance of the interface. Advantageously, in order to ensure the electrical conductivity of the interface, the natural oxide present on the free surface of the donor layer 110 is removed by wet or dry methods by HF (hydrofluoric acid) deoxidation. Alternatively, an initial over-dose of the first few nanometers deposited on the carrier substrate 20 can increase the electrical conductivity of the interface between the donor layer 110 and the carrier substrate 20.

[0035] Similarly advantageously, a cleaning sequence is applied to the donor substrate 111 in order to remove some or all of the particulate matter, metals or organic contaminants that may possibly be present on the front face of said substrate prior to deoxidation and / or the formation of the carrier substrate 20.

[0036] The deposition of step d) may be carried out by various techniques.

[0037] According to the first option, the carrier substrate 20 may be formed by a sintering technique. According to this technique, the SiC powder is compressed at high temperature and under high pressure. Thus, it is possible to obtain a solid ceramic layer. In the context of the present invention, sintering is carried out directly on the injected donor substrate 111, so that immediately after sintering, a carrier substrate 20 that is thick and adheres to the donor layer 110 is obtained. It is essential that the sintered material (carrier substrate 20) acquires sufficient cohesive force to enable the subsequent separation step e) described below later. Therefore, it is necessary to lower the sintering temperature of the SiC powder below this separation temperature. For this purpose, conventional additives such as boron, carbon, or AIN are used or SiC nanopowder is used.

[0038] According to the second option, the carrier substrate 20 may be formed by a liquid phase deposition technique using a solution of ceramic powder. In this case, a pre-ceramic polymer material (PDC for "polymer derived ceramics") is mixed with the ceramic powder (for example, SiC). A viscous solution is obtained, and the viscous solution may be deposited in layer form by spreading, spin coating, or molding. A low-temperature (about 200 °C) bake causes polymerization and cross-linking of the material, resulting in solidification of the deposited layer. Thus, the forming of the carrier substrate 20 is carried out at a low temperature. Thereafter, a bake operation at a high temperature (>600 °C) enables the thermal decomposition of the polymer. And the resulting material is pure ceramic. In the context of the present invention, the goal would be to obtain a SiC or SiCN material. The ceramic raw material is SiC in powder form, and the PDC is a molecule from the class of polycarbosilane or polyorganosilicon (to obtain SiC) and polyorganosilazane (to obtain SiCN).

[0039] According to the third option, the deposition in step d) may be carried out by a chemical vapour deposition (CVD) technique.

[0040] For example, the deposition may be carried out by a thermal CVD technique such as atmospheric-pressure deposition (APCVD) or low-pressure deposition (LPCVD). The precursor may be selected from methylsilane, dimethyldichlorosilane, or dichlorosilane + isobutane otherwise.

[0041] The deposition may be, for example, a plasma-enhanced CVD (PECVD) technique using silicon tetrachloride and methane as precursors. The frequency of the source used to generate the plasma-forming discharge is preferably on the order of 3.3 MHz, and more generally between 10 kHz and 100 GHz.

[0042] The deposition in step d) may further be based on a direct liquid injection-assisted chemical vapour deposition (DLI-CVD) technique. This type of technique limits cost and environmental constraints as it provides a high yield between the supplied substance (precursor) and the resulting deposition thickness without the need to use chlorine-containing precursors. DLI-CVD deposition uses a disilabutane precursor or a polysilylethylene precursor, which may be pure or diluted. This type of technique is described in a paper by Guilhaume Boisselier (2013, “Chemical vapour deposition of chromium, silicon and hafnium carbides, assisted by pulsed liquid injection”) for use in depositing ceramic coatings on components, such as metal components made of steel or alloy, to protect those components during processing at very high temperatures.

[0043] The applicant has developed a deposition step d) based on the DLI-CVD technique for forming a carrier substrate 20 of SiC on a donor layer 110 of c-SiC for a quite different use, namely for creating a composite substrate intended for the field of microelectronic devices. The deposition parameters (for example, a pressure of 6.7 kPa, a temperature between 700 °C and 850 °C) are such that the carrier substrate 20 has a good electrical conductivity between 0.015 ohm.cm and 0.03 ohm.cm, a high thermal conductivity of 200 W.m -1 .K -1 or more, and a coefficient of thermal expansion equal to that of the thin layer 10, typically between 3.8 E -6 / K and 4.2 E -6 / K at ambient temperature.

[0044] To obtain these properties, the carrier substrate 20 may exhibit, for example, the following structural characteristics: a polycrystalline structure, 3C SiC particles, a 111 orientation, an average size between 1 μm and 10 μm, and N-type doping for a final resistivity of 0.03 ohm.cm or less.

[0045] Regardless of the technique used, it is advantageous for the CVD deposition to be carried out at a rate faster than 10 microns / hour, and even faster than 50 microns / hour, and still faster than 100 microns / hour. As much as for obvious economic reasons, it is important to quickly reach a significant thickness of the carrier substrate 20 in order to ensure a stiffening effect on the embedded brittle plane 12, within which cavities follow a thermally activated growth.

[0046] At the end of step d), the carrier layer 20 has a thickness of 50 microns or more, or even 100 microns or more. The laminate 211 obtained by step d) comprises a carrier substrate 20 disposed on the donor layer 110, and the donor layer 110 is then disposed on the initial substrate 11.

[0047] The process according to the invention then comprises step e) of separating along the embedded brittle plane 12, forming on the one hand the composite structure 1 and on the other hand the residue 111' of the donor substrate (Figure 2e).

[0048] According to one advantageous embodiment, the separation step e) acts by applying a heat treatment to the laminate 211 at a separation temperature above the temperature of the deposition of step d). More specifically, the microcavities present within the embedded brittle plane 12 grow according to a growth rate until a fracture wave is initiated, which fracture wave propagates over the entire extent of the embedded brittle plane 12 and will result in the separation between the composite structure 1 and the residue 111' of the initial substrate. In practice, the temperature may be between 950 °C and 1200 °C, depending on the injection conditions of step c).

[0049] According to an alternative embodiment, the separation step e) acts by applying a mechanical stress to the laminate 211. The stress may be effected, for example, by inserting a tool (e.g. a laser blade) in contact with the embedded brittle plane 12. As an example, the separation stress may be on the order of several GPa and preferably greater than 2 GPa.

[0050] According to yet another embodiment, the separation step e) along the embedded brittle plane 12 is carried out during or immediately after the formation of the carrier substrate 20 in step d), more specifically when the deposition temperature in that step is in the range from 800 °C to 1100 °C.

[0051] As is known per se, at the end of the separation step e), the free surface 10a of the thin layer 10 of the composite structure 1 has a surface roughness (by measurement using an atomic force microscope (AFM) for a 20 micron × 20 micron scan) between 5 nm RMS and 100 nm RMS.

[0052] Thus, the process according to the invention comprises step f) of mechanically and / or chemically treating (multiple treatments possible) the composite structure 1 to smooth the free surface 10a of the thin layer 10 and correct the film thickness uniformity of the composite structure 1 (Figure 2f).

[0053] Accordingly, step f) may include chemical-mechanical polishing (CMP) of the free surface 10a of the thin layer 10, typically involving removal of material on the order of 50 nm to 1000 nm, to obtain a final roughness smaller than 0.5 nm RMS (on a 20 μm × 20 μm AFM field of view), or even smaller than 0.3 nm. Step f) may further include chemical or plasma treatment (cleaning or etching), such as SC (Standard Clean) 1 / SC2 (standard cleaning 1 / standard cleaning 2) cleaning and / or HF (hydrofluoric acid) cleaning or N2, Ar, CF4 plasma, etc., to further improve the quality of the free surface 10a of the thin layer 10.

[0054] Furthermore, step f) may include chemical-mechanical polishing (CMP) and / or chemical treatment (etching or cleaning) and / or mechanical treatment (grinding) of the back surface 20b of the carrier substrate 20 to improve the thickness uniformity of the carrier substrate 20 and similarly its back surface roughness. A roughness smaller than 0.5 nm RMS (by measurement using an atomic force microscope (AFM) for a 20 micron × 20 micron field of view) is desired for creating vertical components, for which at least one metal electrode will be present on the back surface 20b of the composite structure 1.

[0055] During this step f), it is also possible to perform polishing or grinding of the edges of the composite structure 1 to adapt the shape of its circular contour and edge rounding to the requirements of the microelectronic fabrication process.

[0056] According to one advantageous embodiment, the chemical-mechanical treatment step f) comprises a simultaneous polishing (CMP) of the front face 10a and the back face 20b of the structure 1 in order to smooth the composite structure 1 and improve the thickness uniformity of said composite structure 1. The polishing parameters may be different between the front face and the back face, and the smoothing of the c-SiC surface and the smoothing of the p-SiC surface generally require different consumables. Emphasis is placed, more particularly, on the mechanical component of the polishing for the back face 20b when the carrier substrate 20 is made of p-SiC, in order to limit the peripheral attack of the grain boundaries by the chemical composition of the polishing. By way of example, the rotation speed (polishing head and plate), the pressure, the concentration, and the physical characteristics of the abrasive (i.e., the diameter of diamond nanoparticles between about 10 nm and 1 μm) may be modified in order to emphasize the mechanical component.

[0057] Also according to one advantageous embodiment, step f) is preceded or followed by a heat treatment step f) at a temperature between 1000 °C and 1800 °C for a period of about 1 hour and up to several hours. The purpose of this step is to stabilize the composite structure 1 by developing, if necessary, the crystal structure of the carrier substrate 20 so that the structure 1 is adapted to subsequent heat treatment at high temperature, and the subsequent heat treatment is required for the fabrication of components on the thin layer 10.

[0058] The process according to the invention may comprise a second step g) of epitaxial growth of a further layer 10' of single-crystalline silicon carbide on the thin layer 10 of the composite structure 1 (Figure 2g). This type of step is applied typically when a fairly substantial useful layer thickness 100 is required for the fabrication of components on the order of 5 microns to 50 microns. The epitaxy conditions may be optionally selected, preferably at low temperature, in the same way as the conditions of step b), in order to limit the stress induced in the useful layer 100 (corresponding to the assembly of the thin layer 10 and the further layer 10') for the composite structure 1.

[0059] Finally, the fabrication process may include a step of reconditioning the residue 111' of the donor substrate for reuse as the initial substrate 1 or as the donor substrate 111. This type of reconditioning step is based on one or more treatments of the surface 110'a by chemical-mechanical polishing of the edges or surfaces and / or by mechanical grinding and / or by wet or dry chemical etching (FIG. 2e). The thickness of the donor layer 110 formed in step b) is preferably defined such that the residue 111' of the donor substrate 111 can be reused at least twice as the donor substrate 111. Preferably, when the conversion layer 13 is present, care is taken to keep the layer untreated, in other words, to always maintain a part of the donor layer 10 on the residue 111' of the donor substrate. Thus, when a part of the donor layer 10 is insufficient to create the composite structure 1, only the step of epitaxial growth of the donor layer 10 is required, and no prior step of growth of the conversion layer 13 is necessary.

[0060] Example 1: According to one non-limiting and exemplary embodiment, the initial substrate 11 prepared in step a) of the fabrication process is a wafer made of 4H polytype c-SiC, having an orientation of 4.0° with respect to the <11-20> axis ±0.5°, a diameter of 150 mm, and a thickness of 350 μm.

[0061] A conventional RCA cleaning sequence (Standard Clean 1 + Standard Clean 2) followed by caro acid (a mixture of sulfuric acid and hydrogen peroxide) and then HF (hydrofluoric acid) is performed on the initial substrate 11 prior to the step b) of epitaxial growth of the c-SiC donor layer 110.

[0062] The growth is carried out in an epitaxy chamber at a temperature of 1650°C using precursors such as monosilane (SiH4) and propane (C3H8) or ethylene (C2H4) to produce a c-SiC donor layer 110 having a thickness of 30 microns (growth rate: 10 microns / hour). The donor layer has a BPD defect density on the order of 1 / cm 2 of the order.

[0063] Hydrogen ions are implanted through the free surface of the donor layer 110 with an energy of 150 keV and a dose of 6 E 16 H+ / cm 2 . The embedded brittle plane 12 is thus created at a depth of approximately 800 nm within the initial substrate 11.

[0064] The RCA + carboxylic acid cleaning sequence is performed on the donor substrate 111 to remove possible contaminants from the free surface of the donor layer 110.

[0065] DLI-CVD deposition is performed on the donor layer 110 at a temperature of 850 °C, using the precursor disilanebutane (DSB) under a pressure of 6.7 kPa for 7 minutes, in order to reach a thickness of at least 10 microns for the carrier substrate 20. Under these conditions, the carrier substrate 20 is polycrystalline.

[0066] A 1000 °C bake is then applied to the laminate 211 for 50 minutes, during which separation occurs at the embedded brittle plane 12.

[0067] At the end of this separation step e), the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the residue 111' of the donor substrate.

[0068] Double-sided polishing is performed to restore the surface roughness of the back surfaces of the thin layer 10 and the carrier substrate 20.

[0069] Example 2: According to one non-limiting and exemplary embodiment, the initial substrate 11 prepared in step a) of the fabrication process is a wafer made of 4H polytype c-SiC, having an orientation of 4.0° with respect to the <11-20> axis ±0.5°, a diameter of 150 mm, and a thickness of 350 μm.

[0070] The conventional RCA cleaning sequence (Standard Clean 1 + Standard Clean 2) followed by caro's acid (a mixture of sulfuric acid and hydrogen peroxide) and subsequent HF (hydrofluoric acid) is carried out on the initial substrate 11 prior to step b) of the epitaxial growth of the c-SiC donor layer 110.

[0071] The conversion layer 13 is formed in an epitaxy chamber. Before starting the epitaxial growth of this layer 13 on the initial substrate 11, a hydrogen bake is carried out in the chamber at a temperature of 1700 °C for a time between 10 minutes and 20 minutes. The epitaxial growth of the c-SiC conversion layer 13 is then carried out in the epitaxy chamber at a temperature of 1650 °C using precursors such as monosilane (SiH4) and propane (C3H8) or ethylene (C2H4) and at a growth rate of about 6 microns / hour to reach a thickness of 1 micron. The C / Si ratio obtained from the gas precursors is maintained at approximately 1, typically close to a value between 0.95 and 1.05.

[0072] In the same epitaxy chamber, the c-SiC donor layer 110 grows at a temperature of 1650 °C using the same precursors, but with the C / Si ratio adjusted to be close to a value of 1.2 or substantially greater. The total flow rate of the precursors is increased compared to the flow rate used for the growth of the conversion layer 13 - for example, the flow rate is doubled. A donor layer 10 with a thickness of 30 microns is obtained after about 180 minutes (growth rate: 10 microns / hour). The donor layer 10 has a BPD defect density on the order of 1 / cm 2 or even smaller than 1 / cm 2 and has a smaller BPD defect density.

[0073] Hydrogen ions are implanted through the free surface of the donor layer 110 with an energy of 150 keV and a dose of 6 E 16H+ / cm 2 and thus an implantation brittle plane 12 is created at a depth of approximately 800 nm within the initial substrate 11.

[0074] The cleaning sequence of RCA + carboxylic acid is applied to the donor substrate 111 to remove possible contaminants from the free surface of the donor layer 110.

[0075] PECVD deposition is carried out on the donor layer 110 at a temperature of 800 °C in an SiCl4 / CH4 / Ar atmosphere using a plasma generation frequency of 3.3 MHz; the pressure within the deposition section is adjusted to reach a deposition rate on the order of 300 microns per hour for the carrier substrate 20. The deposition rate must not be too high in order to limit roughness after deposition on the free surface of the carrier substrate 20. Under these conditions, the carrier substrate 20 is polycrystalline.

[0076] An 1100 °C bake is then applied to the laminate 211 for 50 minutes, and during this baking process, separation occurs within the embedded brittle plane 12.

[0077] At the end of this separation step e), the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the residue 111' of the donor substrate.

[0078] Double-sided polishing is carried out to restore the surface roughness of the back surface 20b of the thin layer 10 and the carrier substrate 20.

[0079] The present invention is, of course, not limited to the described embodiments and examples, and variant embodiments may be introduced into the present invention without departing from the scope of the present invention defined by the claims.

Claims

1. A process for creating a composite structure (1) comprising a thin layer (10) of single crystal silicon carbide disposed on a carrier substrate (20) of silicon carbide, a) providing an initial substrate (11) of single crystal silicon carbide; b) epitaxially growing a donor layer (110) of single crystal silicon carbide on the initial substrate (11) at a temperature greater than 1200° C., thereby forming a donor substrate (111), the donor layer (110) having a lower crystal defect density than the initial substrate (11); c) ion implanting a light species into the donor layer (110) to form an embedded brittle plane (12), the embedded brittle plane (12) defining the boundary of the thin layer (10) between the embedded brittle plane (12) and the free surface of the donor layer (110); d) forming a carrier substrate (20) of silicon carbide on the free surface of the donor layer (110), including deposition at a temperature between 400° C. and 1100° C. and defining a non-insulating interface having an electrical conductivity less than 1 mohm·cm² between the donor layer (110) and the carrier substrate (20); e) separating along the embedded brittle plane (12) to form, on the one hand, the composite structure (1) and, on the other hand, a residue (111') of the donor substrate; f) mechanically and / or chemically treating the composite structure (1) to smooth the free surface of the thin layer (10) and correct the film thickness uniformity of the composite structure (1). A process for creating, including the above steps.

2. The process for creating according to claim 1, wherein the deposition in step d) is carried out at a temperature between 600° C. and 900° C. and is based on a chemical vapor deposition technique, a sintering technique, or a liquid phase deposition technique using a solution of ceramic powder.

3. A process for creating a composite structure (1) comprising a thin layer (10) of single crystal silicon carbide disposed on a carrier substrate (20) of silicon carbide, a) providing an initial substrate (11) of single crystal silicon carbide; b) A step of epitaxially growing a donor layer (110) of single-crystalline silicon carbide on the initial substrate (11), which is carried out at a temperature higher than 1200°C, whereby a donor substrate (111) is formed, and the donor layer (110) has a lower crystal defect density than the initial substrate (11), the step of epitaxial growth; c) A step of ion implanting a light species into the donor layer (110) to form an embedded brittle plane (12), wherein the embedded brittle plane (12) defines the boundary of the thin layer (10) between the embedded brittle plane (12) and the free surface of the donor layer (110), the step of forming; d) A step of forming a carrier substrate (20) of silicon carbide on the free surface of the donor layer (110), which includes deposition at a temperature between 400°C and 1100°C and defining a non-insulating interface between the donor layer (110) and the carrier substrate (20), the step of forming; e) A step of separating along the embedded brittle plane (12) to form, on the one hand, the composite structure (1) and, on the other hand, the residue (111') of the donor substrate; f) A step of mechanically and / or chemically treating the composite structure (1) to smooth the free surface of the thin layer (10) and correct the film thickness uniformity of the composite structure (1); comprising; A process for making, wherein the deposition in step d) is chemical vapor deposition assisted by direct liquid injection.

4. The process for making according to claim 2, wherein the deposition in step d) is plasma-enhanced or low-pressure chemical vapor deposition.

5. The process for making according to any one of claims 1 to 4, wherein the deposition in step d) is carried out at a rate faster than 10 microns per hour.

6. The process for making according to any one of claims 1 to 5, wherein at the end of the deposition in step d), the carrier substrate (20) has a thickness of 50 microns or more.

7. The process for making according to any one of claims 1 to 6, wherein step e) acts at a temperature equal to or higher than the temperature of the deposition in step d).

8. The process for making according to any one of claims 1 to 7, wherein step f) includes chemical-mechanical polishing of the front and back surfaces of the composite structure (1).

9. The process of making according to any one of claims 1 to 8, including a step of heat-treating at a temperature between 1000 °C and 1800 °C, either before or after step f).

10. The process of making according to any one of claims 1 to 9, including a step of reconditioning the residue (111') of the donor substrate for reuse as an initial substrate or as a donor substrate.

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