Pin trap detection circuit

Abstract

Aspects of the present disclosure provide an integrated circuit (100). In at least some examples, the integrated circuit includes an input pin (114) and an analog-to-digital converter (ADC) (104) including an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit (102) including an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit (103). In certain examples, the resistance circuit includes a resistor (106) coupled between the input pin and a first node (118), a first switch (108) coupled between the first node and a reference voltage pin (112), and a second switch (110) coupled between the first node and a ground pin (116).

Description

Technical Field

[0001] There are electrical components that include multiple operating modes, operating settings, or other characteristics that can be programmed after the manufacture of the electrical component. These settings may be set by the consumer of the electrical component implementing the electrical component within a larger circuit, device, or system. As the number of available settings for an electrical component increases, the consumer may desire that the electrical component be programmed easily and accurately.

Summary of the Invention

[0002] Aspects of the present specification provide an integrated circuit. In at least some examples, the integrated circuit includes an input pin, and an analog-to-digital converter (ADC) including an input terminal and an output terminal coupled to the input pin. The integrated circuit further includes a logic circuit including an input terminal, a first output terminal, and a second output terminal coupled to the output terminal of the ADC. The integrated circuit further includes a resistor circuit. In one example, the resistor circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

[0003] Other aspects of this specification provide an integrated circuit. In at least some examples, the integrated circuit includes an input pin, and an ADC including an input terminal and an output terminal coupled to the input pin. The integrated circuit also includes a resistive circuit including an output terminal coupled to the input pin and a first input terminal. The integrated circuit also includes a logic circuit including an input terminal coupled to the output terminal of the ADC and a first output terminal coupled to the first input terminal of the resistive circuit. The logic circuit is configured to generate a first ADC control signal that controls the ADC to determine a voltage present at the input pin using a first value of a resistance present at the input pin. The logic circuit is further configured to generate a control signal that controls the resistive circuit to change the first value of the resistance to a second value of the resistance. The circuit is further configured to determine a second voltage present at the input pin changed according to the second value of the resistance, and to generate a second ADC control signal that controls the ADC to determine the first value of the resistance based at least in part on the voltage present at the input pin, the second voltage present at the input pin, the resistance of the resistive circuit, and a reference voltage.

[0004] Other aspects of this specification provide a system. In at least some examples, the system includes a programmable electrical component and a voltage divider. The programmable electrical component includes an input pin, a reference voltage pin, a ground pin, an ADC including an input terminal coupled to the input pin and an output terminal, and a resistance circuit including an output terminal coupled to the input pin, a first input terminal, and a logic circuit. The logic circuit includes an input terminal coupled to the output terminal of the ADC and a first output terminal coupled to the first input terminal of the resistance circuit. The logic circuit is configured to generate a first ADC control signal to control the ADC to determine the voltage present at the input pin using a first value of a resistance present at the input pin. The logic circuit is further configured to generate a control signal to control the resistance circuit to change the first value of the resistance to a second value of the resistance. The logic circuit is further configured to generate a second ADC control signal to control the ADC to determine a second voltage present at the input pin changed according to the second value of the resistance, and to determine the first value of the resistance based in part on the voltage present at the input pin, the second voltage present at the input pin, the resistance of the resistance circuit, and the reference voltage present at the reference voltage pin. The voltage divider is coupled between the reference voltage pin and the ground pin and has an output coupled to the input pin.

Brief Description of the Drawings

[0005] Refer to the accompanying drawings for a detailed description of various examples.

[0006]

Figure 1

[0007]

Figure 2

[0008]

Figure 3

[0009]

Figure 4

[0010]

Figure 5

[0011] For an electrical component intended to be programmable after manufacture, one such approach for programming the component is pin-strap detection. Pin-strap detection is, in some examples, a process in which a known reference voltage (VREF) output by the electrical component performing the pin-strap detection is monitored at an input terminal of the electrical component to determine the voltage present at that input terminal. In some examples, the output terminal of the electrical component that provides VREF is the VREF pin of the electrical component. In other examples, VREF is provided by any suitable source and its value is known to the electrical component via any of reporting to the electrical component, control performed by the electrical component, or measurement by the electrical component. The various voltages present at the input terminal correspond or map to specific settings of the electrical component such that they are communicated to the user of the electrical component via a data sheet or other instructions for implementing the electrical component in a circuit. To program the electrical component, a user may couple a voltage divider between the VREF pin and the ground (GND) pin or node. The output of the voltage divider is then coupled to the input terminal of the electrical component such that the ratio of the resistances in the voltage divider controls the voltage present at the input terminal. Generally, the amount of resistance of the voltage divider present between the VREF pin and the input terminal is called the top resistance (RTOP), and the amount of resistance of the voltage divider present between the input terminal and the GND pin is called the bottom resistance (RBOT). RTOP and RBOT may each be provided by one or more elements having measurable impedance. For example, RTOP and / or RBOT may each be implemented by a single resistor, a potentiometer, multiple coupled resistors, or any other suitable element capable of providing a measurable amount of impedance or resistance. By changing the values of RTOP and / or RBOT, the user may control the voltage present at the input terminal and thereby program the electrical component.

[0012] The above-described pin-strap detection process provides two-stage flexibility when making measurements. For example, in addition to the voltage measurement described above, the values of RTOP or RBOT can also be determined. There are several approaches for pin-strap detection of the resistors of the voltage divider, but these approaches have problems such as limited accuracy and / or relatively high cost (e.g., the die surface area consumed to implement that approach). One such approach involves sending VREF to a buffer and mirroring the output current of the buffer with a current mirror to an internal resistor (RINT) housed within the electrical component. The voltage across both ends of RINT is measured to determine RBOT. However, this approach can be very inaccurate. For example, as the voltage present at the input terminal increases, the buffer offset increases, resulting in an increase in the percentage error in the RBOT determination. Therefore, the buffer is often implemented as a low-offset amplifier, and when combined with a current mirror, it has a larger die surface area compared to other components such as resistors and / or transistors. As the size increases, the cost of manufacturing the electrical component also increases, and in some cases, it goes against the customer's requirements for the minimum size of the electrical component.

[0013] At least some aspects of this specification provide a pinstripe detection circuit. The pinstripe detection circuit of this specification is, in at least some examples, suitable for detecting the voltage present at the input terminal with 5-bit accuracy and detecting RBOT with 4-bit accuracy. In other examples, the pinstripe detection circuit of this specification is suitable for detecting the voltage present at the input terminal with an accuracy greater than 5 bits and RBOT with an accuracy greater than 4 bits based on a minimized component process and temperature variations of the pinstripe detection circuit and / or resistors that provide RTOP and RBOT. For example, the input terminal of an analog-to-digital converter (ADC) is coupled to the input terminal to generate a digital signal representing the voltage present at the input terminal. In at least some examples, this digital signal representing the voltage present at the input terminal is called the pin voltage (VP), such as when RINT is not coupled in parallel with RBOT or RTOP. In other examples, the digital signal representing the voltage present at the input terminal is called the sensed voltage (VS), such as when RINT is coupled in parallel with RBOT or RTOP. In at least some examples, the digital signal is provided to a digital core or other processing element. The digital core or processing element processes the digital code to generate one or more additional values. For example, the digital core processes VP to generate VCODE and is used when determining VS. The digital code is used when processing VS for the determination of RBOT and correspondingly the determination of RCODE. In at least some examples, the voltage present at the input terminal can vary due to resistor tolerance or other factors. Thus, in at least some examples, the digital core uses fewer bits (e.g., only the least significant 5 bits, etc.) than all 11 bits of VP when generating VCODE used when programming the settings of the digital core or another component or device. In some examples, the bit accuracy of VCODE with respect to VP increases when using fewer bits than all the bits of VP to generate the VCODE used when programming the settings.

[0014] In some examples, VS is measured after VP such that the ADC generates two separate digital codes. In other examples, VP is measured after VS. In at least one example, the ADC measures the voltage present at the input pin to generate VP. In at least some examples, after the ADC generates VP, the digital core generates VCODE based on VP. The digital core further determines the value of VCODE with respect to the value of one or more thresholds. Based on that determination, the digital core generates and outputs a control signal (e.g., a switch control signal). The control signal controls the switch of the pin strap detection circuit to couple RENT in parallel with RTOP or RBOT, enabling the measurement of VS. The ADC then measures the voltage present at the input node and generates VS. After the ADC generates VS, the digital core processes VS, VP, VREF, and / or RINT and generates a digital code (RCODE) representing RBOT. In at least some examples, RINT has a value configured to cause VS to have a value closer to VREF / 2 than VP. Causing VS to have a value closer to VREF / 2 than VP maximizes the resolution of the detectable RBOT values. Based on the values of VCODE and RCODE, the digital core is programmed using a specific setting corresponding to the values of VCODE and RCODE. As described above, in at least some examples, fewer bits than all the bits of VCODE are used when programming the digital core. For example, about 5 or more bits of VCODE (e.g., the least significant 5 bits of VCODE) and about 4 bits of RCODE (e.g., the least significant 4 bits of RCODE) are used when programming the digital core. This provides an improvement in the number of settings for an electrical component that can be accurately set using an input provided at one pin of the electrical component. The improvement in the number of programmable settings using one pin is at least partially due to the improved accuracy of RBOT and RCODE determination according to the pin strap detection herein.

[0015] Referring now to FIG. 1, a schematic diagram of an exemplary electrical component 100 is shown. In at least some examples, electrical component 100 represents any electrical component that includes one or more elements, where the one or more elements are disposed on a semiconductor die and / or are surrounded by a component package having a specific number of pins exposed outside the component package for coupling to elements disposed on the semiconductor die. Electrical component 100 may have any suitable primary functionality, the scope of which is not limited herein. For example, electrical component 100 may be an analog component, a digital component, or a combination of the two, and is configured to provide certain processing and / or control functionality. In at least one example, the electrical component is or includes a power controller such as a DC-to-DC power controller. To implement its primary functionality, electrical component 100 may further include various supporting functionality. For example, electrical component 100 may include functionality for a user to specify one or more desired settings for the operation of electrical component 100. This selection may be implemented according to a pin-strapping methodology where a voltage and / or resistance is detected at a pin and mapped to a certain predefined setting or function of electrical component 100 corresponding to the voltage and / or resistance.

[0016] In at least one exemplary architecture, the electrical component 100 includes a logic circuit 102, a resistance circuit 103, and an ADC 104. The resistance circuit 103 includes a resistor 106, a switch 108, and a switch 110. In at least some examples, the resistance circuit 103 further includes a logic circuit 105. In some examples, the logic circuit 102 is a circuit capable of performing processing and / or decision-making such as a digital core. The logic circuit 105 is, in some examples, a circuit capable of or suitable for performing an OR operation according to a plurality of input signals to generate an output signal that is asserted when any of the plurality of input signals is asserted. In at least some examples, the resistor 106 has a resistance of RINT. Although the resistor 106 is illustrated as a single resistor having a defined value, alternatively, it may be a programmable resistor (e.g., a potentiometer) having a resistance value controlled by the logic circuit 102 or any other suitable control device. Alternatively or additionally, the resistor 106 may represent any combination of components connected in parallel and / or in series having a measurable and / or definable amount of resistance. Further, in at least some examples, the electrical component 100 includes a VREF pin 112, an input pin 114, and a GND pin 116. The VREF pin 112, the input pin 114, and the GND pin 116, in some examples, provide an interface to the electrical component 100, allowing a user to interact with the electrical component 100 or components within the electrical component 100 via one or more components external to the electrical component 100. In at least some examples, the input pin 114 is multi-purpose such that after performing pin strap detection according to this specification, the input pin 114 can be used in the electrical component 100 for another purpose, the scope of which is not limited herein.

[0017] In some examples, ADC104 has an input terminal coupled to input pin 114 and an output terminal coupled to an input terminal of logic circuit 102. In at least some examples, ADC104 has one or more additional input terminals, such as when ADC104 is a multi-channel ADC. For example, ADC104 may include another input terminal coupled to VREF pin 112. When ADC104 is a multi-channel ADC, ADC104 is configured to include or be coupled to a multiplexer (not shown) at its input terminals such that ADC104 receives the output of the multiplexer as its input signal. The multiplexer is coupled to the nodes to the input terminals of ADC104 described above herein. For example, the multiplexer includes respective input terminals coupled to input pin 114 and VREF pin 112. ADC104 (or the multiplexer) further includes a control input that receives from logic circuit 102 a control signal (e.g., one or more ADC control signals) for controlling which analog input signal is to be converted to a digital signal by ADC104. Although shown in FIG. 1 as a single connection for the control signal between logic circuit 102 and ADC104, in various examples, any number of connections may exist based on the number of channels of ADC104 (e.g., the number of unique input terminals of the multiplexer) or any other suitable criterion. Resistor 106 has a first terminal coupled to input pin 114 and a second terminal coupled to node 118. Switch 108 is coupled between node 118 and VREF pin 112 and is configured to receive and be controlled by a first control signal (e.g., a switch control signal) received from logic circuit 102. Switch 110 is coupled between node 118 and GND pin 116 and is configured to receive and be controlled by a second control signal (e.g., a switch control signal) received from logic circuit 102. Switches 108 and 110 may each be implemented according to any suitable technique, the scope of which is not limited herein. In at least one example, switches 108 and 110 are each implemented as solid state devices, such as transistors of any suitable processing technology.

[0018] Although not shown in the electrical component 100, in at least some examples, the electrical component 100 includes circuit elements for providing VREF having a known value to the VREF pin 112. The circuit elements for the electrical component 100 for generating and / or providing VREF at the VREF pin 112 can be implemented in a plurality of suitable architectures, the scope of which is not limited herein. The electrical component 100 does not include the voltage divider 120 but is configured to be coupled to the voltage divider 120. The voltage divider 120 includes the resistor 122 and the resistor 124. As described above with respect to the resistor 106, the resistor 122 and the resistor 124 each represent any one or more combined components that provide a measurable and / or defined amount of resistance. As further suggested above, the resistance of the resistor 122 is called RTOP, and the resistance of the resistor 124 is called RBOT.

[0019] In an example of the operation of the electrical component 100, the electrical component 100 is programmable according to a plurality of settings to provide various functionality. In some examples, the electrical component 100 can be programmable according to dozens, hundreds, or thousands of settings. The settings are, in some examples, programmed into the electrical component 100 based at least in part on a mapping between a particular setting and the voltage and / or resistance present at the input pin 114. For example, based on the voltage measured at the input pin 114 and the determination of RBOT, the electrical component 100 is programmed by the logic circuit 102 using a particular setting that maps to the measured voltage and the determined RBOT.

[0020] To program the electrical component, in at least some examples, the user couples resistor 122 between VREF pin 112 and input pin 114, and couples resistor 124 between input pin 114 and GND pin 116. The electrical component 100 provides VREF to VREF pin 112 and causes the voltage modified by voltage divider 120 to be present at input pin 114. The voltage present at input pin 114 is called VP as described above and is determined based on the value of VREF and the values of RBOT and RTOP. In at least some examples, ADC 104 detects the voltage present at VREF pin 112 and generates a digital signal representation of VREF. ADC 104 provides the digital signal representation of VREF to logic circuit 102 and is used as a variable, for example, in an equation for generating RCODE by logic circuit 102 as described in more detail elsewhere in this specification. ADC 104 detects the voltage present at input pin 114 in analog form and generates VP in digital form based on the detected voltage. ADC 104 then provides VP to logic circuit 102. Logic circuit 102, in some examples, then generates and stores VCODE for use when programming electrical component 100. In at least some examples, logic circuit 102 further stores VP for later use, such as when determining RCODE.

[0021] After determining VCODE, in at least some instances, electrical component 100 determines RCODE. In at least some implementations, RCODE is the digital value representation of RBOT. In other implementations, RCODE is the digital value representation of RTOP. To generate RCODE, logic circuit 102 or another suitable control device controls one of switch 108 or switch 110 to close, forming a conductive path across each of switch 108 or switch 110. If switches 108 and 110 are normally open devices, they are controlled to close when the signal received from logic circuit 102 is asserted. Alternatively, in other instances, switch 108 or switch 110 is configured to close when the signal received from logic circuit 102 is de-asserted. When one of switch 108 or switch 110 is closed, the other of switch 108 and switch 110 is opened, such that in some instances, at any given time, neither or only one of switch 108 or switch 110 is closed. Accordingly, by closing switch 108 or switch 110, resistor 106 is coupled in parallel with resistor 122 or resistor 124, respectively. If VP is known based on measurements previously performed for purposes such as the determination of VCODE, and the value of resistor 106 is known based on being a component included within electrical component 100, the value of RTOP or RBOT can be determined.

[0022] For example, after closing either switch 108 or switch 110, a new voltage exists at input pin 114 and is modified from the value that was present before closing switch 108 or switch 110 (e.g., represented as VP in the digital domain). ADC104 detects the new voltage in analog form at input pin 114 and generates VS based on the detected new voltage. ADC104 then provides VS to logic circuit 102, and logic circuit 102 determines RCODE, at least in part, based on VS in some instances. For example, in some implementations, logic circuit 102 implements an equation to determine RCODE based on the received digital code, previously determined and / or stored VP, VREF, and known RENT. In an example where switch 108 couples resistor 106 in parallel with resistor 122, logic circuit 102 determines RCODE based on Equation 1 below. In an example where switch 110 couples resistor 106 in parallel with resistor 124, logic circuit 102 determines RCODE based on Equation 2 below. TIFF0007709004000002.tif21125

[0023] In other examples, the logic circuit 102 accesses a look-up table stored in a memory (not shown) to determine the value of RCODE based on VS and VP. For example, the look-up table includes either VS or VP on the horizontal axis of the look-up table and the other of VS or VP on the vertical axis of the look-up table. The intersection in the look-up table for a particular VS and VP indicates the value of RCODE for that particular combination of VS and VP. In an implementation where the logic circuit 102 uses a look-up table instead of implementing Equation 1 and / or Equation 2, the logic circuit 102 may not include mathematical engine capabilities (e.g., the ability to perform mathematical calculations). By not including mathematical engine capabilities, in at least some examples, the physical size of the logic circuit 102 is reduced (resulting in a cost reduction), the power consumption by the logic circuit 102 is reduced, and / or the time to determine RCODE is shortened.

[0024] In some examples, logic circuit 102 determines which of switch 108 or switch 110 to close based on the value of VCODE. For example, if VCODE has a value greater than a threshold, logic circuit 102 controls one of switch 108 or switch 110 to close. If VCODE has a value less than the threshold, logic circuit 102 controls the other of switch 108 or switch 110 to close. In some implementations, logic circuit 102 generates and outputs a control signal CONNECT_VREF and controls switch 108 to close when the decimal value of VCODE is less than approximately 16. Logic circuit 102 further generates and outputs a control signal CONNECT_GND and controls switch 110 to close when the decimal value of VCODE is greater than approximately 15. More generally, in at least some implementations, logic circuit 102 generates and outputs a control signal CONNECT_VREF and controls switch 108 to close when the decimal value of VCODE is less than approximately VREF / 2. Logic circuit 102 further generates and outputs a control signal CONNECT_GND and controls switch 110 to close when the decimal value of VCODE is greater than approximately VREF / 2. Alternatively, in other examples, logic circuit 102 determines which of switch 108 or switch 110 to close based on the value of VP. In such examples, VP replaces VCODE in the description herein regarding the generation of CONNECT_VREF or CONNECT_GND.

[0025] Based on the above scheme, by coupling resistor 106 in parallel with resistor 122 or resistor 124, in at least some examples, logic circuit 102 causes VS to have a value closer to VREF / 2 than VP. In at least some examples, causing VS to have a value closer to VREF / 2 than VP improves the resolution of detectable changes at RBOT. For example, when the value of VP is very close to VREF, RBOT becomes significantly larger than RTOP (e.g., RBOT >> RTOP). In this situation, a small change in the value of the voltage present at input pin 114 causes a large change in RBOT. Thus, the potential error caused by ADC 104 during the generation of VS causes a large error in RBOT detection. However, coupling resistor 106 in parallel with resistor 124 limits RBOT to a lower value, and thus brings the value of the voltage present at the input pin closer to VREF / 2. In such an example, the error caused by ADC 104 during the generation of VS reduces the error in RBOT detection, thereby improving the resolution of RBOT detection.

[0026] Similarly, when the value of VP is close to the value present at GND pin 116, RTOP >> RBOT. In this situation, a small change in RBOT causes a large change in VS. By coupling resistor 106 in parallel with resistor 122, RTOP is limited to a lower value, thereby bringing the value of VS closer to VREF / 2. In such an example, the error caused by ADC 104 during the generation of VS reduces the error in RBOT detection, thereby improving the RBOT detection resolution. For example, if ADC 104 introduces an error in the value of VS, the effect of the error increases due to the large change in VS measured by ADC 104. However, since the value of VP is close to the value present at GND pin 116 and thus the value of VS is close to VREF / 2, only a small change occurs in RBOT for a large change in VS, and thus the corresponding error in RBOT is minimized.

[0027] In some examples, there is a variation in RINT from the expected or ideal value of the resistance. In at least some examples, if left uncompensated, the percentage error in RINT from the expected or ideal value is directly converted to the same percentage error in the detected or calculated RBOT and thus becomes an error in RCODE. Accordingly, in at least some examples, it is advantageous to determine and / or compensate for this variation. To determine the variation, in at least some examples, the electrical component 100 includes a calibration or test operation mode. To enter the calibration mode of operation, the logic circuit 102 generates and outputs a control signal TEST_EN having an asserted value. The control signal is received by the logic circuit 105 and, when asserted, closes the switch 110 to couple the resistor 106 in parallel with the resistor 124. While operating in the test mode, resistors having known values are used as the resistors 122 and 124. Thereafter, the logic circuit 102 determines RINT. Since the values of the resistors 122 and 124 are known and the expected RINT is known, the logic circuit 102 can then determine the variation of the actual value of RINT from the expected value of RINT. In at least some examples, the logic circuit 102 stores a value indicative of the variation, as an RINT offset, in a storage element (not shown) such as a register, a one-time programmable (OTP) memory, or other suitable memory or data storage structure. In subsequent normal operation (e.g., when not operating in the test mode), the logic circuit 102 modifies RINT according to the RINT offset in the calculations of Equation 1 and Equation 2. In at least some examples, the determination of the RINT offset compensates for the variation in the actual value of RINT with an accuracy within about 0.2% of the expected value of RINT.

[0028] Referring now to FIG. 2, a schematic diagram of an exemplary resistor circuit 200 is shown. In at least some examples, resistor circuit 200 replaces resistor 106, switch 108, and switch 110 of electrical component 100 of FIG. 1. For example, in at least some implementations, resistor circuit 200 is suitable for implementation as (e.g., instead of) resistor circuit 103. Thus, when describing resistor circuit 200, at least some components and / or signals of electrical component 100 may be referenced.

[0029] The resistance circuit 200 includes, in some examples, resistor 202, resistor 204, resistor 206, resistor 208, switch 210, switch 212, switch 214, and switch 216. In at least one exemplary architecture, resistor 202 and switch 210 are coupled in series between input pin 114 and VREF pin 112. Resistor 204 and switch 212 are also coupled in series between input pin 114 and VREF pin 112. Resistor 206 and switch 214 are coupled in series between input pin 114 and GND pin 116. Resistor 208 and switch 216 are also coupled in series between input pin 114 and GND pin 116. Although not shown, each of switch 210, switch 212, switch 214, and switch 216 is configured to receive a respective control signal from logic circuit 102 in some examples to control the state (e.g., open or closed) of switch 210, switch 212, switch 214, and switch 216. Although two resistor and switch pairs are shown and described as being coupled between input pin 114 and each of VREF pin 112 and GND pin 116, in various other examples, any number of resistor and switch pairs are coupled between input pin 114 and each of VREF pin 112 and GND pin 116. In some examples, the same number of resistor and switch pairs are coupled between input pin 114 and each of VREF pin 112 and GND pin 116. In other examples, a different number of resistor and switch pairs are coupled between input pin 114 and one of VREF pin 112 or GND pin 116 than between input pin 114 and the other of VREF pin 112 or GND pin 116.

[0030] In some examples of the operation of the resistance circuit 200, such as when the ADC104 is an 11-bit ADC, the maximum decimal value of VCODE is 31. Based on the decimal value of VCODE, the logic circuit 102 controls one of the switches 210, 212, 214, or 216 to close and leaves the remaining ones of the switches 210, 212, 214, or 216 open or opens them. For example, when the maximum value of VCODE is 31, the logic circuit 102 controls the switch 210 to close (and opens the switches 212, 214, and 216). When the decimal value of VCODE is 0 to 7 (including 0 and 7), the logic circuit 102 further controls the switch 212 to close (and controls the switches 210, 214, and 216 to open) when the decimal value of VCODE is 8 to 15 (including 8 and 15). The logic circuit 102 further controls the switch 214 to close (and controls the switches 210, 212, and 216 to open) when the decimal value of VCODE is 16 to 23 (including 16 and 23). The logic circuit 102 further controls the switch 216 to close (and controls the switches 210, 212, and 214 to open) when the decimal value of VCODE is 24 to 31 (including 24 and 31).

[0031] Generally, the logic circuit 102 generates one or more control signals that control one or more switches of the resistor circuit 200 to have a state that brings the value of VS closer to VREF / 2. For example, in at least some implementations, the resistors 202, 204, 206, and 208 have different values of resistance optimized for a certain value or range of values of VCODE. By determining the value of VCODE, the logic circuit 102 then controls the switches 210, 212, 214, and / or 216 to have a state configured to bring VS closer to VREF / 2. For example, based on the states of the switches 210, 212, 214, and 216, the amount of resistance coupled in parallel with the resistor 222 or the resistor 224 changes. Changing the amount of resistance coupled in parallel with the resistor 222 or the resistor 224 brings the value of VS closer to VREF / 2 than the previously measured value of VP. The least significant 5 bits of the previously measured VP are stored as VCODE by the logic circuit 102 when the switches 210, 212, 214, and 216 are each opened.

[0032] Referring now to FIG. 3, a schematic diagram of an exemplary resistor circuit 300 is shown. In at least some examples, the resistor circuit 300 replaces the resistor 106, the switch 108, and the switch 110 of the electrical component 100 of FIG. 1. For example, in at least some implementations, the resistor circuit 300 is suitable for implementation as (e.g., instead of) the resistor circuit 103. Accordingly, in the description of the resistor circuit 300, at least some components and / or signals of the electrical component 100 may be referenced.

[0033] In at least one example, the resistive circuit 300 includes a resistor 302 and a voltage source 304. The resistor 302 is coupled between the output terminal of the voltage source 304 and the input pin 114. In some examples, the resistive circuit 300 further includes a switch coupled between the resistor 302 and the input pin 114. The voltage source 304 is, in some examples, a digital-to-analog converter (DAC). In other examples, the voltage source 304 is any component, circuit, or device capable of outputting a signal having a controllable value. For example, the output signal of the voltage source 304 can be controllable in values ranging from a minimum of about 0 volts (e.g., substantially equal to that present at the GND pin 116) to a maximum of about VREF (e.g., substantially equal to the value present at the VREF pin 112). In some examples, the voltage source 304 is controlled to generate an output signal having a value determined based on the value of VCODE. For example, based on the value of VCODE and the known resistance value of the resistor 302, the logic circuit 102 controls the voltage source 304 to generate an output signal configured to make the absolute value of the difference between VS and VREF / 2 smaller than the absolute value of the difference between VCODE and VREF / 2. Alternatively, VCODE can also be replaced with VP and used when controlling the voltage source 304. The voltage source 304 is, in at least some examples, controlled based on a signal received from the logic circuit 102. In at least some examples, the switch 306 is configured to disconnect the resistor 302 and the voltage source 304 from the input pin 114 under certain circumstances. For example, as described elsewhere in this specification, when VP is determined by the logic circuit 102, based on the control signal received from the logic circuit 102, the switch 306 opens to disconnect the resistor 302 and the voltage source 304 from the input pin 114. Then, as described elsewhere in this specification, when RCODE is determined by the logic circuit 102, based on the control signal received from the logic circuit 102, the switch 306 closes to couple the resistor 302 and the voltage source 304 to the input pin 114.

[0034] Referring now to FIG. 4, an exemplary timing diagram 400 is shown. In at least some examples, the timing diagram 400 represents at least some of the signals that are present in or related to the electrical component 100 of FIG. 1. Thus, when explaining the timing diagram 400, at least some of the components and / or signals of the electrical component 100 may be referenced.

[0035] The timing diagram 400 illustrates an exemplary pin strap detection sequence and device configuration based on the result of pin strap detection. The timing diagram 400 shows the control signal ADC_PINSTRAP_EN and the control signal ADC_VREF_EN. The timing diagram 400 also shows VP, VCODE, CONNECT_VREF, CONNECT_GND, VS, and RCODE, each as already described herein.

[0036] As already described with respect to FIG. 1, the ADC104 can be a multi-channel ADC. In such an example, ADC_PINSTRAP_EN is a signal output by the logic circuit 102 and controls the ADC104 to output VP based on the voltage present at the input pin 114. For example, when ADC_PINSTRAP_EN is asserted (e.g., has a logic high value), the ADC104 measures the voltage present at the input pin 114 and generates VP. In some examples, the generation of VP is performed by the ADC104 performing a moving average to reduce the possibility of inaccuracies in the value of VP resulting from momentary variations in the value of the voltage present at the input pin 114. Similarly, ADC_VREF_EN is a signal output by the logic circuit and controls the ADC104 to generate a digital signal representation of VREF based on the voltage present at the VREF pin 112. When ADC_VREF_EN is asserted (e.g., has a logic high value), the ADC104 measures the voltage present at the VREF node 112 and generates a digital signal representation of VREF. In some examples, the generation of the digital signal representation of VREF is performed by the ADC104 performing a moving average to reduce the possibility of inaccuracies in the value of VREF resulting from momentary variations in the value VREF present at the VREF pin 112. For the purpose of illustration of the timing diagram 400, it is assumed that VP is less than VREF / 2 and thus the logic circuit 102 asserts CONNECT_VREF, but in other examples, alternatively, VP may be greater than VREF / 2 and thus the states of CONNECT_VREF and CONNECT_GND are opposite to those shown in the timing diagram 400.

[0037] As illustrated in timing diagram 400, the pinstripe detection sequence generally includes seven operations. However, in some examples, more or fewer operations may be included, each of those operations may include one or more sub-operations not specifically shown in timing diagram 400, and timing diagram 400 may not be to scale (e.g., some operations may take longer than others). Further, there may be delays not shown in timing diagram 400 between some operations (e.g., a delay from the completion of one operation that generates a particular signal to the generation of a new signal based on that particular signal).

[0038] After startup, the electrical component 100 waits for the voltage present at the input pin 114 to settle (e.g., stabilize). While waiting for the voltage present at the input pin 114 to settle, the logic circuit 102 controls the ADC via the ADC_VREF_EN signal to generate a digital representation of VREF that will be used later by the storage and the logic circuit 102. After the voltage present at the input pin 114 has settled, the logic circuit 102 controls the ADC104 to measure the voltage present at the input pin 114 and generate VP. The logic circuit 102 performs the control via the ADC_PINSTRAP_EN signal in at least some examples. The ADC104 performs the measurement of VP according to a dynamic averaging process, and upon completion, the ADC104 generates and outputs VP as an 11-bit value (if the ADC104 is an 11-bit ADC). The logic circuit 102 stores at least a part of VP as VCODE and determines whether VP is greater than or less than VREF / 2. The part of VP stored as VCODE can be determined according to any suitable characteristics such as the tolerances of the resistor 122 and the resistor 124, but in at least one example, at least the least significant 5 bits of VP are stored as VCODE. Based on the value of VP relative to VREF / 2, the logic circuit 102 asserts either CONNECT_VREF or CONNECT_GND. CONNECT_VREF is asserted in the timing diagram 400. The electrical component 100 waits again for the voltage present at the input pin 114 to settle. After the voltage present at the input pin 114 has settled again, the logic circuit 102 controls the ADC104 to measure the voltage present at the input pin 114 and generate VS. The logic circuit 102 performs the control via the ADC_PINSTRAP_EN signal in at least some examples. The ADC104 performs the measurement of VS according to a dynamic averaging process, and upon completion, the ADC104 generates and outputs VS as an 11-bit value (if the ADC104 is an 11-bit ADC). After the generation of VS, the logic circuit 102 generates RCODE as at least a 4-bit value.Thereafter, in at least some examples, logic circuit 102 configures electrical component 100 or another device according to the stored VCODE and the determined RCODE. The values of both the VCODE and the RCODE uniquely correspond to one or more specific settings of the electrical component 100 or another device being configured.

[0039] Referring now to FIG. 5, a flowchart of an exemplary method 500 is shown. Method 500 is, in some examples, a pinstripe detection method. In at least some examples, method 500 is implemented at least in part in and by electrical component 100 (or components thereof) of FIG. 1. Accordingly, in the description of method 500, at least some components and / or signals of electrical component 100 may be referenced.

[0040] In operation 502, VREF is sampled. In at least some examples, VREF is sampled by controlling ADC 104 to measure VREF and generate a digital code representing VREF using a channel of ADC 104 coupled to VREF pin 112. In some examples, the control is performed by logic circuit 102 that outputs a channel selection signal to ADC 104 to cause ADC 104 to sample the channel of ADC 104 coupled to VREF pin 112.

[0041] In operation 504, the input pin voltage is sampled to generate VP. In at least some examples, the input pin voltage is sampled by controlling ADC104 to measure the input pin voltage and generate VP as a digital representation of the input pin voltage using the channel of ADC104 coupled to input pin 114. In some examples, the control is performed by logic circuit 102 that outputs a channel selection signal to ADC104 to cause ADC104 to sample the channel of ADC104 coupled to input pin 114. Sampling the input pin voltage is, in at least some examples, a hardware operation that causes ADC104 to generate VP based on the analog value present at input pin 114. VP is provided by ADC104 to logic circuit 102 as one or more electrical impulses representing one or more digital bits in at least some examples.

[0042] In operation 506, the VCODE is calculated. In at least some examples, the VCODE is calculated by logic circuit 102 by operating on the digital code received from ADC104 (storing a portion of the digital code as the VCODE). For example, if ADC104 outputs a digital code having 11 bits, in some implementations, even though all 11 bits are used in other calculations (such as when calculating the RCODE), only the least significant 5 bits of the digital code (or more generally, fewer bits than all 11 bits of the digital code) can be used for programming one or more settings. Thus, in at least some examples, the VCODE is calculated to include fewer bits than all the bits of the VP. In at least some examples, fewer bits than all 11 bits of the digital code are used in programming to correct for potential errors or inaccuracies due to the tolerance (e.g., about 1% or the like) in the actual values of RTOP and RBOT from their ideal values for RTOP and RBOT, respectively. If resistors with lower tolerances (e.g., higher precision) are used for resistor 122 and resistor 124, in at least some examples, a digital code with a number of bits greater than just the least significant 5 bits can be used for programming one or more settings. In other examples, logic circuit 102 can generate the VCODE by directly storing all the bits of the VP as the VCODE. In at least some examples, after generating the VCODE from the VP, logic circuit 102 stores the VCODE in a storage element. In at least some examples, logic circuit 102 also stores the received VP based on which the VCODE is generated. The storage element can be a register, a cache, or any other volatile or non-volatile storage component or device. In at least some examples, the VCODE is an exact digital value up to at least 5 bits.

[0043] In operation 508, a control signal is generated. In at least some examples, the control signal is generated by logic circuit 102. Logic circuit 102 generates the control signal based on the value of VCODE with respect to a threshold in at least some implementations. For example, in one implementation of operation 508, logic circuit 102 determines whether VCODE is less than or greater than the threshold and generates a control signal. For example, if VCODE is less than the threshold, the logic circuit generates a first control signal that is asserted and a second control signal that is de-asserted. If VCODE is greater than the threshold, the logic circuit generates a first control signal that is de-asserted and a second control signal that is asserted. In at least some examples, the threshold is a digital value representing VREF / 2.

[0044] In operation 510, an internal resistor (e.g., resistor 106) is coupled in parallel with the resistors of voltage divider 120. For example, when the first control signal is asserted, the internal resistor is coupled in parallel with resistor 122 between VREF pin 112 and input pin 114. When the second control signal is asserted, the internal resistor is coupled in parallel with resistor 124 between input pin 114 and GND pin 116. In at least some examples, by coupling the internal resistor in parallel with the resistors of voltage divider 120, the voltage value of the signal present at input pin 114 changes to a value closer to VREF / 2 than the voltage of the signal present at input pin 114 in operation 504. In at least some examples, when the first control signal is asserted, the switch that receives the first control signal closes and couples the internal resistor in parallel with resistor 122. Similarly, when the second control signal is asserted, the switch that receives the second control signal closes and couples the internal resistor in parallel with resistor 124.

[0045] In operation 512, the input pin voltage is sampled to generate VS. In at least some examples, the input pin voltage is sampled by controlling ADC104 to measure the input pin voltage and generate VS as a digital representation of the input pin voltage using the channel of ADC104 coupled to input pin 114. In some examples, the control is performed by logic circuit 102 that outputs a channel selection signal to ADC104 to cause ADC104 to sample the channel of ADC104 coupled to input pin 114. Sampling the input pin voltage is, in at least some examples, a hardware operation that causes ADC104 to generate VS based on the analog value present at input pin 114. The generated digital code is provided to logic circuit 102 by ADC104 as one or more electrical impulses representing one or more digital bits in at least some examples.

[0046] In operation 514, the resistance of the resistors of voltage divider 120 is calculated. In at least some examples, the resistance is that of the bottom resistor of voltage divider 120 (e.g., resistor 124). In other examples, the resistance is that of resistor 122. In some examples where an internal resistor is coupled in series with resistor 122 in operation 510, the resistance of the resistor is determined according to Equation 1 as described above with respect to FIG. 1. In an example where an internal resistor is coupled in series with resistor 124 in operation 510, the resistance of the resistor is determined according to Equation 2 as described above with respect to FIG. 1. In at least some examples, the resistance of the resistor is determined by logic circuit 102. In at least some examples, logic circuit 102 stores the resistance of the resistor as RCODE in a storage element. The storage element can be a register, cache, or other volatile or non-volatile storage component or device. In at least some examples, RCODE is an accurate digital value up to at least 4 bits such that both VCODE and RCODE can accurately provide at least 9 bits of programmability (e.g., at least 511 distinct values) to electrical component 100.

[0047] In operation 516, the device is programmed using settings according to the values of VCODE and RCODE. For example, logic circuit 102 may program itself, or another component of electrical component 100 may be programmed using specific settings according to VCODE and RCODE (either by logic circuit 102 or another component). In at least some examples, both VCODE and RCODE can provide a selection from among at least 511 unique settings by controlling the value of VCODE based on the ratio of the top resistor of the voltage divider to the bottom resistor of the voltage divider and by controlling the value of the resistor selected for RCODE.

[0048] The operations of method 500 have been described and presented by numerical reference. However, in various examples, method 500 includes additional operations not described herein. In some examples, any one or more of the operations described herein include one or more sub-operations (e.g., intermediate comparisons, logical operations, output selection via a multiplexer, etc., format conversion, determination, etc.). In some examples, any one or more of the operations described herein are omitted. In some examples, any one or more of the operations described herein are performed in an order other than the order presented herein (e.g., in reverse order, substantially simultaneously, overlapping, etc.). Each of these alternatives is included within the scope of this specification.

[0049] In the foregoing description, the terms "comprising" and "including" are used in an unrestricted sense and should therefore be construed to mean "including but not limited to." The term "coupled" is used throughout this specification. This term can encompass connections, communications, or signal paths that enable a functional relationship consistent with the description herein. For example, if device A controls device B to generate a signal to perform a certain action, in a first example, device A is coupled to device B, and in a second example, device A is coupled to device B via an intermediate component C, provided that the intervening component C does not substantially change the functional relationship between device A and device B via the control signal generated by device A such that device B is controlled by device A. A device "configured" to perform a certain task or function can be configured (e.g., programmed and / or hardwired) by the manufacturer to perform those functions during manufacture, or alternatively, they can be configurable (or reconfigurable) by the user to perform their functions and / or other additional or alternative functions after manufacture. Such configuration can be via the device's firmware and / or software programming, or via the configuration and / or layout of hardware components, or via the interconnection of the device, or via a combination thereof. Further, a circuit or device said to include certain components can instead be configured to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) can instead include only semiconductor elements within a single physical device (such as a semiconductor die and / or an integrated circuit (IC) package) and can be configured to be coupled to at least some of the passive elements and / or sources, thereby forming the described structure at any point in time during or after manufacture, e.g., by an end user and / or a third party.

[0050] Although certain components are described herein as being of a particular process technology, these components may be interchangeable with components of other process technologies. A reconfigured circuit including the interchanged components provides a desired functionality that is at least partially similar to the functionality available prior to the interchange of the components. Unless otherwise specified, a component shown as a resistor generally represents one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the illustrated resistor. Also, the term "ground voltage potential" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this specification. Unless otherwise specified, "about," "approximately," or "substantially" before a value means + / - 10 percent of the recited value.

[0051] The foregoing description is illustrative of the principles and various examples of this specification. Many changes and modifications will become apparent to those skilled in the art when the foregoing description is fully understood. This specification encompasses all such changes and modifications.

Claims

1. An integrated circuit comprising: an analog-to-digital converter (ADC) having an ADC input and an ADC output; a first logic circuit having an input coupled to the ADC output, a first output, and a second output; a resistor circuit comprising: a resistor having a first terminal coupled to the ADC input and a second terminal; a first switch coupled between the second terminal of the resistor and a reference voltage terminal; a second switch coupled between the second terminal of the resistor and a ground terminal; and the resistor circuit; wherein the integrated circuit is configured to couple a top resistor of a voltage divider between the ADC input and the reference voltage terminal, and to couple a bottom resistor of the voltage divider between the ADC input and the ground terminal.

2. The integrated circuit according to claim 1, wherein the first logic circuit is configured to generate a first ADC control signal, and the ADC is configured to determine a first voltage at the ADC input in response to the first ADC control signal.

3. The integrated circuit according to claim 2, wherein the first logic circuit is configured to generate a switch control signal, the first switch is configured to couple the resistor between the ADC input and the reference voltage terminal in response to the switch control signal based on the first voltage with respect to a threshold value, and the second switch is configured to couple the resistor between the ADC input and the ground terminal in response to the switch control signal based on the first voltage with respect to the threshold value.

4. The integrated circuit according to claim 3, wherein the first switch is further configured to couple the resistor between the ADC input and the reference voltage terminal when the first voltage is less than the threshold value, and the second switch is further configured to couple the resistor between the ADC input and the ground terminal when the first voltage is greater than the threshold value.

5. The integrated circuit according to claim 3, wherein the first logic circuit is further configured to generate a second ADC control signal, and the ADC is further configured to determine a second voltage at the ADC input in response to the second ADC control signal. An integrated circuit in which the second voltage is corrected by coupling the resistor between the ADC input and one of the reference voltage terminal or the ground terminal. **Claim 6** The integrated circuit according to claim 5, wherein the first logic circuit is further configured to determine the resistance of an element coupled to the ADC input according to the second voltage, the reference voltage at the reference voltage terminal, and the resistance of the resistor. **Claim 7** The integrated circuit according to claim 6, wherein the first logic circuit is further configured to program the setting of the integrated circuit according to the second voltage and the resistance of the element. **Claim 8** The integrated circuit according to claim 1, further comprising a second logic circuit having an output coupled to the control terminal of the second switch, a first input coupled to the second output of the first logic circuit, and a second input terminal coupled to the third output of the first logic circuit. **Claim 9** The integrated circuit according to claim 8, wherein the second logic circuit is configured to perform a logical OR operation between the first input and the second input of the second logic circuit.

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