Semiconductor device, USB system, and packet transmission method

The semiconductor device with a UMTI+ interface, conversion, determination, and control circuits ensures correct transmission of LPM tokens, addressing the issue of incorrect token transmission in USB systems with UMTI+ and ULPI interfaces, allowing the USB device to enter low power mode.

JP7709364B2Active Publication Date: 2025-07-16RENESAS ELECTRONICS CORP
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Patent Information

Application Number
JP2021186708
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-11-16
Publication Date
2025-07-16
Estimated Expiration
2041-11-16

AI Technical Summary

Technical Problem

When a USB controller with a UMTI+ interface and a transceiver with a ULPI interface are connected, the transceiver fails to transmit LPM tokens correctly, preventing the USB device from entering the low power consumption mode.

Method used

A semiconductor device with a controller having a UMTI+ interface, a conversion circuit, a determination circuit, and a control circuit that analyzes packet identifiers and adds necessary data sequences to ensure LPM tokens are correctly transmitted.

Benefits of technology

The transceiver can now properly transmit LPM tokens to the USB device, enabling the device to enter the low power consumption mode without modifying the USB controller or conversion circuit.

✦ Generated by Eureka AI based on patent content.

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Abstract

To provide a technique for allowing a transceiver to normally transmit an LPM token to a USB device.SOLUTION: A semiconductor device includes: a controller including a first interface circuit in conformity with UTMI+ standards; a converting circuit including a second interface circuit in conformity with the UTMI+ standards and a third interface circuit in conformity with ULPI standards, the second interface circuit converting data received from the first interface circuit to transmit it from the third interface circuit; a first circuit analyzing a packet output from the controller and recognizing and holding a packet identifier contained in the packet; and a second circuit for adding a data string containing the packet identifier indicating LPM after a transmission command if the first circuit determines that the packet identifier is the LPM bringing a USB device into low power consumption.SELECTED DRAWING: Figure 6
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Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and is applicable to, for example, a semiconductor device incorporating a controller (also referred to as a USB controller) that performs control for communication by a Universal Serial Bus (USB).

Background Art

[0002] The USB2.0 (Universal Serial Bus 2.0) standard does not define an interface between a USB controller (logical layer circuit) and a transceiver (physical layer circuit). However, UTMI+ (USB2.0 Transceiver Macrocell Interface) and ULPI (UTMI+ Low Pin Interface) have become de facto standard specifications. ULPI is an interface that reduces the number of wirings of UTMI+.

[0003] Also, the USB2.0 standard has a protocol standard for a low power consumption mode called LPM (Link Power Management). In this standard, the transition to the low power consumption mode is defined by using packets for LPM. Packets for LPM are means for requesting a transition from the normal active state to the low power consumption state. Packets for LPM are also referred to as LPM tokens. The host and the device transition from the active state to the low power consumption state by transmitting and receiving an LPM token and a response packet thereto. When an LPM token transmitted from a USB host (USB controller) to a USB device (connected device) is received (an ACK signal is returned), the USB device and the USB host transition to the low power consumption state.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When a USB controller includes an interface circuit compliant with the UMTI+ standard and a transceiver includes an interface circuit compliant with the ULPI standard, an interface conversion circuit is provided between the USB controller and the transceiver. In this case, when the USB controller transmits an LPM token to the transceiver, the transceiver cannot normally transmit the LPM token to the USB device.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] Briefly described below is an outline of typical ones among the present disclosures. That is, a semiconductor device includes a controller having a first interface circuit compliant with the UMTI+ standard, a second interface circuit compliant with the UMTI+ standard and a third interface circuit compliant with the ULPI standard, a conversion circuit that converts data received from the first interface circuit and transmits the data from the third interface circuit, a first circuit that analyzes a packet output from the controller and recognizes and holds a packet identifier included in the packet, and a second circuit that, when the first circuit determines that the packet identifier is an LPM for reducing power consumption of a USB device, adds a data sequence including the packet identifier indicating the LPM after a transmission command.

Advantages of the Invention

[0008] According to the semiconductor device, the transceiver can normally transmit an LPM token to the USB device.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0010] Hereinafter, embodiments and modification examples will be described with reference to the drawings. However, in the following description, the same reference numerals may be given to the same components and repeated description may be omitted.

[0011] First, to clarify the present embodiment, the configuration of the USB system in the comparative example will be described with reference to FIG. 1. FIG. 1 is a block diagram showing the USB system in the comparative example.

[0012] The USB system 10 is composed of a controller (CNTR) 110 as a USB controller, an interface conversion circuit (CNVR) 120, a transceiver (TRX) 200, and a device (DVC) 300 as a USB device. The controller 110 and the conversion circuit 120 are mounted (built-in) on a semiconductor device 100 such as an FPGA (Field Programmable Gate Array) or a microcontroller, and the transceiver 200 is externally attached to the semiconductor device 100.

[0013] The controller 110 has an interface circuit (hereinafter referred to as a UMTI+ circuit or a first interface circuit) 111 that complies with the UMTI+ standard. The conversion circuit 120 has a UMTI+ circuit 121 as a second interface circuit and an interface circuit (hereinafter referred to as a ULPI circuit or a third interface circuit) 122 that complies with the ULPI standard. The transceiver 200 has a ULPI 201 and an interface circuit (USBI / F) 202 that complies with the USB standard. The device 300 has a USBI / F 301. The controller 110 and the conversion circuit 120 are connected by a bus 131 that complies with the UMTI+ standard, the conversion circuit 120 and the transceiver 200 are connected by a bus 132 that complies with the ULPI standard, and the transceiver 200 and the USB device 300 are connected by a bus 133 that complies with the USB standard.

[0014] The outline of USB 2.0 packet transmission using the ULPI standard will be described with reference to FIG. 3. FIG. 3 is a diagram showing packet data.

[0015] (a) The controller 110 generates a data sequence (D0, D1) starting from a PID (packet identifier). The " / PID" and "PID" shown in FIG. 3 are 4 bits long. " / PID" is the inverted data of "PID". In the drawing, " / PID" is described by adding a " ̄" above "PID". The D0 and D1 of the data are each 8 bits (bit) long. Then, the controller 110 transmits the generated packet data to the conversion circuit 120 via the bus 131.

[0016] (b) The conversion circuit (CNVR) 120 generates a transmission command (TX CMD). That is, the conversion circuit 120 replaces the first byte ( / PID + PID) of the data received from the controller 110 with TX CMD (01_00b + PID). Also, the "b" in "01_00b" indicates that the previous number is in binary. Then, the conversion circuit 120 transmits the converted packet data to the transceiver 200 via the bus 132.

[0017] (c) The transceiver 200 reverses the transmission command (01_00b + PID) to restore the data generated by the controller 110.

[0018] (d) The transceiver 200 performs data conversion according to the USB2.0 standard. Then, the transceiver 200 transmits the generated packet data to the device 300 via the bus 133.

[0019] Normally, when the transceiver 200 transmits an LPM token, the following operations occur and normal transmission cannot be achieved. This will be described with reference to FIG. 4. FIG. 4 is a diagram showing packet data when the USB system shown in FIG. 1 transmits an LPM token.

[0020] (a) The controller 110 generates an LPM token (PID = 0000b). Then, the controller 110 transmits the generated packet data to the conversion circuit 120 via the bus 131.

[0021] (b) The conversion circuit 120 generates "01_00b + 0000b" as a transmission command. Then, the conversion circuit 120 transmits the generated packet data to the transceiver 200 via the bus 132.

[0022] (c) In the ULPI standard, data transmission has a "mode of transmitting PID" and a "mode of not transmitting PID", which is determined by the PID value in the transmission command. When PID = 0000b, it enters the "mode where PID is not transmitted" (ULPI standard operation). Therefore, the data restored by the transceiver 200 becomes a data string "without PID".

[0023] (d) The transceiver 200 performs data conversion according to the USB2.0 standard. Then, the transceiver 200 transmits the generated packet data to the device 300 via the bus 133.

[0024] However, since an invalid packet that is not an LPM token is transmitted from the transceiver 200, the device 300 cannot shift to the low power consumption mode by LPM.

[0025] The details of packet transmission will be described with reference to FIGS. 2 and 5. FIG. 2 is a block diagram showing the details of the bus compliant with the UTMI + standard and the bus compliant with the ULPI standard. FIG. 5 is a timing chart showing the operations of the controller and the conversion circuit shown in FIG. 2.

[0026] As shown in FIG. 4, the bus 131 includes a data bus 131a, a signal line 131b, and a signal line 131c. The data bus 131a inputs 8-bit long data (DataIn[7:0]) from the controller 110 to the conversion circuit 120. The signal line 131b inputs a data valid signal (TxValid) indicating that the data on the data bus 131a is valid from the controller 110 to the conversion circuit 120. The signal line 131c inputs a transmission permission signal (TxReady) indicating that the conversion circuit 120 is ready to receive data from the conversion circuit 120 to the controller 110.

[0027] Bus 132 includes data bus 132a, signal line 132b, and signal line 132c. Data bus 132a exchanges 8-bit data (DATA[7:0]) between conversion circuit 120 and transceiver 200. Signal line 132b inputs a signal (STP) indicating that it is the last byte of packet data from conversion circuit 120 to transceiver 200. Signal line 132c inputs a transmission request signal (NXT) indicating that transceiver 200 has received data from transceiver 200 to conversion circuit 120.

[0028] At timing t1, controller 110 outputs “ / PID+PID” as DataIn[7:0] and activates (asserts) the data valid signal (TxValid). Here, timings t1 to t8 are the rising edges of the clock signal (CLK).

[0029] At timing t2, conversion circuit 120 replaces the “ / PID+PID” of DataIn[7:0] received from controller 110 with a transmission command of “01_00b+PID”. Then, conversion circuit 120 transmits the generated transmission command to transceiver 200 as DATA[7:0].

[0030] After receiving the transmission command of DATA[7:0], transceiver 200 activates the transmission request signal (NXT) at timing t4 and transmits it to conversion circuit 120. Conversion circuit 120 activates the received transmission request signal (NXT) as a transmission permission signal (TxReady) and transmits it to controller 110. Here, DataIn[7:0] and DATA[7:0] are valid at timings t4 to t7.

[0031] In response to the activated transmission permission signal (TxReady), controller 110 outputs “D0” as DataIn[7:0] at timing t5. Conversion circuit 120 transmits the “D0” of DataIn[7:0] received from controller 110 to transceiver 200 as DATA[7:0].

[0032] At timing t6, output "D1" as DataIn[7:0]. The conversion circuit (CNVR) 120 transmits "D1" of DataIn[7:0] received from the controller 110 to the transceiver 200 as DATA[7:0].

[0033] At timing t7, the controller 110 deactivates (negates) the data valid signal (TxValid). Based on the deactivated data valid signal (TxValid) received from the controller 110, the conversion circuit 120 activates the signal (STP) and transmits it to the transceiver 200.

[0034] At timing t8, the transceiver 200 deactivates the transmission request signal (NXT) based on the activated signal (STP).

[0035] Although not shown in FIG. 4, DIR shown in FIG. 5 is a signal indicating the transmission / reception direction of 8-bit data (DATA[7:0]). When transmitted from the conversion circuit 120 to the transceiver 200, it is deactivated, and when transmitted from the transceiver 200 to the conversion circuit 120, it is activated. In FIG. 5, DIR is deactivated.

[0036] As described above, when the transmission command is "01_00b + 0000b", the transceiver 200 converts the packet data into data without a transmission command. Therefore, " / PID + PID" is not transmitted to the device 300.

[0037] Next, the configuration of the USB system in the embodiment will be described with reference to FIG. 6. FIG. 6 is a block diagram showing the USB system in the embodiment.

[0038] The USB system 10 in the embodiment is composed of a USB controller (CNTR) 110, an interface conversion circuit (CNVR) 120, a transceiver (TRX) 200, and a USB device (DVC) 300, which are the same as those in the comparative example. However, a determination circuit (JDG) 141 as the first circuit and a control circuit (CNT) 142 as the second circuit are provided on the bus 131 connecting the controller 110 and the conversion circuit 120.

[0039] The determination circuit 141 is connected to a data bus 131a through which DataIn[7:0] of the bus 131 is transmitted and a signal line 131b through which a data valid signal (TxValid) is transmitted. The determination circuit 141 recognizes and holds the PID of the packet data transmitted from the controller 110. That is, the determination circuit 141 determines whether the PID is an LPM token. The determination circuit 141 outputs a determination result (LPMT) to the signal line 143.

[0040] The control circuit 142 is connected to a signal line 131d through which a first transmission permission signal (TxReady1) is transmitted, a signal line 131c through which a second transmission permission signal (TxReady2) is transmitted, and a signal line 143 through which the determination result (LPMT) is transmitted. The control circuit 142 controls the transmission of the second transmission permission signal (TxReady2) from the conversion circuit 120 to the controller 110 according to the PID.

[0041] The packet data when the USB system in the embodiment transmits an LPM token will be described with reference to FIG. 7. FIG. 7 is a diagram showing the packet data when the USB system shown in FIG. 6 transmits an LPM token.

[0042] (a) The controller 110 generates an LPM token (PID = 0000b). Then, the USB controller 110 outputs the generated packet data to the data bus 131a.

[0043] (a’) The determination circuit 141 discriminates the PID from the data of the first byte of DataIn[7:0]. Here, since DataIn[7:0] = F0h, the determination circuit 141 determines that the PID is an LPM token, activates the LPMT, and outputs it to the control circuit 142 via the signal line 143. Here, the “h” in “F0h” indicates that the previous alphanumeric characters are hexadecimal numbers.

[0044] The control circuit 142 converts the activated first transmission permission signal (TxReady1) transmitted via the signal line 131d into TxReady2. That is, the control circuit 142 masks the first cycle of the activated first transmission permission signal (TxReady1) to generate a second transmission permission signal (TxReady2), and releases the mask from the activation cycle of the next first transmission permission signal (TxReady1). The control circuit 142 transmits the second transmission permission signal (TxReady2) to the controller 110 via the signal line 131d. As a result, the controller (CNTR) 110 holds the output of “ / PID+PID”, and “ / PID+PID” is output in two bytes to the data bus 131a.

[0045] When the determination circuit 141 determines that the PID is other than the LPM token, the control circuit 142 does not mask the first transmission permission signal (TxReady1), and generates a second transmission permission signal (TxReady2) that is the same signal as the first transmission permission signal (TxReady1).

[0046] (b) The conversion circuit 120 generates “01_00b+0000b” as a transmission command from the first byte of “ / PID+PID”, and treats the second byte of “ / PID+PID” as data. Then, the conversion circuit 120 transmits the generated packet data to the transceiver 200 via the bus 132.

[0047] (c) As described above, when PID = 0000b, it enters the "mode where PID is not transmitted" (ULPI standard operation), and the first byte of " / PID + PID" is not transmitted. However, since the second byte of " / PID + PID" is data, the packet data restored by the transceiver 200 will have a data sequence with the second byte of " / PID + PID" remaining.

[0048] (d) The transceiver 200 performs data conversion according to the USB2.0 standard. Then, the transceiver 200 transmits the generated packet data to the device 300 via the bus 133.

[0049] When the PID is other than the LPM token, packet data as shown in Figure 2 is transmitted.

[0050] The details of packet transmission when the PID is the LPM token will be described with reference to Figures 6 and 8. Figure 8 is a timing chart showing the operations of the controller and the conversion circuit shown in Figure 6.

[0051] The operations at timings t1 to t3 and t6 to t8 are the same as those in Figure 5.

[0052] After receiving the transmission command of DATA[7:0], the transceiver 200 activates the transmission request signal (NXT) at timing t4 and transmits it to the conversion circuit 120. The conversion circuit 120 activates the received transmission request signal (NXT) as the first transmission permission signal (TxReady1) and transmits it to the control circuit 142. The control circuit 142 masks the first cycle of the activated first transmission permission signal (TxReady1) to generate the second transmission permission signal (TxReady2), and transmits the inactive second transmission permission signal (TxReady2) to the controller 110 via the signal line 131d. Here, DATA[7:0] is valid at timings t4 to t7.

[0053] Note that at timing t4, since the second transmission permission signal (TxReady2) is deactivated, the controller 110 holds the output of " / PID+PID" as DataIn[7:0] between timings t4' and t5. Here, DataIn[7:0] is valid between timings t4' and t7.

[0054] At timing t4', the control circuit 142 releases the mask of the activated first transmission permission signal (TxReady1) and activates the second transmission permission signal (TxReady2). The control circuit 142 transmits the activated second transmission permission signal (TxReady2) to the controller 110 via the signal line 131c. The conversion circuit 120 transmits the " / PID+PID" of DataIn[7:0] received from the controller 110 to the transceiver 200 as DATA[7:0].

[0055] In response to the activated second transmission permission signal (TxReady2), the controller 110 outputs "D0" as DataIn[7:0] at timing t5. The conversion circuit 120 transmits "D0" received from the controller 110 as DataIn[7:0] to the transceiver 200 as DATA[7:0].

[0056] Note that when the PID is other than the LPM token, the packet data is transmitted in the same timing as shown in FIG. 5.

[0057] According to the embodiment, even when the USB controller having an interface circuit compliant with the UMTI+ standard transmits an LPM token to a transceiver having an interface circuit compliant with the ULPI standard via a conversion circuit, the transceiver can normally transmit the LPM token to the USB device. Also, there is no need to change the USB controller and the conversion circuit.

[0058] As described above in detail based on the embodiments of the disclosure made by the present disclosure, it goes without saying that the present disclosure is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Signs

[0059] 100 Semiconductor device 110 Controller 111 UTMI+ circuit (first interface circuit) 120 Conversion circuit 121 UTMI+ circuit (second interface circuit) 122 ULPI circuit (third interface circuit) 141 Determination circuit (first circuit) 142 Control circuit (second circuit)

Claims

1. A controller having a first interface circuit compliant with the UTMI+ standard, a conversion circuit having a second interface circuit compliant with the UTMI+ standard and a third interface circuit compliant with the ULPI standard, the second interface circuit converting data received from the first interface circuit and transmitting the data from the third interface circuit, a first circuit that analyzes a packet output by the controller and recognizes and holds a packet identifier included in the packet, and a second circuit for adding a data sequence including the packet identifier indicating the LPM (Link Power Management) for reducing the power consumption of the USB device after a transmission command when the first circuit determines that the packet identifier is the LPM. A semiconductor device comprising.

2. In the semiconductor device according to claim 1, the conversion circuit is configured to convert the packet identifier into the transmission command and transmit a first transmission permission signal to the second circuit, and the controller is configured to output the data next to the packet identifier in the data sequence when receiving a second transmission permission signal. A semiconductor device.

3. In the semiconductor device according to claim 2, when the first circuit determines that the packet identifier is the LPM, the second circuit is configured to transmit the second transmission permission signal to the controller. A semiconductor device.

4. In the semiconductor device according to claim 3, the second circuit is configured to activate the second transmission permission signal one clock cycle after detecting that the first transmission permission signal is activated. A semiconductor device.

5. In the semiconductor device according to claim 4, the conversion circuit is configured to output a packet identifier indicating the LPM from the third interface circuit following the transmission command. A semiconductor device.

6. In the semiconductor device according to claim 2, when the first circuit determines that the packet identifier is other than LPM, the second circuit is configured to transmit the second transmission permission signal to the controller. A semiconductor device.

7. In the semiconductor device according to claim 6, the second circuit is configured to activate the second transmission permission signal at the same clock when detecting that the first transmission permission signal is activated. A semiconductor device.

8. In the semiconductor device according to claim 7, The conversion circuit is a semiconductor device configured to output data from the third interface circuit following the transmission command.

9. A controller having a first interface circuit compliant with the UTM I+ standard, A conversion circuit having a second interface circuit compliant with the UTM I+ standard and a third interface circuit compliant with the ULPI standard, wherein the second interface circuit converts data received from the first interface circuit and transmits it from the third interface circuit, A first circuit that analyzes a packet output by the controller and recognizes and holds a packet identifier included in the packet, A semiconductor device comprising: a second circuit for adding a data sequence including a packet identifier indicating the LPM when the first circuit determines that the packet identifier is an LPM (Link Power Management) for reducing power consumption of the USB device, after a transmission command. A transceiver connected to the third interface circuit, A USB device connected to the transceiver, A USB system comprising.

10. A controller having a first interface circuit compliant with the UTM I+ standard, A conversion circuit having a second interface circuit compliant with the UTM I+ standard and a third interface circuit compliant with the ULPI standard, wherein the second interface circuit converts data received from the first interface circuit and transmits it from the third interface circuit, A packet transmission method for a semiconductor device comprising: Analyzing a packet output by the controller, recognizing and holding a packet identifier included in the packet, A packet transmission method in which, when it is determined that the packet identifier is an LPM (Link Power Management) for reducing power consumption of the USB device, a data sequence including a packet identifier indicating the LPM is added after a transmission command.

Citation Information

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