Back-contact battery and method for manufacturing the same

Abstract

Provided are a back contact battery and a method for manufacturing the same, which are advantageous for improving the operating performance of the back contact battery in order to enhance the carrier collection efficiency. 【Solution means】The back contact battery includes a silicon substrate 11, and a first doped semiconductor layer 12 and a second doped semiconductor layer 13 that are alternately distributed at intervals on the non-light-receiving surface side of the silicon substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. On the non-light-receiving surface of the silicon substrate, the region corresponding to the first doped semiconductor layer is the first region 14, the region corresponding to the second doped semiconductor layer is the second region 15, and the region located between the first region and the second region adjacent to itself is the interval region 16. The surface of the second region is recessed into the silicon substrate with respect to the surface of the first region. The surface of the interval region is recessed into the silicon substrate with respect to the surface of the second region, and the depth of the recess into the silicon substrate with respect to the surface of the first region is less than 3000 nm.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic power generation, and particularly to a back contact battery and a manufacturing method thereof.

Background Art

[0002] A back contact battery is a solar cell in which there are no electrodes on the light-receiving surface of the battery cell, and both the positive electrode and the negative electrode are provided on the non-light-receiving surface side of the battery cell. Thereby, the shielding of the battery cell by the electrodes can be reduced, the short-circuit current of the battery cell can be increased, and the energy conversion efficiency of the battery cell can be improved. Further, by forming a surface passivation layer on the non-light-receiving surface side of the back contact battery, the carrier recombination rate on the non-light-receiving surface side of the back contact battery can be reduced, and the photoelectric conversion efficiency of the back contact battery can be improved.

[0003] However, in conventional back contact batteries, the carrier collection efficiency is low, which is disadvantageous for improving the operating performance of the back contact battery.

Summary of the Invention

[0004] An object of the present invention is to provide a back contact battery and a manufacturing method thereof, which are advantageous for improving the operating performance of the back contact battery, shortening the movement distance of some carriers, and increasing the carrier collection efficiency while preventing the first doped semiconductor layer and the second doped semiconductor layer from conducting.

[0005] To achieve the above object, in a first aspect, the present invention provides a back contact battery including a silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer that are alternately distributed at intervals on the non-light-receiving surface side of the silicon substrate. Here, the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. On the non-light-receiving surface of the silicon substrate, the region corresponding to the first doped semiconductor layer is the first region, the region corresponding to the second doped semiconductor layer is the second region, and the region located between the first region and the second region adjacent to itself is the spacing region. The surface of the second region is recessed into the silicon substrate with respect to the surface of the first region. The surface of the spacing region is recessed into the silicon substrate with respect to the surface of the second region, and the depth at which the surface of the spacing region is recessed into the silicon substrate with respect to the surface of the first region is less than 3000 nm.

[0006] When the above technical solution is used, in the back contact battery provided by the present invention, the first doped semiconductor layer and the second doped semiconductor layer with opposite conductivity types are distributed alternately at intervals on the non-light-receiving surface side of the silicon substrate. Based on this, the interval region on the non-light-receiving surface of the silicon substrate isolates the above-mentioned first doped semiconductor layer and the second doped semiconductor layer, and can reduce the carrier recombination rate at the lateral boundary between the first doped semiconductor layer and the second doped semiconductor layer, which is advantageous for improving the photoelectric conversion efficiency of the back contact battery. Next, since the first doped semiconductor layer is formed in the first region of the non-light-receiving surface and the second doped semiconductor layer is formed in the second region of the non-light-receiving surface, when the surface of the second region is recessed into the silicon substrate with respect to the surface of the first region, and the surface of the interval region is recessed into the silicon substrate with respect to the surface of the second region, in the actual manufacturing process, after selectively etching the first doped semiconductor layer that covers the entire layer on the non-light-receiving surface side, not only the portions of the first doped semiconductor layer located in the second region and the interval region are completely removed, but it is obvious that the silicon substrate is also etched with a certain thickness in part, ensuring that there is no residue of the first doped semiconductor layer in the second region and the interval region, preventing short circuits, and it is also advantageous to shift at least partially in the thickness direction of the silicon substrate the first doped semiconductor layer and the second doped semiconductor layer that are both located on the non-light-receiving surface side of the silicon substrate and have opposite conductivity types, further reducing the leakage risk on the non-light-receiving surface side and enhancing the electrical reliability of the back contact battery. Similarly, when the surface of the interval region is recessed into the silicon substrate with respect to the surface of the second region, in the actual manufacturing process, after selectively etching the first doped semiconductor layer, the second doped semiconductor layer deposited in the second region and the interval region, not only the portions of the second doped semiconductor layer located in the first doped semiconductor layer and the interval region are completely removed, but it is obvious that the portion of the silicon substrate corresponding to the interval region is also etched with a certain thickness, ensuring that there is no residue of the second doped semiconductor layer in the first doped semiconductor layer and the interval region, preventing short circuits.

[0007] Also, as can be understood from the above, on the non-light-receiving surface of the silicon substrate, the depth of the recess into the silicon substrate in the spacing region is the largest, and the depth at which the spacing region is recessed into the silicon substrate with respect to the surface of the first region is less than 3000 nm. Based on this, in the back contact battery provided by the present invention, compared with the case where the depth of the recess into the silicon substrate in the spacing region in the prior art is 5 μm, the depth of the recess into the silicon substrate in the spacing region is smaller. In this case, carriers of the corresponding conductivity type can be collected by the first doped semiconductor layer or the second doped semiconductor layer without bypassing the spacing region with a large depth. Thereby, the movement distance of some carriers can be shortened, the carrier collection efficiency can be increased, which is advantageous for improving the operating performance of the back contact battery.

[0008] As a possible implementation form, the surface of the above-mentioned spacing region is flat. In this case, the surface of the spacing region is relatively flat. Based on this, when the back contact battery further includes a surface passivation layer, compared with the texture, the thickness of the portion of the surface passivation layer formed in the spacing region with a flat surface is larger, the passivation effect of the surface passivation layer on the spacing region can be enhanced, the carrier recombination rate on the surface of the spacing region can be reduced, which is advantageous for improving the photoelectric conversion efficiency of the back contact battery.

[0009] As a possible implementation form, the roughness within a range of per 10,000 square micrometers on the surface of the spacing region is 30 μm or less. The beneficial effect in this case is similar to the beneficial effect when the surface of the spacing region is flat, and the description is omitted here.

[0010] As a possible implementation form, in the arrangement direction of the first region and the second region, the length of the spacing region is 20 μm or more and 110 μm or less.

[0011] When the above technical solution is used, the length of the interval region is within the above range. Since the interval is small, leakage between the first doped semiconductor layer and the second doped semiconductor layer can be prevented, and high electrical reliability of the back contact battery can be ensured. Also, since the interval is large, the formation range on the non-light-receiving surface side of the first doped semiconductor layer and / or the second doped semiconductor layer becomes small, preventing carriers on the non-light-receiving surface side from not being timely collected by the first doped semiconductor layer and / or the second doped semiconductor layer and not being able to be led out from the corresponding electrode, and the carrier recombination rate on the non-light-receiving surface side can also be further reduced.

[0012] As a possible implementation form, the surface of the second region is flat. In this case, the surface of the second region is relatively flat, which is advantageous for improving the formation quality of the second doped semiconductor layer formed in the second region. Also, since the undulation degree of the surface of the second doped semiconductor layer formed in the second region is similar to that of the surface of the second region, when the surface of the second region is flat, it is also advantageous for improving the surface flatness of the side of the second doped semiconductor layer away from the silicon substrate. Based on this, when the back contact battery further includes a surface passivation layer, compared with the texture, the thickness of the portion of the surface passivation layer formed on the second doped semiconductor layer with high surface flatness is larger, enhancing the passivation effect of the surface passivation layer on the side of the second doped semiconductor layer away from the silicon substrate, further reducing the carrier recombination rate on the non-light-receiving surface side of the back contact battery, and being advantageous for improving the photoelectric conversion efficiency of the back contact battery.

[0013] As a possible implementation form, the depth of the recess of the surface of the second region into the silicon substrate is 100 nm or more and 1000 nm or less.

[0014] When the above technical solution is used, the recess depth of the surface of the second region into the silicon substrate is within the above range. Since the recess depth of the surface of the second region into the silicon substrate is small, both are located on the non-light-receiving surface side of the silicon substrate, and the degree of displacement in the silicon substrate thickness direction between the first doped semiconductor layer and the second doped semiconductor layer with opposite conductivity types is reduced, which can further reduce the risk of leakage on the non-light-receiving surface side. In addition, since the spacing region is recessed into the silicon substrate with respect to the second region, that is, since the recess depth of the spacing region into the silicon substrate is larger than that of the second region, when the recess depth of the surface of the second region into the silicon substrate is within the above range, due to the large recess depth of the surface of the second region into the silicon substrate, it is possible to prevent the recess depth of the spacing region into the silicon substrate from becoming larger, and to ensure that the movement distance of a part of the carriers transported around the spacing region to the first doped semiconductor layer or the second doped semiconductor layer is small. Also, due to the large recess depths of the second region and the spacing region into the silicon substrate, it is possible to prevent the use of a thick silicon substrate, thereby reducing the manufacturing cost of the back-contact battery and being advantageous for realizing the sheet production of the back-contact battery.

[0015] As a possible implementation form, the height difference between the surface of the second region and the surface of the spacing region is 300 nm or more and less than 2000 nm.

[0016] When the above technical solution is used, the height difference between the surface of the second region and the surface of the spacing region is within the above range. Since the height difference is small, in the actual manufacturing process, if the etching time is not strictly controlled after completely removing the portion of the second doped semiconductor layer located in the spacing region, it can be prevented that the etching depth of the etching agent for the spacing region of the silicon substrate cannot be reduced, and the difficulty of etching can be lowered. Since the height difference is large, it can be prevented that the movement distance of the carriers of the corresponding conductivity type does not decrease too much, and the possibility of improving the carrier collection efficiency can also be ensured.

[0017] As a possible implementation form, the side surfaces close to the spacing region between the first doped semiconductor layer and the second doped semiconductor layer are both substantially wavy. Here, the corresponding fluctuation width of the side surface close to the spacing region of the second doped semiconductor layer is larger than the corresponding fluctuation width of the side surface close to the spacing region of the first doped semiconductor layer, and / or the corresponding fluctuation frequency of the side surface close to the spacing region of the second doped semiconductor layer is smaller than the corresponding fluctuation frequency of the side surface close to the spacing region of the first doped semiconductor layer.

[0018] When the above technical solution is used, when the side surfaces close to the spacing region between the first doped semiconductor layer and the second doped semiconductor layer are both substantially wavy, if the corresponding fluctuation width of the side surface close to the spacing region of the second doped semiconductor layer is larger than the corresponding fluctuation width of the side surface close to the spacing region of the first doped semiconductor layer, the roughness of the local region of the side surface close to the spacing region of the second doped semiconductor layer is smaller than the roughness of the local region of the side surface close to the spacing region of the first doped semiconductor layer, reducing the number of defects in the portion close to the spacing region of the formed second doped semiconductor layer, and further being advantageous for reducing the carrier recombination rate in the portion close to the spacing region of the second doped semiconductor layer, and the operating performance of the back contact battery is further improved.

[0019] As a possible implementation form, on the sidewall of the above spacing region, at least a part of the surface is provided obliquely with respect to the horizontal plane such that at least a part of the cross-sectional area of the spacing region gradually increases in the direction from the light-receiving surface to the non-light-receiving surface.

[0020] When the above technical solution is used, the cross-sectional area of the light-receiving surface side of the spacing region is smaller than that of the non-light-receiving surface side of itself, which is advantageous for increasing the spacing between the first doped semiconductor layer and the second doped semiconductor layer having a conductivity type opposite to that of itself. The leakage risk on the non-light-receiving surface side of the back contact battery is reduced, and high electrical reliability of the back contact battery is ensured. In addition, the portion provided obliquely with respect to the horizontal plane on the side wall of the spacing region is also advantageous for reflection of light rays. More light rays are advantageously incident from the non-light-receiving surface side of the back contact battery into the silicon substrate under the reflection action of the portion provided obliquely with respect to the horizontal plane on the side wall of the spacing region, and further advantageous for improving the photoelectric conversion efficiency of the back contact battery.

[0021] As a possible implementation form, the above back contact battery further includes a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacing region.

[0022] When the above technical solution is used, the surface passivation layer can passivate the non-light-receiving surface side of the back contact battery and reduce the carrier recombination rate on the non-light-receiving surface side. In addition, since the spacing region having the largest recess depth into the silicon substrate has a corresponding recess depth of less than 3000 nm, it is advantageous for reducing the undulation degree of each region on the non-light-receiving surface side of the back contact battery, increasing the formation thickness of the non-light-receiving surface side of the surface passivation layer, and enhancing the passivation effect of the surface passivation layer on the non-light-receiving surface side.

[0023] As a possible implementation form, the above back contact battery further includes a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer.

[0024] When the above technical solution is used, the first passivation layer and the first doped semiconductor layer form a selective contact structure to achieve chemical passivation for the first region on the non-light-receiving surface of the silicon substrate, and also achieve selective collection for carriers of the corresponding conductivity type, which can reduce the carrier recombination rate on the non-light-receiving surface side and is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

[0025] As a possible implementation form, the above back contact battery further includes a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

[0026] When the above technical solution is used, the second passivation layer and the second doped semiconductor layer form a selective contact structure to achieve chemical passivation for the second region on the non-light-receiving surface of the silicon substrate, and also achieve selective collection for carriers of the corresponding conductivity type, which can reduce the carrier recombination rate on the non-light-receiving surface side and is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

[0027] As a possible implementation form, when the back contact battery includes the first passivation layer and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer.

[0028] As a possible implementation form, when the back contact battery includes the second passivation layer and the second passivation layer is a tunnel passivation layer, the second doped semiconductor layer is a doped polycrystalline silicon layer.

[0029] On the second side, the present invention provides a method for manufacturing a back-contact battery, including the steps of preparing a silicon substrate, on the non-light-receiving surface of which there are a first region and a second region that are alternately distributed at intervals, and an interval region located between the first region and the second region adjacent to itself; forming a first doped semiconductor layer in the first region, and recessing both the surfaces of the interval region and the second region into the silicon substrate with respect to the surface of the first region; forming a second doped semiconductor layer in the second region, recessing the surface of the interval region into the silicon substrate with respect to the surface of the second region, and making the depth at which the surface of the interval region is recessed into the silicon substrate with respect to the surface of the first region less than 3000 nm.

[0030] As a possible implementation form, after the step of preparing the silicon substrate and before forming the second doped semiconductor layer in the second region, the method for manufacturing a back-contact battery includes the steps of forming a first doped semiconductor layer provided throughout the layer and a first mask layer located in a portion corresponding to the first region of the first doped semiconductor layer on the non-light-receiving surface of the silicon substrate; and selectively removing portions of the first doped semiconductor layer located in the interval region and the second region under the masking action of the first mask layer, and recessing both the surfaces of the interval region and the second region into the silicon substrate with respect to the surface of the first region.

[0031] As a possible implementation form, the material of the first doped semiconductor layer includes silicon. Further, the step of forming the first doped semiconductor layer provided in all layers and the first mask layer located in a portion corresponding to the first region of the first doped semiconductor layer on the non-light-receiving surface of the silicon substrate includes: forming a first intrinsic semiconductor layer provided in all layers on the non-light-receiving surface of the silicon substrate; doping the first intrinsic semiconductor layer to form the first intrinsic semiconductor layer as the first doped semiconductor layer, and forming a first doped silicate glass layer provided in all layers on the first doped semiconductor layer; heat-treating the spaced region of the first doped silicate glass layer and the portion corresponding to the second region by a laser etching process to form the non-heat-treated portion of the first doped silicate glass layer as the first mask layer; and removing the heat-treated portion of the first doped silicate glass layer.

[0032] When the above technical solution is used, when the material of the first doped semiconductor layer includes silicon, the material of the first intrinsic semiconductor layer for manufacturing the first doped semiconductor layer also includes silicon. Based on this, after doping the first intrinsic semiconductor layer, not only can the first doped semiconductor layer be obtained, but also a first doped silicate glass layer provided in all layers can be formed on the first doped semiconductor layer. Then, a part of the first doped silicate glass layer is heat-treated by a laser etching process. In this case, the laser-treated portion in the first doped silicate glass layer has low density and is easily removed. On the other hand, the non-laser-treated portion in the first doped silicate glass layer has high density and is difficult to remove. As a result, after heat treatment, different portions of the first doped silicate glass layer have different etching selectivity ratios, and a first mask layer for patterning the first doped semiconductor layer is obtained. There is no need to additionally form other mask materials and other mask deposition processes to obtain the above first mask layer, which is advantageous for reducing the manufacturing cost of the back contact battery and simplifying the manufacturing process of the back contact battery.

[0033] As a possible implementation form, by means of a wet chemical process, under the mask action of the first mask layer, the spaced regions of the first doped semiconductor layer and the portions located in the second region are selectively removed, and the surfaces of both the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region. Here, the process temperature of the wet chemical process is 60°C or higher and 80°C or lower, and / or the process time of the wet chemical process is 40 s or longer and 200 s or shorter, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower, and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

[0034] When the above technical solution is used, both the process temperature and the process time of the wet chemical process affect the depth at which the surfaces of the spacer region and the second region are recessed into the silicon substrate with respect to the surface of the first region. Based on this, when the process temperature of the wet chemical process is within the above range, due to the low process temperature, it is possible to prevent the depth at which the surfaces of both the spacer region and the second region are recessed into the silicon substrate with respect to the surface of the first region from becoming small. Also, due to the high process temperature, it is possible to prevent the depth at which the surfaces of both the spacer region and the second region are recessed into the silicon substrate with respect to the surface of the first region from becoming large. After this operation, the depth at which the surfaces of the spacer region and the second region are recessed into the silicon substrate with respect to the surface of the first region is equal to the depth at which the surface of the second region in the formed back contact battery is recessed into the silicon substrate with respect to the surface of the first region. Here, for the beneficial effect of preventing the depth at which the surface of the second region is recessed into the silicon substrate with respect to the surface of the first region from becoming large or small, reference may be made to the foregoing text. Next, the beneficial effect of the process time and the volume ratio of the alkaline component being within the above range is similar to the beneficial effect of the process temperature being 60 °C or higher and 80 °C or lower, and the description thereof will be omitted here. Also, when the volume ratio of the polishing additive in the wet chemical etching solution is within the above range, the flatness of the surfaces of the spacer region and the second region after this operation can be enhanced, and the passivation effect of the surface passivation layer on the spacer region and the second doped semiconductor layer can be further enhanced.

[0035] As a possible implementation form, after the above step of recessing both the surfaces of the spacer region and the second region into the silicon substrate with respect to the surface of the first region, the method for manufacturing a back contact battery includes depositing a first doped semiconductor layer, a spacer region, and a second doped semiconductor layer on the second region, and forming a second mask layer on a portion corresponding to the second region of the second doped semiconductor layer; and selectively removing portions corresponding to the first region and the spacer region of the second doped semiconductor layer under the masking action of the second mask layer, and recessing the surface of the spacer region into the silicon substrate with respect to the surface of the second region.

[0036] As a possible implementation form, the material of the second doped semiconductor layer includes silicon. Further, the steps of depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region, and forming the second mask layer on the portion corresponding to the second region of the second doped semiconductor layer include depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region, doping the second intrinsic semiconductor layer to form the second doped semiconductor layer, and forming a second doped silicate glass layer provided over the entire layer on the second doped semiconductor layer, and heat-treating portions corresponding to the first region and the spacer region of the second doped silicate glass layer by a laser etching process to form a portion corresponding to the second region of the second doped silicate glass layer as the second mask layer, and removing the heat-treated portion of the second doped silicate glass layer.

[0037] When the above technical solution is used, when the material of the second doped semiconductor layer includes silicon, the material of the second intrinsic semiconductor layer for manufacturing the second doped semiconductor layer also includes silicon. Based on this, after doping the second intrinsic semiconductor layer, not only can the second doped semiconductor layer be obtained, but also a second doped silicate glass layer provided over the entire layer can be formed on the second doped semiconductor layer. Then, the portions corresponding to the first region and the spacer region of the second doped silicate glass layer are heat-treated by a laser etching process. In this case, the laser-treated portion in the second doped silicate glass layer has low density and is easily removed. On the other hand, since the portion corresponding to the second region of the second doped silicate glass layer is not laser-treated, it has high density and is difficult to remove. As a result, after heat treatment, different portions of the second doped silicate glass layer have different etching selectivity ratios, and a second mask layer for patterning the second doped semiconductor layer is obtained, eliminating the need to additionally form other mask materials and form other mask deposition processes to obtain the second mask layer, which is advantageous for reducing the manufacturing cost of the back contact battery and simplifying the manufacturing flow of the back contact battery.

[0038] As a possible implementation form, under the masking action of the second mask layer, the portions corresponding to the first region and the spacer region of the second doped semiconductor layer are selectively removed by a wet chemical process, and the surface of the spacer region is recessed into the silicon substrate with respect to the surface of the second region. Here, the process temperature of the wet chemical process is 60°C or higher and 80°C or lower, and / or the process time of the wet chemical process is 50 s or longer and 300 s or shorter, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower, and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

[0039] When the above technical solution is used, both the process temperature and the process time of the wet chemical process affect the depth at which the surface of the spacer region is recessed into the silicon substrate with respect to the surface of the second region by the wet chemical process. Based on this, when the process temperature of the wet chemical process is within the above range, it is possible to prevent the depth at which the surface of the spacer region is recessed into the silicon substrate with respect to the surface of the second region from becoming small due to the small process temperature. Also, it is possible to prevent the depth at which the surface of the spacer region is recessed into the silicon substrate with respect to the surface of the second region from becoming large due to the large process temperature. Here, for the beneficial effects of preventing the depth at which the surface of the spacer region is recessed into the silicon substrate with respect to the surface of the second region from becoming small or large, reference may be made to the foregoing text. Next, the beneficial effects of the process time and the volume ratio of the alkaline component being within the above range are similar to the beneficial effects of the process temperature being 60°C or higher and 80°C or lower, and the description thereof is omitted here. Also, when the volume ratio of the polishing additive in the wet chemical etching solution is within the above range, the flatness of the surface of the spacer region after the operation can be improved, and the passivation effect of the surface passivation layer on the spacer region can be further enhanced.

[0040] As a possible implementation form, after preparing a silicon substrate and before forming a first doped semiconductor layer in a first region, the manufacturing method of the back contact battery further includes a step of forming a first passivation layer in the first region.

[0041] As a possible implementation form, after both the surface of the spacing region and the surface of the second region are recessed into the silicon substrate with respect to the surface of the first region and before forming a second doped semiconductor layer in a portion of the second region, the manufacturing method of the back contact battery further includes a step of forming a second passivation layer in the second region.

[0042] As a possible implementation form, after the surface of the spacing region is recessed into the silicon substrate with respect to the surface of the second region, the manufacturing method of the back contact battery further includes a step of forming a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacing region.

[0043] For the beneficial effects of the second aspect and its various embodiments in the present invention, reference may be made to the analysis of the beneficial effects in the first aspect and its various embodiments, and the description is omitted here.

Brief Description of the Drawings

[0044] The drawings described in this specification are for further understanding of the present invention and form part of the present invention. The exemplary embodiments and their descriptions of the present invention are for interpreting the present invention and are not intended to limit the present invention inappropriately. The description of the drawings is provided below.

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Embodiments for Carrying Out the Invention

[0045] In the following, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are merely exemplary and do not limit the scope of the present disclosure. In the following description, descriptions of known structures and technologies are omitted so as not to be unnecessarily confused with the concept of the present disclosure.

[0046] The drawings show various structural schematic diagrams according to embodiments of the present disclosure. These figures are not drawn to scale, and here, for clear representation, some details may be enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, and their relative sizes and positional relationships are merely exemplary, and in reality, there may be variations due to manufacturing tolerances and technical limitations. Also, those skilled in the art can separately design regions / layers having different shapes, sizes, and relative positions according to actual needs.

[0047] In the context of the present disclosure, when it is described that one layer / element is located "above" another layer / element, this layer / element may be directly located above this other layer / element, or there may be an intermediate layer / element between them. Also, when one layer / element is located "above" another layer / element in a certain orientation, if the orientation is changed, this layer / element can be located "below" the other layer / element. In order to more clearly illustrate the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention, the drawings and embodiments will be combined below to describe the present invention in more detail. It should be understood that the specific embodiments described herein are only for interpreting the present invention and not for limiting the present invention.

[0048] Moreover, the terms "first" and "second" are only for explanatory purposes and should not be understood as indicating or implying relative importance or indicating the quantity of the technical features to be described. Therefore, the features defined as "first" and "second" can explicitly or implicitly include one or more of such features. In the description of the present invention, unless explicitly and specifically limited, "a plurality" means two or more. Unless explicitly and specifically limited, "several" means one or more.

[0049] In the description of the present invention, where it should be explained, unless clearly defined and limited, the terms "attach", "connect", and "couple" should be understood in a broad sense. For example, they may be fixedly connected, removably connected, integrally connected, mechanically connected, electrically connected, directly connected, or indirectly connected through an intermediate medium, and may also be a relationship of internal communication between two elements or an interaction relationship between two elements. A person skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific situation.

[0050] Currently, solar cells are becoming a new alternative energy form with a wider range of applications. Among them, photovoltaic solar cells are devices that convert solar light energy into electrical energy. Specifically, solar cells utilize the principle of photovoltaic effect to generate carriers, and then extract the carriers through electrodes, which is advantageous for effectively using electrical energy.

[0051] Here, if both the positive electrode and the negative electrode included in the solar cell are located on the non-light-receiving surface of the solar cell, the solar cell is a back-contact cell. Since the light-receiving surface of the back-contact cell is not affected by the shielding of the metal electrode, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency than a solar cell with a shielded light-receiving surface, and is currently one of the technological trends for realizing high-efficiency crystalline silicon cells. Specifically, as shown in Figure 1, a conventional back-contact cell usually includes a silicon substrate 11, and a first doped semiconductor layer 12 and a second doped semiconductor layer 13 that are alternately distributed at intervals on the non-light-receiving surface side of the silicon substrate 11. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types.

[0052] In the actual manufacturing process, usually, a first doped semiconductor layer provided throughout the layer is formed on the non-light-receiving surface side, and then the first doped semiconductor layer is selectively etched to retain only the first doped semiconductor layer located in a partial region of the non-light-receiving surface. Then, a second doped semiconductor layer is formed on the first doped semiconductor layer and the portion of the non-light-receiving surface that is exposed by the first doped semiconductor layer, and then the second doped semiconductor layer is selectively etched so that the first doped semiconductor layer and the second doped semiconductor layer are alternately distributed at intervals on the non-light-receiving surface of the silicon substrate.

[0053] However, as shown in FIG. 1, since the conductivity types of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are opposite, in order to prevent the first doped semiconductor layer 12 and the second doped semiconductor layer 13 from conducting and short - circuiting, in the conventional manufacturing method, an interval region 16 having a certain width is formed between the two by wet chemical etching or the like. However, in the conventional back - contact battery, since the recess depth into the silicon substrate 11 of the interval region 16 located between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 is large (for example, larger than 5 μm), carriers in the silicon substrate 11 cannot be collected by the first doped semiconductor layer 12 and the second doped semiconductor layer 13 respectively unless they bypass the interval region with a large depth. The movement distance of the carriers is long, the carrier collection efficiency is low, and the carrier recombination rate is high, which is disadvantageous for improving the operating performance of the back - contact battery.

[0054] In order to solve the above technical problems, on the first aspect, an embodiment of the present invention provides a back - contact battery. As shown in FIG. 2, the back - contact battery provided by the embodiment of the present invention includes a silicon substrate 11, and a first doped semiconductor layer 12 and a second doped semiconductor layer 13 that are alternately spaced and distributed on the non - light - receiving surface side of the silicon substrate 11. Here, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types. On the non - light - receiving surface of the silicon substrate 11, the region corresponding to the first doped semiconductor layer 12 is the first region 14, the region corresponding to the second doped semiconductor layer 13 is the second region 15, and the region located between the first region 14 and the second region 15 adjacent to itself is the interval region 16. The surface of the second region 15 is recessed into the silicon substrate 11 with respect to the surface of the first region 14. The surface of the interval region 16 is recessed into the silicon substrate 11 with respect to the surface of the second region 15, and the depth of the recess into the silicon substrate 11 with respect to the surface of the first region 14 is less than 3000 nm.

[0055] When the above technical solution is used, as shown in FIG. 2, in the back contact battery provided by the embodiment of the present invention, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 with opposite conductivity types are distributed alternately at intervals on the non-light-receiving surface side of the silicon substrate 11. Based on this, the interval region 16 on the non-light-receiving surface of the silicon substrate 11 isolates the above-mentioned first doped semiconductor layer 12 and second doped semiconductor layer 13, and can reduce the carrier recombination rate at the lateral boundary between the first doped semiconductor layer 12 and the second doped semiconductor layer 13, which is advantageous for improving the photoelectric conversion efficiency of the back contact battery. Next, since the first doped semiconductor layer 12 is formed in the first region 14 of the non-light-receiving surface and the second doped semiconductor layer 13 is formed in the second region 15 of the non-light-receiving surface, the surface of the second region 15 is recessed into the silicon substrate 11 with respect to the surface of the first region 14, and when the surface of the interval region 16 is recessed into the silicon substrate 11 with respect to the surface of the second region 15, in the actual manufacturing process, after selectively etching the first doped semiconductor layer 12 that covers the entire non-light-receiving surface side, not only the portions of the first doped semiconductor layer 12 located in the second region 15 and the interval region 16 are completely removed, but it is obvious that the silicon substrate 11 is also etched with a certain thickness in part, ensuring that there is no residue of the first doped semiconductor layer 12 in the second region 15 and the interval region 16, preventing short circuits, and it is also advantageous to shift at least partially in the thickness direction of the silicon substrate 11 the first doped semiconductor layer 12 and the second doped semiconductor layer 13 that are both located on the non-light-receiving surface side of the silicon substrate 11 and have opposite conductivity types, further reducing the leakage risk on the non-light-receiving surface side and enhancing the electrical reliability of the back contact battery. Similarly, when the surface of the interval region 16 is recessed into the silicon substrate 11 with respect to the surface of the second region 15, in the actual manufacturing process, after selectively etching the second doped semiconductor layer 13 deposited on the first doped semiconductor layer 12, the second region 15, and the interval region 16, not only the portions of the second doped semiconductor layer 13 located in the first doped semiconductor layer 12 and the interval region 16 are completely removed, but it is obvious that the portion of the silicon substrate 11 corresponding to the interval region 16 is also etched with a certain thickness, ensuring that there is no residue of the second doped semiconductor layer 13 in the first doped semiconductor layer 12 and the interval region 16, preventing short circuits.Also, as can be understood from the above, on the non-light-receiving surface of the silicon substrate 11, the recess depth of the interval region 16 into the silicon substrate 11 is the largest, and the depth at which the interval region 16 is recessed into the silicon substrate 11 with respect to the surface of the first region 14 is less than 3000 nm. Based on this, compared with the case where the recess depth of the interval region into the silicon substrate in the prior art is 5 μm, in the back contact battery provided by the embodiment of the present invention, the recess depth of the interval region 16 into the silicon substrate 11 is small. In this case, carriers of the corresponding conductivity type can be collected by the first doped semiconductor layer 12 or the second doped semiconductor layer without bypassing the interval region 16 with a large depth. Thereby, the movement distance of some carriers can be shortened, the carrier collection efficiency can be increased, which is advantageous for improving the operating performance of the back contact battery.

[0056] In the actual application process, as shown in FIG. 2, the light-receiving surface of the silicon substrate 11 may be flat, or the light-receiving surface of the silicon substrate may be textured. Here, since the texture has a light confinement effect, when the light-receiving surface of the silicon substrate is textured, it is advantageous to reduce the reflectivity of the light-receiving surface, and more light rays are refracted from the light-receiving surface into the silicon substrate and absorbed and utilized by the silicon substrate, which is advantageous for improving the photoelectric conversion efficiency of the back contact battery.

[0057] Also, from the perspective of range, the boundaries between the first region, the second region, and the spacing region on the non-light-receiving surface side of the silicon substrate are virtual boundaries. As shown in FIG. 2, since the first doped semiconductor layer 12 is formed in the first region 14, the range of the first region 14 on the non-light-receiving surface side of the silicon substrate 11 can be determined according to the formation range requirements of the first doped semiconductor layer 12 in the actual application scenario. Next, since the second doped semiconductor layer 13 is formed in the second region 15, the range of the second region 15 on the non-light-receiving surface side of the silicon substrate 11 can be determined according to the formation range requirements of the second doped semiconductor layer 13 in the actual application scenario. Regarding the spacing region 16, as described above, the spacing region 16 can isolate the first doped semiconductor layer 12 and the second doped semiconductor layer 13 with opposite conductivity types to suppress leakage. Therefore, the range of the spacing region 16 on the non-light-receiving surface side can be determined according to the requirements for the leakage prevention interval between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 in the actual application scenario.

[0058] Exemplarily, in the arrangement direction of the first region and the second region, the length of the spacing region is 20 μm or more and 110 μm or less. For example, the length of the spacing region may be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm, 110 μm, or the like. In this case, the length of the spacing region is within the above range. Since the above spacing is small, leakage between the first doped semiconductor layer and the second doped semiconductor layer can be prevented, and high electrical reliability of the back contact battery can be ensured. Also, since the above spacing is large, the formation range on the non-light-receiving surface side of the first doped semiconductor layer and / or the second doped semiconductor layer becomes small, and it is possible to prevent carriers on the non-light-receiving surface side from not being timely collected by the first doped semiconductor layer and / or the second doped semiconductor layer and not being led out from the corresponding electrode, and further reduce the carrier recombination rate on the non-light-receiving surface side.

[0059] From the perspective of the recess depth, the recess depths of the second region and the interval region in the silicon substrate on the non-light-receiving surface of the silicon substrate, and the height difference between the surfaces of the second region and the interval region may be determined according to the actual application scenario. The second region is recessed inward with respect to the surface of the first region, and the surface of the interval region is recessed inward with respect to the surface of the second region. And it is only necessary to ensure that the depth of the surface of the interval region recessed into the silicon substrate with respect to the surface of the first region is less than 3000 nm.

[0060] Exemplarily, the recess depth of the surface of the second region into the silicon substrate may be 100 nm or more and 1000 nm or less. For example, the recess depth of the surface of the second region into the silicon substrate may be 100 nm, 300 nm, 600 nm, 800 nm, 900 nm, or 1000 nm, etc. In this case, the recess depth of the surface of the second region into the silicon substrate is within the above range. Since the recess depth of the surface of the second region into the silicon substrate is small, both are located on the non-light-receiving surface side of the silicon substrate, and the degree of deviation in the thickness direction of the silicon substrate between the first doped semiconductor layer and the second doped semiconductor layer with opposite conductivity types is reduced, and the leakage risk on the non-light-receiving surface side can be further reduced. Also, since the interval region is recessed into the silicon substrate with respect to the second region, that is, since the recess depth of the interval region into the silicon substrate is larger than that of the second region, when the recess depth of the surface of the second region into the silicon substrate is within the above range, due to the large recess depth of the surface of the second region into the silicon substrate, it is possible to prevent the recess depth of the interval region into the silicon substrate from becoming larger, and ensure that the movement distance of some carriers transported to the first doped semiconductor layer or the second doped semiconductor layer bypassing the interval region is small. Also, since the recess depths of the second region and the interval region into the silicon substrate are large, it is also possible to prevent the use of a thick silicon substrate, thereby reducing the manufacturing cost of the back contact battery and being advantageous for realizing the sheet production of the back contact battery.

[0061] Exemplarily, the height difference between the surface of the second region and the surface of the spacing region may be 300 nm or more and less than 2000 nm. For example, the height difference between the surface of the second region and the surface of the spacing region may be 300 nm, 600 nm, 900 nm, 1200 nm, 1500 nm, 1800 nm, 2000 nm, or the like. In this case, the height difference between the surface of the second region and the surface of the spacing region is within the above range. Since the height difference is small, after completely removing the portion located in the spacing region of the second doped semiconductor layer in the actual manufacturing process, it is possible to prevent the etching depth of the etching agent with respect to the spacing region of the silicon substrate from being unable to be reduced without strictly controlling the etching time, and the difficulty of etching can be reduced. Since the height difference is large, it is possible to prevent the movement distance of carriers of the corresponding conductivity type from being overly reduced, and it is also possible to ensure the possibility of improving the carrier collection efficiency.

[0062] Regarding the recess depth of the spacing region into the silicon substrate, the depth value may be any value greater than the recess depth of the second region surface into the silicon substrate and less than 3000 nm. For example, when the recess depth of the second region surface into the silicon substrate is 500 nm, the depth at which the spacing region is recessed into the silicon substrate with respect to the surface of the first region is greater than 500 nm and may be any value less than 3000 nm (for example, 1000 nm, 1500 nm, 1800 nm, 2000 nm, 2500 nm, 2800 nm, 2900 nm, or the like).

[0063] From the perspective of the surface morphology, as shown in FIG. 2, on the non-light-receiving surface of the silicon substrate 11, the surface of the first region 14 is flat. The surface of the second region 15 may be flat or textured. Here, as shown in FIGS. 2 to 7, when the surface of the second region 15 is flat, the surface of the second region 15 is relatively flat, which is advantageous for improving the formation quality of the second doped semiconductor layer 13 formed in the second region 15. Also, since the undulation degree of the surface of the second doped semiconductor layer 13 formed in the second region 15 is similar to that of the surface of the second region 15, when the surface of the second region 15 is flat, it is also advantageous for improving the surface flatness of the side of the second doped semiconductor layer 13 away from the silicon substrate 11. Based on this, when the back contact battery further includes the surface passivation layer 17, compared with the texture, the thickness of the portion of the surface passivation layer 17 formed on the second doped semiconductor layer 13 with high surface flatness is larger, enhancing the passivation effect of the surface passivation layer 17 on the second doped semiconductor layer 13, further reducing the carrier recombination rate on the non-light-receiving surface side of the back contact battery, and being advantageous for improving the photoelectric conversion efficiency of the back contact battery.

[0064] Regarding the interval region, as shown in FIGS. 2 to 7, the surface of the interval region 16 may be flat or textured. Here, as shown in FIGS. 2 to 7, when the surface of the interval region 16 is flat, the surface of the interval region 16 is relatively flat. Based on this, when the back contact battery further includes the surface passivation layer 17, compared with the texture, the thickness of the portion of the surface passivation layer 17 formed on the interval region 16 with a flat surface is larger, enhancing the passivation effect of the surface passivation layer 17 on the interval region 16, and reducing the carrier recombination rate on the surface of the interval region 16, which is advantageous for improving the photoelectric conversion efficiency of the back contact battery. Specifically, the surface roughness of the interval region 16 may be determined according to the requirements for the passivation effect of the surface passivation layer 17 on the interval region 16 in the actual application scenario and the actual manufacturing process, and is not specifically limited here.

[0065] Exemplarily, the roughness within a range per 10,000 square micrometers (a range of 100 micrometers × 100 micrometers) on the surface of the spacing region may be 30 μm or less. For example, the roughness within a range per 10,000 square micrometers on the surface of the spacing region may be 5 μm, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 30 μm, etc. The beneficial effect in this case is similar to the beneficial effect when the surface of the spacing region is flat, and the description thereof is omitted here.

[0066] Here, when the surface of the second region or the spacing region is a texture, the size of the texture structure on the surface may be determined according to the depth of the recess of the texture into the silicon substrate, and is not specifically limited here. As can be understood, within a certain range, the smaller the depth of the recess of the texture into the silicon substrate, the smaller the size of the texture structure on the surface. Further, it should be noted that when the surface of the second region or the spacing region is a texture, the depth of the recess of the surface of the second region or the spacing region into the silicon substrate is equal to the vertical distance from the middle part of the texture structure in the second region or the spacing region to the surface of the first region.

[0067] Regarding the form of the side wall of the spacing region, as shown in FIG. 2, the side wall of the spacing region 16 may be provided perpendicular to the horizontal plane. Alternatively, as shown in FIG. 13, in the side wall of the spacing region 16, at least a part of the surface is provided obliquely with respect to the horizontal plane such that at least a part of the cross-sectional area of the spacing region 16 gradually increases in the direction from the light-receiving surface to the non-light-receiving surface. In this case, the cross-sectional area of the light-receiving surface side of the spacing region 16 is smaller than the cross-sectional area of its non-light-receiving surface side, which is advantageous for increasing the distance between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 having a conductivity type opposite to its own. The leakage risk on the non-light-receiving surface side of the back-contact battery is reduced, and high electrical reliability of the back-contact battery is ensured. Also, the portion provided obliquely with respect to the horizontal plane in the side wall of the spacing region 16 is also advantageous for reflection of light rays. More light rays are advantageously incident into the silicon substrate 11 from the non-light-receiving surface side of the back-contact battery under the reflection action of the portion provided obliquely with respect to the horizontal plane in the side wall of the spacing region 16, and further advantageous for improving the photoelectric conversion efficiency of the back-contact battery.

[0068] Here, in the above case, the angle formed between the portion provided obliquely with respect to the horizontal plane in the side wall of the spacing region and the horizontal plane may be determined according to the actual manufacturing process and the reflection requirements for the side wall, and is not specifically limited here.

[0069] Exemplarily, the angle formed between the portion provided obliquely with respect to the horizontal plane in the side wall of the spacing region and the horizontal plane may be 52° or more and 58° or less. For example, the angle formed between the portion provided obliquely with respect to the horizontal plane in the side wall of the spacing region and the horizontal plane may be 52°, 53°, 54°, 55°, 56°, 57° or 58°, etc. In this case, when the angle is within the above range, more light rays are ensured to enter the silicon substrate and be utilized by the silicon substrate under the large reflection action of the portion provided obliquely with respect to the horizontal plane in the side wall of the spacing region, and the light utilization rate of the back-contact battery can be further increased.

[0070] Regarding the above-mentioned first doped semiconductor layer and second doped semiconductor layer, from the perspective of materials, the material of the first doped semiconductor layer or the second doped semiconductor layer may be a semiconductor material such as silicon, germanium silicon, germanium, or gallium arsenide. From the perspective of the arrangement form of substances, the crystal phase of the first doped semiconductor layer or the second doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc. From the perspective of the conduction type, as long as it is ensured that the first doped semiconductor layer and the second doped semiconductor layer have opposite conduction types, the conduction type of the first doped semiconductor layer or the second doped semiconductor layer may be opposite to or the same as the conduction type of the silicon substrate. Regarding the thickness of the first doped semiconductor layer and the second doped semiconductor layer, it may be set according to actual needs and is not specifically limited here. For example, the thickness of the first doped semiconductor layer or the second doped semiconductor layer may be 100 nm or more and 500 nm or less.

[0071] In the actual application process, the first doped semiconductor layer may be directly formed on the first region of the silicon substrate. Or, as shown in FIG. 2, the back contact battery further includes a first passivation layer 18 located between the first region 14 of the silicon substrate 11 and the first doped semiconductor layer 12. In this case, the first passivation layer 18 and the first doped semiconductor layer 12 form a selective contact structure to achieve chemical passivation for the first region 14 on the non-light-receiving surface of the silicon substrate 11, and also achieve selective collection for carriers of the corresponding conduction type, which can reduce the carrier recombination rate on the non-light-receiving surface side and is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

[0072] Specifically, the material of the first passivation layer may be determined according to the material of the first doped semiconductor layer and the type of the selective contact structure composed of the first passivation layer and the first doped semiconductor layer in the actual application scenario, and is not specifically limited here.

[0073] For example, when the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a tunnel passivation contact structure, the first doped semiconductor layer is a doped polycrystalline silicon layer, and the first passivation layer is a tunnel passivation layer. The material of the tunnel passivation layer may include materials such as silicon oxide, aluminum oxide, or titanium oxide.

[0074] Furthermore, for example, when the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a heterojunction contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer is an undoped amorphous silicon layer and / or an undoped microcrystalline silicon layer.

[0075] Regarding the thickness of the first passivation layer, it may be set according to actual needs and is not specifically limited here. For example, the thickness of the first passivation layer may be 0.5 nm or more and 3 nm or less.

[0076] Regarding the above-mentioned second doped semiconductor layer, the second doped semiconductor layer may be directly formed on the second region of the silicon substrate. Or, as shown in FIG. 2, the back contact battery further includes a second passivation layer 19 located between the second region 15 of the silicon substrate 11 and the second doped semiconductor layer 13. In this case, the second passivation layer 19 and the second doped semiconductor layer 13 constitute a selective contact structure to achieve chemical passivation for the second region 15 on the non-light-receiving surface of the silicon substrate 11, and also achieve selective collection for carriers of the corresponding conductivity type, which can reduce the carrier recombination rate on the non-light-receiving surface side and is beneficial to improving the photoelectric conversion efficiency of the back contact battery.

[0077] Specifically, for the material and thickness of the above-mentioned second passivation layer, reference may be made to the material and thickness of the first passivation layer described above, and the description is omitted here.

[0078] From the perspective of morphology, in the embodiments of the present invention, the morphology of the side surface close to the spacing region between the first doped semiconductor layer and the second doped semiconductor layer is not specifically limited, and it is only necessary that it can be applied to the back contact battery provided by the embodiments of the present invention. Exemplarily, the side surface close to the spacing region of the first doped semiconductor layer and / or the second doped semiconductor layer may be in a shape such as a straight line, a broken line, an arc, or a substantially wavy shape. Here, the morphology of the side surface close to the spacing region of the first doped semiconductor layer may be the same as or different from the morphology of the side surface close to the spacing region of the second doped semiconductor layer.

[0079] Here, in the actual application process, as shown in FIGS. 3 to 7, the side surfaces close to the spacing region 16 of the above-mentioned first doped semiconductor layer 12 and second doped semiconductor layer 13 may all be substantially wavy. Also, the corresponding variation width of the side surface close to the spacing region 16 of the second doped semiconductor layer 13 may be larger than the corresponding variation width of the side surface close to the spacing region 16 of the first doped semiconductor layer 12, and the corresponding variation frequency of the side surface close to the spacing region 16 of the second doped semiconductor layer 13 may be smaller than the corresponding variation frequency of the side surface close to the spacing region 16 of the first doped semiconductor layer 12. In this case, when the corresponding variation width of the side surface close to the spacing region 16 of the second doped semiconductor layer 13 is larger than the corresponding variation width of the side surface close to the spacing region 16 of the first doped semiconductor layer 12, the roughness of the local region of the side surface close to the spacing region 16 of the second doped semiconductor layer 13 is smaller than the roughness of the local region of the side surface close to the spacing region 16 of the first doped semiconductor layer 12, reducing the number of defects in the portion close to the spacing region 16 of the formed second doped semiconductor layer 13, and further being advantageous for reducing the carrier recombination rate in the portion close to the spacing region 16 of the second doped semiconductor layer 13, and the operating performance of the back contact battery is further improved.

[0080] Here, the corresponding fluctuation width of the side surface close to the spacing region between the first doped semiconductor layer and the second doped semiconductor layer refers to the undulation width of the protruding portion of the side surface with respect to the lowest point of the recessed portion of the side surface. Also, the corresponding fluctuation frequency of the side surface close to the spacing region between the first doped semiconductor layer and the second doped semiconductor layer refers to the frequency at which different protruding portions of the side surface appear. Specifically, when both side surfaces close to the spacing region between the first doped semiconductor layer and the second doped semiconductor layer are substantially wavy, the fluctuation width and the fluctuation frequency of the side surfaces close to the spacing region between the first doped semiconductor layer and the second doped semiconductor layer may be determined according to the actual manufacturing process, and are not specifically limited herein.

[0081] As a possible implementation form, as shown in FIG. 2, the back contact battery may further include a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacing region 16. In this case, the surface passivation layer 17 can passivate the non-light-receiving surface side of the back contact battery and reduce the carrier recombination rate on the non-light-receiving surface side. Also, since the spacing region 16 with the largest recess depth into the silicon substrate 11 has a corresponding recess depth of less than 3000 nm, it is advantageous for reducing the undulation degree of each region on the non-light-receiving surface side of the back contact battery, increasing the formation thickness of the surface passivation layer 17 on the non-light-receiving surface side, and enhancing the passivation effect of the surface passivation layer 17 on the non-light-receiving surface side.

[0082] Specifically, the material of the surface passivation layer may be any of insulating materials having a passivation effect such as silicon oxide, aluminum oxide, or silicon nitride. The thickness of the surface passivation layer may be determined according to the actual application scenario and is not specifically limited herein.

[0083] On the second side surface, the embodiments of the present invention provide a manufacturing method for a back contact battery. Hereinafter, the manufacturing process will be described based on the cross-sectional views of the operations shown in FIGS. 2 to 21. Specifically, the manufacturing method of the back contact battery includes the following steps.

[0084] First, prepare a silicon substrate. On the non-light-receiving surface of the silicon substrate, there are a first region and a second region that are alternately distributed at intervals, and an interval region located between the first region and the second region adjacent to itself.

[0085] Specifically, for the ranges of the first region, the second region, and the interval region on the non-light-receiving surface side, reference may be made to the foregoing text, and the description is omitted here.

[0086] Next, as shown in FIGS. 12 to 14, form a first doped semiconductor layer 12 in the first region 14, and recess the surfaces of both the interval region 16 and the second region 15 into the silicon substrate 11 with respect to the surface of the first region 14.

[0087] In the actual manufacturing process, as shown in FIG. 11, after preparing the silicon substrate 11, a first doped semiconductor layer 12 provided in all layers and a first mask layer 20 located at a portion corresponding to the first region 14 of the first doped semiconductor layer 12 can be formed on the non-light-receiving surface of the silicon substrate 11. Next, as shown in FIGS. 12 and 13, under the masking action of the first mask layer 20, the portions located in the interval region 16 and the second region 15 of the first doped semiconductor layer 12 are selectively removed, and the surfaces of both the interval region 16 and the second region 15 are recessed into the silicon substrate 11 with respect to the surface of the first region 14.

[0088] Here, for the material and thickness of the first doped semiconductor layer, and the depth of recess of the surfaces of the interval region and the second region into the silicon substrate after the operation, reference may be made to the foregoing text. Regarding the first mask layer, the material of the first mask layer may be any material having a masking action, and is not specifically limited here. Next, according to the specific materials of the first doped semiconductor layer and the first mask layer, the formation process and the specific formation process of the first doped semiconductor layer and the first mask layer can be determined.

[0089] Exemplarily, when the material of the first doped semiconductor layer includes silicon, the step of forming the first doped semiconductor layer provided over the entire layer and the first mask layer located at a portion corresponding to the first region of the first doped semiconductor layer on the non-light-receiving surface of the silicon substrate may include the following steps. As shown in FIG. 8, a first intrinsic semiconductor layer 22 provided over the entire layer is formed on the non-light-receiving surface of the silicon substrate 11. Next, as shown in FIG. 9, the first intrinsic semiconductor layer 22 is doped to form the first intrinsic semiconductor layer 22 as the first doped semiconductor layer 12, and a first doped silicate glass layer 23 provided over the entire layer is formed on the first doped semiconductor layer 12. Next, as shown in FIG. 10, by a laser etching process, the interval region 16 of the first doped silicate glass layer 23 and the portion with respect to the second region 15 are heat-treated, and the portion of the first doped silicate glass layer 23 that has not undergone the heat treatment is formed as the first mask layer 20. Next, as shown in FIG. 11, the portion of the first doped silicate glass layer 23 that has undergone the heat treatment is removed.

[0090] Specifically, the fact that the material of the first doped semiconductor layer contains silicon may mean that the material of the first doped semiconductor layer contains only silicon, or it may mean that the material of the first doped semiconductor layer contains not only silicon but also other semiconductor materials such as germanium silicon. Next, in the actual manufacturing process, the first intrinsic semiconductor layer provided on the entire layer on the non-light-receiving surface side can be formed by a process such as chemical vapor deposition. Next, the first intrinsic semiconductor layer can be doped by a process such as diffusion. After the above doping process, not only can the first doped semiconductor layer be obtained, but also the first doped silicate glass layer provided on the entire layer can be formed on the first doped semiconductor layer. Thereafter, a part of the first doped silicate glass layer is heat-treated by a laser etching process. In this case, as shown in FIG. 10, the laser-treated portion in the first doped silicate glass layer has low density and is easily removed. On the other hand, the non-laser-treated portion in the first doped silicate glass layer has high density and is difficult to remove. As a result, after the heat treatment, different portions of the first doped silicate glass layer have different etching selectivity ratios, and the first mask layer 20 for patterning the first doped semiconductor layer 12 is obtained. It is not necessary to additionally form other mask materials and other mask deposition processes to obtain the first mask layer 20, which is advantageous for reducing the manufacturing cost of the back contact battery and simplifying the manufacturing flow of the back contact battery. The specific conditions of the above laser etching process may be set according to the actual application scenario and are not specifically limited here.

[0091] For example, the laser used in the laser etching process may be a nanosecond laser, a picosecond laser, a femtosecond laser, or the like. The laser etching process may be 10 W or more and 100 W or less, and the diameter of the laser spot may be 50 μm or more and 300 μm or less.

[0092] Of course, when the material of the first doped semiconductor layer contains silicon or does not contain silicon, the first doped semiconductor layer provided over the entire layer on the non-light-receiving surface side may be formed by processes such as chemical vapor deposition and doping. Thereafter, a first mask layer having a masking effect and made of another material such as silicon nitride can be formed by processes such as chemical vapor deposition and etching.

[0093] Also, after forming the first mask layer, by a wet chemical process, under the masking effect of the first mask layer, the portions located in the spaced regions and the second region of the first doped semiconductor layer are selectively removed, and both the surfaces of the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region, thereby preventing damage to the silicon substrate by a high-temperature laser, which is advantageous for improving the yield of the back contact battery. Specifically, the process conditions for selectively etching the first doped semiconductor layer can be determined based on the etching process used, the material of the first doped semiconductor layer, and the depth of the recess into the silicon substrate of the surfaces of the spaced regions and the second region after the operation, and are not specifically limited herein.

[0094] Exemplarily, in the wet chemical process, under the masking action of the first mask layer, the spaced regions of the first doped semiconductor layer and the portions located in the second region are selectively removed, and both the surfaces of the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region. In this case, the process temperature of the wet chemical process may be 60°C or higher and 80°C or lower, and the process time of the wet chemical process may be 40 s or longer and 200 s or shorter. Further, the wet chemical etching solution used in the wet chemical process may be an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (for example, NaOH or KOH, etc.) in the alkaline wet chemical etching solution may be 2% or higher and 20% or lower. For example, the process temperature of the wet chemical process may be 60°C, 70°C, 75°C, 78°C, or 80°C, etc. The process time of the wet chemical process may be 40 s, 60 s, 80 s, 100 s, 150 s, or 200 s, etc. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution may be 2%, 3%, 6%, 9%, 12%, 15%, or 20%, etc. In this case, both the process temperature and the process time of the wet chemical process affect the depth at which both the surfaces of the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region. Based on this, when the process temperature of the wet chemical process is within the above range, it is possible to prevent the depth at which both the surfaces of the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region from becoming small due to the low process temperature. Also, it is possible to prevent the depth at which both the surfaces of the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region from becoming large due to the high process temperature. After this operation, the depth at which both the surfaces of the spaced regions and the second region are recessed into the silicon substrate with respect to the surface of the first region is equal to the depth at which the surface of the second region in the formed back contact battery is recessed into the silicon substrate with respect to the surface of the first region.Here, for the beneficial effect of preventing the depth of the surface of the second region from becoming larger or smaller with respect to the surface of the first region and recessing into the silicon substrate, reference may be made to the foregoing text. Next, the beneficial effect of the process time and the volume ratio of the alkaline component being within the above ranges is similar to the beneficial effect of the process temperature being 60°C or higher and 80°C or lower, and the description thereof is omitted here.

[0095] In addition, by adding a polishing additive to the wet chemical etching solution, the flatness of the interval region and the surface of the second region after the operation can be improved, and the passivation effect of the surface passivation layer on the interval region and the second doped semiconductor layer can be further enhanced. Specifically, the components of the polishing additive and the ratio of the polishing additive in the wet chemical etching solution may be determined according to the actual application scenario, and are not specifically limited here. For example, the polishing additive may include sodium benzoate, an antifoaming agent, a surfactant, etc. The volume ratio of the polishing additive in the wet chemical etching solution may be 0.5% or more and 5% or less.

[0096] It should be noted that when the manufactured back contact battery further includes a first passivation layer located between the first region and the first doped semiconductor layer, after preparing the silicon substrate and before forming the first doped semiconductor layer in the first region, the manufacturing method of the back contact battery further includes a step of forming the first passivation layer in the first region first by a deposition and etching process.

[0097] Alternatively, as shown in FIG. 8, after preparing the silicon substrate, the first passivation layer 18 provided over the entire layer on the non-light-receiving surface side may be formed by a process such as chemical vapor deposition. Thereafter, as shown in FIGS. 11 to 13, the first mask layer 20 is formed, and after selectively etching the first doped semiconductor layer 12 under the masking action of the first mask layer 20, the first passivation layer 18 is selectively etched. In this case, it is not necessary to additionally form a corresponding mask layer for forming the first passivation layer 18, and the manufacturing process of the back contact battery is simplified.

[0098] Next, after both the surface of the spacing region and the second region are recessed into the silicon substrate with respect to the surface of the first region, as shown in FIG. 20, a second doped semiconductor layer 13 is formed in the second region 15, and the surface of the spacing region 16 is recessed into the silicon substrate 11 with respect to the surface of the second region 15, and the depth at which the surface of the spacing region 16 is recessed into the silicon substrate 11 with respect to the surface of the first region 14 is less than 3000 nm.

[0099] In the actual manufacturing process, as shown in FIG. 18, after both the surface of the spacing region 16 and the second region 15 are recessed into the silicon substrate 11 with respect to the surface of the first region 14, a second doped semiconductor layer 13 is deposited on the first doped semiconductor layer 12, the spacing region 16, and the second region 15, and a second mask layer 21 can be formed on the portion of the second doped semiconductor layer 13 corresponding to the second region 15. Next, as shown in FIG. 19, under the masking action of the second mask layer 21, the portions of the second doped semiconductor layer 13 corresponding to the first region 14 and the spacing region 16 are selectively removed, and the surface of the spacing region 16 is recessed into the silicon substrate 11 with respect to the surface of the second region 15.

[0100] Specifically, for the material and thickness of the second doped semiconductor layer, and the depth of the recess of the surface of the spacing region into the silicon substrate after the operation, reference may be made to the foregoing, and the description is omitted here. For the second mask layer, its material may be any material having a masking action. In the actual manufacturing process, according to the materials of the second doped semiconductor layer and the second mask layer, the formation process and the specific formation process of the second doped semiconductor layer and the second mask layer may be determined.

[0101] Exemplarily, when the material of the second doped semiconductor layer contains silicon, the steps of depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region, and forming the second mask layer on the portion corresponding to the second region of the second doped semiconductor layer may include the following steps. As shown in FIG. 15, deposit a second intrinsic semiconductor layer 24 on the first doped semiconductor layer 12, the spacer region 16, and the second region 15. Next, as shown in FIG. 16, dope the second intrinsic semiconductor layer 24 to form the second intrinsic semiconductor layer 24 as the second doped semiconductor layer 13, and form a second doped silicate glass layer 25 provided over the entire layer on the second doped semiconductor layer 13. Next, as shown in FIG. 17, heat-treat the portions corresponding to the first region 14 and the spacer region 16 of the second doped silicate glass layer 25 by a laser etching process to form the portion corresponding to the second region 15 of the second doped silicate glass layer 25 as the second mask layer 21. Thereafter, as shown in FIG. 18, remove the heat-treated portion of the second doped silicate glass layer 25.

[0102] Specifically, the fact that the material of the second doped semiconductor layer contains silicon may mean that the material of the second doped semiconductor layer contains only silicon, or it may mean that the material of the second doped semiconductor layer not only contains silicon but also contains other semiconductor materials such as germanium silicon. Next, in the actual manufacturing process, the second intrinsic semiconductor layer provided over the entire layer on the non-light-receiving surface side can be formed by a process such as chemical vapor deposition. Next, the second intrinsic semiconductor layer can be doped by a process such as diffusion. After the above doping process, not only can the second doped semiconductor layer be obtained, but also a second doped silicate glass layer provided over the entire layer can be formed on the second doped semiconductor layer. Thereafter, by a laser etching process, the portions corresponding to the first region and the spaced regions of the second doped silicate glass layer can be heat-treated. In this case, the laser-treated portions in the second doped silicate glass layer have low density and are easily removed. On the other hand, since the portions corresponding to the second region of the second doped silicate glass layer are not laser-treated, they have high density and are difficult to remove. As a result, after the heat treatment, different portions of the second doped silicate glass layer have different etching selectivity ratios, and a second mask layer for patterning the second doped semiconductor layer is obtained, which is advantageous for reducing the manufacturing cost of the back contact battery and simplifying the manufacturing flow of the back contact battery without the need to additionally form other mask materials and form other mask deposition processes. For the specific conditions of the above laser etching process, reference may be made to the foregoing text and will not be specifically limited here.

[0103] Naturally, when the material of the second doped semiconductor layer contains silicon or the material of the second doped semiconductor layer does not contain silicon, the second doped semiconductor layer provided over the entire layer on the non-light-receiving surface side may be formed by processes such as chemical vapor deposition and doping. Thereafter, a second mask layer having a masking action made of other materials such as silicon nitride can be formed by processes such as chemical vapor deposition and etching.

[0104] After forming the second mask layer, by means of a process such as wet chemistry, under the masking action of the second mask layer, the spaced regions of the second doped semiconductor layer and the portions located in the first doped semiconductor layer are selectively removed, and the surface of the spaced region is recessed into the silicon substrate with respect to the surface of the second region, thereby preventing damage to the silicon substrate by a high-temperature laser, which is advantageous for improving the yield of the back contact battery. Specifically, the process conditions for selectively etching the second doped semiconductor layer may be determined based on the etching process used, the material of the second doped semiconductor layer, the depth of the recess of the surface of the spaced region into the silicon substrate, etc., and are not specifically limited herein.

[0105] Exemplarily, in the case of selectively removing, by a wet chemical process, a portion corresponding to the spaced region of the second doped semiconductor layer under the masking action of the second mask layer and recessing the surface of the spaced region into the silicon substrate with respect to the surface of the second region, the process temperature of the wet chemical process may be 60°C or higher and 80°C or lower, and the process time of the wet chemical process may be 50 s or longer and 300 s or shorter. Further, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (such as NaOH or KOH, etc.) in the alkaline wet chemical etching solution may be 2% or higher and 20% or lower. For example, the process temperature of the wet chemical process may be 60°C, 70°C, 75°C, 78°C, 80°C, or the like. The process time of the wet chemical process may be 50 s, 55 s, 60 s, 100 s, 150 s, 200 s, 300 s, or the like. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution may be 2%, 3%, 6%, 9%, 12%, 15%, 20%, or the like. In this case, both the process temperature and the process time of the wet chemical process affect the depth at which the surface of the spaced region is recessed into the silicon substrate with respect to the surface of the second region by the wet chemical process. Based on this, when the process temperature of the wet chemical process is within the above range, it is possible to prevent the depth at which the surface of the spaced region is recessed into the silicon substrate with respect to the surface of the second region from becoming small due to the small process temperature. Further, it is also possible to prevent the depth at which the surface of the spaced region is recessed into the silicon substrate with respect to the surface of the second region from becoming large due to the large process temperature. Here, the beneficial effects of preventing the depth at which the surface of the spaced region is recessed into the silicon substrate with respect to the surface of the second region from becoming small or large may be referred to the foregoing text. Next, the beneficial effects of the process time and the volume ratio of the alkaline component being within the above range are similar to the beneficial effects of the process temperature being 60°C or higher and 80°C or lower, and the description thereof is omitted here.

[0106] In addition, by adding a polishing additive to the wet chemical etching solution, the flatness of the surface of the interval region after the operation can be enhanced, and the passivation effect of the surface passivation layer on the interval region can be further enhanced. Specifically, the components of the polishing additive and the ratio of the polishing additive in the wet chemical etching solution may be determined according to the actual application scenario, and are not specifically limited herein. For example, the polishing additive may include sodium benzoate, an antifoaming agent, a surfactant, etc. The volume ratio of the polishing additive in the wet chemical etching solution may be 0.5% or more and 5% or less.

[0107] It should be noted that when the manufactured back contact battery further includes a second passivation layer located between the second region and the second doped semiconductor layer, after both the surfaces of the interval region and the second region are recessed into the silicon substrate with respect to the surface of the first region, and before forming the second doped semiconductor layer on the portion of the second region, the manufacturing method of the back contact battery further includes a step of forming the second passivation layer on the second region first by a deposition and etching process.

[0108] Alternatively, as shown in FIG. 15, after both the surfaces of the interval region and the second region are recessed into the silicon substrate with respect to the surface of the first region, and before forming the second doped semiconductor layer on the portion of the second region, the second passivation layer 19 may be deposited on the first doped semiconductor layer, the second region, and the interval region by a process such as chemical vapor deposition. Then, as shown in FIGS. 18 and 19, after forming the second mask layer 21 and selectively etching the second doped semiconductor layer under the masking action of the second mask layer 21, the second passivation layer 19 is selectively etched. In this case, there is no need to additionally form a corresponding mask layer for forming the second passivation layer, and the manufacturing process of the back contact battery is simplified.

[0109] In addition, when the manufactured back contact battery further includes a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacer region, after the surface of the spacer region is recessed into the silicon substrate with respect to the surface of the second region, as shown in FIG. 21, a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacer region 16 can be formed by a process such as chemical vapor deposition. For the material and thickness of the surface passivation layer 17, reference may be made to the foregoing text.

[0110] For the beneficial effects of the second side surface and its various embodiments in the examples of the present invention, reference may be made to the analysis of the beneficial effects in the first side surface and its various embodiments, and the description is omitted here.

[0111] In addition, the examples of the present invention further provide one comparative example and one example for explaining the manufacturing process and operating performance of the back contact battery provided by the examples of the present invention. Here, Table 1 shows the test results of the back contact batteries corresponding to Example 1 and Comparative Example 1. Example 1

[0112] Step 1: Perform alkaline polishing treatment on the single crystal silicon wafer using an alkaline solution with a concentration of 15% to form a smooth and clean silicon surface.

[0113] Step 2: Sequentially deposit a tunnel oxide layer and an intrinsic polycrystalline silicon layer on the surface of the single crystal silicon wafer. Here, the thickness of the tunnel oxide layer is 1.8 nm, and the thickness of the intrinsic polycrystalline silicon layer is 350 nm.

[0114] Step 3: Perform boron doping treatment on the deposited intrinsic polycrystalline silicon layer to form the intrinsic polycrystalline silicon layer into a P-type doped polycrystalline silicon layer, and form a borosilicate glass layer on the P-type doped polycrystalline silicon layer. Here, the boron doping concentration is 8×10 19 / cm 3 is.

[0115] Step 4: Heat-treat the borosilicate glass layer by a laser etching process to form a mask layer with a specific pattern. Here, the laser may be a picosecond laser, the processing power may be 40 W, and the spot diameter is 200 μm.

[0116] Step 5: Selectively remove a part of the P-type doped polycrystalline silicon layer under the masking action of the mask layer. Then, perform a surface etching treatment on the single-crystalline silicon wafer to form a concave groove structure. Here, the main components of the etching solution used include alkali and polishing additives. The concentration of the alkali in the etching solution is 5%, the etching temperature is 82 °C, the process time is 300 s, the volume ratio of the polishing additive is 2%, and the main components of the polishing additive include sodium benzoate, an antifoaming agent, and a surfactant.

[0117] Step 6: Form a tunnel oxide layer and an N-type doped polycrystalline silicon layer that are sequentially laminated on the bottom of the concave groove structure, and recess the portion located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer of the single-crystalline silicon wafer into the silicon substrate with respect to the bottom surface of the concave groove structure. Here, the thickness of the N-type doped polycrystalline silicon layer is 150 nm or more and 180 nm or less. The thickness of the tunnel oxide layer is 0.5 nm or more and 3 nm or less. The recess depth of the portion located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer of the single-crystalline silicon wafer into the silicon substrate is less than 3000 nm.

[0118] Step 7: Form a surface passivation layer that covers the single-crystalline silicon wafer, the P-type doped polycrystalline silicon layer, and the N-type doped polycrystalline silicon layer. Comparative Example 1

[0119] The manufacturing method corresponding to Comparative Example 1 is the same as the manufacturing flow of Example 1 except for Step 6. Here, in the manufacturing method provided by Comparative Example 1, after forming a tunnel oxide layer and an N-type doped polycrystalline silicon layer which are sequentially laminated and provided on the groove bottom of the concave groove structure, the depth of the recess in the silicon substrate at the portion located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer of the single crystal silicon wafer is made larger than 5 μm, and the surface of the portion located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer of the single crystal silicon wafer is textured.

[0120]

Table 1

[0121] From the data shown in Table 1, in the back contact battery formed by the manufacturing method provided by Example 1, since the depth of the recess in the silicon substrate in the spacing region is small, the migration distance of carriers can be shortened. Also, when the back contact battery further includes a surface passivation layer, the passivation effect of the surface passivation layer on the spacing region can also be enhanced. As a result, the operating efficiency, open circuit voltage, short circuit current, and fill factor are higher than those of the back contact battery obtained by the corresponding manufacturing method of Comparative Example 1. That is, the back contact battery provided by the embodiments of the present invention has higher operating performance.

[0122] In the above description, technical details such as the configuration and etching of each layer are not described in detail. However, those skilled in the art should understand that layers, regions, etc. of a desired shape can be formed by various technical means. Also, in order to form the same structure, those skilled in the art can design a method that is not exactly the same as the method described above. Also, although each embodiment has been described above, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0123] The above has described the embodiments of the present disclosure. However, these embodiments are merely for illustration and not for limiting the scope of the present disclosure. The scope of the present disclosure is limited by the appended patent claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various replacements and modifications, and all of these replacements and modifications are considered to be within the scope of the present disclosure.

Explanation of Reference Numerals

[0124] 11 Silicon substrate 12 First doped semiconductor layer 13 Second doped semiconductor layer 14 First region 15 Second region 16 Spacing region 17 Surface passivation layer 18 First passivation layer 19 Second passivation layer 20 First mask layer 21 Second mask layer 22 First intrinsic semiconductor layer 23 First doped silicate glass layer 24 Second intrinsic semiconductor layer 25 Second doped silicate glass layer

Claims

1. A silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer which are alternately distributed at intervals on the non-light-receiving surface side of the silicon substrate, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. On the non-light-receiving surface of the silicon substrate, the region corresponding to the first doped semiconductor layer is a first region, the region corresponding to the second doped semiconductor layer is a second region, and the region located between the first region and the second region adjacent to itself is an interval region. The surface of the second region is recessed into the silicon substrate with respect to the surface of the first region. The surface of the interval region is recessed into the silicon substrate with respect to the surface of the second region, and the depth at which the surface of the interval region is recessed into the silicon substrate with respect to the surface of the first region is less than 3000 nm. The side surfaces of the first doped semiconductor layer and the second doped semiconductor layer close to the interval region are both substantially wavy, wherein the corresponding fluctuation width of the side surface of the second doped semiconductor layer close to the interval region is larger than the corresponding fluctuation width of the side surface of the first doped semiconductor layer close to the interval region, and / or the corresponding fluctuation frequency of the side surface of the second doped semiconductor layer close to the interval region is smaller than the corresponding fluctuation frequency of the side surface of the first doped semiconductor layer close to the interval region. The corresponding fluctuation width of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer close to the interval region refers to the undulation width of the protruding part of the side surface with respect to the lowest point of the recessed part of the side surface. The corresponding fluctuation frequency of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer close to the interval region refers to the frequency at which different protruding parts of the side surface appear. A back contact battery is characterized by this.

2. The roughness within a range of per 10,000 square micrometers on the surface of the interval region is 30 μm or less, and / or In the arrangement direction of the first region and the second region, the length of the interval region is 20 μm or more and 110 μm or less. The back contact battery according to claim 1 is characterized by this.

3. The surface of the second region is flat, and / or The recess depth of the surface of the second region into the silicon substrate is 100 nm or more and 1000 nm or less, and / or The height difference between the surface of the second region and the surface of the spacing region is 300 nm or more and less than 2000 nm, the back-contact battery according to claim 1.

4. On the sidewall of the spacing region, at least a part of the surface is provided obliquely with respect to the horizontal plane so that at least a part of the cross-sectional area of the spacing region gradually increases in the direction from the light-receiving surface to the non-light-receiving surface, the back-contact battery according to claim 1.

5. Further comprising a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacing region, and / or, Further comprising a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer, and / or, Further comprising a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer, the back-contact battery according to any one of claims 1 to 4.

6. When the back-contact battery includes the first passivation layer and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer, and / or, When the back-contact battery includes the second passivation layer and the second passivation layer is a tunnel passivation layer, the second doped semiconductor layer is a doped polycrystalline silicon layer, the back-contact battery according to claim 5.

7. A step of preparing a silicon substrate, wherein on the non-light-receiving surface of the silicon substrate, there are a first region and a second region distributed at intervals alternately, and a spacing region located between the first region and the second region adjacent to itself, A step of forming a first doped semiconductor layer in the first region and recessing both the surfaces of the spacing region and the second region into the silicon substrate with respect to the surface of the first region, A step of forming a second doped semiconductor layer in the second region, recessing the surface of the spacing region into the silicon substrate with respect to the surface of the second region, and making the depth at which the surface of the spacing region is recessed into the silicon substrate with respect to the surface of the first region less than 3000 nm, both side surfaces of the first doped semiconductor layer and the second doped semiconductor layer close to the spacing region being substantially wavy, The corresponding variation width of the side surface of the second doped semiconductor layer close to the interval region is larger than the corresponding variation width of the side surface of the first doped semiconductor layer close to the interval region, and / or the corresponding variation frequency of the side surface of the second doped semiconductor layer close to the interval region is smaller than the corresponding variation frequency of the side surface of the first doped semiconductor layer close to the interval region. The corresponding variation width of the side surface of the first doped semiconductor layer and the second doped semiconductor layer close to the interval region refers to the undulation width of the protruding portion of the side surface with respect to the lowest point of the concave portion of the side surface. The corresponding variation frequency of the side surface of the first doped semiconductor layer and the second doped semiconductor layer close to the interval region refers to the frequency at which different protruding portions of the side surface appear. A method for manufacturing a back contact battery is characterized by this.

8. After the step of preparing the silicon substrate and before the step of forming the second doped semiconductor layer in the second region, the method for manufacturing the back contact battery includes forming a first doped semiconductor layer provided in the entire layer and a first mask layer located in a portion corresponding to the first region of the first doped semiconductor layer on the non-light-receiving surface of the silicon substrate; selectively removing portions of the first doped semiconductor layer located in the interval region and the second region under the masking action of the first mask layer, and recessing both the surfaces of the interval region and the second region into the silicon substrate with respect to the surface of the first region. The method for manufacturing a back contact battery according to claim 7 is characterized by including this.

9. The material of the first doped semiconductor layer includes silicon. The step of forming a first doped semiconductor layer provided in the entire layer and a first mask layer located in a portion corresponding to the first region of the first doped semiconductor layer on the non-light-receiving surface of the silicon substrate includes forming a first intrinsic semiconductor layer provided in the entire layer on the non-light-receiving surface of the silicon substrate; doping the first intrinsic semiconductor layer to form the first intrinsic semiconductor layer as the first doped semiconductor layer, and forming a first doped silicate glass layer provided in the entire layer on the first doped semiconductor layer; heat-treating portions of the first doped silicate glass layer corresponding to the interval region and the second region by a laser etching process, and forming the non-heat-treated portion of the first doped silicate glass layer as the first mask layer. The method for manufacturing a back contact battery according to claim 8, comprising the step of removing a heat-treated portion of the first doped silicate glass layer.

10. By a wet chemical process, under the masking action of the first mask layer, selectively removing portions of the first doped semiconductor layer located in the spaced region and the second region, and recessing both the surfaces of the spaced region and the second region into the silicon substrate with respect to the surface of the first region. The process temperature of the wet chemical process is 60°C or higher and 80°C or lower, and / or the process time of the wet chemical process is 40 s or longer and 200 s or shorter, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower, and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower. The method for manufacturing a back contact battery according to claim 8.

11. After the step of recessing both the surfaces of the spaced region and the second region into the silicon substrate with respect to the surface of the first region, the method for manufacturing the back contact battery comprises Depositing a second doped semiconductor layer on the first doped semiconductor layer, the spaced region, and the second region, and forming a second mask layer on a portion corresponding to the second region of the second doped semiconductor layer. Under the masking action of the second mask layer, selectively removing portions of the second doped semiconductor layer corresponding to the first region and the spaced region, and recessing the surface of the spaced region into the silicon substrate with respect to the surface of the second region. The method for manufacturing a back contact battery according to claim 7.

12. The material of the second doped semiconductor layer contains silicon. The step of depositing a second doped semiconductor layer on the first doped semiconductor layer, the spaced region, and the second region, and forming a second mask layer on a portion corresponding to the second region of the second doped semiconductor layer comprises Depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spaced region, and the second region. Doping the second intrinsic semiconductor layer to form the second doped semiconductor layer, and forming a second doped silicate glass layer provided over the entire layer on the second doped semiconductor layer; Thermally treating, by a laser etching process, portions of the second doped silicate glass layer corresponding to the first region and the spaced-apart region to form a portion corresponding to the second region of the second doped silicate glass layer as the second mask layer; Removing the thermally treated portion of the second doped silicate glass layer; The method for manufacturing a back contact battery according to claim 11, characterized by including the steps.

13. By a wet chemical process, under the masking action of the second mask layer, selectively removing portions of the second doped semiconductor layer corresponding to the first region and the spaced-apart region, and recessing the surface of the spaced-apart region into the silicon substrate with respect to the surface of the second region; The process temperature of the wet chemical process is 60°C or higher and 80°C or lower, and / or the process time of the wet chemical process is 50 s or longer and 300 s or shorter, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower, and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower. The method for manufacturing a back contact battery according to claim 11, characterized by this.

14. After the step of preparing the silicon substrate and before the step of forming the first doped semiconductor layer in the first region, the method for manufacturing the back contact battery further includes a step of forming a first passivation layer in the first region, and / or After the step of recessing both the surfaces of the spaced-apart region and the second region into the silicon substrate with respect to the surface of the first region, and before the step of forming the second doped semiconductor layer in a portion of the second region, the method for manufacturing the back contact battery further includes a step of forming a second passivation layer in the second region, and / or After the step of recessing the surface of the spacer region into the silicon substrate with respect to the surface of the second region, the method of manufacturing the back contact battery further includes a step of forming a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacer region, characterized in that, the method of manufacturing the back contact battery according to any one of claims 7 to 13.

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