Method for manufacturing a solar cell

Abstract

To provide a solar cell and a manufacturing method thereof, which can reduce the manufacturing process steps of the cell and reduce manufacturing costs.SOLUTION: A manufacturing method of a solar cell includes removing a second intrinsic amorphous silicon layer and a second tunneling oxide layer located in a second region of a second surface of a substrate, doping a first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer located in a first region with a first element to obtain first and second doped layers, doping the first intrinsic amorphous silicon layer located in the second region with a second element to obtain a third doped layer, and forming an isolation structure in an isolation region to isolate a first tunneling oxide layer located in the first region from the first tunneling oxide layer located in the second region and to isolate both the first doped layer and the second doped layer located in the first region from the third doped layer located in the second region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and particularly to solar cells and their manufacturing methods, photovoltaic modules, and photovoltaic systems.

Background Art

[0002] A solar cell, also called a photovoltaic cell, is a semiconductor device that directly converts solar light energy into electrical energy. It is an environmentally friendly product that does not cause environmental pollution. Since solar energy is a renewable resource, solar cells are new batteries with broad development potential.

[0003] Since the electrodes of an interdigitated back contact (IBC) cell are located on the back surface of the cell, the shielding of the light-receiving surface of the cell can be reduced, and the conversion efficiency of the cell can be improved. It has gradually become the main research and development direction of high-efficiency cells that have been industrialized. The passivation contact structure of the tunneling oxide layer and the doped polysilicon layer in a TOPCon (Tunnel Oxide Passivated Contact) cell can effectively reduce the recombination rate of the contact between the silicon wafer surface and the metal. The TBC cell, which combines the TOPCon cell and the IBC cell technologies, has high efficiency and has become a research hot spot.

[0004] In related technologies, in the manufacturing process of a TBC cell, when manufacturing a passivation contact structure in the P region and the N region on the backlight surface of a silicon substrate respectively, there are many necessary process steps, the manufacturing cost of the cell is high, the mass production cost of the cell is high, which is disadvantageous for the mass production of the cell.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Based on this, the present application provides a solar cell, a method for manufacturing the same, a photovoltaic module, and a photovoltaic system, which can reduce the manufacturing process steps of the battery, reduce the manufacturing cost of the battery, and are further advantageous for mass production of the battery, and can reduce the mass production cost of the battery.

Means for Solving the Problems

[0006] An embodiment of the first aspect of the present application is as follows: Providing a substrate having a first surface and a second surface provided opposite to each other, and dividing the second surface into a first region, a second region, and a separation region located between the two, S1; Sequentially laminating a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer, and a second intrinsic amorphous silicon layer along a direction away from the substrate on the second surface of the substrate to form S2; Removing the second intrinsic amorphous silicon layer and the second tunneling oxide layer located in the second region, S3; Doping a first element into the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer located in the first region to obtain a first doping layer and a second doping layer respectively, and doping a second element into the first intrinsic amorphous silicon layer located in the second region to obtain a third doping layer, S4; Forming a separation structure in the separation region to separate the first tunneling oxide layer located in the first region from the first tunneling oxide layer located in the second region, and separating both the first doping layer and the second doping layer located in the first region from the third doping layer located in the second region, S5. Providing a method for manufacturing a solar cell.

[0007] In some of these embodiments, before step S3, the method further includes: S3a is to sequentially stack a doping source layer and a first protective layer on the side of the second intrinsic amorphous silicon layer away from the substrate, and the doping source layer includes S3a used to provide the first element necessary for doping.

[0008] In some of these embodiments, step S3 specifically includes: S310a of removing, by laser, a part of the second intrinsic amorphous silicon layer that is separated from the first protective layer, the doping source layer, and the second tunneling oxide layer located in the second region; S320a of wet-removing the remaining second intrinsic amorphous silicon layer located in the second region and adjacent to the second tunneling oxide layer, and the second tunneling oxide layer located in the second region.

[0009] In some of these embodiments, step S320a specifically includes: wet-removing the remaining second intrinsic amorphous silicon layer located in the second region and adjacent to the second tunneling oxide layer; forming a mask layer on the side of the first protective layer located in the first region away from the substrate; wet-removing the second tunneling oxide layer located in the second region; removing the mask layer.

[0010] In some of these embodiments, step S4 specifically includes: at a preset temperature, doping the first element from the doping source layer into the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, and obtaining the first doping layer and the second doping layer respectively over a preset time; doping the second element into the first intrinsic amorphous silicon layer located in the second region to obtain the third doping layer.

[0011] In some of these embodiments, after the step S4, the method further comprises removing the doping source layer and the first protective layer.

[0012] In some of these embodiments, before the step S3, the method further comprises including S3b of forming a second protective layer on the side of the second intrinsic amorphous silicon layer away from the substrate.

[0013] In some of these embodiments, the step S3 specifically comprises S310b of removing, by laser, a part of the second intrinsic amorphous silicon layer that is separated from the second protective layer and the second tunneling oxide layer located in the second region; and S320b of wet-removing the remaining second intrinsic amorphous silicon layer located in the second region and adjacent to the second tunneling oxide layer, and the second tunneling oxide layer located in the second region.

[0014] In some of these embodiments, the step S320b specifically comprises wet-removing the remaining second intrinsic amorphous silicon layer located in the second region and adjacent to the second tunneling oxide layer; forming a mask layer on the side of the second protective layer located in the first region away from the substrate; wet-removing the second tunneling oxide layer located in the second region; and removing the mask layer.

[0015] In some of these embodiments, the step S4 specifically comprises doping the second element into the first intrinsic amorphous silicon layer located in the second region to obtain the third doping layer; forming a third protective layer on a side of the third doping layer away from the substrate; removing the second protective layer located in the first region, and doping the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer located in the first region with the first element to obtain the first doping layer and the second doping layer.

[0016] In some embodiments thereof, after the step S4, the method further includes: removing the third protective layer.

[0017] In some embodiments thereof, after the step S5, the method further includes: forming a first passivation reflection reduction layer on a side of the second doping layer and the third doping layer away from the substrate, covering at least the surface of the side of the second doping layer and the third doping layer away from the substrate, and forming a second passivation reflection reduction layer on the first surface of the substrate.

[0018] In some embodiments thereof, the method further includes: forming a first electrode connected to the second doping layer on a side of the first passivation reflection reduction layer located in the first region away from the substrate; forming a second electrode connected to the third doping layer on a side of the first passivation reflection reduction layer located in the second region away from the substrate.

[0019] In some embodiments thereof, the thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are both 1 to 2 nm, and the thicknesses of the first doping layer, the second doping layer, and the third doping layer are all 50 to 500 nm.

[0020] Examples of the second aspect of the present application are: A substrate having a first surface and a second surface provided opposite to each other, wherein the second surface includes a first region, a second region, and a separation region located between the two. A first tunneling oxide layer, a first doping layer, a second tunneling oxide layer, and a second doping layer, which are located in the first region and sequentially stacked along a direction away from the substrate. A first tunneling oxide layer and a third doping layer, which are located in the second region and sequentially stacked along a direction away from the substrate. A separation structure, which is located in the separation region and is used to separate the first tunneling oxide layer located in the first region from the first tunneling oxide layer located in the second region. The separation structure is further used to separate both the first doping layer and the second doping layer located in the first region from the third doping layer located in the second region. A solar cell is provided.

[0021] In some of these embodiments, the separation structure includes a separation groove, the separation groove penetrates the first tunneling oxide layer, the first doping layer, the second tunneling oxide layer, the second doping layer, and the third doping layer along a first direction, and the first direction is perpendicular to the plane in which the substrate is located.

[0022] An embodiment of the third aspect of the present application provides a photovoltaic module including the solar cell according to any one of the second aspect.

[0023] An embodiment of the fourth aspect of the present application provides a photovoltaic system including the photovoltaic module according to the third aspect.

Advantages of the Invention

[0024] The manufacturing method of the above solar cell sequentially laminates a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer, and a second intrinsic amorphous silicon layer on a substrate, removes the second intrinsic amorphous silicon layer and the second tunneling oxide layer located in the second region, and then dopes the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer located in the first region with a first element to obtain a first doping layer and a second doping layer. The first intrinsic amorphous silicon layer located in the second region is doped with a second element to obtain a third doping layer, and a separation structure is formed in the separation region. Thereby, on the second surface of the substrate, passivation contact structures located in the first region and the second region are formed respectively, reducing the process steps required when manufacturing the passivation contact structures in the first region and the second region of the substrate respectively, further reducing the manufacturing process steps of the battery, reducing the manufacturing cost of the battery, being advantageous for mass production of the battery, and being able to reduce the mass production cost of the battery.

[0025] Also, when doping the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer located in the first region with the first element, the first element needs to diffuse into the first intrinsic polysilicon layer through the second tunneling oxide layer. Since the second tunneling oxide layer has a certain barrier effect, excessive first element diffusing into the first intrinsic polysilicon layer can be avoided. Thereby, the doping concentration of the first doping layer can be made smaller than that of the second doping layer, thereby reducing the parasitic absorption of the first doping layer to light and improving the efficiency of the battery. When manufacturing the electrode later, the ohmic contact effect between the second doping layer and the electrode can be improved, and the efficiency and reliability of the battery can be improved. Also, the second tunneling oxide layer has a certain reflection effect on light, thereby improving the light utilization rate and further improving the efficiency of the battery.

Brief Description of the Drawings

[0026]

Figure 1

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Embodiments for Carrying Out the Invention

[0027] To make the above objects, features, and advantages of the present application clearer and easier to understand, the following will describe in detail the specific embodiments of the present application with reference to the drawings. To facilitate a thorough understanding of the present application, many specific details are described in the following description. However, the present application can be implemented in many other ways different from the methods described in this specification, and those skilled in the art can make similar improvements without departing from the content of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0028] In the description of the present application, when terms such as "center", "vertical", "horizontal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial direction", "radial direction", "circumferential direction" appear, the orientation or positional relationship indicated by these terms is based on the orientation or positional relationship shown in the drawings, and is for the convenience and simplification of the description of the present application, and does not indicate or imply that the shown device or element must have a specific orientation and be constructed and operated in a specific orientation. Therefore, it should be understood that it does not limit the present application.

[0029] In addition, when terms such as "first" and "second" appear, these terms are merely for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the shown technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, "a plurality" means at least two, for example, two, three, etc., unless otherwise specified.

[0030] In the present application, when terms such as "attachment", "connection", "connection", "fixation" appear, these terms should be understood in a broad sense unless otherwise explicitly specified and limited. For example, unless specifically limited, it may be a fixed connection, a removable connection, or an integral one, and may be a mechanical connection or an electrical connection, and may be a direct connection or an indirect connection through an intervening medium, or may be an internal communication between two elements or an interaction relationship between two elements. The specific meaning of the above terms in the present application can be understood by those skilled in the art according to the specific situation.

[0031] In this application, unless otherwise explicitly specified or limited, when there are similar descriptions such as the first feature being "above" or "below" the second feature, the meaning may be that the first feature and the second feature are in direct contact, or the first feature and the second feature are in indirect contact through an intervening medium. Further, the first feature being "above", "upper" and "upper surface" of the second feature indicates that the first feature is directly above or obliquely above the second feature, or simply that the first feature has a higher horizontal height than the second feature. The first feature being "below", "lower" and "lower surface" of the second feature indicates that the first feature is directly below or obliquely below the second feature, or simply that the first feature has a lower horizontal height than the second feature.

[0032] Note that when an element is referred to as being "fixed to" or "provided on" another element, it may be directly on the other element, or there may be intervening elements. When an element is considered to be "connected to" another element, it may be directly connected to the other element, or intervening elements may exist simultaneously. If they exist, the terms "vertical", "horizontal", "above", "below", "left", "right", and similar expressions used in this application are for illustrative purposes only and do not indicate the only embodiment.

[0033] FIG. 1 shows a method for manufacturing a solar cell provided in some embodiments of this application. Referring to FIG. 1, an embodiment of the first aspect of this application provides a method for manufacturing a solar cell including the following.

[0034] S1. Provide a substrate 110 having a first surface 111 and a second surface 112 provided opposite to each other, and divide the second surface 112 into a first region 112a, a second region 112b, and a separation region 112c located between the two.

[0035] Specifically, the substrate 110 may be a P-type silicon substrate 110 or an N-type silicon substrate 110. The first surface 111 may be a light-receiving surface, and the second surface 112 may be a backlight surface.

[0036] The first surface 111 and the second surface 112 of the substrate 110 can be polished with a chemical solution prepared with deionized water, KOH, and a polishing additive, which can ensure the flatness of the area in contact with the tunneling oxide layers (the first tunneling oxide layer 120 and the second tunneling oxide layer 140) on the substrate 110 in subsequent procedures, and is advantageous for improving the flatness and uniformity of the subsequently manufactured first tunneling oxide layer 120, second tunneling oxide layer 140, first intrinsic polysilicon layer, and second intrinsic crystalline silicon layer, thereby improving the passivation effect of the passivation contact structure formed on the substrate 110.

[0037] S2. The first tunneling oxide layer 120, the first intrinsic amorphous silicon layer 130, the second tunneling oxide layer 140, and the second intrinsic amorphous silicon layer 150 are sequentially laminated and formed on the second surface 112 of the substrate 110 along the direction away from the substrate 110.

[0038] Specifically, the first tunneling oxide layer 120, the first intrinsic amorphous silicon layer 130, the second tunneling oxide layer 140, and the second intrinsic amorphous silicon layer 150 may be sequentially laminated and formed on the second surface 112 of the substrate 110 by low-pressure chemical vapor deposition method. Of course, they may also be formed by other deposition methods, which are not particularly limited in this application.

[0039] S3. The second intrinsic amorphous silicon layer 150 and the second tunneling oxide layer 140 located in the second region 112b are removed.

[0040] Specifically, the second intrinsic amorphous silicon layer 150 and the second tunneling oxide layer 140 located in the second region 112b may be removed by one or more methods among methods such as laser, chemical etching, photolithography, etc. Preferably, the second intrinsic amorphous silicon layer 150 and the second tunneling oxide layer 140 located in the second region 112b are removed by combining two methods of laser and chemical etching, and damage to the first intrinsic amorphous silicon layer 130 during the removal process is reduced, thereby the third doping layer obtained by doping 130b is beneficial to improving the performance and improving the efficiency of the battery.

[0041] S4. Dope the first element into the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150 located in the first region 112a to obtain the first doping layer 130a and the second doping layer 150a respectively, and dope the second element into the first intrinsic amorphous silicon layer 130 located in the second region 112b to obtain the third doping layer 130b

[0042] The first element may be a boron element, and the second element may be a phosphorus element. By doping the boron element into the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150 located in the first region 112a, the doping types of the first doping layer 130a and the second doping layer obtained by doping 150a can be made to match. The diffusion coefficient of the boron element in the intrinsic amorphous silicon layer (the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer) is much smaller than the diffusion coefficient of the phosphorus element, and the second tunneling oxide layer has a certain barrier effect. Therefore, the first doping layer 130a with a low doping concentration and the second doping layer with a high doping concentration 150a can be obtained, thereby reducing the parasitic absorption of the first doping layer 130a to light and improving the efficiency of the battery. When manufacturing the electrode later, the second doping layer​150a It can improve the ohmic contact effect between the electrode and the electrode, and further improve the efficiency and reliability of the battery.

[0043] S5. By forming the separation structure 190 in the separation region 112c, the first tunneling oxide layer 120 located in the first region 112a and the first tunneling oxide layer 120 located in the second region 112b are separated, and the first doping layer 130a and the second doping layer 150a both located in the first region 112a and the third doping layer 130b located in the second region 112b are separated, thereby avoiding the occurrence of recombination and improving the efficiency of the battery.

[0044] The manufacturing method of the solar cell in the above aspect is to sequentially stack the first tunneling oxide layer 120, the first undoped amorphous silicon layer 130, the second tunneling oxide layer 140, and the second undoped amorphous silicon layer 150 on the substrate 110, and after removing the second undoped amorphous silicon layer 150 and the second tunneling oxide layer 140 located in the second region 112b, the first undoped amorphous silicon layer 130 and the second undoped amorphous silicon layer 150 located in the first region 112a are doped with a first element to obtain the first doping layer 130a and the second doping layer 150a and the first undoped amorphous silicon layer 130 located in the second region 112b is doped with a second element to obtain the third doping layer 130b and by forming the separation structure 190 in the separation region 112c, on the second surface 112 of the substrate 110, passivation contact structures located in the first region 112a and the second region 112b are formed respectively, reducing the process steps required when manufacturing the passivation contact structures in the first region 112a and the second region 112b of the substrate 110 respectively, further reducing the manufacturing process steps of the battery, reducing the manufacturing cost of the battery, being advantageous for mass production of the battery, and being able to reduce the mass production cost of the battery.

[0045] Also, when doping the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150 located in the first region 112a with a first element, the first element needs to diffuse into the first intrinsic polysilicon layer through the second tunneling oxide layer 140. Since the second tunneling oxide layer 140 has a certain barrier effect, excessive first element can be prevented from diffusing into the first intrinsic polysilicon layer. As a result, the doping concentration of the first doping layer 130a can be made lower than that of the second doping layer 150a , thereby reducing the parasitic absorption of the first doping layer 130a to light and improving the efficiency of the battery. When manufacturing the electrodes later, the ohmic contact effect between the second doping layer 150a and the electrodes can be improved, and the efficiency and reliability of the battery can be improved. In addition, the second tunneling oxide layer 140 has a certain reflection effect on light, thereby improving the light utilization rate and further improving the efficiency of the battery.

[0046] As shown in relation to FIGS. 2 and 3, in some of these embodiments, before step S3, the method further includes S3a of sequentially laminating a doping source layer 160 and a first protective layer 170 on the side of the second intrinsic amorphous silicon layer 150 away from the substrate 110, where the doping source layer 160 is used to provide the first element required for doping.

[0047] The doping source layer 160 may be a boron source layer. For example, a borosilicate glass layer is formed on the side of the second intrinsic amorphous silicon layer 150 away from the substrate 110 by Atmospheric Pressure Chemical Vapor Deposition (APCVD), and, for example, a pure boron layer is formed on the side of the second intrinsic amorphous silicon layer 150 away from the substrate 110 by a boron diffusion tube. The first protective layer 170 may be at least one of a silicon oxide layer, silicon oxynitride, and silicon nitride. The first protective layer 170 may be fabricated by Atmospheric Pressure Chemical Vapor Deposition or may be fabricated by plasma enhanced chemical vapor deposition (PECVD). The thickness of the first protective layer 170 is 50 nm to 100 nm.

[0048] In this embodiment, the doping source layer 160 and the first protective layer 170 are sequentially laminated and formed on the side of the second intrinsic amorphous silicon layer 150 away from the substrate 110, so that later, it becomes easy to dope the second intrinsic amorphous silicon layer 150 and the first intrinsic amorphous silicon layer 130 with the first element by the doping source layer 160, and the first doping layer 130a and the second doping layer of the same doping type 150a are obtained, and the first protective layer 170 can later serve as protection and a barrier.

[0049] As shown in relation to FIGS. 2 and 3, in some of these embodiments, step S3 specifically includes S310a of removing, by laser, a part of the second intrinsic amorphous silicon layer 150 that is separated from the first protective layer 170, the doping source layer 160, and the second tunneling oxide layer 140 located in the second region 112b; S320a of wet-removing the remaining second intrinsic amorphous silicon layer 150 located in the second region 112b and adjacent to the second tunneling oxide layer 140, and the second tunneling oxide layer 140 located in the second region 112b.

[0050] In this embodiment, a part of the second intrinsic amorphous silicon layer 150 located in the second region 112b and separated from the first protective layer 170, the doping source layer 160, and the second tunneling oxide layer 140 is removed by a laser, and the remaining second intrinsic amorphous silicon layer 150 located in the second region 112b and adjacent to the second tunneling oxide layer 140, and the second tunneling oxide layer 140 located in the second region 112b are removed wet. In the laser removal process, the second intrinsic amorphous silicon layer 150 can absorb laser energy as a sacrificial layer, and the second tunneling oxide layer 140 can block the conduction of laser energy as a barrier layer, reducing the damage to the first intrinsic amorphous silicon layer 130 by the laser. By removing the remaining second intrinsic amorphous silicon layer 150 and the second tunneling oxide layer 140 wet, damage to the first intrinsic amorphous silicon layer 130 can be avoided, thereby ensuring the performance of the third doping layer obtained by doping and improving the efficiency of the battery. 130b of the battery and improving the efficiency of the battery.

[0051] As shown in FIG. 4, in some of these embodiments, step S320a specifically includes the following.

[0052] S321a, wet-removing the remaining second intrinsic amorphous silicon layer 150 located in the second region 112b and adjacent to the second tunneling oxide layer 140.

[0053] Specifically, the remaining second intrinsic amorphous silicon layer 150 located in the second region 112b and adjacent to the second tunneling oxide layer 140 can be removed by a polishing additive, and the polishing additive does not damage the first protective layer 170 and the second tunneling oxide layer 140, thereby avoiding damage to the first intrinsic amorphous silicon layer 130 and the doping source layer 160 by the polishing additive.

[0054] S322a. Form a mask layer on the side of the first protective layer 170 located in the first region 112a away from the substrate 110.

[0055] Specifically, the mask layer may be a photoresist layer, and the mask layer can play a protective role for the first protective layer 170 when removing the second tunneling oxide layer 140 located in the second region 112b, ensuring that the first protective layer 170 is not damaged, which is advantageous for subsequent diffusion.

[0056] S323a. Wet-remove the second tunneling oxide layer 140 located in the second region 112b.

[0057] Specifically, the second tunneling oxide layer 140 may be removed by an acid solution, for example, the second tunneling oxide layer 140 may be removed by a hydrogen fluoride solution.

[0058] S324a. Remove the mask layer.

[0059] Note that the thickness of the first protective layer 170 may be 50 nm to 100 nm, the thickness of the second tunneling oxide layer 140 is 1 to 2 nm, the thickness of the first protective layer 170 is greater than the thickness of the second tunneling oxide layer 140, and under the conditions allowed by the etching process, there is no need to form a mask layer on the side of the first protective layer 170 located in the first region 112a away from the substrate. By controlling the etching process parameters, when removing the second tunneling oxide layer 140 located in the second region 112b, the damage to the first protective layer 170 is reduced as much as possible.

[0060] In some of these embodiments, step S4 specifically includes At a preset temperature, And over a preset time, The doping source layer 160 dopes the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150 with a first element , the 1 doping layer 130a and the second doping layer150a including obtaining each of them.

[0061] Specifically, the preset temperature may be 850°C to 1000°C, and the preset time may be 5 min to 25 min, which can be determined according to the thicknesses of the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150. For example, when the thickness of the first intrinsic amorphous silicon layer 130 is 50 nm and the thickness of the second intrinsic amorphous silicon layer 150 is 100 nm, the preset temperature may be 890°C to 920°C, and the preset time may be 8 min to 10 min.

[0062] Doping the first intrinsic amorphous silicon layer 130 located in the second region with a second element to obtain a third doping layer 130b thereof.

[0063] In this embodiment, the entire doping diffusion process can be performed in the same diffusion tube, eliminating the need to replace the tube, improving the diffusion efficiency, and simplifying the diffusion process. Due to the barrier effect of the first protective layer 170, contamination of the diffusion tube by the first element in the doping source layer 160 is avoided. When doping the first intrinsic amorphous silicon layer 130 located in the second region 112b with the second element by the diffusion tube, the first protective layer 170 can prevent the second element from entering the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150 located in the first region 112a, thereby ensuring that the doping types of both the obtained first doping layer 130a and the second doping layer 150a are the same, and ensuring that the doping types of both the first doping layer 130a and the second doping layer 150a are different from the doping type of the third doping layer 130b thereof, and guaranteeing the passivation effect of the passivation contact structure formed on the substrate 110.

[0064] In some of these embodiments, after the step S4, the method further includes removing the doping source layer 160 and the first protective layer 170.

[0065] Specifically, the doping source layer 160 and the first protective layer 170 may be removed wet, or the doping source layer 160 and the first protective layer 170 may be removed by an acid solution (such as HF acid).

[0066] As shown in connection with FIGS. 5 and 6, in some of these embodiments, before step S3, the method further includes S3b of forming a second protective layer 180 on the side of the second intrinsic amorphous silicon layer 150 away from the substrate 110.

[0067] Specifically, the second protective layer 180 may be at least one of a silicon oxide layer, a silicon oxynitride, and a silicon nitride, and the second protective layer 180 may be fabricated by a deposition method such as an atmospheric pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method. By forming the second protective layer 180 on the side of the second intrinsic amorphous silicon layer 150 away from the substrate 110, it can play a role of protection and barrier in subsequent manufacturing processes. The thickness of the second protective layer 180 is 50 nm to 100 nm.

[0068] As shown in connection with FIGS. 5 and 6, in some of these embodiments, the step S3 specifically includes S310b of removing a part of the second intrinsic amorphous silicon layer 150 that is separated from the second protective layer 180 and the second tunneling oxide layer 140 located in the second region 112b by laser; S320b of removing the remaining second intrinsic amorphous silicon layer 150 located in the second region 112b and adjacent to the second tunneling oxide layer 140, and the second tunneling oxide layer 140 located in the second region 112b wet.

[0069] In this embodiment, a part of the second intrinsic amorphous silicon layer 150 located in the second region 112b and separated from the second protective layer 180 and the second tunneling oxide layer 140 is removed by laser, and the remaining second intrinsic amorphous silicon layer 150 and the second tunneling oxide layer 140 located in the second region 112b are removed wet. In the laser removal process, the second intrinsic amorphous silicon layer 150 can absorb laser energy as a sacrificial layer, and the second tunneling oxide layer 140 can block the conduction of laser energy as a barrier layer, reducing the damage to the first intrinsic amorphous silicon layer 130 caused by the laser. By removing the remaining second intrinsic amorphous silicon layer 150 and the second tunneling oxide layer 140 wet, damage to the first intrinsic amorphous silicon layer 130 can be avoided, thereby ensuring the performance of the third doping layer 130b obtained by doping and improving the efficiency of the battery.

[0070] As shown in FIG. 7, in some of these embodiments, the step S320b specifically includes the following.

[0071] S321b, wet-remove the remaining second intrinsic amorphous silicon layer 150 located in the second region 112b and adjacent to the second tunneling oxide layer 140.

[0072] Specifically, the remaining second intrinsic amorphous silicon layer 150 located in the second region 112b and adjacent to the second tunneling oxide layer 140 can be removed by a polishing additive, and the polishing additive does not damage the second protective layer 180 and the second tunneling oxide layer 140, thereby avoiding damage to the first intrinsic amorphous silicon layer 130 caused by the polishing additive.

[0073] S322b, form a mask layer on the side of the second protective layer 180 located in the first region 112a and separated from the substrate 110.

[0074] Specifically, the mask layer may be a photoresist layer, and the mask layer can play a protective role for the second protective layer 180 when removing the second tunneling oxide layer 140 located in the second region 112b, ensuring that the second protective layer 180 is not damaged, which is advantageous for subsequent diffusion.

[0075] S323b. Wet-remove the second tunneling oxide layer 140 located in the second region 112b.

[0076] Specifically, the second tunneling oxide layer 140 may be removed by an acid solution, for example, the second tunneling oxide layer 140 may be removed by a hydrogen fluoride solution.

[0077] S324b. Remove the mask layer.

[0078] Note that the thickness of the second protective layer 180 may be 50 nm to 100 nm, the thickness of the second tunneling oxide layer 140 is 1 to 2 nm, the thickness of the second protective layer 180 is greater than the thickness of the second tunneling oxide layer 140, and under the conditions allowed by the etching process, it is not necessary to form a mask layer on the side of the second protective layer 180 located in the first region away from the substrate. By controlling the etching process parameters, when removing the second tunneling oxide layer 140 located in the second region, the damage to the second protective layer 180 is reduced as much as possible.

[0079] In some of these embodiments, step S4 specifically includes: Dope a second element into the first intrinsic amorphous silicon layer 130 located in the second region 112b to obtain a third doped layer 130b and form a third protective layer on the side of the third doped layer 130b away from the substrate 110. Remove the second protective layer 180 located in the first region 112a, and dope the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150 located in the first region 112a with a first element to obtain a first doped layer 130a and a second doped layer 150a including obtaining the above.

[0080] In this embodiment, in the process of doping the first intrinsic amorphous silicon layer 130 located in the second region 112b with a second element, the second protective layer 180 plays a role as a barrier, and the second element can be prevented from diffusing into the first intrinsic amorphous silicon layer 130 and the second intrinsic amorphous silicon layer 150 located in the first region 112a, and a third doped layer 130b Form a third protective layer on the side of the substrate 110 away from the third doped layer. The third protective layer plays a role as a barrier, and the first element can be prevented from diffusing into the third doped layer 130b so that the doping types of both the obtained first doped layer 130a and the second doped layer 150a are the same, and it is ensured that the doping types of both the first doped layer 130a and the second doped layer 150a are different from the doping type of the third doped layer 130b Thereby, the passivation effect of the passivation contact structure formed on the substrate 110 can be ensured.

[0081] Furthermore, the third protective layer may be at least one of a silicon oxide layer, a silicon oxynitride, and a silicon nitride, and the second protective layer 180 may be fabricated by a deposition method such as a chemical vapor deposition method at atmospheric pressure or a plasma enhanced chemical vapor deposition method.

[0082] In some of these embodiments, after the step S4, the method further includes removing the third protective layer.

[0083] Specifically, the third protective layer can be removed wet.

[0084] As shown in FIG. 8, in some of these embodiments, after step S5, the method further a second doping layer 150a and a third doping layer 130b on the side away from the substrate 110 of the second doping layer 150a and the third doping layer 130b forming a first passivation reflection reduction layer 200a that at least covers the surface on the side away from the substrate 110 of the second doping layer and the third doping layer, and forming a second passivation reflection reduction layer 200b on the first surface of the substrate 110.

[0085] Furthermore, both the first passivation reflection reduction layer 200a and the second passivation reflection reduction layer 200b may each be at least one of aluminum oxide, silicon nitride, silicon oxide, gallium oxide, aluminum nitride, and silicon oxynitride. The first passivation reflection reduction layer 200a and the second passivation reflection reduction layer 200b may be formed synchronously.

[0086] In some of these embodiments, the method further forming a first electrode 210 connected to the second doping layer on the side away from the substrate 110 of the first passivation reflection reduction layer 200a located in the first region, 150a and forming a second electrode 220 connected to the third doping layer on the side away from the substrate 110 of the first passivation reflection reduction layer 200a located in the second region. 130b

[0087] In some of these embodiments, the thicknesses of both the first tunneling oxide layer 120 and the second tunneling oxide layer 140 are each 1 - 2 nm, and the thicknesses of the first doping layer 130a, the second doping layer 150a and the third doping layer 130b are each 50 - 500 nm.

[0088] ​As shown in FIG. 8, an embodiment of the second aspect of the present application is a substrate 110 having a first surface 111 and a second surface 112 provided opposite to each other, wherein the second surface 112 includes a first region 112a, a second region 112b, and a separation region 112c located between the two, a first tunneling oxide layer 120, a first doping layer 130a, a second tunneling oxide layer 140, and a second doping layer, which are sequentially stacked along a direction away from the substrate 110 and are located within the first region 112a, 150a and a first tunneling oxide layer 120 and a third doping layer, which are sequentially stacked along a direction away from the substrate 110 and are located within the second region 112b, 130b and a separation structure 190, which is located in the separation region 112c and is used to separate the first tunneling oxide layer 120 located in the first region 112a from the first tunneling oxide layer 120 located in the second region 112b. The separation structure further separates the first doping layer 130a and the second doping layer 150a both located in the first region 112a from the third doping layer 130b located in the second region 112b. The separation structure 190 is included. A solar cell is provided.

[0089] The solar cell in the embodiment of the present application can be manufactured by the manufacturing method in the first aspect, which can reduce the manufacturing cost of the battery, is advantageous for mass production of the battery, reduces the mass production cost of the battery, and can also make the doping concentration of the first doping layer 130a smaller than the doping concentration of the second doping layer 150a Thereby reducing the parasitic absorption of the first doping layer 130a to light and improving the efficiency of the battery. The second doping layer 150aIt can improve the ohmic contact effect with the electrode, improve the efficiency and reliability of the battery. Also, the second tunneling oxide layer 140 can reduce recombination, and at the same time, the second tunneling oxide layer 140 has a certain reflection effect on light, thereby improving the light utilization efficiency and further improving the efficiency of the battery.

[0090] In some of these embodiments, the isolation structure 190 includes isolation grooves, and the isolation grooves penetrate the first tunneling oxide layer 120, the first doping layer 130a, the second tunneling oxide layer 140, the second doping layer 150a and the third doping layer 130b along the first direction X, and the first direction X is perpendicular to the plane where the substrate 110 is located. In this way, it separates the first tunneling oxide layer 120 located in the first region 112a from the first tunneling oxide layer 120 located in the second region 112b, and also separates both the first doping layer 130a and the second doping layer 150a located in the first region 112a from the third doping layer 130b located in the second region 112b, thereby avoiding the occurrence of recombination and improving the efficiency of the battery.

[0091] An embodiment of the third aspect of the present application includes the solar cell described in any one of the second aspects, and further provides a photovoltaic module that improves the efficiency of the photovoltaic module.

[0092] An embodiment of the fourth aspect of the present application includes the photovoltaic module described in the third aspect, and further provides a photovoltaic system that improves the efficiency of the photovoltaic module.

[0093] The technical features of the above-described embodiments can be arbitrarily combined. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered that all are within the scope described in this specification.

[0094] The embodiments described above merely represent some embodiments of the present application. Although the description is specific and detailed, it should not be understood as limiting the scope of the claimed patent. It should be noted that those skilled in the art can make some modifications and improvements on the premise of not departing from the concept of the present application, and these belong to the protection scope of the present application. Therefore, the protection scope of the present invention should be based on the content of the appended claims.

Description of Reference Numerals

[0095] 110 Substrate, 111 First surface, 112 Second surface, 112a First region, 112b Second region, 112c Separation region, 120 First tunneling oxide layer, 130 First intrinsic amorphous silicon layer, 130a First doping layer, 150a Second doping layer, 140 Second tunneling oxide layer, 150 Second intrinsic amorphous silicon layer, 130b Third doping layer, 160 Doping source layer, 170 First protective layer, 180 Second protective layer, 190 Separation structure, 200a First passivation reflection reduction layer, 200b Second passivation reflection reduction layer, 210 First electrode, 220 Second electrode, X First direction.

Claims

1. A method for manufacturing a solar cell, comprising: providing a substrate having a first surface and a second surface provided opposite to each other, and dividing the second surface into a first region, a second region, and a separation region located between both of them in S1; forming, in S2, a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer, and a second intrinsic amorphous silicon layer in sequence along a direction away from the substrate on the second surface of the substrate; removing, in S3, the second intrinsic amorphous silicon layer and the second tunneling oxide layer located in the second region; doping a first element into the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer located in the first region to obtain a first doping layer and a second doping layer respectively, and doping a second element into the first intrinsic amorphous silicon layer located in the second region to obtain a third doping layer in S4; forming a separation structure in the separation region to separate the first tunneling oxide layer located in the first region from the first tunneling oxide layer located in the second region, and to separate both the first doping layer and the second doping layer located in the first region from the third doping layer located in the second region in S5. A method for manufacturing a solar cell, characterized by the above.

2. Before S3, further comprising: S3a of sequentially forming a doping source layer and a first protective layer on a side of the second intrinsic amorphous silicon layer away from the substrate, wherein the doping source layer is used to provide the first element necessary for doping. The method for manufacturing a solar cell according to claim 1, characterized by the above.

3. Specifically, S3 includes: S310a of removing, by laser, a part of the second intrinsic amorphous silicon layer that is separated from the first protective layer, the doping source layer, and the second tunneling oxide layer located in the second region; S320a of wet-removing the remaining second intrinsic amorphous silicon layer located in the second region and adjacent to the second tunneling oxide layer, and the second tunneling oxide layer located in the second region. The method for manufacturing a solar cell according to claim 2, characterized by the above.

4. Specifically, S320a includes: S321a for wet-removing the remaining second intrinsic amorphous silicon layer that is located in the second region and adjacent to the second tunneling oxide layer S322a for forming a mask layer on the side of the first protective layer located in the first region and away from the substrate S323a for wet-removing the second tunneling oxide layer located in the second region including S324a for removing the mask layer The method for manufacturing a solar cell according to claim 3, characterized in that

5. Specifically, the S4 doping the first element into the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer by the doping source layer at a preset temperature and for a preset time to obtain the first doping layer and the second doping layer respectively doping the second element into the first intrinsic amorphous silicon layer located in the second region to obtain the third doping layer, the method for manufacturing a solar cell according to claim 3, characterized in that

6. After the S4, further including removing the doping source layer and the first protective layer The method for manufacturing a solar cell according to claim 5, characterized in that

7. Before the S3, further including S3b for forming a second protective layer on the side of the second intrinsic amorphous silicon layer away from the substrate The method for manufacturing a solar cell according to claim 1, characterized in that

8. Specifically, the S3 S310b for removing, by laser, a part of the second intrinsic amorphous silicon layer that is located in the second region and away from the second protective layer and the second tunneling oxide layer including S320b for wet-removing the remaining second intrinsic amorphous silicon layer that is located in the second region and adjacent to the second tunneling oxide layer, and the second tunneling oxide layer located in the second region The method for manufacturing a solar cell according to claim 7, characterized in that

9. Specifically, the S320b S321b for wet-removing the remaining second intrinsic amorphous silicon layer that is located in the second region and adjacent to the second tunneling oxide layer S322b for forming a mask layer on the side of the second protective layer located in the first region and away from the substrate S323b that wet-removes the second tunneling oxide layer located in the second region, S324b that removes the mask layer, and A method for manufacturing a solar cell according to claim 8, characterized in that.

10. Specifically, the S4 includes Doping the second element into the first intrinsic amorphous silicon layer located in the second region to obtain the third doping layer, Forming a third protective layer on the side of the third doping layer away from the substrate, removing the second protective layer located in the first region, and doping the first element into the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer located in the first region to obtain the first doping layer and the second doping layer. A method for manufacturing a solar cell according to claim 8, characterized in that.

11. After the S4, further Removing the third protective layer, A method for manufacturing a solar cell according to claim 10, characterized in that.

12. After the S5, further Forming a first passivation reflection reduction layer that at least covers the surfaces on the sides of the second doping layer and the third doping layer away from the substrate on the sides of the second doping layer and the third doping layer away from the substrate, and forming a second passivation reflection reduction layer on the first surface of the substrate. A method for manufacturing a solar cell according to claim 1, characterized in that.

13. Furthermore, Forming a first electrode connected to the second doping layer on the side of the first passivation reflection reduction layer located in the first region away from the substrate, Forming a second electrode connected to the third doping layer on the side of the first passivation reflection reduction layer located in the second region away from the substrate, A method for manufacturing a solar cell according to claim 12, characterized in that.

14. The thicknesses of the first tunneling oxide layer and the second tunneling oxide layer are both 1 to 2 nm, and the thicknesses of the first doping layer, the second doping layer, and the third doping layer are all 50 to 500 nm. A method for manufacturing a solar cell according to any one of claims 1 to 13, characterized in that.

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