Apparatus and method (Integration of high-density ReRAM by interconnection)

Abstract

To solve the problem in which resistive random-access memory (ReRAM) memory is integrated in a higher level of BEOL interconnect and it is desired to incorporate the ReRAM into a lower BEOL level.SOLUTION: A cross-bar resistive random-access memory (ReRAM) comprises a substrate, and multiple first columns extending parallel to each other on the top surface of the substrate, where each of the first columns includes a ReRAM stack consisting of multiple layers. Multiple second columns extend parallel to each other and extend perpendicular to the multiple first columns, where the multiple second columns are located on top of the multiple first columns, such that the multiple second columns cross over the multiple first columns. A dielectric layer fills the space between the multiple first columns and the multiple second columns, and is in direct contact with a sidewall of each of the multiple layers of the ReRAM stack.SELECTED DRAWING: Figure 12B

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuits, and more particularly to the formation of logic circuits and ReRAM arrays.

Background Art

[0002] Further aspects and / or advantages, or both, will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Resistive random access memory (ReRAM) memories are integrated at a higher level of BEOL interconnects, and it is desired to incorporate ReRAM at a lower BEOL level.

Means for Solving the Problems

[0004] An apparatus in one embodiment of the present application may include a substrate, a plurality of first columns extending parallel to each other on the uppermost surface of the substrate, each of the plurality of first columns including a resistive random access memory (ReRAM) stack composed of a plurality of layers, a plurality of second columns extending parallel to each other and perpendicular to the plurality of first columns, the plurality of second columns being disposed on the uppermost part of the plurality of first columns such that the plurality of second columns intersect the plurality of first columns, and a dielectric layer filling a space between the plurality of first columns and the plurality of second columns, the dielectric layer being in direct contact with sidewalls of each of the plurality of layers of the ReRAM stack.

[0005] The method in one embodiment of the present application includes forming a first liner on a substrate and forming a first metal layer on the first liner; forming a resistive random access memory (ReRAM) stack on the first metal layer, the ReRAM stack being composed of a plurality of layers; etching the first liner, the first metal layer, and the ReRAM stack to form a plurality of first columns extending parallel to each other; forming a dielectric layer to fill the region between the plurality of first columns such that the dielectric layer is in direct contact with the sidewalls of the respective layers of the ReRAM stack; forming a second liner directly on the top surface of the dielectric layer and directly on the top of the ReRAM stack; forming a second metal layer on the top of the second liner; and etching the second liner and the second metal layer to form a plurality of second columns, the plurality of second columns extending parallel to each other, the plurality of second columns extending perpendicular to the plurality of first columns, and the plurality of second columns intersecting the plurality of first columns and being disposed on the top of the plurality of first columns.

[0006] The method in one embodiment of the present application is a step of simultaneously forming a logic circuit and a random access memory (ReRAM) array on a substrate, and the step of forming the ReRAM array includes forming a first liner on the substrate and forming a first metal layer on the first liner; forming a resistive random access memory (ReRAM) stack on the first metal layer, the ReRAM stack being composed of a plurality of layers; etching the first liner, the first metal layer, and the ReRAM stack to form a plurality of first columns extending parallel to each other; forming a dielectric layer to fill the region between the plurality of first columns so that the dielectric layer is in direct contact with the sidewalls of each of the plurality of layers of the ReRAM stack; forming a second liner directly on the uppermost surface of the dielectric layer and directly on the uppermost part of the ReRAM stack; forming a second metal layer on the uppermost part of the second liner; and etching the second liner and the second metal layer to form a plurality of second columns, the plurality of second columns extending parallel to each other, the plurality of second columns extending perpendicular to the plurality of first columns, and the plurality of second columns intersecting the plurality of first columns and being disposed on the uppermost part of the plurality of first columns. The step of forming the ReRAM array may be provided.

Brief Description of the Drawings

[0007] The above and other aspects, features, and advantages of specific exemplary embodiments of the present invention will become more apparent from the following description in conjunction with the accompanying drawings.

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DETAILED DESCRIPTION OF THE INVENTION

[0038] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the present invention as defined by the claims and their equivalents. Various specific details are included to assist in that understanding, but these are to be regarded as merely exemplary. Accordingly, those skilled in the art will recognize that various changes and modifications to the embodiments described herein can be made without departing from the scope and spirit of the present invention. Further, descriptions of well-known functions and structures may be omitted for clarity and conciseness.

[0039] The terms and words used in the following description and claims are not limited to their bibliographical meanings and are merely used to enable a clear and consistent understanding of the present invention. Therefore, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only and is not intended to limit the present invention as defined by the appended claims and their equivalents.

[0040] The singular forms "a," "an," and "the" are to be understood to include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more such surfaces unless the context clearly dictates otherwise.

[0041] Although detailed embodiments of the claimed structures and methods are disclosed herein, it is to be understood that the disclosed embodiments are merely illustrative examples of the claimed structures and methods that may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. Details of well-known features and techniques may be omitted in the description to avoid unnecessarily obscuring the present embodiments.

[0042] References herein to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Further, such phrases are not necessarily referring to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0043] For the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof are related to the disclosed structures and methods as oriented within the drawings. The terms "overlying", "atop", "on top", "positioned on", or "positioned atop" mean that a first element, such as a first structure, is present over a second element, such as a second structure, and intervening elements, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intervening conductive, insulating, or semiconductor layer at the contact surfaces of the two elements.

[0044] To avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and explanation, and in some instances may not be described in detail. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description is focused rather on the distinguishing features or elements of the various embodiments of the present invention.

[0045] Various embodiments of the present invention are described herein with reference to the accompanying drawings. Alternative embodiments can be devised without departing from the scope of the present invention. Note that in the following description and drawings, various connection and positional relationships (e.g., above, below, adjacent, etc.) between elements are shown. These connections or positional relationships, or both, can be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this regard. Thus, the coupling of entities can refer to either direct or indirect coupling, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, herein, a reference to forming layer "A" on layer "B" includes a situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B" unless the relevant properties and functions of layer "A" and layer "B" are substantially changed by the intermediate layer.

[0046] The following definitions and abbreviations are used in the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or other variations thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements, but can include other elements not explicitly listed or other elements inherent to such composition, mixture, process, method, article, or apparatus.

[0047] Furthermore, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Embodiments or designs described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "a plurality" is understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connection" can include both indirect "connections" and direct "connections".

[0048] As used herein, the term "about", which modifies the amounts of the components, constituents, or reactants of the invention used, refers to variations in numerical values that can occur through typical measurement and liquid handling procedures used, for example, to make concentrations or solutions. Further, variations can occur from inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of the components used to make the compositions or execute the methods. The term "about" or "substantially" is intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing. For example, about can include a range of ±8% or 5%, or 2% of a given value. In another aspect, the term "about" means within 5% of the reported numerical value. In another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported numerical value.

[0049] The various processes used to form microchips that are packaged into integrated circuits (ICs) are classified into four general categories: namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical vapor deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Removal / etching is the process of removing material from the wafer. Examples include etching processes (wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP). Semiconductor doping is the modification of electrical properties, for example, generally by diffusion or ion implantation or both, by doping the source and drain of a transistor. Following these doping processes, furnace annealing or rapid thermal annealing (RTA) is performed. Annealing helps to activate the implanted dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and insulate electrical components. By selectively doping various regions of the semiconductor substrate, the conductivity of the substrate can be changed by applying a voltage.

[0050] Next, embodiments of the present invention will be described in detail. Examples thereof are shown in the accompanying drawings, where like reference numerals refer to like elements throughout. Embodiments of the present invention are generally directed to apparatuses and methods for simultaneously forming a logic circuit and a crossbar ReRAM array on the same device.

[0051] Resistive change memory (ReRAM) memories are integrated into higher levels of BEOL interconnects, and it is desired to incorporate ReRAM into lower BEOL levels. ReRAM stacks typically include TiN electrodes for compatibility with the CMOS flow. To incorporate ReRAM into the Cu damascene process, an additional metal layer (e.g., TaN) is required on top of the ReRAM stack for protection during the removal of the TiN hard mask. Further, since the dimensions of the Cu Via are typically larger than those of the ReRAM stack pillars, sidewall protection is required. Conventional spacers can be damaged during the via open process, which may result in weaknesses in the TiN wet etching.

[0052] ReRAM is regarded as a promising technology for neuromorphic computing electronic synapse devices or memristors, and high-density and high-speed non-volatile memory applications. In neuromorphic computing applications, resistive memory devices can be used as connections (synapses) between pre-neurons and post-neurons that represent connection weights in the form of device resistance. Multiple pre-neurons and post-neurons can be connected through a crossbar array of ReRAM, which of course represents a fully connected neural network.

[0053] The crossbar ReRAM structure is composed of ReRAM stacks sandwiched between a lower metal line and an upper metal line. A first metal liner exists between the lower metal line and the underlying layer. A second metal liner exists between the upper metal line and the ReRAM stack. However, there is no metal liner on the sidewalls of the ReRAM stack, nor is there a metal liner on the sidewalls of the lower metal line. The method of forming the crossbar ReRAM structure comprises forming a bottommost metal layer and forming a ReRAM stack on the bottommost metal layer. The ReRAM stack and the bottommost metal layer are patterned into lines, and a dielectric layer is formed to fill the space between the lines. The uppermost metal layer is formed on the topmost of the dielectric layer, and the uppermost metal layer is etched into a second set of lines. The second set of lines extends perpendicular to the lines composed of the lower metal layer and the ReRAM stack.

[0054] FIG. 1A shows a top view of the BEOL interconnects of the logic circuit 100 according to an embodiment of the present invention. The logic circuit 100 is disposed on the same substrate as the crossbar ReRAM array 200, and the logic circuit 100 is connected to the ReRAM array 200. The following descriptions including the letter "A" in the numbers from FIGS. 2 to 12 refer to the cross-section A shown in FIG. 1A. The cross-section A is a vertical slice along three lower bars in the logic circuit 100 and a slice along the length of the upper bar.

[0055] FIG. 1B shows a top view of the ReRAM array according to an embodiment of the present invention. The crossbar ReRAM array 200 is on the same substrate as the logic circuit 100. The following descriptions including the letters "B, C, or D" in the numbers from FIGS. 2 to 12 refer to the cross-sections B, C, or D shown in FIG. 1B. The cross-section B is a slice along one of the upper pillars extending vertically over a plurality of lower pillars. The cross-section C is a slice along one of the lower pillars extending vertically under a plurality of upper pillars. The cross-section D is a slice along the space between two lower pillars where a plurality of upper pillars intersect.

[0056] FIG. 2A shows the cross-section A of the logic circuit 100 during manufacturing according to an embodiment of the present invention.

[0057] The underlying layer device 105 functions as the base of the logic circuit 100. The underlying layer device 105 can be composed of, for example, a substrate, a silicon wafer, a sapphire wafer, a MOS device, a CMOS device, a BTJ device, a diode, a resistor, a capacitor, a metal layer, a dielectric layer, or any type of material for manufacturing the logic circuit 100. The first metal liner 110 is formed on the top of the underlying layer device 105 by an appropriate deposition technique. The material of the first metal liner 110 can include, for example, TiN, TaN, TiC, TiAlC, or another appropriate material. The first metal layer 115 is formed on the top of the first metal liner 110 by an appropriate deposition technique. The material of the first metal layer 115 can include, for example, Ru, W, Cu, Al, Co, or another appropriate metal layer.

[0058] Figure 2B shows a cross-section B of the ReRAM array 200 during manufacturing, according to an embodiment of the present invention.

[0059] The underlying layer device 205 functions as the base of the ReRAM array 200. The underlying layer device 105 can be, for example, a substrate, a silicon wafer, a sapphire wafer, a MOS device, a CMOS device, a BTJ device, a diode, a resistor, a capacitor, a metal layer, a dielectric layer, or any type of material for manufacturing the ReRAM array 200. The figure shows that the ReRAM array 200 and the logic circuit 100 are manufactured on the same underlying layer devices 105, 205. However, the ReRAM array 200 and the logic circuit 100 can be manufactured on separate underlying layer devices 105, 205. The first metal liner 210 is formed on the top of the underlying layer device 105 by an appropriate deposition technique. The material of the first metal liner 210 can include, for example, TiN, TaN, TiC, TiAlC, or another appropriate material. The first metal layer 215 is formed on the top of the first metal liner 210 by an appropriate deposition technique. The material of the first metal layer 215 can include, for example, Ru, W, Cu, Al, Co, or another appropriate metal layer.

[0060] Figure 3A shows a cross-section A of the logic circuit 100 during manufacturing according to an embodiment of the present invention. Figure 3B shows a cross-section B of the ReRAM array during manufacturing according to an embodiment of the present invention. The ReRAM stack is composed of a plurality of layers formed on top of the first metal layers 115 and 215 during the same process. The ReRAM stack is composed of a first layer 120, 220, a second layer 125, 225, a third layer 130, 230, a fourth layer 126, 226, and a fifth layer 121, 221. The first layer 120, 220 and the fifth layer 121, 221 are composed of the same material, for example, TaN. The second layer 125, 225 and the fourth layer 126, 226 are composed of the same material, for example, TiN. The third layer 130, 230 may be composed of, for example, HfO2. These materials listed for the ReRAM stack are for illustrative purposes only and are not meant to be limiting. Any type of material that can be used to form the ReRAM stack can be used herein.

[0061] Figure 4A shows a cross-section A of the logic circuit 100 during manufacturing according to an embodiment of the present invention. The ReRAM stack is formed uniformly across the logic circuit 100 and the ReRAM array 200. Since the ReRAM stack is not required for the logic circuit 100, the ReRAM stack is removed from the logic circuit 100 region using an appropriate etching process. This is achieved by forming a patterning mask such as an optical planarization layer (OPL) on the device, followed by performing a lithography process to define the region where the ReRAM stack is to be removed, and then etching away the OPL and the ReRAM stack in that region, after which the first metal layer 115 is exposed.

[0062] Figure 4B shows a cross-section B of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. As described in the previous paragraph, the optical planarization layer 235 is not removed in the top ReRAM array region of the fifth layer 221. The optical planarization layer 235 protects the ReRAM stack from damage when the ReRAM layer is removed from the logic circuit 100 region.

[0063] FIG. 5A shows a cross-section A of the logic circuit 100 during manufacturing, according to an embodiment of the present invention. The hard mask 140 is formed on the uppermost surface of the first metal layer 115. The material of the hard mask 140 may include, for example, SiO2, SiN, SiBCN, SiCO, SiC, or other suitable hard mask materials. The hard mask 140 is planarized by CMP to make the uppermost portion of the hard mask 140 flush with the uppermost portion of the fifth layer 221 of the ReRAM stack.

[0064] FIG. 5B shows a cross-section B of the ReRAM array 200 during manufacturing, according to an embodiment of the present invention. The optical planarization layer 235 is removed to expose the surface of the fifth layer 221. Thereafter, the hard mask 140 is deposited on the uppermost portion of the fifth layer 221 of the ReRAM stack. The combined height of the hard mask 140 and the ReRAM stack is higher than the uppermost surface of the hard mask 140 disposed on the logic circuit 100. Since the hard mask between the logic circuit 100 and the ReRAM array 200 is of different heights, it affects the downstream processing of the components. Therefore, a CMP process is applied to polish and remove the hard mask 140 material on the fifth layer 221 so that the uppermost surface of the fifth layer 221 is flush with the uppermost surface of the hard mask 140.

[0065] FIG. 6A shows a cross-section A of the logic array 100 during manufacturing, according to an embodiment of the present invention. Additional hard mask material is deposited on the uppermost portion of the hard mask 140, enabling the formation of the hard mask 240 on the uppermost portion of the ReRAM stack while maintaining a flat uppermost surface between the logic circuit 100 and the ReRAM array 200. Therefore, the thickness of the hard mask 140 increases together with the additional hard mask material.

[0066] FIG. 6B shows a cross-section B of the ReRAM array 200 during manufacturing, according to an embodiment of the present invention. The hard mask 240 is formed on the uppermost portion of the fifth layer 221. The formation of the hard mask 240 increases the thickness of the hard mask 140. Since the hard mask 240 is necessary for patterning the layer, the hard mask 240 formed on the uppermost portion of the ReRAM stack is required.

[0067] Figure 7A shows a cross-section A of a logic circuit 100 during manufacturing according to an embodiment of the present invention. The hard mask 140 is a pattern for determining the portion of the logic circuit 100 to be etched to form a desired pattern. The etching process can utilize any etching technique that removes a desired layer at a specified location down to the underlying layer 105. The etching process creates pillars (extending in the foreground and background) of multiple layers where each pillar is composed of a first metal line 110, a first metal layer 115, and the hard mask 140. Although Figure 7A may appear to give the impression that the pillars extend only in the vertical direction, Figure 7A shows a cross-section A of the logic circuit 100. Figure 1A shows that three pillars extend a distance between the region of the cross-section A.

[0068] Figure 7B shows a cross-section B of a ReRAM array 200 during manufacturing according to an embodiment of the present invention. The hard mask 240 is a pattern for determining the portion of the ReRAM array to be etched to form a desired pattern. The etching process can utilize any etching technique that removes a desired layer at a specified location down to the underlying layer 205. The etching process creates pillars (extending in the foreground and background) of multiple layers where each pillar is composed of a first metal line 210, a first metal layer 215, a first layer 220, a second layer 225, a third layer 230, a fourth layer 226, a fifth layer 221, and the hard mask 240. The advantage of this design is that no metal liner is formed on the sidewalls of the pillars, that is, no metal liner exists on the sidewalls of the ReRAM stack. By not directly contacting the sidewalls of each layer of the ReRAM stack with a metal liner, the resistance of the ReRAM can be more appropriately controlled. Furthermore, by not having a metal liner, damage to the underlying layer caused by the formation and patterning of the metal liner can be avoided. Furthermore, since the ReRAM stack was formed directly on the first metal layer 215 before the patterning of the pillars, the ReRAM stack is self-aligned with the first metal layer 215.

[0069] FIG. 8A shows a cross-section A of the logic array 100 during manufacturing, according to an embodiment of the present invention. A dielectric layer 145 is deposited on the logic circuit 100. The dielectric layer 145 is formed on the top of each pillar during the deposition process. The dielectric layer 145 is planarized, for example, by chemical mechanical polishing (CMP) to expose the top of the hard mask 140 on each pillar. The dielectric layer 145 is in direct contact with the sidewalls of each pillar on the logic circuit 100.

[0070] FIG. 8B shows a cross-section B of the ReRAM array 200 during manufacturing, according to an embodiment of the present invention. A dielectric layer 245 is deposited on the ReRAM array 200 to fill the space between each pillar. The dielectric layer 245 is in direct contact with the sidewalls of the first metal layer 215, the first layer 220, the second layer 225, the third layer 230, the fourth layer 226, and the fifth layer 221, respectively. The dielectric layer 245 is formed on the top of each pillar during the deposition process. The dielectric layer 245 is planarized, for example, by chemical mechanical polishing (CMP) to expose the top of the hard mask 240 on each pillar. The advantage of this design is that since no metal liner is formed on the sidewalls of each pillar, the dielectric layer 245 can be in direct contact with the sidewalls of the ReRAM stack and the sidewalls of the first metal layer 215.

[0071] FIG. 9A shows a cross-section A of the logic circuit 100 during manufacturing, according to an embodiment of the present invention. An optical planarization layer 136 is deposited on the top surface of the dielectric layer 145 and the top of the exposed hard mask 140. Depending on the design of the logic circuit 100, a part of the optical planarization layer 136 can be removed. By removing these parts of the optical planarization layer 136, the hard mask 140 is exposed. As shown in FIG. 9A, the exposed part of the hard mask 140 can be removed to expose the top surface of the first metal layer 115. By removing the hard mask 140, a channel is created by the dielectric layer 145 that extends higher than the top of the first metal layer 115. This channel enables the extension of the second metal layer 155 to extend downward and connect to the first metal layer 215.

[0072] FIG. 9B shows a cross-section B of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. The optical planarization layer 136 is deposited on the topmost surface of the dielectric layer 245 and the topmost part of the exposed hard mask 240. The optical planarization layer 136 is removed to expose a part of the underlying hard mask 240 and the topmost surface of the dielectric layer 245. As shown in FIG. 9B, the exposed hard mask 240 is removed. By removing the hard mask 240, channels are created by the dielectric layer 245 that extends higher than the topmost part of the fifth layer 221. These channels allow the extension of the second metal layer 255 to extend downward and connect to the ReRAM stack. Further, these channels allow the second metal layer 255 to align with the topmost part of the exposed ReRAM stack.

[0073] FIG. 10A shows a cross-section A of the logic circuit 100 during manufacturing according to an embodiment of the present invention. The optical planarization layer 136 is removed to expose the topmost surface of the dielectric layer 145 and the topmost surface of the hard mask 140 remaining on some of the pillars. The thin liner layer 150 is formed on the topmost surface of the dielectric layer 145, the topmost surface of the hard mask 140, the sidewalls of the dielectric layer 145 from which the hard mask 140 has been removed, and the topmost surface of the first metal layer 115. Thus, the thin liner layer 150 covers the channels created by the removal of the hard mask 140. The material of the thin liner layer 150 may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. The second metal layer 155 is formed on the topmost surface of the thin liner layer 150. The second metal layer 155 extends downward into the channels and makes an electrical connection with the first metal layer 115 through the thin liner layer 150. The material of the second metal layer 255 may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer. The second metal layer 155 and the first metal layer 115 can be composed of the same material or different materials.

[0074] FIG. 10B shows a cross-section B of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. A thin liner layer 250 is deposited on the topmost surface of the dielectric layer 245, the sidewalls of the dielectric layer 245 from which the hard mask 240 has been removed, and the topmost surface of the fifth layer 221. Thus, the thin liner layer 250 covers the channels created by the removal of the hard mask 240. The material of the thin liner layer 250 may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. A second metal layer 255 is formed on the topmost surface of the thin liner layer 250. The second metal layer 255 extends downwardly into the channels and makes electrical contact with the fifth layer 221 of the ReRAM stack through the thin liner layer 250. The material of the second metal layer 255 may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer. The second metal layer 255 and the first metal layer 215 can be composed of the same material or different materials.

[0075] FIG. 10C shows a cross-section C of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. As shown in FIG. 1B, the cross-section C of the ReRAM array 200 is perpendicular to the cross-section B. A thin liner layer 250 is deposited on the topmost surface of the fifth layer 221. The material of the thin liner layer 250 may include, for example, TiN, TaN, TiC, TiAlC, or another suitable material. A second metal layer 255 is formed on the topmost surface of the thin liner layer 250. The material of the second metal layer 255 may include, for example, Ru, W, Cu, Al, Co, or another suitable metal layer. The second metal layer 255 and the first metal layer 215 can be composed of the same material or different materials.

[0076] FIG. 10D shows a cross-section D of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. The cross-section D of the ReRAM array 200 is parallel to the cross-section C. The dielectric layer 245 is formed directly on the topmost portion of the underlying layer 205, the thin liner layer 250 is formed on the topmost portion of the dielectric layer 245, and the second metal layer 255 is formed on the topmost portion of the thin liner layer 250.

[0077] FIG. 11A shows a cross-section A of the logic circuit 100 during manufacturing according to an embodiment of the present invention. The hard mask 141 is formed on the topmost part of the second metal layer 155. Based on the design of the logic circuit 100, a part of the hard mask 141, the second metal layer 155, and the thin liner layer 150 is removed. FIG. 11A shows that the right part is removed, which corresponds to the part along the cross-section A of FIG. 1A without the second metal layer 155. FIG. 11B shows a cross-section B of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. The hard mask 241 is formed along the top surface of the second metal layer 255. FIG. 11C shows a cross-section C of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. The hard mask 241 is patterned, and in the unpatterned regions, the material of the underlying layer is removed. The layer is removed until reaching the first metal layer 215. FIG. 11C shows that three pillars are created, which corresponds to the three columns that the cross-section C crosses as shown in FIG. 1B. FIG. 11D shows a cross-section D of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. The hard mask 241 is patterned, and the underlying layer is removed. The layer is removed until reaching the dielectric layer 245. FIG. 11C shows that three pillars are created, which corresponds to the three columns that the cross-section D crosses as shown in FIG. 1B. The process steps shown in FIGS. 11A to 11D are performed simultaneously, resulting in only one lithography step and one etching step.

[0078] FIG. 12A shows a cross-section A of the logic array 100 during manufacturing according to an embodiment of the present invention. An additional dielectric layer 145 is formed on the topmost part of the exposed surface to fill any regions. The dielectric layer 145 is CMP for removing excess material and creating the topmost surface of the plane. FIG. 12B shows a cross-section B of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. FIG. 12C shows a cross-section C of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. FIG. 12D shows a cross-section D of the ReRAM array 200 during manufacturing according to an embodiment of the present invention. An additional dielectric layer 245 is formed on the topmost part of the exposed surface to fill any regions. The dielectric layer 245 is CMP for removing excess material and creating the topmost surface of the plane. The process steps shown in FIGS. 12A - 12D are performed simultaneously, resulting in only one dielectric deposition step and one CMP step.

[0079] The ReRAM stack formed by the above process is aligned with the first metal layer 215 and the second metal layer 255. Since the ReRAM stack is self-aligned with the first metal layer 215 and the second metal layer 255, it becomes possible to design the ReRAM array 200 for different scales. Further, since the metal liner is in direct or some form of contact with the sidewalls of the ReRAM stack, it becomes possible to more finely control the resistance of the ReRAM stack.

[0080] The above method explains that the formation of the logic circuit 100 and the ReRAM array 200 occurs simultaneously on the same wafer. The two devices can be connected to each other via high-density interconnects (not shown). Thereby, since high-density interconnects can be fabricated simultaneously with the logic circuit 100 and the ReRAM array 200, the fabrication process can be simplified.

[0081] Although the present invention has been shown and described with reference to its specific exemplary embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents.

[0082] The descriptions of the various embodiments of the present invention are presented for purposes of illustration, but are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of one or more embodiments, actual applications, or technological improvements over technologies found in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

Claims

1. A substrate, A plurality of first columns extending parallel to each other on the uppermost surface of the substrate, each of the plurality of first columns including a resistive change type memory (ReRAM) stack composed of a plurality of layers, A plurality of second columns extending parallel to each other and perpendicular to the plurality of first columns, the plurality of second columns being disposed on the uppermost part of the plurality of first columns so that the plurality of second columns intersect the plurality of first columns, A dielectric layer filling the space between the plurality of first columns and the plurality of second columns, the dielectric layer being in direct contact with side walls of each of the plurality of layers of the ReRAM stack, Comprising, The plurality of layers of each ReRAM stack, A first layer composed of a first material, A second layer formed on the first layer, the second layer being composed of a second material different from the first material, A third layer formed on the second layer, the third layer being composed of a third material different from the first material and the second material, A fourth layer formed on the third layer, the fourth layer being composed of the second material, A fifth layer formed on the fourth layer, the fifth layer being composed of the first material, and an apparatus.

2. The first material is TaN, the second material is TiN, and the third material is HfO ２ The device according to claim 1, wherein the device is as described above.

3. The apparatus according to claim 2, wherein the dielectric layer is in direct contact with side walls of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

4. Each of the plurality of first columns, A first liner formed on the substrate, A first metal layer formed on the first liner, And the ReRAM stack formed on the first metal layer, Composed of, The apparatus according to any one of claims 1 to 3.

5. The apparatus according to claim 4, wherein the ReRAM stack is in direct contact with one of the plurality of second columns.

6. Each of the plurality of second columns, A second liner formed directly on the dielectric layer and on the uppermost part of the ReRAM stack, And a second metal layer formed directly on the second liner, Composed of, The apparatus according to claim 5.

7. The apparatus according to claim 5 or 6, wherein the dielectric layer extends higher than each of the plurality of first columns and creates a channel between a sidewall of the dielectric layer and the top of the ReRAM stack.

8. Each of the plurality of second columns A second liner, wherein the second liner is formed directly on the dielectric layer and on the top of the ReRAM stack such that the second liner is formed on the wall of the channel; A second metal layer, wherein the second metal layer is formed directly on the second liner such that the second metal layer fills the channel. Composed of The apparatus according to claim 7.

9. Forming a first liner on a substrate and forming a first metal layer on the first liner; Forming a resistive random access memory (ReRAM) stack on the first metal layer, the ReRAM stack being composed of a plurality of layers; Etching the first liner, the first metal layer, and the ReRAM stack to form a plurality of first columns extending parallel to each other; Forming the dielectric layer to fill an area between the plurality of first columns such that the dielectric layer is in direct contact with sidewalls of each of the plurality of layers of the ReRAM stack; Forming a second liner directly on the top surface of the dielectric layer and directly on the top of the ReRAM stack; Forming a second metal layer on the top of the second liner; Etching the second liner and the second metal layer to form a plurality of second columns, the plurality of second columns extending parallel to each other, the plurality of second columns extending perpendicular to the plurality of first columns, and the plurality of second columns being arranged on the top of the plurality of first columns such that the plurality of second columns intersect the plurality of first columns. Comprising The plurality of layers of each ReRAM stack A first layer composed of a first material; A second layer formed on the first layer, the second layer being composed of a second material different from the first material; A third layer formed on the second layer, the third layer being composed of a third material different from the first material and the second material. A fourth layer formed on the third layer, the fourth layer comprising a fourth layer composed of the second material, and A fifth layer formed on the fourth layer, the fifth layer comprising a fifth layer composed of the first material. **Claim 10** The first material is TaN, the second material is TiN, and the third material is HfO ２ The method according to claim 9, wherein the third material is HfO **Claim 11** The method according to claim 9 or 10, wherein the dielectric layer is in direct contact with the sidewalls of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer. **Claim 12** The method according to claim 9 or 10, wherein the dielectric layer is in direct contact with the sidewalls of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer. **Claim 13** The method according to any one of claims 9 to 12, wherein the ReRAM stack is in direct contact with one of the plurality of second columns. **Claim 14** The method according to any one of claims 9 to 13, wherein the dielectric layer extends higher than each of the plurality of first columns, creating a channel between the sidewall of the dielectric layer and the top of the ReRAM stack. **Claim 15** The step of forming each of the plurality of second columns comprises Forming the second liner directly on the dielectric layer and on top of the ReRAM stack such that the second liner is formed on the wall of the channel; and Forming the second metal layer directly on the second liner such that the second metal layer fills the channel. Comprising The method according to any one of claims 9 to 14. **Claim 16** Simultaneously forming a logic circuit and a resistive random access memory (ReRAM) array on a substrate, wherein The step of forming the ReRAM array comprises Forming a first liner on the substrate and forming a first metal layer on the first liner; and Forming a resistive random access memory (ReRAM) stack on the first metal layer, the ReRAM stack being composed of a plurality of layers; and Etching the first liner, the first metal layer, and the ReRAM stack to form a plurality of first columns extending parallel to each other; and Forming the dielectric layer to fill the region between the plurality of first columns such that the dielectric layer is in direct contact with the sidewalls of each of the plurality of layers of the ReRAM stack. Forming a second liner directly on the top surface of the dielectric layer and directly on the top of the ReRAM stack; Forming a second metal layer on the top of the second liner; Etching the second liner and the second metal layer to form a plurality of second columns, wherein the plurality of second columns extend parallel to each other, the plurality of second columns extend perpendicular to the plurality of first columns, and the plurality of second columns are arranged on the top of the plurality of first columns so as to intersect the plurality of first columns. A step of forming a ReRAM array having a step of etching; Comprising; The plurality of layers of each ReRAM stack are A first layer composed of a first material; A second layer formed on the first layer, the second layer being composed of a second material different from the first material; A third layer formed on the second layer, the third layer being composed of a third material different from the first material and the second material; A fourth layer formed on the third layer, the fourth layer being composed of the second material; A fifth layer formed on the fourth layer, the fifth layer being composed of the first material, and the dielectric layer being in direct contact with the sidewalls of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer. A fifth layer; A method consisting of.

17. The step of forming the logic circuit is Forming the first liner on the substrate; Forming the first metal layer on the first liner; Forming the ReRAM stack on the first metal layer to correspond to the step of forming the ReRAM on the ReRAM array; Removing the ReRAM stack; Forming a hard mask on the top of the first metal layer; Etching the first liner, the first metal layer, and the hard mask to form a plurality of third columns extending parallel to each other; Forming the dielectric layer to fill the region between the plurality of third columns; Forming a second liner directly on the top surface of the dielectric layer and directly on the top of the hard mask; Forming a second metal layer on the top of the second liner; Etching the second liner and the second metal layer to form a plurality of fourth columns, wherein the plurality of fourth columns extend parallel to each other, the plurality of fourth columns extend perpendicular to the plurality of third columns, and the plurality of fourth columns are arranged at the top of the plurality of third columns so that the plurality of fourth columns intersect the plurality of third columns, and the step of etching Having The method according to claim 16

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