Imaging Array with Improved Optical Transmission from Surface to Detector

Abstract

To provide an imaging array in which a small pixel has the same acceptance angles as a large pixel.SOLUTION: A pixel sensor array includes: a plurality of surface pixel sensors 10a and 10b disposed in a substrate 12; an interlayer dielectric layer 14 formed over the surface of the pixel sensors; and a plurality of apertures formed in the interlayer dielectric layer 14, each aperture being aligned with one of the surface pixel sensors and having an inner side wall. Lining layers 48a and 48b are formed on the inner side wall of respective apertures and substantially fully reflective to visible light. The lining layers 48a and 48b are spaced apart from the surface of the substrate 12 and have a smaller cross-sectional area than that of each of the surface pixel sensors 10a and 10b. A filler material substantially transparent to visible light is disposed inside of the reflective lining layers and has a top surface lying in the same plane as that of the dielectric material layer. A microlens is disposed over the top surface of each aperture.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an imaging array integrated circuit. In particular, the present invention relates to an imaging array having improved light transmission from the upper surface of the integrated circuit to the detector region.

Background Art

[0002] As digital cameras become thinner, the angle of light irradiating individual pixel sensors in the imaging array increases when measured perpendicular to the surface. Designers have used several techniques to accommodate these angles.

[0003]

[0004] According to one possible solution, the pixel sensors that make up the array can increase in size at the expense of a decrease in resolution. This is generally not considered a satisfactory solution in view of the tendency to increase rather than decrease the resolution of digital cameras.In very small pixels such as those used in the camera sensors of mobile phones, "optical pipes" have been used. This is conceptually similar to an optical fiber cable that relies on total internal reflection (TIR). Therefore, it requires the use of a high-index polymer as the core of the optical pipe. This concept works well for small angles of incidence (steep angles of incidence with respect to the sidewalls), but it becomes less useful as the angle of incidence increases. According to a particular prior art optical pipe solution depicted in FIG. 1, an optical pipe that uses internal reflection at the edge of a lens is positioned over a pixel sensor. Adjacent pixel sensors 10a and 10b are shown formed in a p-type substrate (or well) 12. A dielectric layer 14 is formed over the pixel sensors 10a and 10b, and vias are formed over and aligned with the pixel sensors 10a and 10b, respectively, and are filled with a polymer together to form optical pipes (denoted by reference numerals 16a and 16b) having a high refractive index (e.g., n≈1.6). Lenses 18a and 18b are formed on the surface of the dielectric layer as is known in the art. A layer of material (denoted by reference numeral 20) that provides total internal reflection is formed at the edges of the lenses 18a and 18b between adjacent pixel areas.

[0005] Two of the light rays directed towards the surface of the pixel sensor array including the pixel sensors 10a and 10b are symbolically denoted by reference numeral 22. As shown in FIG. 1, the light rays are refracted at the interface of the lenses 18a and 18b. The light ray 22 is also shown reflected from the layer 20 at the edge of the lens. In the absence of the material layer 20, these light rays 22 would continue to travel along a path leading to the next adjacent pixel, but the presence of the reflecting material layer 20 reflects these light rays back within the pixel area into which they entered.

[0006] Since the light rays 22 continue to travel downward from the lens into the polymer layers 16a and 16b, these light rays are reflected by the interfaces (indicated by reference numerals 24a and 24b) between each of the polymer layers 16a and 16b and the dielectric layer 14 (which has a refractive index of approximately n = 1.53). This interface does not reflect 100%, and thus, a portion of the light indicated by reference numeral 26 passes through the interface, passes through the dielectric layer separating two adjacent pixels, and undesirably enters the adjacent pixel sensors, causing unwanted crosstalk.

[0007] According to another specific prior art solution depicted in FIG. 2, backside illumination (BSI) has been used. In this embodiment, shown in a vertical orientation opposite to that of FIG. 1, a general photodiode pixel sensor 10 is formed and shown in a substrate or well 12. The dielectric layer 14 formed on top of the pixel sensor 10 includes transistor diffusions 28 and metal interconnect segments 30, shown arbitrarily in any location for illustrative purposes only.

[0008] The microlens 18 of the pixel sensor 10 is formed on top of a silicon dioxide layer 32 on the backside 34 of the silicon wafer on which the pixel sensor is fabricated. The silicon dioxide layer 32 is much thinner than the dielectric layer 14 of the prior art example shown in FIG. 1 and thus receives light from relatively large angles.

[0009] All of these techniques have drawbacks. Ideally, it is desirable for small pixels to have the same light-receiving angle as large pixels without the drawbacks of current solutions. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0010] According to a first aspect of the present invention, a pixel sensor array includes a plurality of surface pixel sensors disposed on a substrate, a dielectric layer formed on the surface of the pixel sensors, and a plurality of openings formed in the dielectric layer, each of which is aligned with one of the surface pixel sensors and has an inner sidewall. The lining layer is formed on the inner sidewall of each opening and substantially completely reflects visible light. The lining layer is spaced from the surface of the substrate and has a cross-sectional area smaller than the cross-sectional area of each surface pixel sensor. A filling material substantially transparent to visible light is disposed inside the reflecting lining layer and has an upper surface in the same plane as the upper surface of the dielectric layer. The microlens is disposed on the upper surface of each opening.

[0011] According to one aspect of the present invention, the pixel sensing layer is a layer of silicon doped with dopant species having a first conductivity type, and each surface pixel sensing element is a photodiode formed on the surface of the silicon layer. Each photodiode has an anode formed from a region of silicon doped with dopant species having a second conductivity type opposite to the first conductivity type.

[0012] According to another aspect of the present invention, the pixel sensor array also includes a first subsurface pixel sensing element disposed in the lower pixel sensing layer, aligned with the surface pixel sensing element, and insulated from the surface pixel sensing element, and a second subsurface pixel sensing element disposed in the lower pixel sensing layer, aligned with the first subsurface pixel sensing element, and insulated from the first subsurface pixel sensing element.

[0013] According to another aspect of the present invention, the reflecting lining layer is formed from an Al-Cu metal layer.

[0014] According to another aspect of the present invention, the filling material is formed from a polymer or a dielectric material such as silicon dioxide.

[0015] According to another aspect of the present invention, the inner wall of each reflecting lining layer is tapered from a larger cross-sectional area at its upper surface to a smaller cross-sectional area at its bottom surface.

[0016] According to another aspect of the present invention, each aperture is aligned with one of the surface pixel sensing elements within a predetermined error range.

[0017] According to another aspect of the present invention, the reflective lining layer is capacitively coupled to a low-resistance metal layer biased at one of the supply voltages of the integrated circuit containing the pixel sensor array.

[0018] The present invention will be described in more detail below with reference to embodiments and the drawings.

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Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0031] Those skilled in the art will realize that the following description of the present invention is merely exemplary and in no way limiting. Other embodiments of the present invention will be readily suggested to those skilled in the art.

[0032] Referring now to FIG. 3, there is depicted a portion 40 of an exemplary pixel sensor array including a pair of surface pixel sensors 10a and 10b, according to an aspect of the present invention, formed on a substrate 12. In FIG. 3, the substrate is shown as a p-type substrate, and the surface pixel sensors 10a and 10b are n-type regions disposed on the p-type substrate that forms the anode of a photodiode, as is known in the art, and the substrate forms the cathode of the photodiode. Those skilled in the art will recognize that the p-type substrate may be a p-well formed in a semiconductor substrate underlying it. Although the portion 40 of the array depicted in FIG. 3 shows only two pixel sensors 10a and 10b, those skilled in the art will also recognize that an array actually fabricated in accordance with the principles of the present invention may include any number of pixel sensors.

[0033] A first interlayer dielectric layer 14 is formed over the surface of the substrate 12 and over the n-type regions that form the surface pixel sensors 10a and 10b. Vias are formed to function as optical pipes 16a and 16b. As is presently preferred, the optical pipes 16a and 16b have a tapered shape such that the cross-sectional area at the upper ends 42a and 42b, which are in the same plane as the upper surface 44 of the first interlayer dielectric layer 14, is larger than the cross-sectional area at the lower ends 46a and 46b. The cross-sectional area of the lower ends 46a and 46b of the optical pipes 16a and 16b is smaller than the cross-sectional area of the pixel sensors 10a and 10b and is substantially centered over the pixel sensors 10a and 10b. The lower ends 46a and 46b of the optical pipes 16a and 16b are spaced from the upper surface of the substrate.

[0034] Conceptually, providing vertical sidewalls is simpler, but it has several practical drawbacks. The most significant drawback is that it limits the viewing angle at the top of the optical pipe, which requires a larger pixel size and / or imposes very strict limitations on process control. In view of these drawbacks, a tapered design is preferred.

[0035] According to one aspect of the present invention, the process of forming the tapered vias that form the optical pipes 16a and 16b uses an etching chemistry that includes fluorine (F) for etching SiO2 and a chemical for generating an organic polymer that adheres to the etched sidewalls to protect the etched sidewalls. The fluorine etches the bottom of the via, while the polymer adheres to the sidewalls to protect the sidewalls from the etching process. Every time interval Δt, the SiO2 is etched a distance Δy downward, and a polymer having a thickness Δx is adhered to the sidewalls. By controlling the amounts of F and the polymer, the degree of taper is controlled. Since the process varies from factory to factory, periodic testing can be used to achieve the desired degree of taper in a given process.

[0036] A typical plasma etching chemistry can include CF4, which functions as a major source of F, CHF3, which is a major source of the hydrocarbon polymer C x H y …C x H y F z and Ar, which functions as a carrier gas and as an ion source.

[0037] The optical pipes 16a and 16b each run along a reflective liner indicated by reference numerals 48a and 48b.

[0038] The optical pipe of the present invention can be formed in one of two ways. According to one aspect of the present invention, where the first interlayer dielectric layer 14 is formed from silicon dioxide (SiO2), the vias of the optical pipe can be filled with a filling material that is substantially transparent in the visible spectrum. Examples of suitable filling materials include dielectric materials such as SiO2 or polymers having a refractive index higher than that of the surrounding first silicon dioxide interlayer dielectric layer 14.

[0039] To form a well-reflecting surface on the sidewalls of the optical pipes 16a and 16b, the reflecting inner liner layers, denoted by reference numerals 48a and 48b, which are adhered to line the inner walls of the optical pipes, need to exhibit good reflection across the entire visible wavelength range. That is, it preferably has a silver appearance. The reflecting inner liner layer is a metallic inner liner layer and preferably has a smooth surface since a rough surface is known to scatter light, and a surface with high specular reflectivity is preferred. The thickness of the metal layer is sufficient to prevent light from penetrating the sidewalls to avoid crosstalk between pixel sensors at large incident angles and also needs to be thick enough to avoid pinhole defects.

[0040] According to an aspect of the present invention, the Al-Cu metallization material, which is commonly used in the CMOS process as a metallization interconnect layer, has the required properties. Tungsten metallization is also currently in use but has a dull gray appearance and an unacceptably large surface roughness, resulting in insufficient reflectivity.

[0041] At a light wavelength of 750 nm, the theoretically minimum Al-Cu thickness for a light transmission attenuation of 10e6 is about 0.028 μm. However, the resistivity of the Al-Cu thin film may be higher than the bulk resistivity, and films with thicknesses within this range are known to have pinholes, so this may be insufficient. The minimum thickness of the Al-Cu film is at least about 0.14 μm. Furthermore, since the step coverage of plasma vapor deposition (PVD) Al-Cu is relatively poor, a sputter thickness of about 0.24 μm is currently preferred at the upper ends 42a and 42b, which results in a minimum thickness of about 0.14 μm at the lower ends 46a and 46b of the optical pipes 16a and 16b.

[0042] In certain non-limiting example embodiments, the upper ends 42a and 42b of the optical pipes are chosen to provide a minimum photoresist width between adjacent optical pipe holes of 0.8 μm. In an exemplary embodiment where a pixel sensor size of 4.15 μm is assumed, this gives a top dimension of 4.15 - 0.8 = 3.35 μm.

[0043] In a tapered optical pipe design, the bottom of the optical pipe must be smaller than the dimension of the top surface of the photodiode, which, in one non-limiting example, is assumed to be approximately 2.8 μm active. As an example, if the active enclosure of the optical pipe is considered to be 0.2 μm, the width of the bottom can be determined to be 2.8 - 0.4 = 2.4 μm.

[0044] The length of the optical pipe is not critical to the optical system design and a fair amount of freedom is provided in choosing it. For additional metal layers, it is advantageous to have a thicker back end of line (BEOL). In one example embodiment, the thickness of the interlayer dielectric layer 14 is chosen to be approximately 6 μm, which allows for four metal interconnect layers to be included within the interlayer dielectric layer 14.

[0045] Given the above parameters, the sidewall angle is nominally about 3.6°. The thicker first interlayer dielectric layer 14 further reduces the angle, but an increase in the thickness of the first interlayer dielectric layer 14 from 6 μm to 7 μm only reduces the sidewall angle by 0.5° (which is not a significant benefit), and one of ordinary skill in the art will recognize that it increases the aspect ratio of the vias forming the optical pipes 16a and 16b.

[0046] The base layer 50 is inserted to separate the bottoms of the optical pipes 16a and 16b from the surfaces of the pixel sensors 10a and 10b. It would be optically advantageous if the optical pipes extended all the way down to the silicon surface. However, this can damage the silicon, result in dark current, and etch into the silicon. Additionally, when a metallic substance creating a reflective lining contacts the upper surface of the pixel sensor, the thermal budget of subsequent process steps causes metal ions to diffuse into the pixel sensor layer and severely damage the pixel sensor layer, rendering the pixel sensors 10a and 10b inoperable. The base layer consists of residual SiO2 from the first interlayer dielectric layer left without etching under the lower ends 46a and 46b.

[0047] If the thickness of the base layer 50 is too large, light escapes under the metal and is allowed to deviate from the active areas of the pixel sensors 10a and 10b, and the efficiency of light capture decreases, especially as the angle increases.

[0048] In an exemplary embodiment, for light entering the optical pipe at an incident angle of 40°, it has a maximum angle of 55°. The thickness of the base layer is selected to allow no more than 1% of the light to deviate from the active pixel sensor area and to allow for a misalignment of 0.1 μm between the active pixel sensor area and the optical pipe. When the misalignment between the active pixel sensor area and the optical pipe is zero, the simulation shows that no light deviates from the active pixel sensor area, and for a misalignment of 0.1 μm, 0.6% of the light deviates from the active pixel sensor area. Based on the simulation results, a thickness of approximately 0.1 μm for the base layer 50 was found to be satisfactory. When a base layer thickness of 0.2 μm was used, the simulation results showed that for a misalignment of zero between the active pixel sensor area and the optical pipe, 6.4% of the light deviates from the active pixel sensor area, and for a misalignment of 0.1 μm, 11.7% of the light deviates from the active pixel sensor area.

[0049] The second interlayer dielectric layer 52 is disposed on the first interlayer dielectric layer 14, on the planarized uppermost portions of the reflective inner lining layers 44a and 44b, and on the uppermost portions of the filling materials in the optical pipes 16a and 16b, respectively. In certain embodiments, this second interlayer dielectric layer 50 may have a thickness of about 2.5 μm, at which thickness it can support two metal interconnect layers.

[0050] The passivation layer 54 is formed on the upper surface of the second interlayer dielectric layer 52, and the planarization layer 56 is formed on the upper surface of the passivation layer 54. In certain embodiments, the thickness of the passivation layer 54 may be about 0.3 μm, and the thickness of the planarization layer 56 may be about 0.4 μm. These layers can be formed, for example, from deposited silicon dioxide.

[0051] FIG. 3 shows a plurality of light rays 58a and 58b entering the pixel sensors 10a and 10b through the microlenses 18a and 18b, respectively. The focal lengths of the microlenses 18a and 18b are selected such that the foci of the light rays are located at positions 60a and 60b, respectively. One of ordinary skill in the art will note that the positions of the foci 60a and 60b are within the optical pipes 16a and 16b. Thus, as seen in FIG. 3, all of the incident light rays 58a and 58b that diverge beyond the foci 60a and 60b strike the pixel sensors 10a and 10b either directly or after reflection from the reflective inner lining layers 48a and 48b.

[0052] Referring now to FIGS. 4A and 4B, these two figures illustrate a structure for eliminating the effect of flare light in a pixel sensor according to an embodiment of the present invention. FIG. 4A is a cross-sectional view of a pair of adjacent optical pipe structures 16a and 16b. One of ordinary skill in the art will recognize that the layers 54, 56, and the microlenses 18a and 18b are present in the structure depicted in FIG. 4A but are omitted from the drawing.

[0053] Flare in the lens and the camera can result in an incident light angle of incidence within the range of about 70° to about 75°. In conventional optical designs, it is impossible to protect the pixel sensor from flare light, but according to certain aspects of the present invention, there are several measures that can be taken to suppress flare light. The influence of flare light must be considered at both the upper ends 42a and 42b and the lower ends 46a and 46b of the light pipes 16a and 16b. As described above, at the lower ends 46a and 46b of the light pipes 16a and 16b, flare can be minimized by using a thin base layer (i.e., in the case of the light pipes having the dimensions described herein in the above-described embodiment example, a thickness of about 0.1 μm). Although up to 15% of the flare light can deviate from the active pixel sensor area, the amount of flare light captured in a single pixel sensor 10a or 10b should not be a problem since it is only a small part of the total light.

[0054] As shown in FIG. 4A, the holes 62a and 62b of the metal interconnect layer 64 formed in the second interlayer dielectric layer 52 define the optical apertures of the pixel sensors 10a and 10b. The structure for minimizing flare light may include a metal layer 66 formed in the first interlayer dielectric region 14 and a metal layer 68 formed in the second interlayer dielectric layer 52. The holes of the metal layers 66 and 68 are wider than the holes 62a and 62b in the metal interconnect layer 64 and do not affect the optical apertures of the pixel sensors 10a and 10b.

[0055] A high density array of through-silicon vias, one of which is shown by reference numeral 70, can be used between metal interconnect layer 64 and metal interconnect layer 66 in the region between adjacent pixel sensors to block flare light. Similarly, a plurality of through-silicon vias, one of which is shown by reference numeral 72, are formed between metal interconnect layer 64 and metal interconnect layer 68 in the region between adjacent pixel sensors. FIG. 4B shows an exemplary top view of a vertical structure showing the layout of interconnect vias 70 and 72. Vias 70 and 72 are each positioned laterally so as to effectively block flare light, indicated by the arrows as coming in from the left side of FIG. 4B, from traveling between any of the metal interconnect layer segments 64, 66, and 68 that make up the vertical structure. The plurality of sheets of metal interconnect layers 64, 66, and 68 are all connected to Vpix.

[0056] Referring now to FIG. 5, a cross-sectional view of a portion 80 of a non-limiting example of a pixel sensor array showing a pair of vertical color pixel sensors formed on substrate 12, according to an aspect of the present invention, shows that the principles of the present invention are applicable to vertical color pixel sensors such as the X3™ sensor by Foveon, Inc. of San Jose, Calif. The fabrication and use of such vertical color pixel sensors are known in the art. The embodiment shown in FIG. 5 is substantially similar to the embodiment depicted in FIG. 3, and the elements of portion 60 of the vertical pixel sensor array of FIG. 5 corresponding to the elements of the portion of the pixel sensor array of FIG. 3 are identified using the same reference numerals as those used in FIG. 3.

[0057] The first vertical color pixel sensor includes a surface blue pixel sensor 10b1, an embedded green pixel sensor 10g1, and an embedded red pixel sensor 10r1. The second vertical color pixel sensor includes a surface blue pixel sensor 10b2, an embedded green pixel sensor 10g2, and an embedded red pixel sensor 10r2. The substrate is shown as a p-type substrate in FIG. 5, and the vertical color pixel sensors including the blue, green, and red pixel sensors 10b, 10g, and 10r are n-type regions disposed in a p-type substrate that forms the anode of a photodiode as is known in the art, and the substrate forms the cathode of the photodiode. Those skilled in the art will recognize that the p-type substrate may be a p-well formed in a semiconductor substrate below.

[0058] The arrangement of elements on the substrate 12 of the portion 80 of the array in FIG. 5 is the same as the arrangement of elements on the substrate 12 of the portion 40 of the array in FIG. 3 and the portion 60 in FIG. 4A, and is disclosed with reference to the description of the embodiments of FIGS. 3 and 4A.

[0059] Referring now to FIG. 6, a cross-sectional view of an adjacent pair of pixel sensors and a light pipe structure illustrates a portion 90 of an array including a standard pixel sensor 10n and an exemplary reduced-sensitivity highlight pixel sensor 10h according to an embodiment of the present invention. The concept and use of the highlight pixel sensor are disclosed in U.S. Patent No. 9,191,556, issued November 17, 2015, which is hereby incorporated by reference in its entirety. FIG. 6 shows a single surface pixel sensor, but those skilled in the art will recognize that the illustrated highlight pixel concept is applicable to the vertical color pixel sensors disclosed herein.

[0060] The arrangement shown in FIG. 6 is substantially similar to FIGS. 4A and 5 and will not be described in detail except to refer to the differences between the standard sensitivity pixel sensor 10n and the reduced sensitivity highlight pixel sensor 10h, according to certain aspects of the present invention. The array portion 90 shown in FIG. 6 is substantially similar to the embodiments depicted in FIGS. 4A and 5, and the elements of the vertical pixel sensor array portion 90 in FIG. 6 corresponding to the elements of the pixel sensor array portion 40 in FIG. 4A and the pixel sensor array portion 70 in FIG. 5 are identified using the same reference numbers as those used in FIG. 5.

[0061] Above the standard pixel 10n configured as a standard pixel, the optical aperture 92 formed in the metal interconnect layer 64 on the light pipe 16n extends to a position aligned with the uppermost end of the light pipe 16b. Above the reduced sensitivity highlight pixel 10h, the optical aperture 94 formed in the metal interconnect layer 64 on the light pipe 16h extends across the uppermost end of the light pipe 16a and prevents some of the light from entering the light pipe 16a. Due to the restricted optical aperture 94 formed by the ends of the metal interconnect layer 64, the highlight pixel sensor 16a has a lower gain than the pixel sensor 16b. As described above, the vertical structures formed by the vias 70 and 72 between the metal interconnect layers 64 and 66 and between 64 and 68, respectively, eliminate the error in the relative gain structure of the standard pixel sensor and the highlight pixel sensor in the array fabricated according to this aspect of the present invention from causing flare light.

[0062] According to certain aspects of the present invention, the exemplary target range for the reduced sensitivity highlight pixel is generally about one-half to one-eighth of the standard pixel, although those skilled in the art will readily recognize that other ranges may be used. For example, if the amount of light entering the pixel is reduced to one-fourth of the light entering the standard pixel, the sensitivity will be about one-fourth of the sensitivity of the standard pixel. As will be readily appreciated by those skilled in the art, the smaller the size of the aperture 92, the greater the reduction in light sensitivity obtained.

[0063] The use of vertical color pixels sensors is shown in FIGS. 5 and 6. However, the principles of the present invention are equally applicable to monochromatic pixel sensors and vertical color pixel sensors, and those skilled in the art will readily understand that no preference is intended between the two types of sensors in the various drawings and disclosed embodiments presented herein.

[0064] According to one aspect of the present invention illustrated in FIG. 7, the low-sensitivity pixels 10h are regularly placed throughout the imaging array of standard pixels 10n. FIG. 7 is a top view of the metal layer 64 showing the layout of the holes 92 and 94 to illustrate an example layout of the highlight pixels. The non-limiting exemplary layout of FIG. 7 shows a hole 94 for one highlight pixel 10h for every 10 positions in both the horizontal and vertical directions of the array. The low-sensitivity pixels are arranged not to degrade the overall quality of the image, but to supplement the image processing of the highlight data. An example layout of the pixels according to the present invention is about every 2 to 100 pixels on a given matrix, but those skilled in the art will recognize that different intervals such as periodic, pseudo-random, and random can be used. As a result, the low-sensitivity pixels can occupy from about 40% to about 0.01% of the total number of pixels. In one example, one arrangement includes one low-sensitivity pixel for every 10×10 pixel region. Those skilled in the art will recognize that an appropriate ratio can be selected depending on the size of the pixels and the array.

[0065] According to one aspect of the present invention, the highlight pixels can be placed in a regular pattern in the imaging array. For example, the highlight pixels can be arranged in a diamond pattern as shown in FIG. 8. Generally, such a diamond pattern is generated by first creating a regular pixel spacing and then adding a highlight pixel at the center of a square of four existing standard pixels. As another non-limiting example of the arrangement shown in FIG. 8, the highlight pixels can be placed every 10 pixels horizontally and vertically and every 5 pixels diagonally.

[0066] Referring now to FIG. 9A, a simplified cross-sectional view of the optical pipe structure illustrates the problem of coupling of stray capacitance due to the relatively large surface area of the reflective liner identified by reference numeral 48. The metal liner 48 functions as one plate of the parasitic capacitance to other metal segments in the interconnect structure of the integrated circuit. In FIG. 9A, the stray capacitance is shown as capacitors 100a - 100j coupling between the reflective liner 48 and the metal interconnect segments 102a - 102j at the metal interconnect levels M1 - M5 of the integrated circuit, respectively.

[0067] The metal wire segments 102a - 102j carry digital or analog signals, switch between high and low logic states, or switch between different analog voltages. As shown in FIG. 9B, the capacitors 100a - 100j parasitically couple the digital and analog voltage variations to the other of the reflective liner and the metal wire segments 102a - 102j. Each path can be represented by a series RC circuit coupled between one power potential represented by the amplifier 104 and the reflective liner 48, and reference numerals 106a - 106d represent the resistance of each metal wire.

[0068] FIGS. 10A and 10B illustrate a solution to the problem of parasitic signal coupling shown in FIGS. 9A and 9B. The metal interconnect level M4 is designated as the DC power bus. M4 can be formed as a very wide metal (basically, a metal sheet having an opening formed around the optical pipe). Also, the M4 metal layer may be located closer to the reflective liner 48 than the metal segments of the other metal layers M1 - M3.

[0069] By forming the M4 layer as a large sheet, its resistance path to the power ground is much smaller than the resistance of the other metal interconnect segments to the power ground (R M4 <<R M1 、R M2 、R M3) By disposing the metal layer M4 near the inner lining 48 that reflects more than the metal interconnect segments of the other metal layers M1 to M3, the coupling capacitance between the metal layer M4 and the reflecting inner lining 48 is much larger than the coupling capacitance between the metal interconnect segments of the other metal layers M1 to M3 and the metal inner lining 48 (C4(100a and 100b) >> C1, C2, C3). As a result, an impedance path from the metal inner lining 48 to power ground is provided, which is much lower than the impedance path from the metal inner lining 48 to the other metal wire segments M1 to M3. As a result, more of the parasitic signals coupled to the metal inner lining 48 are shunted to ground rather than to the metal interconnect segments carrying other signals.

[0070] Although the embodiments and application examples of the present invention have been illustrated and described, it will be apparent to those skilled in the art that many more modifications are possible without departing from the inventive concept of this specification. Therefore, the present invention is not limited except as defined by the spirit of the appended claims.

Claims

A pixel sensor array formed on a substrate, wherein the pixel sensor array comprises: a plurality of surface pixel sensors formed on the surface of the substrate; a dielectric layer formed on the surface of the substrate and covering the entire area of the cross-section of each surface pixel sensor; a plurality of openings formed in the dielectric layer, each opening being aligned with one of the surface pixel sensors, each opening having an inner sidewall, the plurality of openings; a reflective lining layer formed on the inner sidewall of each opening, the lining layer substantially completely reflecting visible light, the inner wall of each reflective lining layer being spaced from the surface of the substrate and having a cross-sectional area smaller than the cross-sectional area of each surface pixel sensor, the inner wall of each reflective lining layer being in the same plane as the upper surface of the dielectric layer, the reflective lining layer; a filling material disposed in each opening inside the reflective lining layer and having an upper surface in the same plane as the upper surface of the dielectric layer, the filling material being substantially transparent to visible light; a microlens disposed on the upper surface of each opening; a vertical structure disposed between each adjacent pair of the pixel sensors and forming an entrance opening for light to enter the pixel sensor, each vertical structure comprising: a segment of a first metal interconnect layer located under the upper surface of the reflective lining layer of the adjacent pair of the pixel sensors; a segment of a second metal interconnect layer located on the upper surface of the reflective lining layer of the adjacent pair of the pixel sensors; a segment of a third metal interconnect layer located on the segment of the second metal interconnect layer; a plurality of first metal interconnect vias disposed between the segment of the first metal interconnect layer and the segment of the second metal interconnect layer; a plurality of second metal interconnect vias disposed between the segment of the second metal interconnect layer and the segment of the third metal interconnect layer; comprising: The plurality of first metal interconnect vias and the plurality of second metal interconnect vias are laterally positioned relative to each other to prevent flare light from passing through any of the vertical structures, the pixel sensor array. Claim 2 The pixel sensor array according to claim 1, wherein the plurality of first metal interconnect vias and the plurality of second metal interconnect vias are arranged in rows, and the metal interconnect vias in adjacent rows are offset from each other.

3. The segments of the second metal interconnect layer disposed between the first plurality of adjacent pairs of pixel sensors are spaced apart by a distance for forming a first pixel sensor having an aperture with a first area, The segments of the second metal interconnect layer disposed between the second plurality of adjacent pairs of pixel sensors are spaced apart by a distance for forming a second pixel sensor having an aperture with a second area smaller than the first area, and the aperture having the second area has a smaller number than the aperture having the first area. The pixel sensor array according to claim 1.

4. The aperture of the second pixel sensor is selected to permit from about one-eighth to about one-half of the light permitted by the aperture of the first pixel sensor. The pixel sensor array according to claim 3.

5. The second pixel sensor is placed every 2 to 100 pixels on a given row of the array. The pixel sensor array according to claim 3.

6. The second pixel sensors are distributed in a regular pattern across the entire imaging array. The pixel sensor array according to claim 3.

7. The second pixel sensors are distributed in a diamond pattern across the imaging array. The pixel sensor array according to claim 5.

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