Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: An interlayer insulating film IL includes an insulating film IF1 formed on a semiconductor layer ND, and an insulating film IF2 formed on the insulating film IF1. The insulating film IF1 is a silicon oxide film. The insulating film IF2 is a BPSG (BoroPhosphoSilicate Glass) film. A thickness of the insulating film IF2 is larger than that of the insulating film IF1. A contact hole CH consists of a first contact hole CH1 and a second contact hole CH2. The first contact hole CH1 penetrates through an emitter region NE to reach a base region PB. The second contact hole CH2 is formed on the insulating film IF1 and the insulating film IF2 to be communicated with the first contact hole CH1. An opening width of the second contact hole CH2 is larger than that of the first contact hole CH1.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including contact holes formed in an interlayer insulating film and a method for manufacturing the same.

Background Art

[0002] As an IGBT (Insulated Gate Bipolar Transistor) having a low on-resistance, a trench gate type IGBT is widely used.

[0003] For example, Patent Document 1 discloses an IGBT having a GGEE structure. In such an IGBT, in an active cell, a pair of trenches are formed in an n-type semiconductor layer, a gate electrode is embedded inside the pair of trenches, and an n-type emitter region is formed in a p-type base region located between the pair of trenches. Further, in an inactive cell, an emitter region is not formed in the base region located between the pair of trenches. Then, a gate potential is supplied to the gate electrode of the active cell, while an emitter potential is supplied to the gate electrode of the inactive cell.

[0004] Patent Document 2 discloses an IGBT having a GGEE structure similar to that of Patent Document 1. An interlayer insulating film is formed on the semiconductor layer, and contact holes penetrating the interlayer insulating film and the emitter region are formed. Further, the interlayer insulating film is composed of a silicon oxide film formed by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method and a laminated film of a silicon oxide film such as a PSG (Phospho Silicate Glass) film, a BPSG (Boro Phospho Silicate Glass) film, an NSG (Non-doped Silicate Glass) film, or a SOG (Spin On Glass) film.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-140885 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-225566 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] When trying to form a thick interlayer insulating film, it is often the case that a PSG film and a SOG film are laminated. However, in a fab that performs a general CMOS process, an apparatus for forming a SOG film is often not introduced. When configuring the interlayer insulating film only with a PSG film without using a SOG film, the following problems have been found.

[0007] For example, after forming a contact hole in the interlayer insulating film, the inside of the contact hole is filled with a plug mainly composed of a tungsten film. Since the tungsten film is deposited not only inside the contact hole but also on the interlayer insulating film, it is necessary to remove the tungsten film on the interlayer insulating film. At that time, if the upper surface of the interlayer insulating film is not flat, there is a problem that a part of the tungsten film is likely to remain as a residue.

[0008]

[0009] In addition, when a semiconductor device has a region for forming other semiconductor elements such as a diode in addition to the region for forming an IGBT, if the upper surface of the interlayer insulating film is not flat, the thickness of the interlayer insulating film will be different for each region. Therefore, since it is necessary to form contact holes individually for each region, there is a problem that the number of masks increases and the manufacturing cost increases.

[0010] ​The main object of the present application is to improve the reliability of a semiconductor device by ensuring the flatness of the upper surface of a thick interlayer insulating film and suppressing residues such as tungsten films. Another object of the present application is to suppress an increase in manufacturing cost. Still another object of the present application is to provide a manufacturing method with relatively high versatility that is easy to implement in various fabs.

[0011] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0012] Among the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

[0013] A semiconductor device according to an embodiment includes a semiconductor substrate having a semiconductor layer of a first conductivity type, a first impurity region of a second conductivity type, which is formed in the semiconductor layer and has a conductivity type opposite to that of the first conductivity type, a second impurity region of the first conductivity type, which is formed in the first impurity region, a trench that penetrates the first impurity region and the second impurity region and reaches the semiconductor layer, a gate insulating film formed inside the trench, a gate electrode formed on the gate insulating film so as to fill the inside of the trench, an interlayer insulating film formed on the semiconductor layer, a contact hole that penetrates the interlayer insulating film and the second impurity region and reaches the first impurity region, and a plug that fills the inside of the contact hole and is electrically connected to the first impurity region and the second impurity region. Here, the interlayer insulating film includes a first insulating film formed on the semiconductor layer and a second insulating film formed on the first insulating film. The first insulating film is a silicon oxide film, the second insulating film is a BPSG film, the thickness of the second insulating film is greater than the thickness of the first insulating film, the contact hole includes a first contact hole that penetrates the second impurity region and reaches the first impurity region, and a second contact hole that is formed in the first insulating film and the second insulating film and communicates with the first contact hole, and the opening width of the second contact hole is greater than the opening width of the first contact hole.

[0014] A method for manufacturing a semiconductor device according to an embodiment includes: (a) preparing a semiconductor substrate having a semiconductor layer of a first conductivity type; (b) forming a trench in the semiconductor layer; (c) forming a gate insulating film inside the trench; (d) forming a gate electrode on the gate insulating film so as to fill the inside of the trench; (e) forming a first insulating film on the semiconductor layer; (f) forming a first impurity region of a second conductivity type, which is opposite to the first conductivity type, in the semiconductor layer; (g) forming a second impurity region of the first conductivity type in the first impurity region; (h) forming a second insulating film having a thickness greater than that of the first insulating film on the first insulating film, thereby forming an interlayer insulating film including the second insulating film and the first insulating film on the semiconductor layer; (i) forming a contact hole that penetrates the interlayer insulating film and the second impurity region and reaches the first impurity region; (j) forming a plug electrically connected to the first impurity region and the second impurity region so as to fill the inside of the contact hole. Here, the first insulating film is a silicon oxide film, and the second insulating film is a BPSG film. Further, the step (i) includes: (i1) forming a first contact hole in the second insulating film, the first insulating film, the second impurity region, and the first impurity region; (i2) after the step (h1), performing an isotropic etching process on the second insulating film and the first insulating film to form a second contact hole in the second insulating film and the first insulating film, the opening width of which is larger than the opening width of the first contact hole and which communicates with the first contact hole.

Advantages of the Invention

[0015] According to one embodiment, the performance of the semiconductor device can be improved. Also, according to one embodiment, an increase in manufacturing cost can be suppressed.

Brief Description of the Drawings

[0016]

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Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.

[0018] (Embodiment 1) <Structure of Semiconductor Device> Hereinafter, the semiconductor device 100 in Embodiment 1 will be described with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing a semiconductor chip which is the semiconductor device 100.

[0019] As shown in FIG. 1, most of the semiconductor device 100 is covered with an emitter electrode EE. A gate wiring GW is formed on the outer periphery of the emitter electrode EE. The region surrounded by the broken line in the emitter electrode EE is an emitter pad EP, and the region surrounded by the broken line in the gate wiring GW is a gate pad GP. A part of each of the emitter electrode EE and the gate wiring GW is covered with a protective film (not shown). The regions exposed from this protective film are the emitter pad EP and the gate pad GP. By connecting external connection terminals such as wire bonding or clips (copper plates) on the emitter pad EP and the gate pad GP, the semiconductor device 100 is electrically connected to other semiconductor chips or wiring boards.

[0020] FIG. 2 is a cross-sectional view of the main part corresponding to the region 1A in FIG. 1. The region 1A is a cell region where an IGBT is formed. The IGBT shown in FIG. 2 is an IGBT having a GGEE structure and is an IE-type IGBT that can utilize the IE (Injection Enhancement) effect.

[0021] The IE effect is a technology that increases the concentration of charges accumulated in the semiconductor layer ND by making it difficult for holes to be discharged from the emitter electrode EE side when the IGBT is in the on state. For this reason, the semiconductor device 100 has an active cell region AC for performing the main operation of the IGBT and an inactive cell region IAC other than the active cell region AC. The gate electrode GE1 of the active cell region AC is electrically connected to the gate wiring GW, and a gate potential is supplied during the operation of the IGBT. The gate electrode GE2 of the inactive cell region IAC is electrically connected to the emitter electrode EE, and an emitter potential is supplied during the operation of the IGBT.

[0022] The semiconductor substrate SUB has a low-concentration n-type semiconductor layer (drift region) ND. On the back side of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS having a higher impurity concentration than the semiconductor layer ND, a p-type collector region (impurity region) PC, and a collector electrode CE made of a metal film are formed. During the operation of the IGBT, a collector potential is supplied to the collector region PC through the collector electrode CE.

[0023] On the surface side of the semiconductor substrate SUB, trenches TR are formed in the semiconductor layer ND. The trenches TR penetrate through an emitter region NE and / or a base region PB, which will be described later, and reach the semiconductor layer ND. A gate insulating film GI is formed inside the trenches TR. The gate electrodes GE1, GE2 are formed on the gate insulating film GI so as to fill the inside of the trenches TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrodes GE1, GE2 are, for example, polycrystalline silicon films into which n-type impurities are introduced.

[0024] In the active cell region AC, in the semiconductor layer ND between a pair of gate electrodes GE1, a hole barrier region (impurity region) NHB having an impurity concentration higher than that of the semiconductor layer ND is formed. In the hole barrier region NHB, a p-type base region (impurity region) PB is formed. In the p-type base region PB, an n-type emitter region (impurity region) NE having an impurity concentration higher than that of the hole barrier region NHB is formed.

[0025] In the inactive cell region IAC, in the semiconductor layer ND between a pair of gate electrodes GE2, a hole barrier region NHB is formed. Also, in the semiconductor layer ND between the gate electrode GE1 and the gate electrode GE2, a p-type floating region (impurity region) PF is formed. In the floating region PF, a p-type base region PB having an impurity concentration higher than that of the floating region PF is formed. The floating region PF is preferably formed to a position deeper than the bottom of the trench TR in order to enhance the high breakdown voltage characteristics, and more preferably formed so as to cover the bottom of the trench TR.

[0026] An interlayer insulating film IL is formed on the semiconductor layer ND. In the active cell AC, the contact hole CH penetrates the interlayer insulating film IL and the emitter region NE and reaches the base region PB. The contact hole CH is formed so as to be in contact with the emitter region NE and the base region PB. The plug PG fills the inside of the contact hole CH and is electrically connected to the emitter region NE and the base region PB. The configuration of the contact hole CH and the plug PG in the inactive cell IAC is substantially the same as that of the active cell AC except that the emitter region NE is absent.

[0027] Around the bottom of the contact hole CH, a p-type high-concentration diffusion region (impurity region) PR having an impurity concentration higher than that of the base region PB is formed. The high-concentration diffusion region PR is provided to reduce the contact resistance with the plug PG and to prevent latch-up.

[0028] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to an emitter region NE, a base region PB, and a high-concentration diffusion region PR via a plug PG, and supplies an emitter potential to these regions. Although not shown here, a gate wiring GW formed in the same process as the emitter electrode EE is also formed on the interlayer insulating film IL. Such an emitter electrode EE and a gate wiring GW are composed of, for example, a TiW film and an aluminum film formed on the TiW film. The aluminum film is a conductor film of the emitter electrode EE and the gate wiring, and is sufficiently thicker than the TiW film.

[0029] FIG. 3 is a cross-sectional view of a main part corresponding to the region 2A in FIG. 1. The region 2A is a semiconductor element formation region different from the region in the semiconductor substrate SUB where an IGBT (such as a trench TR) is formed. In FIG. 3, for example, a resistance element 10 is shown as a semiconductor element formed in the region 2A. The resistance element 10 is composed of a conductive film formed on a semiconductor layer ND with a gate insulating film GI interposed therebetween. Such a conductive film is composed of the same layer as the gate electrodes GE1 and GE2, and is, for example, a polycrystalline silicon film into which n-type impurities are introduced.

[0030] Although not shown in detail, in the region 2A, not only the resistance element 10 but also other semiconductor elements such as a pn diode are formed. These resistance elements 10 and other semiconductor elements are electrically connected to a gate wiring GW (gate pad GP) via a plug PG, and constitute a protection circuit for protecting the semiconductor device 100 from a surge voltage or the like applied to the gate pad GP.

[0031] In Embodiment 1, the interlayer insulating film IL includes an insulating film IF1 formed on the semiconductor layer ND and an insulating film IF2 formed on the insulating film IF1. The insulating film IF1 is a silicon oxide film containing no impurities and is a thermal oxide film formed by a thermal oxidation method. Even if the insulating film IF1 contains impurities, the impurity concentration is very low and lower than the impurity concentration of the impurities contained in the PSG film or the BPSG film. The insulating film IF2 is a silicon oxide film containing boron and phosphorus and is a BPSG film.

[0032] The phosphorus contained in the insulating film IF2 plays a role of fixing (gettering) Na ions that deteriorate the characteristics of the semiconductor element. The boron contained in the insulating film IF2 plays a role of lowering the melting point of the insulating film IF2, making the insulating film IF2 easily melt by heat treatment. Since the softening point of the insulating film IF2 is lower than the softening point of the PSG film, the upper surface of the insulating film IF2 is flattened by performing a reflow process.

[0033] Therefore, by increasing the thickness of the insulating film IF2 and making the insulating film IF2 the main film of the interlayer insulating film IL, even if a step occurs between each region of the semiconductor substrate SUB, it becomes easier to keep the upper surface of the interlayer insulating film IL flat. For example, a step is likely to occur during the formation of the insulating film IF2 between the region 2A and the region 1A as shown in FIG. 3. (Refer to FIGS. 10 and 11 described later.)

[0034] On the other hand, if there is no insulating film IF1, phosphorus diffusion from the insulating film IF2 to the semiconductor layer ND will occur. The insulating film IF1 functions as a protective film for preventing phosphorus diffusion. In order to maintain such a function, the thickness of the insulating film IF1 is, for example, 100 to 500 Å. Also, the thickness of the insulating film IF2 is thicker than the thickness of the insulating film IF1 and is, for example, 8000 to 10000 Å.

[0035] The contact hole CH in Embodiment 1 includes a first contact hole CH1 and a second contact hole CH2 communicating with the first contact hole CH1. The first contact hole CH1 is formed in the semiconductor layer ND, penetrates the emitter region NE, and reaches the base region PB. The second contact hole CH2 is formed in the insulating film IF1 and the insulating film IF2.

[0036] The opening width of the second contact hole CH2 is larger than the opening width of the first contact hole CH1 and is larger than the opening width of the first contact hole CH1 by 600 Å or more. In other words, in plan view, the second contact hole CH2 encloses the first contact hole CH1.

[0037] Therefore, when forming the plug PG, the aspect ratio is improved, so that it becomes easier to satisfactorily embed the plug PG inside the contact hole CH. Also, since the opening width of the second contact hole CH2 is large, the upper surface of the emitter region NE is also exposed. Accordingly, the plug PG not only contacts the side surface of the emitter region NE but also contacts the upper surface of the emitter region NE inside the contact hole CH. Thereby, the contact resistance between the plug PG and the emitter region NE can be reduced.

[0038] The plug PG is composed of a laminated film of a barrier metal film BM and a conductive film CF. The barrier metal film is composed of, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film CF is composed of, for example, a tungsten film.

[0039] Inside the contact hole CH, a silicide film SI composed of a metal material contained in the barrier metal film BM and silicon is formed on the upper surface and the side surface of the emitter region NE, on the base region PB, and on the high-concentration diffusion region PR. More specifically, the silicide film SI is an alloy film of the titanium film contained in the barrier metal film BM and the silicon constituting the emitter region NE, the base region PB, and the high-concentration diffusion region PR, and is a titanium silicide film.

[0040] As a problem with the conventional technology, when the plug PG is formed, if the upper surface of the interlayer insulating film IL is not flat, a part of the conductive film CF (tungsten film) remains as a residue. Further, if the upper surface of the interlayer insulating film IL is not flat, the thickness of the interlayer insulating film IL will be different for each region, so it was necessary to individually form the contact hole CH for each region. Also, although it is conceivable to planarize the upper surface of the interlayer insulating film IL by polishing treatment using the CMP method, there was a problem that the manufacturing cost increased.

[0041] In contrast, in Embodiment 1, the thickness of the insulating film IF2 is increased, and the insulating film IF2 is used as the main film of the interlayer insulating film IL. By performing a reflow process on the insulating film IF2 having a low softening point such as a BPSG film, the upper surface of the insulating film IF2 is planarized. Therefore, the problem of the generation of residues in the conductive film CF (tungsten film) and the problem of the necessity of individually forming the contact hole CH for each region can be solved. Therefore, the reliability of the semiconductor device can be improved. Also, since an expensive polishing process using the CMP method is not required, an increase in manufacturing cost can be suppressed. In addition, a manufacturing method with relatively high versatility that can be easily implemented in various fabs can be provided.

[0042] <Method of manufacturing a semiconductor device> Hereinafter, with reference to FIGS. 4 to 15, the method of manufacturing the semiconductor device 100 in Embodiment 1 will be described. In the following, mainly the region 1A will be described, but the region 2A will also be described as necessary.

[0043] As shown in FIG. 4, first, a semiconductor substrate SUB having an n-type semiconductor layer ND is prepared. The semiconductor layer ND is formed by growing an epitaxial layer on the semiconductor substrate SUB by an epitaxial growth method after preparing a p-type semiconductor substrate SUB. Alternatively, a semiconductor substrate SUB into which an n-type impurity has been introduced in advance can be prepared and used as the n-type semiconductor layer ND. Next, an n-type hole barrier region NHB and a p-type floating region PF are formed in the semiconductor layer ND by photolithography and ion implantation methods.

[0044] As shown in FIG. 5, first, an insulating film made of, for example, a silicon oxide film is formed on the semiconductor layer ND, and a hard mask is formed by patterning the insulating film by photolithography and dry etching processes. Next, an anisotropic etching process is performed on the semiconductor layer ND using the hard mask as a mask to form a trench TR in the semiconductor layer ND. Thereafter, the hard mask is removed by a wet etching process or the like.

[0045] As shown in FIG. 6, first, the semiconductor substrate SUB is heat-treated at, for example, 1000 to 1200° C. to diffuse the impurities contained in the hole barrier region NHB and the floating region PF. By this heat treatment, the hole barrier region NHB diffuses to near the bottom of the trench TR, and the floating region PF diffuses to a position deeper than the bottom of the trench TR so as to cover the bottom of the trench TR.

[0046] Next, a gate insulating film GI is formed inside the trench TR and on the semiconductor layer ND by performing a thermal oxidation process on the semiconductor layer ND. Next, a conductive film PL such as a polycrystalline silicon film into which an n-type impurity has been introduced is formed on the gate insulating film GI by, for example, a CVD method so as to fill the inside of the trench TR. The thickness of the gate insulating film GI is, for example, 1000 Å.

[0047] Although not shown here, a gate insulating film GI is also formed on the semiconductor layer ND in the region 2A, and a conductive film PL is formed on the gate insulating film GI. The thickness of the conductive film PL in the region 2A is, for example, 3000 to 6000 Å.

[0048] As shown in FIG. 7, first, the conductive film PL formed outside the trench TR is removed by dry etching. The conductive film PL formed inside the trench TR remains as the gate electrodes GE1 and GE2. Next, the gate insulating film GI formed outside the trench TR is removed by isotropic etching or anisotropic etching.

[0049] The dry etching process of the conductive film PL is performed using a resist pattern having a pattern that opens the region 1A and covers a part of the region 2A. Thereby, the conductive film PL in the region 2A is patterned, and the resistance element 10 is formed. (See FIG. 10 described later.)

[0050] As shown in FIG. 8, first, an insulating film IF1 made of a thermal oxide film is formed on the semiconductor layer ND by, for example, a thermal oxidation method. The thickness of the insulating film IF1 is thinner than the thickness of the gate insulating film GI and is less than or equal to half of the thickness of the gate insulating film GI, for example, 100 to 500 Å. By removing the thick gate insulating film GI on the semiconductor layer ND and reforming the thin insulating film IF1 on the semiconductor layer ND, it becomes easier to form the second contact hole CH2 in a later process.

[0051] Next, using the insulating film IF1 as a through film, a p-type base region PB is formed in the semiconductor layer ND (floating region PF and hole barrier region NHB) by photolithography and ion implantation. Next, an n-type emitter region NE is formed on the surface of the base region PB in the active cell region AC by photolithography and ion implantation.

[0052] Note that the ion implantation of the base region PB is performed using boron, with an energy of 50 to 300 keV and a dose of 1×10 13 cm 2 under the conditions specified. Thereafter, a heat treatment is performed, for example, at 1000 °C for 100 to 200 minutes, to diffuse the impurities contained in the base region PB. The ion implantation of the emitter region NE is performed using arsenic or phosphorus, or both, with an energy of 100 keV and a dose of 1×10 15 cm 2 under the conditions specified. Thereafter, a heat treatment is performed, for example, at 950 °C for 30 seconds, to activate the impurities contained in each impurity region.

[0053] As shown in FIG. 9, an insulating film IF2 is formed on the insulating film IF1 by, for example, the CVD method. The insulating film IF2 is a silicon oxide film containing boron and phosphorus, and is a BPSG film. The insulating film IF1 and the insulating film IF2 each constitute a part of the interlayer insulating film IL. The thickness of the insulating film IF2 is greater than the thickness of the insulating film IF1, and is, for example, 6000 to 10000 Å.

[0054] Next, a heat treatment (reflow treatment) is performed on the insulating film IF2, for example, at 900 to 950 °C for 30 minutes. By this reflow treatment, the insulating film IF2 softens and the upper surface of the insulating film IF2 is planarized. For example, the upper surface of the insulating film IF2 after the reflow treatment is more planarized than the upper surface of the insulating film IF2 before the reflow treatment.

[0055] FIGS. 10 and 11 show the state of the insulating film IF2 before and after the reflow treatment. As shown in FIG. 10, before the reflow treatment, a step is generated on the upper surface of the insulating film IF2 between region 1A and region 2A. However, as shown in FIG. 11, by performing the reflow treatment, the upper surface of the insulating film IF2 is planarized. Thus, in Embodiment 1, since an expensive polishing process by the CMP method is not performed, an increase in manufacturing cost can be suppressed.

[0056] Here, a resistive element 10 is formed in the region 2A, and the insulating film IF2 is formed so as to cover the resistive element 10. After the reflow process, since the thickness of the insulating film IF2 formed on the resistive element 10 becomes relatively thin, it is necessary to adjust the thickness of the insulating film IF2 so that the resistive element 10 is not exposed after the reflow process. Therefore, before the reflow process, the thickness of the insulating film IF2 formed on the resistive element 10 is preferably thicker than the thickness of the resistive element 10, and is preferably about twice the thickness of the resistive element 10.

[0057] As shown in FIG. 12, a first contact hole CH1 is formed in the insulating film IF2, the insulating film IF1, the emitter region NE, and the base region PB by photolithography and dry etching.

[0058] Next, a p-type body region PR is formed at the bottom of the contact hole CH1 by photolithography and ion implantation. Thereafter, a heat treatment for activating each impurity region is performed. The ion implantation of the body region PR is performed using boron difluoride, with an energy of 50 to 100 keV and a dose of 1×10 15 cm 2 under the conditions described above. Thereafter, a heat treatment is performed, for example, at 950°C for 30 seconds to activate the impurities contained in each impurity region.

[0059] As shown in FIG. 13, the insulating films IF2 and IF1 are recessed by performing an isotropic etching process on the insulating films IF2 and IF1. For this isotropic etching process, an aqueous solution containing, for example, hydrofluoric acid is used. Thereby, a second contact hole CH2 is formed in the insulating films IF2 and IF1. The opening width of the second contact hole CH2 is larger than the opening width of the first contact hole CH1, and is in communication with the first contact hole CH1.

[0060] By the steps of FIGS. 12 and 13, in the active cell AC, a contact hole CH is formed that penetrates the interlayer insulating film IL and the emitter region NE and reaches the base region PB. Also in the inactive cell IAC, a contact hole CH is formed that penetrates the interlayer insulating film IL and reaches the base region PB.

[0061] Note that the recession amounts of the insulating film IF2 and the insulating film IF1 by the isotropic etching process are preferably 300 Å or more. As a result, the opening width of the second contact hole CH2 becomes larger than the opening width of the first contact hole CH1 and becomes 600 Å or more larger than the opening width of the first contact hole CH1.

[0062] Incidentally, since the insulating film IF2 is a film containing boron and phosphorus, in the above isotropic etching process, the etching rate of the insulating film IF2 is different from the etching rate of the insulating film IF1 and is faster than the etching rate of the insulating film IF1. Therefore, if the thickness of the insulating film IF1 is too thick, the insulating film IF1 may not be completely removed and may remain, and the upper surface of the emitter region NE may not be exposed.

[0063] As shown in FIG. 14, as the insulating film IF2 is etched, the upper surface of the insulating film IF1 is exposed. Then, the insulating film IF1 is etched from above and laterally as indicated by the arrow in FIG. 14. By appropriately setting the thickness of the insulating film IF1, the insulating film IF1 can be removed by the isotropic etching process. In this way, the difference between the etching rate of the insulating film IF2 and the etching rate of the insulating film IF1 can be effectively reduced.

[0064] Instead of the insulating film IF1, it is also conceivable to leave the gate insulating film GI on the semiconductor layer ND outside the trench TR. However, usually, in a device driven at a high voltage such as an IGBT, the thickness of the gate insulating film GI is set to be as thick as 1000 Å. Therefore, it becomes difficult to completely remove the gate insulating film GI outside the trench TR by the isotropic etching process. In Embodiment 1, by using the insulating film IF1 having a thickness thinner than that of the gate insulating film GI (for example, 100 to 500 Å), it becomes easier to expose the upper surface of the emitter region NE when forming the second contact hole CH2.

[0065] FIG. 15 shows the manufacturing process following FIG. 13. As shown in FIG. 15, first, a barrier metal film BM is formed on the inside of the contact hole CH and on the interlayer insulating film IL. For example, a titanium film can be formed on the inside of the contact hole CH and on the interlayer insulating film IL by a sputtering method, and a titanium nitride film can be formed on the titanium film by a sputtering method, for example, to form the barrier metal film BM.

[0066] Next, by performing a heat treatment on the barrier metal film BM, a silicide film SI is formed on the upper surface and side surface of the emitter region NE, on the base region PB, and on the high-concentration diffusion region PR inside the contact hole CH. The silicide film SI is an alloy film of a metal material (titanium film) contained in the barrier metal film BM and silicon, and is a titanium silicide film.

[0067] Next, a conductive film CF made of, for example, a tungsten film is formed on the barrier metal film BM so as to fill the inside of the contact hole CH, for example, by a CVD method.

[0068] As shown in FIG. 16, first, the conductive film CF and the barrier metal film BM formed outside the contact hole CH are removed by a dry etching process. Thereby, a plug PG that is embedded inside the contact hole CH and electrically connected to the emitter region NE and the base region PB is formed.

[0069] Here, although the conductive film CF was also formed on the insulating film IF2, since the upper surface of the insulating film IF2 is planarized, it has become easier to remove the conductive film CF. Therefore, it is possible to suppress the problem of the generation of residues of the conductive film CF on the insulating film IF2.

[0070] Next, for example, by a sputtering method, a TiW film is formed on the interlayer insulating film IL, and for example, by a sputtering method, an aluminum film is formed on the above TiW film. Next, by a photolithography method and a dry etching process, the above TiW film and the above aluminum film are patterned to form the emitter electrode EE. The emitter electrode EE is electrically connected to the emitter region NE and the base region PB via the plug PG.

[0071] Although not shown here, in the same process as FIGS. 12 and 13, a contact hole for the gate electrode reaching a part of the gate electrode GE is also formed. Also, in the same process as FIGS. 15 and 16, a plug is formed inside the contact hole for the gate electrode, and a gate wiring GW in the same layer as the emitter electrode EE is formed.

[0072] In the region 2A, in the same process as FIGS. 12 and 13, a contact hole CH3 is formed on the resistor element 10, and in the same process as FIGS. 15 and 16, a plug PG is formed inside the contact hole CH3. Also, the opening width of the contact hole CH3 in the region 2A does not need to be the same as the opening width of the contact hole CH2 in the region 1A and can be freely set.

[0073] Here, if we attempt to simultaneously form contact holes in regions 2A and 1A in a state as shown in FIG. 10, since there is a step on the upper surface of the insulating film IF2, focus misalignment is likely to occur during the development of the resist pattern for forming the contact holes. Therefore, it becomes necessary to form the contact holes individually for each region. However, in Embodiment 1, since the upper surface of the insulating film IF2 is planarized, such a problem does not exist, and contact holes can be formed in regions 2A and 1A simultaneously.

[0074] Thereafter, a field stop region NS, a collector region PC, and a collector electrode CE are formed on the back surface side of the semiconductor substrate SUB. First, a polishing process is performed on the back surface of the semiconductor substrate SUB to reduce the thickness of the semiconductor substrate SUB. Next, an n-type field stop region NS and a p-type collector region PC are formed by performing ion implantation from the back surface side of the semiconductor substrate SUB. Next, a collector electrode CE made of a metal film such as a titanium nitride film is formed on the surface of the collector region PC exposed on the back surface side of the semiconductor substrate SUB, for example, by sputtering.

[0075] As described above, the structures of FIGS. 2 and 3 are obtained, and the semiconductor device 100 in Embodiment 1 is manufactured.

[0076] (Embodiment 2) Hereinafter, the semiconductor device 100 in Embodiment 2 will be described with reference to FIG. 17. In the following, mainly the differences from Embodiment 1 will be described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0077] As shown in FIG. 17, the interlayer insulating film IL in Embodiment 2 further includes an insulating film IF3 between the insulating film IF1 and the insulating film IF2. The insulating film IF3 is a silicon oxide film containing phosphorus and is a PSG film. Also, the insulating film IF1 in Embodiment 2 is a TEOS (Tetra Ethoxy Silane) film formed by CVD method.

[0078] In Embodiment 2, the thickness of the insulating film IF1 is, for example, 60 to 100 Å, and the thickness of the insulating film IF3 is, for example, 1000 to 2000 Å. Also, the thickness of the insulating film IF2 is greater than the thicknesses of the insulating film IF1 and the insulating film IF3 respectively, and is, for example, 6000 to 8000 Å.

[0079] To form such an insulating film IF3, a step of forming the insulating film IF3 is performed between the step of forming the insulating film IF1 in FIG. 8 and the step of forming the insulating film IF2 in FIG. 9. That is, the insulating film IF3 is formed on the insulating film IF1, for example, by the CVD method. Thereafter, the insulating film IF2 is formed on the insulating film IF3.

[0080] Also, the isotropic etching process in FIG. 13 is also performed on the insulating film IF3. As a result, the second contact hole CH2 is also formed in the insulating film IF3.

[0081] Even in Embodiment 2, since the thickness of the insulating film IF2 is increased and the insulating film IF2 is made the main film of the interlayer insulating film IL, the same effects as in Embodiment 1 can be obtained in Embodiment 2.

[0082] Also, in Embodiment 1, the insulating film IF1 was formed by the thermal oxidation method. Therefore, near the upper part of the trench TR, the gate insulating film GI is likely to be re-oxidized and thickened. Then, a problem that variations occur in the threshold voltage is likely to occur. On the other hand, in Embodiment 2, the insulating film IF1 is formed by the CVD method. For this reason, Embodiment 2 has the advantage that the above problem is less likely to occur.

[0083] On the other hand, the quality of the CVD film is more hydrophobic than that of the thermal oxide film. Therefore, if the thickness of the insulating film IF1 is about 60 to 100 Å, the function of preventing the diffusion of phosphorus from the insulating film IF2 may not be fully exerted. Therefore, by forming the insulating film IF3 between the insulating film IF1 and the insulating film IF2, the diffusion of phosphorus can be prevented. Note that the diffusion of phosphorus from the insulating film IF3 (PSG film) is less than that from the insulating film IF2 (BPSG film), so even a thin insulating film IF1 can prevent the diffusion of phosphorus from the insulating film IF3.

[0084] (Embodiment 3) Hereinafter, the semiconductor device 100 in Embodiment 3 will be described with reference to FIG. 18. In the following, mainly the differences from Embodiment 1 will be described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0085] As shown in FIG. 18, in Embodiment 3, the insulating film IF1 is a part of the gate insulating film GI. And the thickness of the insulating film IF1 formed on the semiconductor layer ND outside the trench TR is thinner than the thickness of the gate insulating film GI formed inside the trench TR. Also in Embodiment 3, the thickness of the insulating film IF1 is 100 to 500 Å.

[0086] To form such an insulating film IF1, in the process of FIG. 7, an isotropic etching process is performed on the gate insulating film GI formed on the semiconductor layer ND. In Embodiment 1, the gate insulating film GI was completely removed, but in Embodiment 3, the thickness of the gate insulating film GI is thinned and the gate insulating film GI is left remaining. This remaining gate insulating film GI becomes the insulating film IF1.

[0087] In Embodiment 3, compared with Embodiment 1, since it is not necessary to re-form the insulating film IF1, the manufacturing process can be simplified. Therefore, Embodiment 3 is superior to Embodiment 1 in that the manufacturing cost can be suppressed.

[0088] On the other hand, adjusting the thickness of the insulating film IF1 by isotropic etching treatment is more difficult than forming the insulating film IF1 again. That is, variations are likely to occur in the thickness of the insulating film IF1. If there are variations in the thickness of the insulating film IF1, variations may occur in the implantation depth of impurities during subsequent ion implantation, or variations may occur in the opening width of the second contact hole when forming the second contact hole. Therefore, Embodiment 1 is superior to Embodiment 3 in terms of improving the accuracy of the thickness of the insulating film IF1.

[0089] (Embodiment 4) Hereinafter, the semiconductor device 100 in Embodiment 4 will be described with reference to FIG. 19. In the following, the differences from Embodiment 1 will be mainly described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0090] In Embodiment 1, in the process of FIG. 8, after forming the insulating film IF1, ion implantation was performed using the insulating film IF1 as a through film to form the base region PB and the emitter region NE.

[0091] In Embodiment 4, as shown in FIG. 19, before ion implantation, an insulating film IF4 made of a silicon oxide film is formed on the semiconductor layer ND by, for example, thermal oxidation or CVD. Next, ion implantation is performed using this insulating film IF4 as a through film. Next, after ion implantation, the insulating film IF4 is removed by isotropic etching treatment. Next, an insulating film IF1 is formed on the semiconductor layer ND. The subsequent steps are the same as those in Embodiment 1.

[0092] When ion implantation is performed using the insulating film IF1 as a through film as in Embodiment 1, the film quality of the insulating film IF1 may deteriorate, and the function of preventing the diffusion of phosphorus from the insulating film IF2 may decrease. Therefore, by using an insulating film IF4 different from the insulating film IF1 during ion implantation as in Embodiment 4, deterioration of the film quality of the insulating film IF1 can be prevented.

[0093] Note that the technology of Embodiment 4 can also be applied to Embodiment 2.

[0094] As described above, the present invention has been specifically described based on the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the gist thereof.

[0095] For example, in the above embodiment, an IGBT is exemplified as the device formed in the region 1A. However, the technology disclosed in the above embodiment is not limited to the IGBT, and can also be applied to a power MOSFET having a vertical trench gate.

Description of Reference Numerals

[0096] 100 Semiconductor device 10 Resistor element 1A Region (cell region) 2A Region (semiconductor element formation region) AC Active cell BM Barrier metal film CE Collector electrode CF Conductive film CH Contact hole CH1 First contact hole CH2 Second contact hole EE Emitter electrode EP Emitter pad GE1, GE2 Gate electrode GI Gate insulating film GP Gate pad GW Gate wiring IAC Inactive cell IF1~IF4 Insulating film IL Interlayer insulating film ND Semiconductor layer (drift region) NE Emitter region NHB Hole barrier region NS Field stop region PB Base region PC Collector region PF Floating region PG Plug PL Conductive film PR High-Concentration Diffusion Region Si Silicide Film SUB Semiconductor Substrate TR Trench

Claims

1. A semiconductor substrate having a semiconductor layer of a first conductivity type, a first impurity region of a second conductivity type, which is formed in the semiconductor layer and has a conductivity type opposite to that of the first conductivity type, a second impurity region of the first conductivity type, which is formed in the first impurity region, a trench that penetrates the first impurity region and the second impurity region and reaches the semiconductor layer, a gate insulating film formed inside the trench, a gate electrode formed on the gate insulating film so as to fill the inside of the trench, an interlayer insulating film formed on the semiconductor layer, a contact hole that penetrates the interlayer insulating film and the second impurity region and reaches the first impurity region, a plug that fills the inside of the contact hole and is electrically connected to the first impurity region and the second impurity region, comprising: the interlayer insulating film includes a first insulating film formed on the semiconductor layer and a second insulating film formed on the first insulating film, the first insulating film is a silicon oxide film, the second insulating film is a BPSG film, the thickness of the second insulating film is greater than the thickness of the first insulating film, the contact hole includes a first contact hole that penetrates the second impurity region and reaches the first impurity region, and a second contact hole that is formed in the first insulating film and the second insulating film and communicates with the first contact hole, the opening width of the second contact hole is larger than the opening width of the first contact hole, the first insulating film is a part of the gate insulating film, a semiconductor device, wherein the thickness of the first insulating film formed on the semiconductor layer outside the trench is smaller than the thickness of the gate insulating film formed inside the trench.

2. The semiconductor device according to claim 1, wherein the thickness of the first insulating film is equal to or less than half of the thickness of the gate insulating film.

3. The semiconductor device according to claim 1, wherein the interlayer insulating film further includes a third insulating film between the first insulating film and the second insulating film, the third insulating film is a PSG film, the thickness of the second insulating film is greater than the thickness of the third insulating film, and the second contact hole is also formed in the third insulating film.

4. The semiconductor device according to claim 1, wherein the plug is formed of a laminated film of a barrier metal film and a conductive film. A semiconductor device in which, inside the contact hole, a silicide film, which is an alloy film of a metal material contained in the barrier metal film and silicon, is formed on the upper surface and the side surface of the first impurity region.

5. (a) A step of preparing a semiconductor substrate having a semiconductor layer of a first conductivity type; (b) A step of forming a trench in the semiconductor layer; (c) A step of forming a gate insulating film inside the trench; (d) A step of forming a gate electrode on the gate insulating film so as to fill the inside of the trench; (e) A step of forming a first insulating film on the semiconductor layer; (f) A step of forming a first impurity region of a second conductivity type, which is a conductivity type opposite to the first conductivity type, in the semiconductor layer; (g) A step of forming a second impurity region of the first conductivity type in the first impurity region; (h) A step of forming an interlayer insulating film including the second insulating film and the first insulating film on the semiconductor layer by forming a second insulating film having a thickness greater than the thickness of the first insulating film on the first insulating film; (i) A step of forming a contact hole that penetrates the interlayer insulating film and the second impurity region and reaches the first impurity region; (j) A step of forming a plug electrically connected to the first impurity region and the second impurity region so as to fill the inside of the contact hole; comprising: The first insulating film is a silicon oxide film; The second insulating film is a BPSG film; The step (i) is: (i1) A step of forming a first contact hole in the second insulating film, the first insulating film, the second impurity region, and the first impurity region; (i2) After the step (i1), an isotropic etching process is performed on the second insulating film and the first insulating film to form a second contact hole in the second insulating film and the first insulating film, the opening width of which is larger than the opening width of the first contact hole and which communicates with the first contact hole; having: In the step (c), the gate insulating film is also formed on the semiconductor layer outside the trench; In the step (e), the first insulating film is formed by performing an isotropic etching process on the gate insulating film formed on the semiconductor layer outside the trench. A method of manufacturing a semiconductor device, wherein the thickness of the first insulating film formed on the semiconductor layer outside the trench is smaller than the thickness of the gate insulating film formed inside the trench. **Claim 6** In the method of manufacturing a semiconductor device according to claim 5, A method of manufacturing a semiconductor device, wherein the thickness of the first insulating film is equal to or less than half of the thickness of the gate insulating film. **Claim 7** In the method of manufacturing a semiconductor device according to claim 5, A method of manufacturing a semiconductor device, wherein the gate insulating film is formed by a thermal oxidation method. **Claim 8** In the method of manufacturing a semiconductor device according to claim 5, In the step (h), after forming the second insulating film by CVD method, a heat treatment is performed on the second insulating film, A method of manufacturing a semiconductor device, wherein the upper surface of the second insulating film after the heat treatment is flatter than the upper surface of the second insulating film before the heat treatment. **Claim 9** In the method of manufacturing a semiconductor device according to claim 8, In the step (d), in a semiconductor element formation region different from the region where the trench is formed in the semiconductor substrate, a first conductive film of the same layer as the gate electrode is formed on the semiconductor layer, In the step (h), in the semiconductor element formation region, the second insulating film is formed so as to cover the first conductive film, A method of manufacturing a semiconductor device, wherein the thickness of the second insulating film formed on the first conductive film before the heat treatment is greater than the thickness of the first conductive film. **Claim 10** In the method of manufacturing a semiconductor device according to claim 5, The step (h) further includes a step of forming a third insulating film made of a PSG film on the first insulating film before forming the second insulating film, the thickness of the third insulating film being smaller than the thickness of the second insulating film, The second insulating film is formed on the third insulating film, The interlayer insulating film includes the first insulating film, the second insulating film, and the third insulating film, In the step (i1), the first contact hole is also formed in the third insulating film, In the step (i2), the isotropic etching treatment is also performed on the third insulating film, and the second contact hole is also formed in the third insulating film. A method of manufacturing a semiconductor device. **Claim 11** In the method of manufacturing a semiconductor device according to claim 5, The step (j) is (j1) A step of forming a barrier metal film inside the contact hole Step (j2): By performing a heat treatment on the barrier metal film, a silicide film, which is an alloy film of the metal material contained in the barrier metal film and silicon, is formed on the upper surface and the side surface of the first impurity region inside the contact hole. Step (j3): A second conductive film is formed on the barrier metal film so as to fill the inside of the contact hole. A method for manufacturing a semiconductor device, comprising the above steps.

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