Semiconductor device

Abstract

Provided is a semiconductor device with little variation in properties. This semiconductor device comprises: an oxide; a first conductor and a second conductor on the oxide; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator on the first insulator and the second insulator; a fourth insulator on the third insulator; a fifth insulator which is on the oxide and disposed between the first conductor and the second conductor; a sixth insulator on the fifth insulator; and a third conductor on the sixth insulator. The third conductor has a region that overlaps the oxide. The fifth insulator has a region that contacts each of the oxide, the first conductor, the second conductor, and the first to fourth insulators. The fifth insulator contains nitrogen, oxygen, and silicon.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device. Another aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, the semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. may be said to have semiconductor devices.

[0003] One aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Background Art

[0004] In recent years, the development of semiconductor devices has been advanced and they are mainly used in LSIs, CPUs, memories, etc. A CPU is an aggregate of semiconductor elements obtained by processing a semiconductor wafer into a chip (at least a transistor and a memory) and having electrodes as connection terminals formed thereon.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on a circuit board, for example, a printed wiring board, and used as one of the components of various electronic devices.

[0006] In addition, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] In addition, a transistor using an oxide semiconductor is known to have an extremely small leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that applies the characteristic of a small leakage current of a transistor using an oxide semiconductor. Further, for example, Patent Document 2 discloses a memory device that can hold stored contents for a long time by applying the characteristic of a small leakage current of a transistor using an oxide semiconductor.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integration of integrated circuits has been increasing. In addition, improvement in the productivity of semiconductor devices including integrated circuits is required.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0010] One aspect of the present invention aims to provide a semiconductor device with little variation in transistor characteristics. Or, one aspect of the present invention aims to provide a semiconductor device with good reliability. Or, one aspect of the present invention aims to provide a semiconductor device having good electrical characteristics. Or, one aspect of the present invention aims to provide a semiconductor device with a large on-current. Or, one aspect of the present invention aims to provide a semiconductor device capable of miniaturization or high integration. Or, one aspect of the present invention aims to provide a low-power semiconductor device.

[0011] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0012] One aspect of the present invention is to form a first insulator, form an oxide film on the first insulator, perform a first heat treatment, sequentially form a first conductive film and a first insulating film on the oxide film, process the oxide film, the first conductive film, and the first insulating film into an island shape to form an oxide, a conductive layer, and an insulating layer, form a second insulator on the first insulator, the oxide, the conductive layer, and the insulating layer, form a third insulator on the second insulator, form an opening reaching the oxide in the conductive layer, the insulating layer, the second insulator, and the third insulator, and by forming the opening, a first conductor and a second conductor are formed from the conductive layer, and a fourth insulator and a fifth insulator are formed from the insulating layer. Then, perform a second heat treatment, form a second insulating film on the third insulator and on the opening, form a third insulating film on the second insulating film, perform a microwave treatment, form a second conductive film on the third insulating film, and perform a CMP process until the upper surface of the third insulator is exposed on the second insulating film, the third insulating film, and the second conductive film to form a sixth insulator, a seventh insulator, and a third conductor. The second insulating film is formed by a PEALD method using a gas containing silicon and no hydrocarbon and an oxidizing gas, which is a method for manufacturing a semiconductor device.

[0013] Also, in the above, the film formation by the PEALD method includes a first step of introducing a gas containing silicon and no hydrocarbon and an oxidizing gas into the reaction chamber, a second step of stopping the introduction of the gas containing silicon and no hydrocarbon and purging the gas containing silicon and no hydrocarbon remaining in the reaction chamber, a third step of applying high-frequency power to generate plasma by the oxidizing gas, and a fourth step of stopping the application of high-frequency power. The first step to the fourth step are defined as one cycle, and it is preferable to perform one cycle to 500 cycles.

[0014] In addition, in the above, the gas containing silicon and not containing hydrocarbons contains any one or more selected from SiH4, Si2H6, SiF4, SiCl4, SiBr4, SiH2Cl2, and SiH2I2, and the oxidizing gas preferably contains any one or more selected from O2, O3, N2O, NO2, and H2O.

[0015] In addition, in the above, the gas containing silicon and not containing hydrocarbons is preferably SiH4, and the oxidizing gas is preferably N2O.

[0016] In addition, in the above, the pressure in the reaction chamber in the first step is preferably 400 Pa or more and 1000 Pa or less.

[0017] In addition, in the above, the temperature of the first heat treatment is preferably higher than the temperature of the second heat treatment.

[0018] In addition, one aspect of the present invention includes an oxide, a first conductor and a second conductor on the oxide, a first insulator on the first conductor, a second insulator on the second conductor, a third insulator on the first insulator and on the second insulator, a fourth insulator on the third insulator, a fifth insulator on the oxide and disposed between the first conductor and the second conductor, a sixth insulator on the fifth insulator, and a third conductor on the sixth insulator. The third conductor has a region overlapping with the oxide, the fifth insulator has regions respectively in contact with the oxide, the first conductor, the second conductor, and the first insulator to the fourth insulator, and the fifth insulator contains nitrogen, oxygen, and silicon, and is a semiconductor device.

[0019] In addition, in the above, the sixth insulator preferably contains hafnium.

[0020] In addition, in the above, the film thickness of the sixth insulator is preferably 0.5 nm or more and 5.0 nm or less.

[0021] Further, in the above, it is preferable that the film thickness of the fifth insulator is 0.5 nm or more and 15.0 nm or less.

[0022] Further, in the above, it is preferable that the oxide is an oxide semiconductor containing any one or more selected from In, Ga, or Zn.

Advantages of the Invention

[0023] According to one aspect of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Or, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Or, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Or, according to one aspect of the present invention, a low-power consumption semiconductor device can be provided.

[0024] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be naturally apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0025] FIG. 1A is a top view of a semiconductor device according to one aspect of the present invention. FIGS. 1B to 1D are cross-sectional views of a semiconductor device according to one aspect of the present invention. FIG. 2A is a top view of a semiconductor device according to one aspect of the present invention. FIGS. 2B to 2D are cross-sectional views of a semiconductor device according to one aspect of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. FIG. 4A is a diagram for explaining the classification of the crystal structure of IGZO. FIG. 4B is a diagram for explaining the XRD spectrum of the CAAC-IGZO film. FIG. 4C is a diagram for explaining the selected area electron diffraction pattern of the CAAC-IGZO film. FIG. 5 is a diagram for explaining a process flow which is one aspect of the present invention. FIGS. 6A and 6B are diagrams for explaining a film formation sequence which is one aspect of the present invention. FIG. 7A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 7B to 7D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 8A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 8B to 8D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 9A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 9B to 9D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 10A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 10B to 10D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 11A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 11B to 11D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 12A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 12B to 12D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 13A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 13B to 13D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 14A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 14B to 14D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 15A is a top view showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIGS. 15B to 15D are cross-sectional views showing a method of manufacturing a semiconductor device which is one aspect of the present invention. FIG. 16A is a top view showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIGS. 16B to 16D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 17A is a top view showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIGS. 17B to 17D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 18A is a top view showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIGS. 18B to 18D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 19A is a top view showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIGS. 19B to 19D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 20A is a top view showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIGS. 20B to 20D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 21A is a top view showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIGS. 21B to 21D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 22A is a top view showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIGS. 22B to 22D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 23 is a top view for explaining a microwave processing apparatus according to an aspect of the present invention. FIG. 24 is a cross-sectional view for explaining a microwave processing apparatus according to an aspect of the present invention. FIG. 25 is a cross-sectional view for explaining a microwave processing apparatus according to an aspect of the present invention. FIG. 26 is a cross-sectional view for explaining a microwave processing apparatus according to an aspect of the present invention. FIGS. 27A and 27B are cross-sectional views of a semiconductor device according to an aspect of the present invention. FIG. 28 is a cross-sectional view showing the configuration of a storage device according to an aspect of the present invention. FIG. 29 is a cross-sectional view showing the configuration of a storage device according to an aspect of the present invention. FIG. 30A is a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIG. 30B is a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIG. 31A is a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIG. 31B is a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIG. 32 is a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIG. 33 is a cross-sectional view of a semiconductor device according to an aspect of the present invention. FIGS. 34A and 34B are block diagrams showing a configuration example of a storage device according to an aspect of the present invention. FIGS. 35A to 35H are circuit diagrams showing a configuration example of a storage device according to an aspect of the present invention. FIGS. 36A and 36B are schematic diagrams of a semiconductor device according to an aspect of the present invention. FIGS. 37A and 37B are diagrams for explaining an example of an electronic component according to an aspect of the present invention. FIGS. 38A to 38E are schematic diagrams of a storage device according to an aspect of the present invention. FIGS. 39A to 39H are diagrams showing an electronic device according to an aspect of the present invention. FIG. 40 is a diagram for explaining the ALD Window according to the present embodiment. FIG. 41 is a diagram plotting the GPC at each substrate temperature according to the present embodiment. FIG. 42A is a STEM cross-sectional photograph according to the present embodiment. FIG. 42B is a diagram summarizing the film thickness measurement results.

MODE FOR CARRYING OUT THE INVENTION

[0026] Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different modes, and the forms and details thereof can be variously changed without departing from the spirit and scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0027] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may unintentionally become thinner due to processes such as etching, but this may not be reflected in the figures for ease of understanding. Also, in the drawings, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and repeated descriptions thereof may be omitted. Also, when referring to similar functions, the hatch patterns may be the same and may not be particularly labeled.

[0028] Also, particularly in top views (also referred to as "plan views"), perspective views, etc., for ease of understanding the invention, the description of some components may be omitted. Also, the description of some hidden lines, etc. may be omitted.

[0029] Also, in this specification, etc., ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third", etc. and described. Also, the ordinal numbers described in this specification, etc. may not match the ordinal numbers used to specify an aspect of the present invention.

[0030] Also, in this specification, etc., terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0031] For example, in this specification and the like, when it is explicitly described that X and Y are connected, it shall be disclosed in this specification and the like that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text shall also be regarded as disclosed in the figure or the text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0032] Also, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And it has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0033] Also, the functions of the source and the drain may be interchanged when transistors of different polarities are employed or when the direction of current changes in circuit operation. For this reason, in this specification and the like, the terms source and drain may be used interchangeably in some cases.

[0034] Note that the channel length refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be a single value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0035] Note that the channel width refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the length of the channel formation region in the vertical direction with respect to the channel length direction in the channel formation region. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to be a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0036] Note that in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may be different from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor where the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

[0037] In such a case, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0038] In this specification, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

[0039] Note that the semiconductor impurities refer to, for example, components other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main component of the oxide semiconductor, etc., such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Note that water may also function as an impurity. Also, for example, due to the incorporation of impurities, oxygen vacancies (V O : also referred to as oxygen vacancy) may be formed in the oxide semiconductor.

[0040] In addition, in this specification and the like, silicon oxynitride refers to a substance having a higher oxygen content than nitrogen in its composition. Further, silicon nitride oxide refers to a substance having a higher nitrogen content than oxygen in its composition. Similarly, aluminum oxynitride refers to a substance having a higher oxygen content than nitrogen in its composition. Further, aluminum nitride oxide refers to a substance having a higher nitrogen content than oxygen in its composition. Similarly, hafnium oxynitride refers to a substance having a higher oxygen content than nitrogen in its composition. Further, hafnium nitride oxide refers to a substance having a higher nitrogen content than oxygen in its composition.

[0041] In addition, in this specification and the like, the term "insulator" can be rephrased as an insulating film or an insulating layer. Also, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be rephrased as a semiconductor film or a semiconductor layer.

[0042] In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0043] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0044] In addition, in this specification and the like, "normally off" means that when no potential is applied to the gate or the gate is given a ground potential, the drain current per 1 μm of channel width flowing through the transistor is 1 × 10 -20 A or less at room temperature, 1 × 10 -18 A or less at 85°C, or 1 × 10 -16 A or less at 125°C.

[0045] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1A to 22D.

[0046] <Configuration Example of Semiconductor Device> The configuration of a semiconductor device having a transistor 200 will be described with reference to FIGS. 1A to 1D. FIGS. 1A to 1D are top views and cross-sectional views of a semiconductor device having a transistor 200. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 1A and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 1C is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 1A and is also a cross-sectional view in the channel width direction of the transistor 200. FIG. 1D is a cross-sectional view of the portion indicated by the dashed line A5 - A6 in FIG. 1A. Note that in the top view of FIG. 1A, some elements are omitted for clarity of the drawing.

[0047] A semiconductor device according to an aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 (insulator 282a and insulator 282b) on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, an insulator 284 on the insulator 283 and on the insulator 274, and an insulator 286 on the insulator 284. The insulators 212, 214, 280, 282, 283, 284, and 274 function as interlayer films. Further, it has conductors 240 (conductor 240a and conductor 240b) that are electrically connected to the transistor 200 and function as plugs. Note that insulators 241 (insulator 241a and insulator 241b) are provided in contact with side surfaces of the conductors 240 that function as plugs. Also, on the insulator 284 and on the conductors 240, conductors 246 (conductor 246a and conductor 246b) that are electrically connected to the conductors 240 and function as wirings are provided. Further, an insulator 286 is provided on the conductors 246 and on the insulator 284.

[0048] The insulator 283 is in contact with a part of the upper surface of the insulator 214, side surfaces of the insulator 216, side surfaces of the insulator 222, side surfaces of the insulator 272, side surfaces of the insulator 280, and side surfaces of the insulator 282.

[0049] An insulator 241a is provided in contact with the inner walls of the openings of the insulators 280, 282, 283, and 284. A first conductor of the conductor 240a is provided in contact with the side surface of the insulator 241a, and a second conductor of the conductor 240a is further provided inside. Also, an insulator 241b is provided in contact with the inner walls of the openings of the insulators 280, 282, 283, and 284. A first conductor of the conductor 240b is provided in contact with the side surface of the insulator 241b, and a second conductor of the conductor 240b is further provided inside. Here, the height of the upper surface of the conductor 240 can be made approximately the same as the height of the upper surface of the insulator 284 in the region overlapping with the conductor 246. Note that in the transistor 200, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the formation order for distinction.

[0050] [Transistor 200] As shown in FIGS. 1A to 1D, the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductor 205a, conductor 205b, and conductor 205c) disposed to be embedded in the insulator 214 and / or the insulator 216, an insulator 222 on the insulator 216 and on the conductors 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, oxides 243 (oxide 243a and oxide 243b) on the oxide 230b, a conductor 242a on the oxide 243a, an insulator 271a on the conductor 242a, a conductor 242b on the oxide 243b, an insulator 271b on the conductor 242b, an insulator 250a on the oxide 230b, an insulator 250b on the insulator 250a, conductors 260 (conductor 260a and conductor 260b) located on the insulator 250b and overlapping a part of the oxide 230b, and an insulator 272 disposed on the insulator 222, on the insulator 224, on the oxides 230 (oxide 230a and oxide 230b), on the oxides 243, on the conductors 242 (conductor 242a and conductor 242b), and on the insulators 271 (insulator 271a and insulator 271b). Here, as shown in FIGS. 1B and 1C, the upper surface of the conductor 260 is disposed substantially flush with the upper surface of the insulator 250 and the upper surface of the insulator 280. Also, the insulator 282 is in contact with the upper surfaces of the conductor 260, the insulator 250, and the insulator 280, respectively.

[0051] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. Also, the insulator 250a and the insulator 250b may be collectively referred to as the insulator 250. Also, the insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0052] The insulator 280 and the insulator 272 are provided with openings reaching the oxide 230b. The insulator 250 and the conductor 260 are disposed within the openings. Also, in the channel length direction of the transistor 200, the conductor 260 and the insulator 250 are provided between the insulator 271a, the conductor 242a, and the oxide 243a and between the insulator 271b, the conductor 242b, and the oxide 243b. The insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

[0053] The oxide 230 preferably has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By having the oxide 230a under the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed.

[0054] Note that, in the transistor 200, the oxide 230 is shown as having a structure in which two layers of the oxide 230a and the oxide 230b are stacked, but the present invention is not limited to this. For example, a single layer of the oxide 230b or a stacked structure of three or more layers may be provided, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0055] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. Also, the insulator 250 functions as a first gate insulator, and the insulators 222 and 224 function as second gate insulators. Further, the conductor 242a functions as one of a source or a drain, and the conductor 242b functions as the other of the source or the drain. Also, at least a part of the region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0056] Here, an enlarged view of the vicinity of the channel formation region in FIG. 1B is shown in FIG. 3. As shown in FIG. 3, the oxide 230b has a region 230bc that functions as the channel formation region of the transistor 200, and regions 230ba and 230bb that are provided so as to sandwich the region 230bc and function as a source region or a drain region. At least a part of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in the region between the conductor 242a and the conductor 242b. The region 230ba is provided to overlap with the conductor 242a, and the region 230bb is provided to overlap with the conductor 242b.

[0057] The region 230bc that functions as the channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 230ba and 230bb. Also, the regions 230ba and 230bb that function as the source region or the drain region are regions where the carrier concentration increases and the resistance is reduced due to a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, and metal elements. That is, the regions 230ba and 230bb are regions with a high carrier concentration and low resistance compared to the region 230bc.

[0058] Here, the carrier concentration of the region 230bc that functions as the channel formation region is preferably 18 cm -3 or less, more preferably 17 cm -3 less, even more preferably 16 cm -3 less, even more preferably 13 cm -3 less, and even more preferably 12 cm -3 less. Note that the lower limit value of the carrier concentration of the region 230bc that functions as the channel formation region is not particularly limited, but can be, for example, -9 cm -3 or the like.

[0059] Further, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than the carrier concentrations of regions 230ba and 230bb, and equal to or higher than the carrier concentration of region 230bc. That is, the region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in the junction region may be equal to or lower than the hydrogen concentrations of regions 230ba and 230bb, and equal to or higher than the hydrogen concentration of region 230bc. Also, the oxygen deficiency in the junction region may be equal to or less than the oxygen deficiencies of regions 230ba and 230bb, and equal to or more than the oxygen deficiency of region 230bc.

[0060] Note that in FIG. 3, an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b is shown, but the present invention is not limited thereto. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0061] Also, in oxide 230, it may be difficult to clearly detect the boundary of each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region are not limited to stepwise changes from region to region, and may continuously change within each region. That is, the closer the region is to the channel formation region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, may be.

[0062] For transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for oxide 230 (oxide 230a and oxide 230b) including the channel formation region.

[0063] In addition, as the metal oxide functioning as a semiconductor, it is preferable to use one having a band gap of 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0064] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Also, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0065] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for the oxide 230b is larger than the atomic ratio of In to element M in the metal oxide used for the oxide 230a.

[0066] By arranging the oxide 230a under the oxide 230b in this way, the diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b can be suppressed.

[0067] In addition, since the oxide 230a and the oxide 230b have a common element (as the main component) other than oxygen, the density of defect levels at the interface between the oxide 230a and the oxide 230b can be lowered. Since the density of defect levels at the interface between the oxide 230a and the oxide 230b can be lowered, the influence on carrier conduction due to interface scattering is small, and a high on-current can be obtained.

[0068] The oxide 230b preferably has crystallinity respectively. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 230b.

[0069] CAAC-OS has a highly crystalline and dense structure, and is a metal oxide with few impurities and defects (such as oxygen vacancies (also referred to as V O :oxygen vacancy)). In particular, after the formation of the metal oxide, by heat-treating at a temperature at which the metal oxide does not polycrystallize (for example, 400°C or higher and 600°C or lower), CAAC-OS can be made to have a more highly crystalline and dense structure. In this way, by increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0070] On the other hand, since it is difficult to confirm clear grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0071] In a transistor using an oxide semiconductor, if there are impurities and oxygen vacancies in the region where the channel in the oxide semiconductor is formed, the electrical characteristics are likely to vary and the reliability may deteriorate. Also, hydrogen near the oxygen vacancy may form a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H), and may generate electrons serving as carriers. For this reason, if the region where the channel in the oxide semiconductor is formed contains oxygen vacancies, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists even without applying a voltage to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, impurities, oxygen vacancies, and V OIt is preferable that H is reduced as much as possible. In other words, in the region where the channel is formed in the oxide semiconductor, it is preferable that the carrier concentration is reduced and the region is i-type (intrinsic) or substantially i-type.

[0072] On the other hand, by providing an insulator containing oxygen that desorbs by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing a heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen deficiency and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, there is a risk of causing a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. Furthermore, if the oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0073] Therefore, in the oxide semiconductor, it is preferable that the region 230bc functioning as the channel formation region has a reduced carrier concentration and is i-type or substantially i-type, but the regions 230ba and 230bb functioning as the source region or the drain region preferably have a high carrier concentration and are n-type. That is, it is preferable to reduce the oxygen deficiency and V O H in the region 230bc and prevent an excessive amount of oxygen from being supplied to the regions 230ba and 230bb.

[0074] Therefore, in the present embodiment, with the conductors 242a and 242b provided on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to reduce the oxygen deficiency and V O H in the region 230bc. Here, the microwave treatment refers to a treatment using, for example, a device having a power source that generates high-density plasma using microwaves.

[0075] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF (Radio Frequency), and the oxygen plasma can be made to act. At this time, high-frequency waves such as microwaves or RF can also be irradiated onto region 230bc. Due to the action of plasma, microwaves, etc., the V O H in region 230bc is broken, hydrogen (H) is removed from region 230bc, and oxygen vacancies (V O ) can be filled with oxygen. That is, in region 230bc, the reaction of "V O H → H + V O " occurs, and the hydrogen concentration in region 230bc can be reduced. Therefore, the oxygen vacancies and V O H in region 230bc can be reduced, and the carrier concentration can be decreased.

[0076] Also, when performing microwave treatment in an oxygen-containing atmosphere, the action of high-frequency waves such as microwaves or RF and oxygen plasma is shielded by conductor 242a and conductor 242b and does not reach region 230ba and region 230bb. Furthermore, the action of oxygen plasma can be reduced by insulator 271 and insulator 280 provided to cover oxide 230b and conductor 242. As a result, during microwave treatment, in region 230ba and region 230bb, reduction of V O H and excessive oxygen supply do not occur, so a decrease in the carrier concentration can be prevented.

[0077] In particular, the above-described effect is significant when microwave treatment is performed in an atmosphere containing oxygen after the formation of the insulating film that becomes the insulator 250b. Further, it is preferable to perform microwave treatment in an atmosphere containing oxygen after the formation of the insulating film that becomes the insulator 250a, and further to perform microwave treatment in an atmosphere containing oxygen after the formation of the insulating film that becomes the insulator 250b. By performing microwave treatment in an atmosphere containing oxygen via the insulator 250a or the insulator 250b in this manner, oxygen can be efficiently injected into the region 230bc. Further, the oxygen injected into the region 230bc exists in various forms such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions having unpaired electrons). Note that the oxygen injected into the region 230bc may be any one or more of the above-described forms, and oxygen radicals are particularly suitable. Further, by performing microwave treatment in an atmosphere containing oxygen after the formation of the insulating film that becomes the insulator 250b, the film quality of the insulator 250a and the insulator 250b can be improved, so that the reliability of the transistor 200 is improved.

[0078] In this way, oxygen deficiency and V O H can be selectively removed in the region 230bc of the oxide semiconductor, and the region 230bc can be made i-type or substantially i-type. Further, supply of excessive oxygen to the regions 230ba and 230bb that function as the source region or the drain region can be suppressed, and the n-type can be maintained. Thereby, fluctuations in the electrical characteristics of the transistor 200 can be suppressed, and variations in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.

[0079] By adopting the above configuration, a semiconductor device with little variation in transistor characteristics can be provided. Further, a semiconductor device with good reliability can be provided. Further, a semiconductor device having good electrical characteristics can be provided.

[0080] In FIG. 1 and the like, the side surface of the opening for embedding the conductor 260 and the like is substantially perpendicular to the surface to be formed of the oxide 230b, including the groove portion of the oxide 230b. However, the present embodiment is not limited to this. For example, the bottom of the opening may have a gentle curved surface and may have a U-shaped configuration. Further, for example, the side surface of the opening may be inclined with respect to the surface to be formed of the oxide 230b.

[0081] Also, as shown in FIG. 1C, in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be provided between the side surface and the upper surface of the oxide 230b. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter also referred to as a rounded shape).

[0082] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping the conductor 242, or smaller than half of the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. By adopting such a shape, the covering properties of the insulator 250 and the conductor 260 on the oxide 230b can be improved.

[0083] The oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element as the main component is preferably greater than the atomic ratio of the element M to the metal element as the main component in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0084] Further, the oxide 230b is preferably an oxide having crystallinity such as CAAC-OS. Oxides having crystallinity such as CAAC-OS have a dense structure with few impurities and defects (such as oxygen deficiencies) and high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0085] Here, at the junction of the oxide 230a and the oxide 230b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of the oxide 230a and the oxide 230b can also be said to change continuously or be continuously joined. To achieve this, it is preferable to lower the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0086] Specifically, by having a common element other than oxygen as a main component in the oxide 230a and the oxide 230b, a mixed layer with a low defect level density can be formed. For example, when the oxide 230b is an In-M-Zn oxide, as the oxide 230a, an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, etc. may be used.

[0087] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used. Also, as the oxide 230b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof may be used. Note that the vicinity of the composition includes a range of ±30% of the desired atomic ratio. Also, as the element M, it is preferable to use gallium.

[0088] In addition, when forming a metal oxide film by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, and may be the atomic ratio of the sputtering target used for forming the metal oxide film.

[0089] By configuring the oxide 230a and the oxide 230b as described above, the density of defect energy levels at the interface between the oxide 230a and the oxide 230b can be reduced. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.

[0090] At least one of the insulator 212, the insulator 214, the insulator 271, the insulator 272, the insulator 282, the insulator 283, the insulator 284, and the insulator 286 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms (it is difficult for the above impurities to permeate). Or, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (it is difficult for the above oxygen to permeate).

[0091] In this specification, the barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier property means a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Or, it means a function of capturing and fixing the corresponding substance (also referred to as gettering).

[0092] As the insulators 212, 214, 271, 272, 282, 283, 284, and 286, it is preferable to use insulators having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, as the insulators 212, 272, 283, and 286, it is preferable to use silicon nitride or the like having higher hydrogen barrier properties. Further, for example, as the insulators 214, 271, 282, and 284, it is preferable to use aluminum oxide or magnesium oxide or the like having a high function of capturing and fixing hydrogen. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Or, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed outside the insulator 286 to the transistor 200 side. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulators 212 and 214. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 280 or the like above the transistor 200 through the insulator 282 or the like. In this way, it is preferable to form the transistor 200 in a structure surrounded by the insulators 212, 214, 271, 272, 282, 283, 284, and 286 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0093] Here, as the insulators 212, 214, 271, 272, 282, 283, 284, and 286, it is preferable to use oxides having an amorphous structure. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as (y is an arbitrary number greater than 0). In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen existing around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0094] Also, the insulator 212, the insulator 214, the insulator 271, the insulator 272, the insulator 282, the insulator 283, the insulator 284, and the insulator 286 preferably have an amorphous structure, but a polycrystalline structure region may be formed in part. Further, the insulator 212, the insulator 214, the insulator 271, the insulator 272, the insulator 282, the insulator 283, the insulator 284, and the insulator 286 may have a multilayer structure in which an amorphous structure layer and a polycrystalline structure layer are laminated. For example, a laminated structure in which a polycrystalline structure layer is formed on an amorphous structure layer may be used.

[0095] The film formation of the insulators 212, 214, 271, 272, 282, 283, 284, and 286 may be performed, for example, using a sputtering method. Since the sputtering method does not require hydrogen in the film formation gas, the hydrogen concentration of the insulators 212, 214, 271, 272, 282, 283, 284, and 286 can be reduced. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. may be appropriately used.

[0096] In addition, there may be cases where it is preferable to lower the resistivity of the insulators 212, 272, 283, and 286. For example, by setting the resistivity of the insulators 212, 272, 283, and 286 to approximately 1×10 13 Ωcm, in a process using plasma or the like in the semiconductor device manufacturing process, the insulators 212, 272, 283, and 286 may be able to relax the charge-up of the conductors 205, 242, 260, or 246. The resistivity of the insulators 212, 272, 283, and 286 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0097] In addition, the insulators 216, 274, and 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 216, 274, and 280, silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. may be appropriately used.

[0098] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216.

[0099] The conductor 205 has a conductor 205a, a conductor 205b, and a conductor 205c. The conductor 205a is provided in contact with the bottom surface and the side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c substantially coincides with the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. That is, the conductor 205b is configured to be wrapped by the conductor 205a and the conductor 205c.

[0100] Here, for the conductor 205a and the conductor 205c, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0101] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductors 205a and 205c, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide 230 through the insulator 224 or the like. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductors 205a and 205c, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, as the conductor 205a, the above conductive material may be a single layer or a laminate. For example, the conductor 205a may use titanium nitride.

[0102] Also, for the conductor 205b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductor 205b may use tungsten.

[0103] The conductor 205 may function as a second gate electrode. In that case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no negative potential is applied.

[0104] In addition, the electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. Also, the film thickness of the insulator 216 is made substantially the same as that of the conductor 205. Here, it is preferable to reduce the film thicknesses of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the film thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the diffusion of the impurities into the oxide 230 can be reduced.

[0105] Note that, as shown in FIG. 1A, the conductor 205 is preferably provided to be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 preferably extends also in a region outside the end portions in the channel width direction of the oxides 230a and 230b. That is, outside the side surfaces of the oxide 230 in the channel width direction, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator. By having such a configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, the structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (S-channel) structure.

[0106] Note that, in this specification and the like, an S-channel structure transistor refers to the structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Also, the S-channel structure disclosed in this specification and the like is different from the Fin type structure and the planar type structure. By adopting the S-channel structure, it is possible to enhance the resistance to the short channel effect, in other words, to make a transistor in which the short channel effect hardly occurs.

[0107] Also, as shown in FIG. 1C, the conductor 205 is stretched and made to function as a wiring. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor that functions as a wiring is provided under the conductor 205. Also, the conductor 205 does not necessarily have to be provided one by one for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.

[0108] In the transistor 200, the conductor 205 is shown as a configuration in which the conductor 205a, the conductor 205b, and the conductor 205c are laminated. However, the present invention is not limited to this. For example, the conductor 205 may be provided in a single layer, a two-layer, or a four-layer or more laminated structure.

[0109] The insulators 222 and 224 function as gate insulators.

[0110] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). Also, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0111] The insulator 222 may be made of an insulator containing one or both of oxides of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inside of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. In addition, the reaction of the conductor 205 with the oxygen contained in the insulator 224 or the oxide 230 can be suppressed.

[0112] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulator. Alternatively, these insulators may be nitrided. Further, the insulator 222 may be used by laminating silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0113] Further, the insulator 222 may be a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0114] For the insulator 224 in contact with the oxide 230, for example, silicon oxide, silicon oxynitride, etc. may be appropriately used.

[0115] Further, during the manufacturing process of the transistor 200, it is preferable to perform a heat treatment in a state where the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 600°C or lower, more preferably at 350°C or higher and 550°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 230 to reduce oxygen vacancies (V O ). Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0116] Note that by performing an oxygen addition treatment on the oxide 230, the oxygen vacancies in the oxide 230 are repaired by the supplied oxygen, in other words, the reaction of "V O +O→null" can be promoted. Further, by reacting the supplied oxygen with the hydrogen remaining in the oxide 230, the hydrogen can be removed (dehydrated) as H2O. Thereby, it is possible to suppress the recombination of the hydrogen remaining in the oxide 230 with oxygen vacancies to form V O H.

[0117] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. Further, the insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 272 is configured to contact the side surface of the insulator 224 and the upper surface of the insulator 222.

[0118] Oxide 243a and oxide 243b are provided on oxide 230b. Oxide 243a and oxide 243b are provided separately with conductor 260 interposed therebetween.

[0119] Oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing an oxide 243 having a function of suppressing oxygen permeation between conductor 242 which functions as a source electrode or a drain electrode and oxide 230b, the electrical resistance between conductor 242 and oxide 230b is preferably reduced. With such a configuration, the electrical characteristics of transistor 200 and the reliability of transistor 200 can be improved. Note that when the electrical resistance between conductor 242 and oxide 230b can be sufficiently reduced, a configuration in which oxide 243 is not provided may be employed.

[0120] As oxide 243, a metal oxide containing element M may be used. In particular, element M is preferably aluminum, gallium, yttrium, or tin. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Further, gallium oxide may be used as oxide 243. Further, a metal oxide such as an In-M-Zn oxide may be used as oxide 243. Specifically, in the metal oxide used for oxide 243, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for oxide 230b. The film thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and still more preferably 1 nm or more and 2 nm or less. Further, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, the release of oxygen in oxide 230 can be preferably suppressed. For example, if oxide 243 has a crystal structure such as a hexagonal crystal, the release of oxygen in oxide 230 may be suppressed.

[0121] The conductor 242a is preferably provided in contact with the upper surface of the oxide 243a, and the conductor 242b is preferably provided in contact with the upper surface of the oxide 243b. The conductor 242a and the conductor 242b each function as a source electrode or a drain electrode of the transistor 200.

[0122] As the conductor 242 (the conductor 242a and the conductor 242b), for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Also, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. These materials are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0123] Note that hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using nitrides containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b or the like easily diffuses into the conductor 242a or the conductor 242b, and the diffused hydrogen may combine with nitrogen possessed by the conductor 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a or the conductor 242b.

[0124] Also, it is preferable that a curved surface is not formed between the side surface and the upper surface of the conductor 242. By making the conductor 242 without the formation of the curved surface, as shown in FIG. 1D, the cross-sectional area of the conductor 242 in the cross-section in the channel width direction can be increased. Thereby, the conductivity of the conductor 242 can be increased, and the on-current of the transistor 200 can be increased.

[0125] Insulator 271a is provided in contact with the upper surface of conductor 242a, and insulator 271b is provided in contact with the upper surface of conductor 242b. Insulator 271 preferably functions as at least a barrier insulating film against oxygen. Therefore, insulator 271 preferably has a function of suppressing the diffusion of oxygen. For example, insulator 271 preferably has a function of suppressing the diffusion of oxygen more than insulator 280. As insulator 271, for example, a nitride containing silicon such as silicon nitride may be used. Further, insulator 271 preferably has a function of capturing impurities such as hydrogen. In that case, as insulator 271, an insulator having an amorphous structure, such as aluminum oxide or magnesium oxide, may be used. In particular, using aluminum oxide having an amorphous structure or aluminum oxide with an amorphous structure as insulator 271 may be preferable because hydrogen can be captured or fixed more effectively. Thereby, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0126] Insulator 272 is provided so as to cover insulator 224, oxide 230a, oxide 230b, oxide 243, conductor 242, and insulator 271. As insulator 272, it preferably has a function of capturing hydrogen and fixing hydrogen. In that case, insulator 272 preferably contains silicon nitride or an insulator having an amorphous structure, such as aluminum oxide or magnesium oxide.

[0127] By providing insulator 271 and insulator 272 as described above, conductor 242 can be surrounded by an insulator having barrier properties against oxygen. That is, it is possible to prevent oxygen contained in insulator 224 and insulator 280 from diffusing into conductor 242. Thereby, it is possible to suppress the direct oxidation of conductor 242 by oxygen contained in insulator 224 and insulator 280, which increases the resistivity and reduces the on-current.

[0128] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230b. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0129] Similar to the insulator 224, it is preferable that the insulator 250 (insulator 250a and insulator 250b) has a reduced concentration of impurities such as water and hydrogen in the insulator 250. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less. In particular, the film thickness of the insulator 250a is preferably 0.5 nm or more and 15.0 nm or less.

[0130] As shown in FIGS. 1B and 1C, when the insulator 250 has a two-layer stacked structure, the lower-layer insulator 250a is preferably formed using an insulator that easily permeates oxygen, and the upper-layer insulator 250b is preferably formed using an insulator having a function of suppressing the diffusion of oxygen. With such a configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. In addition, oxidation of the conductor 260 due to oxygen contained in the insulator 250a can be suppressed. For example, the insulator 250a may be provided using a material that can be used for the above-described insulator 250, and the insulator 250b may be an insulator containing one or both of oxides of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing aluminum and silicon (hafnium silicate), etc. can be used. In the present embodiment, hafnium oxide is used as the insulator 250b. The film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, more preferably 1.0 nm or more and 3.0 nm or less.

[0131] The insulator 250a preferably contains silicon and is formed by the PEALD method using a hydrocarbon-free gas 401 (precursor) containing silicon and an oxidizing gas 402 (reactant). Further, a noble gas such as helium, neon, argon, krypton, or xenon may be added to the reactant.

[0132] The ALD method includes a thermal ALD method that performs the reaction of the precursor and the reactant only with thermal energy, a PEALD (Plasma Enhanced ALD) method that uses a plasma-excited reactant, and the like.

[0133] In addition, the ALD method utilizes the self-control property of atoms and can deposit atoms one by one, so it has effects such as enabling extremely thin film formation, enabling film formation on a structure with a high aspect ratio, enabling film formation with few defects such as pinholes, enabling film formation with excellent coverage, and enabling film formation at low temperatures. In the PEALD method, it may be preferable because film formation at a lower temperature is possible by utilizing plasma. Note that some precursors used in the ALD method contain carbon and the like. Therefore, the film provided by the ALD method may contain more impurities such as carbon compared to the film provided by other film formation methods. The quantification of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0134] In the present embodiment, the PEALD method is used. As the gas 401 containing silicon and not containing hydrocarbons, SiH4, Si2H6, SiF4, SiCl4, SiBr4, SiH2Cl2, SiH2I2, etc. can be used. As the oxidizing gas 402, O2, O3, N2O, NO2, H2O, etc. can be used. In the present embodiment, SiH4 is used as the gas 401 containing silicon and not containing hydrocarbons, and N2O is used as the oxidizing gas 402.

[0135] Using SiH4 as the silicon-containing and hydrocarbon-free gas 401 and N2O as the oxidizing gas 402 in FIG. 5, the process flow of forming silicon oxide as the insulator 250a by the PEALD method is shown in the film formation sequences of FIGS. 6A and 6B.

[0136] First, SiH4 and N2O are introduced into the reaction chamber, and the pressure in the reaction chamber is kept constant (step S01). Helium may be introduced here. When the flow rate ratio of SiH4 to N2O is such that the SiH4 flow rate is 1, N2O is 10 or more and 3000 or less, preferably 10 or more and 800 or less, more preferably 50 or more and 400 or less. Also, by setting it to 50 or more, NO generation in the insulator 250a can be suppressed. Also, the pressure in the reaction chamber is 200 Pa or more and 1200 Pa or less, preferably 400 Pa or more and 1000 Pa or less, more preferably 600 Pa or more and 800 Pa or less. Also, the substrate temperature is 100°C or more and 500°C or less, preferably 200°C or more and 400°C or less. Also, the substrate may not be heated, and film formation may be performed at room temperature. x Next, the introduction of SiH4 is stopped, and the SiH4 remaining in the reaction chamber is purged (step S02).

[0137] Next, high-frequency power 403 is applied to the reaction chamber to generate plasma by N2O. The frequency of the high frequency is 13.56 MHz or more and 60 MHz or less. By oxidizing SiHx adsorbed on the substrate in step S01 by N2O plasma, silicon oxide of approximately one molecular layer can be formed (step S03). Note that nitrogen injected by N2O plasma may be contained in the silicon oxide. Also, silicon oxide containing nitrogen may be called silicon oxynitride in some cases.

[0138] Next, the application of the high-frequency power 403 is stopped (step S04).

[0139]

[0140] ​By repeating the above steps S01 to S04 as one cycle until the desired film thickness is reached, silicon oxide that becomes the insulator 250a can be formed. Also, the number of cycles is set to be 1 cycle or more and 500 cycles or less. However, the number of cycles may be appropriately determined according to the required film thickness of the insulator 250a. Also, as shown in FIG. 6B, in step S02, a vacuum evacuation step of stopping the introduction of SiH4 and N2O and exhausting SiH 4、 and N2O remaining in the reaction chamber may be inserted. At this time, the introduction of SiH4 and the introduction of N2O may be stopped simultaneously, or the introduction of N2O may be stopped after the introduction of SiH4 is stopped. Also, it is preferable to resume the introduction of N2O before the start of step S03.

[0141] The silicon oxide that becomes the insulator 250a formed as described above can form a good insulator with a reduced hydrogen concentration and carbon concentration compared to the silicon oxide formed by the PECVD method using SiH 4、 and N2O.

[0142] SiH 4、 In the PECVD method using and N2O, since high-frequency power is applied in a state where SiH 4、 and N2O are introduced to generate plasma, SiH4 is decomposed in the plasma, a large amount of hydrogen radicals are generated, and hydrogen is mixed into the silicon oxide that becomes the insulator 250a. Also, as shown in FIG. 3, since the insulator 250a is in contact with the region 230bc that functions as a channel formation region, when oxygen in the region 230bc is extracted by the reduction reaction of hydrogen radicals and V O H is formed, the hydrogen concentration in the region 230bc increases.

[0143] On the other hand, in the PEALD method using SiH 4、 and N2O, which is one aspect of the present invention, in step 01 of the above, SiH 4、During the introduction of N2O, high-frequency power is not applied. In Step 02, after purging the remaining SiH4, in Step 03, with only N2O introduced, high-frequency power is applied to generate plasma, so the generation of hydrogen radicals can be suppressed. Therefore, the incorporation of hydrogen into the silicon oxide that becomes the insulator 250a and into the region 230bc in contact with the silicon oxide that becomes the insulator 250a can be suppressed. Also, SiH 4、 In the PEALD method using SiH4 and N2O, since SiH4 is used as a precursor and a precursor containing impurities such as carbon, for example, an organic precursor having a CH group, is not used, the incorporation of impurities such as carbon and hydrocarbons into the silicon oxide that becomes the insulator 250a can be suppressed. The silicon oxide thus formed has a reduced impurity concentration and is a denser film, so the diffusion of In from the region 230bc of the oxide 230b into the silicon oxide that becomes the insulator 250a can be prevented.

[0144] The carbon concentration in the silicon oxide that becomes the insulator 250a is preferably, by analysis using SIMS, 1×10 18 atoms / cm 3 or more and 5×10 20 atoms / cm 3 or less, more preferably, 5×10 18 atoms / cm 3 or more and 1×10 20 atoms / cm 3 or less. Also, the silicon oxide that becomes the insulator 250a contains nitrogen, and the nitrogen concentration is preferably, by SIMS analysis, 1×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less, more preferably, 3×10 19 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less. Also, the In concentration contained in the silicon oxide that becomes the insulator 250a is preferably, by SIMS analysis, 1.0×10 19 atoms / cm 3 or less, more preferably, 1.0×1018 atoms / cm 3 More preferably, 1.0×10 17 atoms / cm 3 or less.

[0145] In addition, when the silicon oxide that becomes the insulator 250a is in contact with the oxide 230b, the carbon concentration, nitrogen concentration, and In concentration in the insulator may be the concentrations in a region more than 1 nm away from the interface with the oxide 230b.

[0146] As described above, by using a silicon-containing and hydrocarbon-free gas (precursor) and an oxidizing gas (reactant), which are aspects of the present invention, to form silicon oxide that becomes the insulator 250a by the PEALD method, a transistor having excellent electrical characteristics and high reliability can be obtained.

[0147] In addition, when silicon oxide, silicon oxynitride, etc. are used for the insulator 250a, the insulator 250b may be made of an insulating material that is a high-k material having a high relative permittivity. By making the gate insulator have a laminated structure of the insulator 250a and the insulator 250b, a laminated structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it is possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator.

[0148] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Also, it is possible to suppress the oxidation of the conductor 260 by the oxygen in the insulator 250.

[0149] Incidentally, the above metal oxide may be configured to function as part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 can be used as the above metal oxide. In that case, by forming the conductor 260a by sputtering, the electrical resistance value of the above metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0150] By having the above metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Also, by maintaining the distance between the conductor 260 and the oxide 230 based on the physical thickness of the insulator 250 and the above metal oxide, the leakage current between the conductor 260 and the oxide 230 can be suppressed. Further, by providing a laminated structure of the insulator 250 and the above metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted appropriately.

[0151] The conductor 260 functions as the first gate electrode of the transistor 200. The conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to wrap the bottom surface and the side surface of the conductor 260b. Also, as shown in FIGS. 1B and 1C, the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250. Incidentally, in FIGS. 1B and 1C, the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b, but it may be a single-layer structure or a laminated structure of three or more layers.

[0152] For the conductor 260a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0153] In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250 and the resulting decrease in conductivity. As the conductive material having the function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0154] In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, as the conductor 260b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 260b may have a laminated structure. For example, a laminated structure of titanium or titanium nitride and the above conductive material may be used.

[0155] In the transistor 200, the conductor 260 is self-alignedly formed so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be surely arranged in the region between the conductor 242a and the conductor 242b without alignment.

[0156] Also, as shown in FIG. 1C, in the channel width direction of the transistor 200, when the bottom surface of the insulator 222 is used as a reference, the height of the bottom surface of the region of the conductor 260 where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap when the bottom surface of the insulator 222 is used as a reference is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0157] The insulator 280 is provided on the insulator 272, and an opening is formed in a region where the insulator 250 and the conductor 260 are provided. Also, the upper surface of the insulator 280 may be planarized.

[0158] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably provided using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen that desorbs upon heating.

[0159] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, the insulator 280 may appropriately use oxides containing silicon such as silicon oxide and silicon oxynitride.

[0160] The insulator 282 and the insulator 284 preferably function as barrier insulating films that suppress the diffusion of impurities such as water and hydrogen from above to the insulator 280, and preferably have a function of capturing impurities such as hydrogen. Further, the insulator 282 and the insulator 284 preferably function as barrier insulating films that suppress the permeation of oxygen. As the insulator 282 and the insulator 284, an insulator having an amorphous structure, for example, an insulator such as aluminum oxide may be used. By providing the insulator 282 having a function of capturing impurities such as hydrogen in contact with the insulator 280 within the region sandwiched between the insulator 212 and the insulator 283, impurities such as hydrogen contained in the insulator 280 and the like can be captured, and the amount of hydrogen in the region can be set to a constant value. In particular, as the insulator 282 and the insulator 284, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure because hydrogen can be captured or fixed more effectively in some cases. Thereby, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0161] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 280. The insulator 283 is disposed on the insulator 282. As the insulator 283, it is preferable to use a silicon-containing nitride such as silicon nitride or silicon oxynitride. For example, silicon nitride formed by a sputtering method may be used as the insulator 283. By forming the insulator 283 by a sputtering method, silicon nitride having a high density and difficult to form voids and the like can be formed. Further, as the insulator 283, silicon nitride formed by a PEALD method or a CVD method may be laminated on silicon nitride formed by a sputtering method.

[0162] For the conductor 240a and the conductor 240b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor 240a and the conductor 240b may have a laminated structure.

[0163] Also, when the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulator 283, the insulator 284, the insulator 282, the insulator 280, the insulator 272, and the insulator 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. Further, it is possible to suppress impurities such as water and hydrogen contained in the upper layer of the insulator 283 from mixing into the oxide 230 through the conductor 240a and the conductor 240b.

[0164] As the insulator 241a and the insulator 241b, for example, insulators such as silicon nitride, aluminum oxide, and silicon oxynitride may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 283, the insulator 284, the insulator 282, the insulator 280, the insulator 272, and the insulator 271, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 from mixing into the oxide 230 through the conductor 240a and the conductor 240b. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Also, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0165] Also, conductors 246 (conductor 246a and conductor 246b) that function as wiring may be arranged in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 246. Also, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.

[0166] The insulator 286 is provided on the conductor 246 and on the insulator 284. As a result, the upper surface and the side surface of the conductor 246 are in contact with the insulator 286, and the lower surface of the conductor 246 is in contact with the insulator 283. That is, the conductor 246 can be configured to be wrapped by the insulator 283 and the insulator 286. By adopting such a configuration, the permeation of oxygen from the outside can be suppressed, and the oxidation of the conductor 246 can be prevented. Further, it is preferable because impurities such as water and hydrogen can be prevented from diffusing from the conductor 246 to the outside.

[0167] <Constituent Materials of Semiconductor Devices> Hereinafter, the constituent materials that can be used in semiconductor devices will be described.

[0168] [[Substrate]] As the substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there is a substrate having a metal nitride or a metal oxide. Further, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, or a substrate in which a semiconductor or an insulator is provided on a conductor substrate. Alternatively, those with elements provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0169] [[Insulator]] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. that have insulating properties.

[0170] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it becomes possible to lower the operating voltage of the transistor while maintaining the physical film thickness. On the other hand, for the insulator that functions as the interlayer film, by using a material with a low relative permittivity, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is advisable to select the material according to the function of the insulator.

[0171] Examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium, etc.

[0172] Examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin, etc.

[0173] In addition, a transistor using a metal oxide can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0174] In addition, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated.

[0175] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0176] In addition, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen may be used. Further, a laminated structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0177] In addition, when an oxide is used for the channel formation region of the transistor, for the conductor functioning as the gate electrode, it is preferable to use a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is advisable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is easily supplied to the channel formation region.

[0178] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen included in the metal oxide in which the channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may also be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may also be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0179] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described.

[0180] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Further, in addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0181] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0182] In addition, in this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0183] <Classification of Crystal Structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 4A. FIG. 4A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0184] As shown in FIG. 4A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Also, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). Note that the classification of "Crystalline" excludes single crystal, poly crystal, and completely amorphous. Also, "Crystal" includes single crystal and poly crystal.

[0185] Note that the structure within the thick frame shown in Fig. 4A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be described as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0186] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, Fig. 4B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 4B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 4B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 4B is 500 nm.

[0187] In Fig. 4B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [a.u.]. As shown in Fig. 4B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. Note that, as shown in Fig. 4B, the peak near 2θ = 31° is asymmetric about the angle at which the peak intensity is detected.

[0188] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 4C. FIG. 4C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 4C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano beam electron diffraction method, electron beam diffraction is performed with a probe diameter of 1 nm.

[0189] As shown in FIG. 4C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0190] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 4A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0191] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0192] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that strain refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0193] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be about several tens of nm.

[0194] Also, in an In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0195] When performing structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0196] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0197] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be lattice arrangements such as pentagons and heptagons. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0198] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and there is a high possibility of causing a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carriers being trapped. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that to form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0199] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Thus, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation, defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of an oxide semiconductor having CAAC-OS are stable. For this reason, an oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0200] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as restricted field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0201] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0202] [[Constitution of Oxide Semiconductor]] Next, the details of the above-mentioned CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0203] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0204] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0205] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0206] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0207] Note that there may be a case where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0208] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0209] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily to endow CAC-OS with a switching function (on / off function). That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ) and a high field-effect mobility (μ), as well as a good switching operation, can be realized.

[0210] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0211] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0212] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0213] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, still more preferably 1×10 11 cm -3 or less, and even more preferably 1×10 10 cm -3is less than 1×10 -9 cm -3 or more. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be decreased and the density of defect levels may be decreased. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0214] In addition, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low.

[0215] In addition, the charge trapped in the trap level of the oxide semiconductor may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0216] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0217] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0218] When silicon or carbon, which is a Group 14 element, is contained in the oxide semiconductor, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon (concentration obtained by SIMS) near the interface between the channel formation region of the oxide semiconductor are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0219] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0220] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as the semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 less than, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0221] In addition, hydrogen contained in the oxide semiconductor may react with oxygen that binds to metal atoms to form water, thereby forming oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons that serve as carriers may be generated. Also, a part of the hydrogen may bind to oxygen that binds to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 ; more preferably less than 1×10 19 atoms / cm 3 ; still more preferably less than 5×10 18 atoms / cm 3 ; still more preferably less than 1×10 18 atoms / cm 3 .

[0222] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0223] <<Other Semiconductor Materials>> The semiconductor materials that can be used for the oxide 230 are not limited to the metal oxides described above. As the oxide 230, a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use semiconductor materials such as elemental semiconductors like silicon, compound semiconductors like gallium arsenide, and layer materials that function as semiconductors (also referred to as atomic layer materials, two-dimensional materials, etc.). In particular, it is suitable to use a layer material that functions as a semiconductor as the semiconductor material.

[0224] Here, in this specification and the like, the layer material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0225] Examples of the layer material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, chalcogens are a general term for elements belonging to Group 16 and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0226] As the oxide 230, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0227] <Method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to an aspect of the present invention shown in FIGS. 1A to 1D will be described with reference to FIGS. 7A to 22D.

[0228] In each figure, A shows a top view. Also, B in each figure is a cross-sectional view corresponding to the part indicated by the dashed line A1 - A2 shown in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Further, C in each figure is a cross-sectional view corresponding to the part indicated by the dashed line A3 - A4 shown in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, D in each figure is a cross-sectional view of the part indicated by the dashed line A5 - A6 shown in A of each figure. Note that in the top view of A in each figure, some elements are omitted for clarity of the figure.

[0229] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed into a film by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc.

[0230] Note that the sputtering method includes an RF sputtering method using a high-frequency power source for the sputtering power supply, a DC sputtering method using a DC power source, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed pulsingly. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal conductive film. Also, the pulsed DC sputtering method is mainly used when forming a compound such as an oxide, a nitride, or a carbide by a reactive sputtering method.

[0231] Note that the CVD method can be classified into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method according to the raw material gas used.

[0232] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Also, the thermal CVD method does not use plasma, so it is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0233] Also, as the ALD method, a thermal ALD (Thermal ALD) method that performs the reaction of the precursor and the reactant only with thermal energy, a PEALD method that uses a plasma-excited reactant, etc. can be used.

[0234] The CVD method and the ALD method are film-forming methods in which a film is formed by a gas-phase reaction on the surface of the object to be processed, different from film-forming methods in which particles emitted from a target or the like are deposited. Therefore, it is a film-forming method that is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film-forming rate, it may be preferably used in combination with other film-forming methods such as the CVD method with a high film-forming rate in some cases.

[0235] Also, in the CVD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required compared to the case of forming a film using a plurality of film-forming chambers. Therefore, the productivity of the semiconductor device may be increased in some cases.

[0236] In addition, in the ALD method, a film with an arbitrary composition can be formed by simultaneously introducing a plurality of precursors with different compositions or by controlling the number of introductions of a plurality of precursors with different compositions during one cycle of each precursor.

[0237] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 7A to 7D). The formation of the insulator 212 is preferably performed using a sputtering method. By using a sputtering method that does not require hydrogen in the film-forming gas, the hydrogen concentration in the insulator 212 can be reduced. However, the formation of the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, etc. may be appropriately used.

[0238] In the present embodiment, as the insulator 212, silicon nitride is formed by a pulsed DC sputtering method using a silicon target in an atmosphere containing nitrogen gas. By using the pulsed DC sputtering method, the generation of particles due to arcing on the target surface can be suppressed, so that the film thickness distribution can be made more uniform. In addition, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than that of a high-frequency voltage. As a result, power can be supplied to the electrode more efficiently, and the sputtering rate and film quality can be improved.

[0239] By using an insulator such as silicon nitride through which impurities such as water and hydrogen hardly permeate, the diffusion of impurities such as water and hydrogen contained in the lower layer than the insulator 212 can be suppressed. Further, by using an insulator such as silicon nitride as the insulator 212 through which copper hardly permeates, even if a metal such as copper that easily diffuses is used for the conductor in the lower layer (not shown) than the insulator 212, the diffusion of the metal upward through the insulator 212 can be suppressed.

[0240] Next, an insulator 214 is formed on the insulator 212 (see FIGS. 7A to 7D). The formation of the insulator 214 is preferably performed using a sputtering method. By using a sputtering method that does not require hydrogen in the film-forming gas, the hydrogen concentration in the insulator 214 can be reduced. However, the formation of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, etc. may be appropriately used.

[0241] In this embodiment, as the insulator 214, aluminum oxide is formed by a pulsed DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the lower layer than the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is 0 W / cm 2 or more and 1.86 W / cm 2 or less. That is, by the RF power at the time of forming the insulator 214, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be injected. Also, the frequency of the RF is preferably 10 MHz or more. Typically, it is 13.56 MHz. The higher the frequency of the RF, the smaller the damage to the substrate.

[0242] As the insulator 214, it is preferable to use a metal oxide having an amorphous structure with a high function of capturing and fixing hydrogen, for example, aluminum oxide. Thereby, the hydrogen contained in the insulator 216 or the like can be captured or fixed, and the diffusion of the hydrogen into the oxide 230 can be prevented. In particular, as the insulator 214, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide of an amorphous structure because hydrogen can be captured or fixed more effectively in some cases. Thereby, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0243] Next, an insulator 216 is formed on the insulator 214. The formation of the insulator 216 is preferably performed using a sputtering method. By using a sputtering method that does not require hydrogen in the film-forming gas, the hydrogen concentration in the insulator 216 can be reduced. However, the formation of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, etc. may be appropriately used.

[0244] In this embodiment, as the insulator 216, silicon oxide is formed by a pulsed DC sputtering method using a silicon target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0245] The insulator 212, the insulator 214, and the insulator 216 are preferably formed continuously without being exposed to the atmosphere. For example, a multi-chamber type film-forming apparatus may be used. Thereby, the insulator 212, the insulator 214, and the insulator 216 can be formed with reduced hydrogen in the film, and furthermore, the mixing of hydrogen into the film during the intervals between the respective film-forming steps can be reduced.

[0246] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove, a slit, etc. In some cases, the region where the opening is formed may be referred to as an opening portion. The formation of the opening may use wet etching, but dry etching is more preferable for microfabrication. Also, it is preferable to select the insulator 214 as an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 for forming the groove, the insulator 214 may use silicon nitride, aluminum oxide, or hafnium oxide.

[0247] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0248] After the formation of the opening, a conductive film 205A is formed (see FIGS. 7A to 7D). The conductive film 205A desirably contains a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, it can be a laminated film of a conductor having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like. The conductive film 205A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0249] In the present embodiment, titanium nitride is formed as the conductive film 205A. By using such a metal nitride as the lower layer of the conductor 205b, oxidation of the conductor 205b by the insulator 216 or the like can be suppressed. Further, even if a metal such as copper that easily diffuses is used as the conductor 205b, diffusion of the metal outside the conductor 205a can be prevented.

[0250] Next, a conductive film 205B is formed (see FIGS. 7A to 7D). As the conductive film 205B, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The formation of the conductive film 205B can be performed using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, tungsten is formed as the conductive film 205B.

[0251] Next, by performing CMP processing, a part of the conductive film 205A and the conductive film 205B is removed to expose the insulator 216 (see FIGS. 8A to 8D). As a result, the conductors 205a and 205b remain only in the openings. Note that a part of the insulator 216 may be removed by the CMP processing.

[0252] Next, etching is performed to remove the upper part of the conductor 205b (see FIGS. 9A to 9D). As a result, the upper surface of the conductor 205b becomes lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. For the etching of the conductor 205b, dry etching or wet etching may be used, but dry etching is more preferable for microfabrication.

[0253] Next, a conductive film 205C is formed on the insulator 216, the conductor 205a, and the conductor 205b (see FIGS. 10A to 10D). Similar to the conductive film 205A, the conductive film 205C preferably includes a conductor having a function of suppressing oxygen permeation.

[0254] In the present embodiment, titanium nitride is formed as the conductive film 205C. By using such a metal nitride for the upper layer of the conductor 205b, oxidation of the conductor 205b can be suppressed by the insulator 222 or the like. Further, even when a metal such as copper that easily diffuses is used as the conductor 205b, diffusion of the metal to the outside from the conductor 205c can be prevented.

[0255] Next, by performing CMP processing, a part of the conductive film 205C is removed to expose the insulator 216 (see FIGS. 11A to 11D). As a result, only the conductors 205a, 205b, and 205c remain in the opening. Thereby, the conductor 205 having a flat upper surface can be formed. Further, the conductor 205b is configured to be surrounded by the conductors 205a and 205c. Therefore, impurities such as hydrogen from the conductor 205b can be prevented from diffusing outside the conductors 205a and 205c, and oxygen can be prevented from mixing in from outside the conductors 205a and 205c to oxidize the conductor 205b. Note that a part of the insulator 216 may be removed by the CMP processing.

[0256] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, an insulator containing one or both of oxides of aluminum and hafnium may be formed. Note that as the insulator containing one or both of oxides of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator containing one or both of oxides of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in the structure provided around the transistor 200 into the inside of the transistor 200 through the insulator 222 can be suppressed, and generation of oxygen vacancies in the oxide 230 can be suppressed.

[0257] The insulator 222 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, hafnium oxide is formed as the insulator 222 using the ALD method.

[0258] Subsequently, heat treatment is preferably performed. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be adjusted to about 20%. Also, the heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or inert gas.

[0259] Also, the gas used in the above heat treatment is preferably highly purified. For example, the water content in the gas used in the above heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less. By performing heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the insulator 222 as much as possible.

[0260] In this embodiment, as heat treatment, after the formation of the insulator 222, the flow rate ratio of nitrogen gas to oxygen gas is set to 4 slm:1 slm, and treatment is performed at a temperature of 400°C for 1 hour. By this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Also, when an oxide containing hafnium is used as the insulator 222, a part of the insulator 222 may be crystallized by this heat treatment. Also, the heat treatment can be carried out at the timing such as after the formation of the insulator 224.

[0261] Next, an insulator 224 is formed on the insulator 222. The formation of the insulator 224 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, as the insulator 224, silicon oxide is formed using a sputtering method. By using a sputtering method that does not require hydrogen in the film-forming gas, the hydrogen concentration in the insulator 224 can be reduced. Since the insulator 224 is in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration is reduced in this way.

[0262] Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see FIGS. 12A to 12D). Note that it is preferable that the oxide film 230A and the oxide film 230B are continuously formed without being exposed to the air environment. By forming the film without opening to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the oxide film 230A and the oxide film 230B, and it is possible to keep the vicinity of the interface between the oxide film 230A and the oxide film 230B clean.

[0263] The formation of the oxide film 230A and the oxide film 230B can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The formation of the oxide film 230A and the oxide film 230B is preferably performed using the ALD method because a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio. Further, by using the PEALD method, the oxide film 230A and the oxide film 230B can be formed at a lower temperature than the thermal ALD method, which is preferable. In the present embodiment, the sputtering method is used to form the oxide film 230A and the oxide film 230B.

[0264] For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. Further, when the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target or the like can be used.

[0265] In particular, when forming the oxide film 230A, a part of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0266] Also, when forming the oxide film 230B by the sputtering method, if the proportion of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, an oxygen-excess type oxide semiconductor is formed. A transistor using an oxygen-excess type oxide semiconductor in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this. When forming the oxide film 230B by the sputtering method, if the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type oxide semiconductor is formed. A transistor using an oxygen-deficient type oxide semiconductor in the channel formation region can obtain relatively high field-effect mobility. Further, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

[0267] In this embodiment, as the oxide film 230A, film formation is performed by the sputtering method using an oxide target of In:Ga:Zn = 1:3:4 [atomic ratio]. Also, as the oxide film 230B, film formation is performed by the sputtering method using an oxide target of In:Ga:Zn = 4:2:4.1 [atomic ratio], an oxide target of In:Ga:Zn = 1:1:1 [atomic ratio], or an oxide target of In:Ga:Zn = 1:1:0.5 [atomic ratio]. Note that each oxide film may be formed in accordance with the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and the atomic ratio.

[0268] Next, an oxide film 243A is formed on the oxide film 230B (see FIGS. 12A to 12D). The formation of the oxide film 243A can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable that the atomic ratio of Ga to In in the oxide film 243A is larger than the atomic ratio of Ga to In in the oxide film 230B. In the present embodiment, as the oxide film 243A, a film is formed by a sputtering method using an oxide target of In:Ga:Zn = 1:3:4 [atomic ratio].

[0269] Note that it is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A by a sputtering method without exposing them to the atmosphere. For example, a multi-chamber type film forming apparatus may be used. Thereby, the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be formed while reducing hydrogen in the film, and furthermore, the mixing of hydrogen into the film during the intervals between the respective film forming steps can be reduced.

[0270] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not crystallize polycrystallinely, and may be performed at 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be set to about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after performing the heat treatment in an atmosphere of nitrogen gas or an inert gas.

[0271] Also, the gas used in the above heat treatment is preferably highly purified. For example, the water content in the gas used in the above heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the oxide film 230A, the oxide film 230B, the oxide film 243A, etc. as much as possible.

[0272] In the present embodiment, as the heat treatment, after performing a treatment at a temperature of 400 ° C for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400 ° C for 1 hour is continuously performed in an oxygen atmosphere. By this heat treatment, impurities such as water and hydrogen in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be removed. Further, by this heat treatment, the crystallinity of the oxide film 230B can be improved, and a denser structure with higher density can be obtained. Thereby, the diffusion of oxygen or impurities in the oxide film 230B can be reduced.

[0273] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 12A to 12D). The conductive film 242A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the conductive film 242A, tantalum nitride may be formed using a sputtering method. Note that a heat treatment may be performed before forming the conductive film 242A. The heat treatment is performed under reduced pressure, and the conductive film 242A may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and further, the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be reduced. The temperature of the heat treatment is preferably 100 ° C or higher and 400 ° C or lower. In the present embodiment, the temperature of the heat treatment is 200 ° C.

[0274] Next, an insulating film 271A is formed on the conductive film 242A (see FIGS. 12A to 12D). The insulating film 271A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film having a function of suppressing oxygen permeation for the insulating film 271A. For example, as the insulating film 271A, aluminum oxide or silicon nitride may be formed by a sputtering method.

[0275] In this embodiment, as the insulating film 271A, aluminum oxide is formed by a pulsed DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. The RF power applied to the substrate is 0.62 W / cm 2 The following is adopted. Preferably, it is 0 W / cm 2 or more and 0.31 W / cm 2 or less. By reducing the RF power, the amount of oxygen injected into the conductive film 242A can be suppressed, and oxidation of the conductive film 242A can be prevented.

[0276] Note that it is preferable to form the conductive film 242A and the insulating film 271A by a sputtering method without exposing them to the atmosphere. For example, a multi-chamber type film forming apparatus may be used. Thereby, the conductive film 242A and the insulating film 271A can be formed while reducing hydrogen in the film, and furthermore, the mixing of hydrogen into the film during the intervals between the respective film forming steps can be reduced. When providing a hard mask on the insulating film 271A, the film serving as the hard mask may be continuously formed without exposing it to the atmosphere.

[0277] Next, using a lithography method, the oxide films 230A, 230B, 243A, the conductive film 242A, the insulating film 271A, and the insulator 224 are processed into island shapes to form the oxides 230a, 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 13A to 13D). Further, a dry etching method or a wet etching method can be used for this processing. Processing by the dry etching method is suitable for fine processing. Also, the processing of the oxide films 230A, 230B, 243A, the conductive film 242A, the insulating film 271A, and the insulator 224 may be performed under different conditions. In this step, the insulator 224 is superimposed on the oxide 230a and processed into an island shape.

[0278] In the lithography method, first, a resist is exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Next, by performing an etching process through the resist mask, a conductor, semiconductor, insulator, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using a KrF excimer laser beam, an ArF excimer laser beam, EUV (Extreme Ultraviolet) light, etc. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0279] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material. Etching of the conductive film 242A or the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film 242A or the like. On the other hand, when the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask. In the present embodiment, when the insulating layer 271B is used as a hard mask, it is preferable to appropriately adjust the film thickness of the insulating layer 271B to suppress the disappearance of the insulating layer 271B during etching of the conductive film 242A or the like.

[0280] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, as shown in FIGS. 13B to 13D, the conductive layer 242B does not have a curved surface between the side surface and the upper surface. As a result, the ends where the side surfaces and the upper surfaces of the conductors 242a and 242b shown in FIGS. 1B and 1D intersect are angular. When the ends where the side surfaces and the upper surfaces of the conductor 242 intersect are angular, the cross-sectional area of the conductor 242 is larger than when the ends have a curved surface. Thereby, since the resistance of the conductor 242 is reduced, the on-current of the transistor 200 can be increased.

[0281] Also, the insulator 224, the oxides 230a, 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are formed such that at least a part thereof overlaps with the conductor 205. Also, the side surfaces of the insulator 224, the oxides 230a, 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are preferably substantially perpendicular to the upper surface of the insulator 222. When the side surfaces of the insulator 224, the oxides 230a, 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are substantially perpendicular to the upper surface of the insulator 222, miniaturization and high density can be achieved when providing the plurality of transistors 200. Alternatively, the configuration may be such that the angle formed by the side surfaces of the insulator 224, the oxides 230a, 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 is a low angle. In that case, the angle formed by the side surfaces of the insulator 224, the oxides 230a, 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, in subsequent processes, the covering property of the insulator 272 and the like can be improved, and defects such as looseness can be reduced.

[0282] Also, by-products generated in the etching process may be formed in layers on the side surfaces of the insulator 224, the oxides 230a, 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B. In this case, the layered by-products will be formed between the insulator 224, the oxides 230a, 230b, the oxide 243, the conductor 242, and the insulator 271 and the insulator 272. Similarly, layered by-products may be formed on the insulator 222. If the process is advanced to fabricate the transistor 200 with the layered by-products formed on the insulator 222, the reliability of the transistor 200 may deteriorate. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 222.

[0283] Next, an insulator 272 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 14A to 14D). The formation of the insulator 272 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 272, silicon nitride, aluminum oxide, or the like can be used. Further, the insulator 272 may have a laminated structure. For example, silicon nitride may be formed and aluminum oxide may be formed on the silicon nitride, or aluminum oxide may be formed and silicon nitride may be formed on the aluminum oxide. In the present embodiment, silicon nitride is formed as the insulator 272 by a sputtering method.

[0284] In this way, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B can be covered with the insulator 272 and the insulating layer 271B having a function of suppressing the diffusion of oxygen. Thereby, in a later process, the diffusion of oxygen into the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B can be reduced.

[0285] Next, an insulating film that becomes the insulator 280 is formed on the insulator 272. The formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulating film, a silicon oxide film may be formed using a sputtering method. By forming the insulating film in an atmosphere containing oxygen using a sputtering method, an insulator 280 containing excess oxygen can be formed. Further, by using a sputtering method that does not require hydrogen in the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before the formation of the insulating film. The heat treatment is performed under reduced pressure, and the insulating film may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 272 and the like can be removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. The above-described heat treatment conditions can be used for the heat treatment.

[0286] Next, a CMP treatment is performed on the insulating film that becomes the insulator 280 to form an insulator 280 having a flat upper surface (see FIGS. 14A to 14D). Note that, for example, a silicon nitride film may be formed on the insulator 280 by a sputtering method, and the CMP treatment may be performed until the silicon nitride reaches the insulator 280.

[0287] Next, a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, and a part of the oxide layer 243B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap with the conductor 205. By forming the opening, an insulator 271a, an insulator 271b, a conductor 242a, a conductor 242b, an oxide 243a, and an oxide 243b are formed (see FIGS. 15A to 15D).

[0288] When forming the above opening, the upper part of the oxide 230b may be removed. By removing a part of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the opening forming step or in a step different from the opening forming step.

[0289] In addition, for the processing of a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, and a part of the oxide layer 243B, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Also, the processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by the dry etching method, a part of the insulator 272 and a part of the insulating layer 271B may be processed by the wet etching method, and a part of the conductive layer 242B and a part of the oxide layer 243B may be processed by the dry etching method. Also, the processing of a part of the conductive layer 242B and the processing of a part of the oxide layer 243B may be performed under different conditions.

[0290] Here, it is preferable to remove impurities attached to the surface or diffused inside the oxide 230a, the oxide 230b, etc. Also, it is preferable to remove the damaged region formed on the surface of the oxide 230b by the above dry etching. Examples of the impurities include those caused by components contained in the insulator 280, the insulator 272, a part of the insulating layer 271B, and the conductive layer 242B, components contained in members used in the apparatus used for forming the above opening, and components contained in the gas or liquid used for etching. Examples of the impurities include aluminum, silicon, tantalum, fluorine, chlorine, etc.

[0291] In particular, impurities such as aluminum or silicon inhibit the CAAC-OS conversion of the oxide 230b. Therefore, it is preferable that impurity elements that inhibit CAAC-OS conversion, such as aluminum or silicon, are reduced or removed. For example, the concentration of aluminum atoms in the oxide 230b and in its vicinity may be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, still more preferably 1.0 atomic% or less, and even more preferably less than 0.3 atomic%.

[0292] Incidentally, a region of a metal oxide in which CAAC-OS conversion is inhibited by impurities such as aluminum or silicon and which becomes a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor) may be referred to as a non-CAAC region. In the non-CAAC region, since the density of the crystal structure is reduced, a large amount of V O H is formed, and the transistor is likely to be normally turned on. Therefore, it is preferable that the non-CAAC region of the oxide 230b is reduced or removed.

[0293] On the other hand, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has a CAAC structure up to the lower end of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as a drain. That is, it is preferable that the oxide 230b in the vicinity of the lower end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end that significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed and having a CAAC structure can further suppress fluctuations in the electrical characteristics of the transistor 200. Also, the reliability of the transistor 200 can be improved.

[0294] To remove the above-mentioned impurities and the like, a cleaning process is performed. As the cleaning method, there are wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, cleaning by heat treatment, etc., and the above cleaning may be appropriately combined. Note that the groove portion may become deeper by the cleaning process.

[0295] As the wet cleaning, cleaning treatment may be performed using an aqueous solution obtained by diluting aqueous ammonia, oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning using these aqueous solutions, pure water, or carbonated water may be performed. Alternatively, these cleanings may be appropriately combined.

[0296] In this specification and the like, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available aqueous ammonia with pure water may be referred to as diluted aqueous ammonia. Also, the concentration, temperature, etc. of the aqueous solution may be appropriately adjusted according to the impurities to be removed, the configuration of the semiconductor device to be cleaned, etc. The ammonia concentration of the diluted aqueous ammonia may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. Also, the hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0297] Note that for ultrasonic cleaning, a frequency of 200 kHz or more, preferably 900 kHz or more is used. By using this frequency, damage to the oxide 230b and the like can be reduced.

[0298] Also, the above cleaning process may be performed multiple times, and the cleaning liquid may be changed for each cleaning process. For example, as the first cleaning process, a process using diluted hydrofluoric acid or diluted aqueous ammonia may be performed, and as the second cleaning process, a process using pure water or carbonated water may be performed.

[0299] As the above cleaning process, in this embodiment, wet cleaning is performed using diluted hydrofluoric acid, and subsequently wet cleaning is performed using pure water or carbonated water. By performing this cleaning process, impurities adhering to the surface or diffused inside the oxide 230a, oxide 230b, etc. can be removed. Furthermore, the crystallinity of the oxide 230b can be enhanced.

[0300] Due to the previous processing such as dry etching or the above cleaning process, the film thickness of the insulator 224 in the region overlapping the above opening and not overlapping the oxide 230b may become thinner than the film thickness of the insulator 224 in the region overlapping the oxide 230b.

[0301] Heat treatment may be performed after the above etching or after the above cleaning. The heat treatment may be performed at 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 230a and the oxide 230b to reduce oxygen deficiency. Also, by performing such heat treatment, the crystallinity of the oxide 230b can be improved. Also, the heat treatment may be performed under reduced pressure. Or, after heat treatment in an oxygen atmosphere, heat treatment may be continuously performed in a nitrogen atmosphere without exposure to the atmosphere.

[0302] Next, an insulating film 250A that will become the insulator 250a is formed (see FIGS. 16A to 16D). Heat treatment may be performed before forming the insulating film 250A. The heat treatment is performed under reduced pressure, and the insulating film 250A may be continuously formed without exposure to the atmosphere. Also, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b, etc. can be removed, and furthermore, the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0303] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes the insulator 250 that contacts the oxide 230b in a later process, it is preferable that the hydrogen concentration is reduced in this way.

[0304] In addition, the insulating film 250A preferably contains silicon and is formed by the PEALD method using a gas (precursor) that does not contain hydrocarbons and an oxidizing gas (reactant). The film thickness of the insulator 250 that functions as a gate insulating film of the miniaturized transistor 200 is extremely thin (for example, about 0.5 nm or more and 15.0 nm or less), and it is necessary to reduce the variation. On the other hand, the PEALD method is a film formation method in which a precursor and a reactant (oxidizing agent) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so precise film thickness adjustment is possible. Therefore, the accuracy of the gate insulating film required by the miniaturized transistor 200 can be achieved. Further, as shown in FIGS. 16B and 16C, the insulating film 250A needs to be formed with good coverage on the bottom surface and side surfaces of the opening formed by the insulator 280 or the like. Since atomic layers can be deposited one by one on the bottom surface and side surfaces of the opening, the insulating film 250A can be formed with good coverage for the opening. Further, by using the PEALD method, the film can be formed at a relatively low substrate temperature.

[0305] Moreover, by using a silicon-containing gas (precursor) that does not contain hydrocarbons and an oxidizing gas (reactant), the incorporation of hydrogen into the insulating film 250A and the oxide 230b can be suppressed. Also, since a precursor containing impurities such as carbon, for example, an organic precursor having a CH group, is not used, the incorporation of impurities such as carbon and hydrocarbons into the insulating film 250A can be suppressed. In this way, a denser film without impurities can be formed, thereby preventing the diffusion of In from the oxide 230b to the insulating film 250A.

[0306] In this embodiment, SiH4 is used as the precursor and N2O is used as the reactant. Also, the formation of the insulating film 250A is repeatedly performed in accordance with the process flow shown in FIG. 5 and the sequences shown in FIGS. 6A and 6B, with steps S01 to S04 as one cycle until the desired film thickness is reached.

[0307] Next, an insulating film 250B that becomes the insulator 250b is formed (see FIGS. 17A to 17D). The insulating film 250B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250B is preferably formed using an insulator having a function of suppressing the diffusion of oxygen. With such a configuration, the oxygen contained in the insulator 250a can be prevented from diffusing into the conductor 260. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Also, the oxidation of the conductor 260 by the oxygen contained in the insulator 250a can be suppressed. For example, the insulating film 250A can be provided using a material that can be used for the insulator 250 described above, and the insulating film 250B can be provided using the same material as the insulator 222.

[0308] As the insulating film 250B, specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230 can be used. In particular, it is preferable to use an insulator containing one or both oxides of aluminum and hafnium.

[0309] In this embodiment, silicon oxynitride is formed as the insulating film 250A by the PECVD method, and hafnium oxide is formed as the insulating film 250B by the thermal ALD method.

[0310] Next, microwave treatment is performed in an oxygen-containing atmosphere (see FIGS. 17A to 17D). Here, the dotted lines shown in FIGS. 17B, 17C, and 17D indicate microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For the microwave treatment, it is preferable to use a microwave treatment apparatus having a power source for generating high-density plasma using microwaves. Further, the microwave treatment apparatus may have a power source for applying RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. Also, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230b. Further, the above microwave treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and still more preferably 400 Pa or more. Also, the oxygen flow ratio (O2 / (O2+Ar)) is preferably 50% or less, preferably 10% or more and 30% or less. Also, the treatment temperature may be 750°C or less, preferably 500°C or less, for example, about 400°C. Further, after the oxygen plasma treatment, heat treatment may be continuously performed without exposing to the outside air.

[0311] As shown in FIGS. 17B, 17C, and 17D, by performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act on the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 230bc. That is, microwaves, high-frequency waves such as RF, oxygen plasma, etc. can be made to act on the region 230bc shown in FIG. 3. Due to the action of plasma, microwaves, etc., the V O H is broken, and hydrogen can be removed from the region 230bc. That is, in the region 230bc, the reaction of "V O H→H+V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, the oxygen deficiency and V O H in the region 230bc can be reduced, and the carrier concentration can be decreased. Also, by supplying oxygen radicals generated by the above oxygen plasma or oxygen contained in the insulator 250 to the oxygen deficiency formed in the region 230bc, the oxygen deficiency in the region 230bc can be further reduced, and the carrier concentration can be decreased.

[0312] On the other hand, conductors 242a and 242b are provided on the regions 230ba and 230bb shown in FIG. 3. As shown in FIGS. 17B, 17C, and 17D, the conductors 242a and 242b shield the action of microwaves, high-frequency waves such as RF, oxygen plasma, etc., so these actions do not reach the regions 230ba and 230bb. Thereby, by microwave treatment, reduction of V O H and supply of an excessive amount of oxygen do not occur in the regions 230ba and 230bb, so a decrease in the carrier concentration can be prevented.

[0313] In this way, oxygen deficiency and V OHydrogen can be removed to make region 230bc of type I or substantially type I. Further, the supply of excessive oxygen to regions 230ba and 230bb that function as a source region or a drain region can be suppressed, and n-type formation can be maintained. Thereby, fluctuations in the electrical characteristics of transistor 200 can be suppressed, and variations in the electrical characteristics of transistor 200 within the substrate surface can be suppressed.

[0314] Therefore, a semiconductor device with little variation in transistor characteristics can be provided. Also, a semiconductor device with good reliability can be provided. Further, a semiconductor device having good electrical characteristics can be provided.

[0315] Also, microwave treatment may be performed after the formation of insulating film 250A. Also, by performing microwave treatment after the formation of insulating film 250A, microwave treatment may not be performed after the formation of insulating film 250B.

[0316] Also, after the formation of insulating film 250A and after the microwave treatment after the formation of insulating film 250B respectively, heat treatment may be performed while maintaining a reduced pressure state. By performing such treatment, hydrogen in insulating film 250A, insulating film 250B, oxide 230b, and oxide 230a can be efficiently removed. Also, a part of the hydrogen may be gettered by conductor 242 (conductor 242a and conductor 242b). Alternatively, the step of performing heat treatment while maintaining a reduced pressure state after microwave treatment may be repeated a plurality of times. By repeatedly performing heat treatment, hydrogen in insulating film 250A, oxide 230b, and oxide 230a can be removed more efficiently. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0317] In addition, by performing microwave treatment to modify the film quality of the insulating films 250A and 250B, diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in subsequent processes such as film formation of the conductive film that becomes the conductor 260, or in post-treatments such as heat treatment, diffusion of hydrogen, water, impurities, etc. into the oxide 230b, oxide 230a, etc. via the insulator 250 can be suppressed.

[0318] Next, the conductive film that becomes the conductor 260a and the conductive film that becomes the conductor 260b are formed in sequence. The film formation of the conductive film that becomes the conductor 260a and the conductive film that becomes the conductor 260b can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc. In the present embodiment, the conductive film that becomes the conductor 260a is formed using the ALD method, and the conductive film that becomes the conductor 260b is formed using the CVD method.

[0319] Next, by performing CMP treatment to polish the insulating film 250A, insulating film 250B, the conductive film that becomes the conductor 260a, and the conductive film that becomes the conductor 260b until the insulator 280 is exposed, the insulator 250a, insulator 250b, and conductor 260 (conductor 260a and conductor 260b) are formed (see FIGS. 18A to 18D). Thereby, the insulator 250 is disposed so as to cover the opening reaching the oxide 230b and the inner walls (side walls and bottom surface) of the groove portion of the oxide 230b. Also, the conductor 260 is disposed so as to fill the above opening and the above groove portion via the insulator 250.

[0320] Next, heat treatment may be performed under the same conditions as the above heat treatment. In the present embodiment, treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. By this heat treatment, the moisture concentration and hydrogen concentration in the insulator 250 and in the insulator 280 can be reduced. Note that after the above heat treatment, the film formation of the insulator 282 may be continuously performed without exposing to the atmosphere.

[0321] Next, insulator 282a and insulator 282b are successively formed on insulator 250, conductor 260, and insulator 280 (see FIGS. 19A to 19D). The film formation of insulator 282a and insulator 282b can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The film formation of insulator 282a and insulator 282b is preferably performed using a sputtering method. By using a sputtering method that does not require hydrogen in the film formation gas, the hydrogen concentration in insulator 282a and insulator 282b can be reduced.

[0322] In the present embodiment, as insulator 282a and insulator 282b, aluminum oxide is formed by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Also, the RF power applied to the substrate is 1.86 W / cm 2 shall be as follows. Preferably, it shall be 0 W / cm 2 or more and 0.31 W / cm 2 or less. By reducing the RF power, the amount of oxygen injected into insulator 280 can be suppressed. In the present embodiment, insulator 282a is formed with the RF power applied to the substrate being 0 W / cm 2 and insulator 282b is formed with the RF power applied to the substrate being 0.31 W / cm 2 .

[0323] Next, insulator 282a, insulator 282b, insulator 280, insulator 272, insulator 222, and insulator 216 are processed until reaching the upper surface of insulator 214 (see FIGS. 20A to 20D). This processing may use wet etching, but dry etching is more preferable for fine processing.

[0324] Next, heat treatment may be performed. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. Also, the heat treatment temperature is preferably lower than the heat treatment temperature performed after the formation of the oxide film 243A. Note that the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas. By performing the heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the insulator 280 formed by processing the insulator 282a, the insulator 282b, the insulator 280, the insulator 272, the insulator 222, and the insulator 216. In addition, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside. Note that hydrogen bonded to oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.

[0325] Next, an insulator 283 is formed on the insulator 282b (see FIGS. 21A to 21D). The film formation of the insulator 283 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The film formation of the insulator 283 is preferably performed using a sputtering method. By using a sputtering method that does not require hydrogen as a film formation gas, the hydrogen concentration in the insulator 283 can be reduced. Also, the insulator 283 may be multilayered. For example, silicon nitride may be formed by a sputtering method, and silicon nitride may be formed on the silicon nitride by an ALD method. By surrounding the transistor 200 with the insulator 283 and the insulator 214 having high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside.

[0326] Next, an insulator 274 is formed on the insulator 283. The film formation of the insulator 274 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxide is formed as the insulator 274 by a CVD method.

[0327] Next, by polishing the insulator 274 by CMP processing until the insulator 283 is exposed, the upper surface of the insulator 274 is planarized (see FIGS. 22A to 22D). By this CMP processing, a part of the upper surface of the insulator 283 may be removed.

[0328] Next, an insulator 284 is formed on the insulator 274 and on the insulator 283 (see FIGS. 22A to 22D). The film formation of the insulator 284 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The film formation of the insulator 284 is preferably performed using a sputtering method. By using a sputtering method that does not require hydrogen in the film formation gas, the hydrogen concentration in the insulator 284 can be reduced.

[0329] In the present embodiment, as the insulator 284, aluminum oxide is formed by a pulsed DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and the film quality can be improved. Also, the RF power applied to the substrate is 0.62 W / cm 2 The following shall be adopted. Preferably, 0 W / cm 2 or more and 0.31 W / cm 2 or less. Also, the RF power applied to the substrate is preferably greater than the RF power applied to the substrate during the film formation of the insulator 282.

[0330] Next, openings reaching the conductor 242 are formed in the insulator 271, the insulator 272, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 (see FIGS. 22A and 22B). The formation of the openings may be performed using a lithography method. Note that in FIG. 22A, the shape of the opening is circular in a top view, but it is not limited thereto. For example, the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are rounded in a top view.

[0331] Next, a dielectric film that will become the dielectric 241 is formed, and the dielectric film is anisotropically etched to form the dielectric 241. (See FIG. 22B.). The formation of the dielectric film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the dielectric film, it is preferable to use a dielectric film having a function of suppressing oxygen permeation. For example, it is preferable to form aluminum oxide using the ALD method. Alternatively, it is preferable to form silicon nitride using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0332] Also, as the anisotropic etching of the dielectric film that will become the dielectric 241, for example, a dry etching method or the like can be used. By providing the dielectric 241 on the sidewall portion of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 240a and the conductor 240b to be formed next can be prevented. In addition, it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240a and the conductor 240b.

[0333] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film preferably has a laminated structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. The formation of the conductive film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0334] Next, by performing CMP processing, a part of the conductive film that will become the conductor 240a and the conductor 240b is removed, and the upper surface of the dielectric 284 is exposed. As a result, the conductor 240a and the conductor 240b having a flat upper surface can be formed by the remaining conductive film only in the opening (see FIG. 22B.). Note that a part of the upper surface of the dielectric 284 may be removed by the CMP processing.

[0335] Next, a conductive film that will become the conductor 246 is formed. The formation of the conductive film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0336] Next, the conductive film that will become the conductor 246 is processed by a lithography method to form a conductor 246a that contacts the upper surface of the conductor 240a and a conductor 246b that contacts the upper surface of the conductor 240b. At this time, a part of the insulator 284 in a region where the conductor 246a and the conductor 246b do not overlap with the insulator 284 may be removed.

[0337] Next, an insulator 286 is formed on the conductor 246 and on the insulator 284. The formation of the insulator 286 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Also, the insulator 286 may be multilayered. For example, silicon nitride may be formed using a sputtering method, and then silicon nitride may be formed on the silicon nitride using a CVD method.

[0338] As described above, a semiconductor device having the transistor 200 shown in FIGS. 1A to 1D can be manufactured. As shown in FIGS. 7A to 22D, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device according to the present embodiment.

[0339] <Microwave processing apparatus> Hereinafter, a microwave processing apparatus that can be used in the method for manufacturing the semiconductor device will be described.

[0340] First, the configuration of a manufacturing apparatus with less impurity contamination during the manufacture of a semiconductor device or the like will be described with reference to FIGS. 23 to 26.

[0341] FIG. 23 schematically shows a top view of a single-sheet multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmospheric-side substrate supply chamber 2701 having a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, an atmospheric-side substrate transfer chamber 2702 for transferring the substrate from the atmospheric-side substrate supply chamber 2701, a load lock chamber 2703a for loading the substrate and switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading the substrate and switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring the substrate in a vacuum, and chambers 2706a, 2706b, 2706c, and 2706d.

[0342] Further, the atmospheric-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704. The transfer chamber 2704 is connected to the chambers 2706a, 2706b, 2706c, and 2706d.

[0343] Note that a gate valve GV is provided at the connection part of each chamber, and each chamber can be independently maintained in a vacuum state except for the atmospheric-side substrate supply chamber 2701 and the atmospheric-side substrate transfer chamber 2702. Further, a transfer robot 2763a is provided in the atmospheric-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. The substrate can be transferred in the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b.

[0344] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 Pa or less. Also, the partial pressure of gas molecules (atoms) having a mass-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa. Also, the partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Below Pa, preferably 1×10 -5 Below Pa, more preferably 3×10 -6 Below Pa.

[0345] Note that the total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0346] Also, the transfer chamber 2704 and each chamber are preferably configured to have little external leakage or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. Also, for example, the leak rate of gas molecules (atoms) with m / z of 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6Pa·m 3 shall be below / s.

[0347] Regarding the leak rate, it may be derived from the total pressure and partial pressure measured using the above-mentioned mass spectrometer. The leak rate depends on external leaks and internal leaks. An external leak is the inflow of gas from outside the vacuum system due to minute holes, poor seals, etc. An internal leak is caused by leakage from partitions such as valves within the vacuum system or the release gas from internal members. In order to make the leak rate below the above-mentioned numerical value, it is necessary to take countermeasures from both aspects of external leaks and internal leaks.

[0348] For example, the opening and closing parts of the transfer chamber 2704 and each chamber may be sealed with a metal gasket. It is preferable to use a metal coated with iron fluoride, aluminum oxide, or chromium oxide for the metal gasket. The metal gasket has higher adhesion compared to an O-ring and can reduce external leaks. Also, by using the passivation of the metal coated with iron fluoride, aluminum oxide, chromium oxide, etc., the release gas containing impurities released from the metal gasket can be suppressed, and internal leaks can be reduced.

[0349] Also, as the members constituting the manufacturing apparatus 2700, use aluminum, chromium, titanium, zirconium, nickel, or vanadium that emits less release gas containing impurities. Alternatively, the above-mentioned metal that emits less release gas containing impurities may be coated with an alloy containing iron, chromium, nickel, etc. and used. Alloys containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the release gas can be reduced.

[0350] Alternatively, the members of the above-mentioned manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, etc.

[0351] The members of the manufacturing apparatus 2700 are preferably composed of only metal as much as possible. For example, even when installing a viewing window composed of quartz or the like, the surface should be thinly coated with iron fluoride, aluminum oxide, chromium oxide, etc. to suppress the released gas.

[0352] The adsorbates present in the transfer chamber 2704 and each chamber are adsorbed on the inner wall or the like and thus do not affect the pressure in the transfer chamber 2704 and each chamber, but they cause gas release when the transfer chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with a high exhaust capacity to desorb the adsorbates present in the transfer chamber 2704 and each chamber as much as possible and evacuate them in advance. In addition, in order to promote the desorption of the adsorbates, the transfer chamber 2704 and each chamber may be baked. By baking, the desorption rate of the adsorbates can be increased by about 10 times. The baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbates are removed while introducing an inert gas into the transfer chamber 2704 and each chamber, the desorption rate of water or the like that is difficult to desorb by simply evacuating can be further increased. In addition, by heating the introduced inert gas to about the same temperature as the baking temperature, the desorption rate of the adsorbates can be further increased. Here, it is preferable to use a noble gas as the inert gas.

[0353] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as heated rare gas or oxygen, and then perform a process of evacuating the transfer chamber 2704 and each chamber again after a certain period of time. By introducing the heated gas, the adsorbed substances in the transfer chamber 2704 and each chamber can be desorbed, and the impurities present in the transfer chamber 2704 and each chamber can be reduced. This process is effectively repeated in the range of 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C or higher and 400°C or lower, preferably 50°C or higher and 200°C or lower, the pressure in the transfer chamber 2704 and each chamber is set to 0.1 Pa or higher and 10 kPa or lower, preferably 1 Pa or higher and 1 kPa or lower, more preferably 5 Pa or higher and 100 Pa or lower, and the period for maintaining the pressure is 1 minute or longer and 300 minutes or shorter, preferably 5 minutes or longer and 120 minutes or shorter. Then, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes or longer and 300 minutes or shorter, preferably 10 minutes or longer and 120 minutes or shorter.

[0354] Next, the chamber 2706b and the chamber 2706c will be described with reference to the cross-sectional schematic diagram shown in FIG. 24.

[0355] The chamber 2706b and the chamber 2706c are chambers capable of performing microwave treatment on the object to be processed, for example. Note that the only difference between the chamber 2706b and the chamber 2706c is the atmosphere during the microwave treatment. Since the other configurations are common, they will be described together below.

[0356] Chambers 2706b and 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also, outside Chambers 2706b and 2706c, etc., there are provided a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0357] The high-frequency generator 2803 is connected to the mode converter 2805 via the waveguide 2804. The mode converter 2805 is connected to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is arranged in contact with the dielectric plate 2809. Also, the gas supply source 2801 is connected to the mode converter 2805 via the valve 2802. Then, gas is sent to Chambers 2706b and 2706c by the mode converter 2805, the waveguide 2807, and the gas pipe 2806 passing through the dielectric plate 2809. Also, the vacuum pump 2817 has a function of exhausting gas, etc., from Chambers 2706b and 2706c via the valve 2818 and the exhaust port 2819. Also, the high-frequency power supply 2816 is connected to the substrate holder 2812 via the matching box 2815.

[0358] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically chucking or mechanically chucking the substrate 2811. Also, it has a function as an electrode to which power is supplied from the high-frequency power supply 2816. Also, it has a heating mechanism 2813 inside and has a function of heating the substrate 2811.

[0359] As the vacuum pump 2817, for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used. Further, in addition to the vacuum pump 2817, a cryotrap may be used. It is particularly preferable to use a cryopump and a cryotrap because water can be efficiently exhausted.

[0360] Further, as the heating mechanism 2813, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs a heat treatment using a high-temperature gas. As the gas, an inert gas is used.

[0361] Further, the gas supply source 2801 may be connected to the purification machine via a mass flow controller. As the gas, a gas having a dew point of -80°C or lower, preferably -100°C or lower is preferably used. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0362] As the dielectric plate 2809, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) may be used. Further, another protective layer may be formed on the surface of the dielectric plate 2809. As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide may be used. Since the dielectric plate 2809 will be exposed to a particularly high-density region of the high-density plasma 2810 described later, damage can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.

[0363] The high-frequency generator 2803 has a function of generating microwaves, for example, in the range of 0.3 GHz or higher and 3.0 GHz or lower, 0.7 GHz or higher and 1.1 GHz or lower, or 2.2 GHz or higher and 2.8 GHz or lower. The microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as the TE mode are converted to the TEM mode. Then, the microwaves are transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and high-density plasma 2810 can be generated. In the high-density plasma 2810, there are ions and radicals corresponding to the gas species supplied from the gas supply source 2801. For example, oxygen radicals exist.

[0364] At this time, the substrate 2811 can be modified, such as the film on the substrate 2811, by the ions and radicals generated by the high-density plasma 2810. In some cases, it is preferable to apply a bias to the substrate 2811 side using the high-frequency power supply 2816. For the high-frequency power supply 2816, an RF (Radio Frequency) power supply with a frequency such as 13.56 MHz or 27.12 MHz can be used, for example. By applying a bias to the substrate side, the ions in the high-density plasma 2810 can efficiently reach the depth of the openings such as the film on the substrate 2811.

[0365] For example, in the chamber 2706b or the chamber 2706c, oxygen can be introduced from the gas supply source 2801 to perform oxygen radical treatment using the high-density plasma 2810.

[0366] Next, the chambers 2706a and 2706d will be described using the cross-sectional schematic diagram shown in FIG. 25.

[0367] Chambers 2706a and 2706d are chambers that can irradiate an object to be processed with electromagnetic waves, for example. Note that chambers 2706a and 2706d only differ in the type of electromagnetic waves. Since there are many common parts in other configurations, they will be described together below.

[0368] Chambers 2706a and 2706d have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Further, outside chambers 2706a and 2706d, etc., a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0369] The gas supply source 2821 is connected to the gas inlet 2823 via the valve 2822. The vacuum pump 2828 is connected to the exhaust port 2830 via the valve 2829. The lamp 2820 is disposed facing the substrate holder 2825. The substrate holder 2825 has a function of holding the substrate 2824. Further, the substrate holder 2825 has a heating mechanism 2826 inside and has a function of heating the substrate 2824.

[0370] As the lamp 2820, for example, a light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light may be used. For example, a light source having a function of emitting electromagnetic waves having a peak at a wavelength of 10 nm or more and 2500 nm or less, 500 nm or more and 2000 nm or less, or 40 nm or more and 340 nm or less may be used.

[0371] For example, as the lamp 2820, a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp may be used.

[0372] For example, part or all of the electromagnetic waves radiated from lamp 2820 can be absorbed by substrate 2824, thereby modifying a film or the like on substrate 2824. For example, generation or reduction of defects, or removal of impurities can be achieved. Note that when performing this while heating substrate 2824, generation or reduction of defects, or removal of impurities can be efficiently achieved.

[0373] Alternatively, for example, the electromagnetic waves radiated from lamp 2820 may be used to generate heat in substrate holder 2825 and heat substrate 2824. In that case, heating mechanism 2826 need not be provided inside substrate holder 2825.

[0374] For vacuum pump 2828, refer to the description of vacuum pump 2817. Also, for heating mechanism 2826, refer to the description of heating mechanism 2813. Also, for gas supply source 2821, refer to the description of gas supply source 2801.

[0375] The microwave processing apparatus that can be used in this embodiment is not limited to the above. The microwave processing apparatus 2900 shown in FIG. 26 can be used. The microwave processing apparatus 2900 includes a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas tube 2806, a vacuum pump 2817, and a valve 2818. Further, the microwave processing apparatus 2900 includes a substrate holder 2902 that holds a plurality of substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901. Further, the microwave processing apparatus 2900 may include heating means 2903 outside the quartz tube 2901.

[0376] The microwave generated by the high-frequency generator 2803 is irradiated onto the substrate provided in the quartz tube 2901 via the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 via the valve 2818, and can adjust the pressure inside the quartz tube 2901. Also, the gas supply source 2801 is connected to the gas tube 2806 via the valve 2802, and can introduce a desired gas into the quartz tube 2901. Further, the substrate 2811 inside the quartz tube 2901 can be heated to a desired temperature by the heating means 2903. Alternatively, the gas supplied from the gas supply source 2801 may be heated by the heating means 2903. The microwave processing apparatus 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Also, after heating the substrate 2811, a microwave treatment can be performed. Also, after performing a microwave treatment on the substrate 2811, a heat treatment can be performed.

[0377] All of the substrates 2811_1 to 2811_n may be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Also, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because when performing microwave processing or heat treatment, a plurality of processing substrates are uniformly processed, and variations between the processing substrates can be reduced. For example, it is preferable to arrange a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804, because this can prevent the processing substrate from being directly exposed to microwaves.

[0378] By using the above manufacturing apparatus, it is possible to perform film modification and the like while suppressing the mixing of impurities into the object to be processed.

[0379] <Modification Example of Semiconductor Device> Hereinafter, an example of a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 2A to 2D.

[0380] FIG. 2A shows a top view of the semiconductor device. FIG. 2B is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 shown in FIG. 2A. FIG. 2C is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in FIG. 2A. FIG. 2D is a cross-sectional view corresponding to the portion indicated by the dashed line A5 - A6 in FIG. 2A. In the top view of FIG. 2A, some elements are omitted for clarity of the figure.

[0381] In the semiconductor device shown in FIGS. 2A to 2D, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that also in this section, as the constituent materials of the semiconductor device, the materials described in detail in <Configuration Example of Semiconductor Device> can be used.

[0382] The semiconductor device shown in FIGS. 2A to 2D is a modified example of the semiconductor device shown in FIGS. 1A to 1D. The semiconductor device shown in FIGS. 2A to 2D is different from the semiconductor device shown in FIGS. 1A to 1D in that the insulator 283 is in contact with a part of the upper surface of the insulator 212. Therefore, the transistor 200 is disposed within the region sealed by the insulator 283 and the insulator 212. With the above configuration, it is possible to suppress hydrogen contained outside the sealed region from mixing into the sealed region. Also, in the transistor 200 shown in FIGS. 2A to 2D, a configuration in which the insulator 212 and the insulator 283 are provided as a single layer is shown, but the present invention is not limited thereto. For example, each of the insulator 212 and the insulator 283 may be provided with a laminated structure of two or more layers.

[0383] <Application Example of Semiconductor Device> Hereinafter, with reference to FIGS. 27A and 27B, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention, which is different from those shown in the previous <configuration example of a semiconductor device> and the previous <modified example of a semiconductor device>, will be described. In the semiconductor device shown in FIGS. 27A and 27B, the same reference numerals are assigned to the structures having the same functions as those of the semiconductor device (see FIGS. 1A to 1D) shown in the <configuration example of a semiconductor device>. In this section, the materials described in detail in the <configuration example of a semiconductor device> can be used for the constituent materials of the transistor 200.

[0384] FIGS. 27A and 27B show a configuration in which transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 214. In FIGS. 27A and 27B, the transistors 200_1 to 200_n appear to be arranged in the channel length direction, but this is not restrictive. The transistors 200_1 to 200_n may be arranged in the channel width direction or may be arranged in a matrix. Also, depending on the design, they may be arranged without regularity.

[0385] As shown in FIG. 27A, outside the transistors 200_1 to 200_n, a portion where the insulator 283 and the insulator 214 are in contact (hereinafter sometimes referred to as a sealing portion 265) is formed. The sealing portion 265 is formed so as to surround the transistors 200_1 to 200_n. With such a structure, the transistors 200_1 to 200_n can be wrapped by the insulator 283 and the insulator 214. Therefore, a plurality of transistors (also referred to as a transistor group) surrounded by the sealing portion 265 will be provided in plurality on the substrate.

[0386] Also, a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) may be provided overlapping the sealing portion 265. Since the above substrate is divided at the dicing line, the transistor group surrounded by the sealing portion 265 will be taken out as one chip.

[0387] Also, in FIG. 27A, an example in which transistors 200_1 to 200_n are surrounded by a single sealing portion 265 is shown, but the present invention is not limited to this. As shown in FIG. 27B, a configuration in which transistors 200_1 to 200_n are surrounded by a plurality of sealing portions may be employed. In FIG. 27B, transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0388] In this way, by adopting a configuration in which transistors 200_1 to 200_n are surrounded by a plurality of sealing portions, the contact area between insulator 283 and insulator 214 increases, so that the adhesion between insulator 283 and insulator 214 can be further improved. As a result, transistors 200_1 to 200_n can be more reliably sealed.

[0389] In this case, a dicing line may be provided overlapping sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0390] Note that, in the transistors shown in FIGS. 27A and 27B, an example of a configuration in which insulator 283 and insulator 214 are in contact is shown, but as shown in FIG. 2 and <Modification Example of Semiconductor Device>, a configuration in which insulator 283 and insulator 212 are in contact may be employed.

[0391] According to one aspect of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Also, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Also, according to one aspect of the present invention, a low-power-consumption semiconductor device can be provided.

[0392] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with other configurations, methods shown in this embodiment, configurations, methods shown in other embodiments, or configurations, methods shown in examples.

[0393] (Embodiment 2) In this embodiment, one form of the semiconductor device will be described with reference to FIGS. 28 to 33.

[0394] [Memory device 1] An example of a semiconductor device (memory device) according to one aspect of the present invention is shown in FIG. 28. In the semiconductor device of one aspect of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor element 100 is provided above the transistor 300 and the transistor 200. Note that, as the transistor 200, the transistor 200 described in the previous embodiment can be used.

[0395] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, by using this for a memory device, it is possible to hold the stored content for a long time. That is, since a refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

[0396] In the semiconductor device shown in FIG. 28, a wiring 1001 is electrically connected to the source of the transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. Also, a wiring 1003 is electrically connected to one of the source and drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor element 100, and a wiring 1005 is electrically connected to the other of the electrodes of the capacitor element 100.

[0397] In addition, the memory device shown in FIG. 28 can form a memory cell array by being arranged in a matrix.

[0398] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. The transistor 300 may be either p-channel type or n-channel type.

[0399] Here, in the transistor 300 shown in FIG. 28, the semiconductor region 313 (a part of the substrate 311) where the channel is formed has a convex shape. Also, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. Note that the conductor 316 may use a material for adjusting the work function. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN-type transistor. Note that an insulator that functions as a mask for forming the convex portion may be in contact with the upper portion of the convex portion. Here, a case where a part of the semiconductor substrate is processed to form a convex portion is shown, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0400] Note that the transistor 300 shown in FIG. 28 is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0401] <Capacitor element 100> The capacitor element 100 is provided above the transistor 200. The capacitor element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, it is preferable to use an insulator that can be used as the insulator 286 shown in the above embodiment for the insulator 130.

[0402] Also, for example, the conductor 112 and the conductor 110 can be formed simultaneously. Note that the conductor 112 has a function as a plug or wiring that is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300.

[0403] In FIG. 28, the conductor 112 and the conductor 110 are shown as a single-layer structure, but the present invention is not limited to this configuration, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property, and a conductor having high adhesiveness to the conductor having a barrier property and the conductor having high conductivity may be formed between the conductor having a barrier property and the conductor having high conductivity.

[0404] Also, the insulator 130 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and may be provided in a laminated or single-layer form.

[0405] For example, it is preferable to use a laminated structure of a material having a high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor element 100 can secure a sufficient capacitance by having a high dielectric constant (high-k) insulator, and can improve the dielectric strength by having an insulator having a high dielectric strength, thereby suppressing the electrostatic breakdown of the capacitor element 100.

[0406] Note that examples of the high dielectric constant (high-k) material (material having a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, or nitrides having silicon and hafnium.

[0407] On one hand, examples of materials with high dielectric breakdown strength (materials with low relative permittivity) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0408] <Wiring layer> A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may sometimes be given the same reference numeral collectively for multiple structures. Also, in this specification, etc., the wiring and the plug electrically connected to the wiring may be an integral body. That is, there are cases where a part of the conductor functions as wiring and cases where a part of the conductor functions as a plug.

[0409] For example, on the transistor 300, as an interlayer film, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated and provided in order. Also, a capacitor element 100, or conductors 328 and 330 electrically connected to the transistor 200, etc. are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductors 328 and 330 function as plugs or wiring.

[0410] Also, the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0411] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 28, an insulator 350, an insulator 352, and an insulator 354 are laminated and provided in order. Also, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.

[0412] Similarly, in the insulators 210, 212, 214, and 216, conductors such as the conductor 218 and the conductors (conductors 205) constituting the transistor 200 are embedded. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the capacitor element 100 or the transistor 300. Further, an insulator 150 is provided on the conductor 120 and the insulator 130.

[0413] Here, similarly to the insulator 241 shown in the above embodiment, an insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner walls of the openings formed in the insulators 210, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may be formed in contact with the side surface of the conductor 205 in some cases.

[0414] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride may be used. Since the insulator 217 is provided in contact with the insulators 210, 212, 214, and 222, it is possible to suppress impurities such as water or hydrogen from the insulators 210 or 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is suitable because it has high blocking properties against hydrogen. Also, it is possible to prevent oxygen contained in the insulator 210 or 216 from being absorbed by the conductor 218.

[0415] The insulator 217 can be formed in the same manner as the insulator 241. For example, silicon nitride may be deposited using the PEALD method, and an opening reaching the conductor 356 may be formed using anisotropic etching.

[0416] Examples of insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. that have insulating properties.

[0417] For example, by using a material with a low relative permittivity for the insulator that functions as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0418] For example, it is preferable that the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. have an insulator with a low relative permittivity. For example, the insulator preferably has silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores, and resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a low relative permittivity can be obtained by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, or acrylic.

[0419] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 214, the insulator 212, the insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

[0420] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a laminate. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, silicon oxynitride or silicon nitride can be used.

[0421] As a conductor that can be used for wiring and plugs, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0422] For example, as the conductor 328, conductor 330, conductor 356, conductor 218, conductor 112, etc., a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials can be used in a single layer or in a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0423] <Wiring or plug of the layer provided with the oxide semiconductor> In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In this case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and a conductor provided on the insulator having the excess oxygen region.

[0424] For example, in FIG. 28, an insulator 241 may be provided between an insulator 280 having excess oxygen and a conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the transistor 200 can have a structure sealed by an insulator having a barrier property.

[0425] That is, by providing the insulator 241, it is possible to suppress the absorption of the excess oxygen contained in the insulator 280 by the conductor 240. Further, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, into the transistor 200 via the conductor 240.

[0426] As the insulator 241, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen may be used. For example, it is preferable to use silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because it has a high blocking property against hydrogen. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can also be used.

[0427] Also, as shown in the above embodiment, the transistor 200 may be configured to be sealed with the insulator 212, the insulator 214, the insulator 282, and the insulator 283. By adopting such a configuration, it is possible to reduce the mixing of hydrogen contained in the insulator 274, the insulator 150, etc. into the insulator 280, etc.

[0428] Here, the conductor 240 penetrates the insulators 283 and 282, and the conductor 218 penetrates the insulators 214 and 212. However, as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. Thereby, hydrogen mixed inside the insulators 212, 214, 282, and 283 can be reduced via the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, and impurities such as hydrogen contained in the insulator 274 and the like can be reduced from entering from the outside.

[0429] <Dicing line> Hereinafter, a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in chip form by dividing a large-area substrate for each semiconductor element will be described. As a dividing method, for example, first, a groove (dicing line) for dividing the semiconductor element is formed in the substrate, and then cutting is performed at the dicing line to divide (split) into a plurality of semiconductor devices.

[0430] Here, for example, as shown in FIG. 28, it is preferable to design such that the region where the insulator 283 and the insulator 214 are in contact overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 272, 222, and 216 in the vicinity of the region that becomes the dicing line provided at the outer edge of the memory cell having a plurality of transistors 200.

[0431] That is, at the openings provided in the insulators 282, 280, 272, 222, and 216, the insulator 214 and the insulator 283 are in contact.

[0432] Further, for example, openings may be provided in insulator 282, insulator 280, insulator 272, insulator 222, insulator 216, and insulator 214. With such a configuration, insulator 212 and insulator 283 are in contact with each other at the openings provided in insulator 282, insulator 280, insulator 272, insulator 222, insulator 216, and insulator 214. At this time, insulator 212 and insulator 283 may be formed using the same material and the same method. By providing insulator 212 and insulator 283 using the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use silicon nitride.

[0433] With this structure, transistor 200 can be wrapped by insulator 212, insulator 214, insulator 282, and insulator 283. Since at least one of insulator 212, insulator 214, insulator 282, and insulator 283 has a function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into a plurality of chips by dividing the substrate for each circuit region in which the semiconductor device shown in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface direction of the divided substrate and diffusing into transistor 200.

[0434] Further, with this structure, it is possible to prevent the excess oxygen in insulator 280 and insulator 224 from diffusing to the outside. Therefore, the excess oxygen in insulator 280 and insulator 224 is efficiently supplied to the oxide in which the channel in transistor 200 is formed. By this oxygen, the oxygen deficiency in the oxide in which the channel in transistor 200 is formed can be reduced. As a result, the oxide in which the channel in transistor 200 is formed can be an oxide semiconductor having stable characteristics with a low defect level density. That is, the variation in the electrical characteristics of transistor 200 can be suppressed and the reliability can be improved.

[0435] In the memory device shown in FIG. 28, the shape of the capacitance element 100 is planar, but the memory device shown in the present embodiment is not limited to this. For example, as shown in FIG. 29, the shape of the capacitance element 100 may be cylindrical. Note that the configuration of the memory device shown in FIG. 29 below the insulator 150 is the same as that of the semiconductor device shown in FIG. 28.

[0436] The capacitance element 100 shown in FIG. 29 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a part of the conductor 115, the insulator 145, and the conductor 125 is disposed in the opening formed in the insulator 150 and the insulator 142.

[0437] The conductor 115 functions as a lower electrode of the capacitance element 100, the conductor 125 functions as an upper electrode of the capacitance element 100, and the insulator 145 functions as a dielectric of the capacitance element 100. The capacitance element 100 is configured such that the upper electrode and the lower electrode face each other with the dielectric interposed therebetween not only on the bottom surface but also on the side surface in the openings of the insulator 150 and the insulator 142, and the capacitance per unit area can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitance element 100 can be. By increasing the capacitance per unit area of the capacitance element 100 in this way, miniaturization or high integration of the semiconductor device can be promoted.

[0438] As the insulator 152, an insulator that can be used for the insulator 280 may be used. In addition, the insulator 142 preferably functions as an etching stopper when forming the opening of the insulator 150, and an insulator that can be used for the insulator 214 may be used.

[0439] The shape of the openings formed in the insulator 150 and the insulator 142, as viewed from above, may be a quadrilateral, a polygon other than a quadrilateral, a shape in which the corners are curved in a polygon, or a circular shape including an ellipse. Here, in a top view, it is preferable that the area of the opening overlapping with the transistor 200 is larger. By adopting such a configuration, the occupied area of the semiconductor device having the capacitor element 100 and the transistor 200 can be reduced.

[0440] The conductor 115 is disposed in contact with the openings formed in the insulator 142 and the insulator 150. The upper surface of the conductor 115 preferably substantially coincides with the upper surface of the insulator 142. Also, the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by a film formation method such as an ALD method or a CVD method. For example, a conductor that can be used for the conductor 205 may be used.

[0441] The insulator 145 is disposed so as to cover the conductor 115 and the insulator 142. For example, it is preferable to form the insulator 145 by a film formation method such as an ALD method or a CVD method. The insulator 145 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and can be provided in a laminated or single-layer form. For example, as the insulator 145, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0442] Also, for the insulator 145, it is preferable to use a material having a high dielectric breakdown strength such as silicon oxynitride or a high dielectric constant (high-k) material. Alternatively, a laminated structure of a material having a high dielectric breakdown strength and a high dielectric constant (high-k) material may be used.

[0443] Note that, as high-k (high dielectric constant) materials (materials with a high relative dielectric constant), there are gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, and the like. By using such high-k materials, even if the insulator 145 is thickened, the capacitance of the capacitor element 100 can be sufficiently ensured. By thickening the insulator 145, the leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

[0444] On the other hand, as materials with high dielectric breakdown strength, there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, resins, and the like. For example, a dielectric film laminated in the order of silicon nitride (SiN x ) formed by using the PEALD method, silicon oxide (SiO x ) formed by using the PEALD method, and silicon nitride (SiN x ) formed by using the PEALD method can be used. Alternatively, a dielectric film laminated in the order of zirconium oxide, silicon oxide formed by using the ALD method, and zirconium oxide can be used. By using such a dielectric with high dielectric breakdown strength, the dielectric breakdown strength is improved, and the dielectric breakdown of the capacitor element 100 can be suppressed.

[0445] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. Further, the conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by using the ALD method, the CVD method, or the like. For example, a conductor that can be used for the conductor 205 may be used.

[0446] Further, the conductor 153 is provided on the insulator 154 and covered with the insulator 156. The conductor 153 may be a conductor that can be used for the conductor 112, and the insulator 156 may be an insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the upper surface of the conductor 140 and functions as a terminal of the capacitor element 100, the transistor 200, or the transistor 300.

[0447] [Storage device 2] An example of a semiconductor device (storage device) according to an aspect of the present invention is shown in FIGS. 30A and 30B.

[0448] <Configuration example 1 of memory device> FIG. 30A is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 shown in FIG. 30A has a capacitor device 292 in addition to the transistor 200 shown in FIGS. 1A to 1D. FIG. 30A corresponds to a cross-sectional view in the channel length direction of the transistor 200.

[0449] The capacitor device 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with the upper surface and side surfaces of the insulator 271b and the side surface of the conductor 242b, and a conductor 294 on the insulator 272. That is, the capacitor device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. Note that one of the pair of electrodes included in the capacitor device 292, that is, the conductor 242b, can also serve as the source electrode of the transistor. In addition, the dielectric layer included in the capacitor device 292 can also serve as the protective layer provided for the transistor, that is, the insulator 271 and the insulator 272. Therefore, in the manufacturing process of the capacitor device 292, a part of the manufacturing process of the transistor can be shared, so that a highly productive semiconductor device can be obtained. Further, since one of the pair of electrodes included in the capacitor device 292, that is, the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area where the transistor and the capacitor device are arranged.

[0450] As the conductor 294, for example, a material that can be used for the conductor 242 may be used.

[0451] <Configuration Example 2 of Memory Device> FIG. 30B is a cross-sectional view of a semiconductor device having a memory device 290, which is different from the structure shown in FIG. 30A. The memory device 290 shown in FIG. 30B has a capacitor device 292 in addition to the transistor 200 shown in FIGS. 1A to 1D. Here, a part of the capacitor device 292 shown in FIG. 30B is provided in openings formed in the insulator 280, the insulator 272, and the insulator 271b, which is different from the capacitor device 292 shown in FIG. 30A. Note that FIG. 30B corresponds to a cross-sectional view in the channel length direction of the transistor 200.

[0452] The capacitor device 292 includes a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. Here, the insulator 293 and the conductor 294 are disposed in openings formed in the insulator 280, the insulator 272, and the insulator 271b. The insulator 293 is provided in contact with the bottom surface and the side wall of the opening. That is, the insulator 293 is in contact with the upper surface of the conductor 242b, the side surface of the insulator 271b, the side surface of the insulator 272, and the side surface of the insulator 280. Further, the insulator 293 is provided so as to form a concave portion along the shape of the opening. The conductor 294 is disposed in contact with the upper surface and the side surface of the insulator 293 so as to fill the concave portion. Note that the heights of the upper surfaces of the insulator 293 and the conductor 294 may be substantially the same as the heights of the upper surfaces of the insulator 280, the insulator 250, and the conductor 260.

[0453] Here, the conductor 242b functions as the lower electrode of the capacitor device 292, the conductor 294 functions as the upper electrode of the capacitor device 292, and the insulator 293 functions as the dielectric of the capacitor device 292. In this way, the capacitor device 292 constitutes a MIM capacitor. Note that one of the pair of electrodes of the capacitor device 292, that is, the conductor 242b, can also serve as the source electrode of the transistor. Therefore, in the manufacturing process of the capacitor device 292, a part of the manufacturing process of the transistor can be shared, so that a highly productive semiconductor device can be obtained. In addition, since the insulator 293 can be provided separately from the configuration of the transistor 200, the structure and material of the insulator 293 can be appropriately selected according to the performance required for the capacitor device 292. Also, since one of the pair of electrodes of the capacitor device 292, that is, the conductor 242b, also serves as the source electrode of the transistor, it is possible to reduce the area where the transistor and the capacitor device are arranged.

[0454] It is preferable to use a high dielectric constant (high-k) material for the insulator 293. Examples of high dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium. Also, as the insulator 293, a film obtained by laminating these high dielectric constant materials may be used. For example, as the insulator 293, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0455] Also, as the conductor 294, for example, a material that can be used for the conductor 260 may be used. Also, the conductor 294 may have a laminated structure similar to that of the conductor 260.

[0456] Note that the insulator 293 and the conductor 294 may be formed before the formation of the insulator 282, that is, before the process shown in FIG. 19. The insulator 293 and the conductor 294 can be formed in the same manner as the formation of the insulator 250 and the conductor 260. That is, openings are formed in the insulator 280, the insulator 272, and the insulator 271b, and a laminated film that will become the insulator 293 and the conductor 294 is formed so as to be embedded in the openings, and a part of the laminated film is removed using CMP processing to form the insulator 293 and the conductor 294.

[0457] <Modification Example of Memory Device> Hereinafter, with reference to FIGS. 31A, 31B, 32, and 33, an example of a semiconductor device having a transistor 200 and a capacitor device 292 according to an aspect of the present invention, which is different from that shown in the previous <Configuration Example 1 of Memory Device>, will be described. In the semiconductor devices shown in FIGS. 31A, 31B, 32, and 33, the same reference numerals are assigned to the structures having the same functions as the structures constituting the semiconductor devices (see FIG. 30A) shown in the previous embodiment and <Configuration Example 1 of Memory Device>. In this section, for the constituent materials of the transistor 200 and the capacitor device 292, the materials described in detail in the previous embodiment and <Configuration Example 1 of Memory Device> can be used. Also, in FIGS. 31A, 31B, 32, and 33, etc., the memory device shown in FIG. 30A is used as the memory device, but it is not limited thereto. For example, a memory device shown in FIG. 30B may be used.

[0458] <<Modification Example 1 of Memory Device>> Hereinafter, an example of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitor device 292a, and a capacitor device 292b according to an aspect of the present invention will be described with reference to FIG. 31A.

[0459] FIG. 31A is a cross-sectional view of a semiconductor device 600 in the channel length direction, which has a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b. Here, the capacitive device 292a includes a conductor 242a, an insulator 271a on the conductor 242a, an insulator 272 that contacts the upper surface of the insulator 271a, the side surfaces of the insulator 271a, and the side surfaces of the conductor 242a, and a conductor 294a on the insulator 272. The capacitive device 292b includes a conductor 242b, an insulator 271b on the conductor 242b, an insulator 272 that contacts the upper surface of the insulator 271b, the side surfaces of the insulator 271b, and the side surfaces of the conductor 242b, and a conductor 294b on the insulator 272.

[0460] As shown in FIG. 31A, the semiconductor device 600 has a line-symmetric configuration with the one-dot chain line of A3 - A4 as the axis of symmetry. One of the source electrode or drain electrode of the transistor 200a and one of the source electrode or drain electrode of the transistor 200b are configured such that the conductor 242c serves as both. An insulator 271c is provided on the conductor 242c. Also, a conductor 246 that functions as a wiring and a conductor 240 that also functions as a plug for connecting to the transistor 200a and the transistor 200b are configured to serve as both. By configuring the two transistors, the two capacitive devices, and the connection between the wiring and the plug as described above, a semiconductor device capable of miniaturization or high integration can be provided.

[0461] Regarding the respective configurations and effects of the transistor 200a, the transistor 200b, the capacitive device 292a, and the capacitive device 292b, the configuration example of the semiconductor device shown in FIG. 30A can be referred to.

[0462] <<Modification Example 2 of Memory Device>> In the above description, transistor 200a, transistor 200b, capacitor device 292a, and capacitor device 292b are given as configuration examples of the semiconductor device. However, the semiconductor device shown in this embodiment is not limited thereto. For example, as shown in FIG. 31B, a semiconductor device 600 and a semiconductor device having the same configuration as the semiconductor device 600 may be connected via a capacitance portion. In this specification, a semiconductor device having transistor 200a, transistor 200b, capacitor device 292a, and capacitor device 292b is referred to as a cell. Regarding the configurations of transistor 200a, transistor 200b, capacitor device 292a, and capacitor device 292b, the descriptions related to the above-mentioned transistor 200a, transistor 200b, capacitor device 292a, and capacitor device 292b can be referred to.

[0463] FIG. 31B is a cross-sectional view in which a semiconductor device 600 having transistor 200a, transistor 200b, capacitor device 292a, and capacitor device 292b and a cell having the same configuration as the semiconductor device 600 are connected via a capacitance portion.

[0464] As shown in FIG. 31B, a conductor 294b that functions as one electrode of the capacitor device 292b included in the semiconductor device 600 also serves as one electrode of the capacitor device of a semiconductor device 601 having the same configuration as the semiconductor device 600. Although not shown, a conductor 294a that functions as one electrode of the capacitor device 292a included in the semiconductor device 600 also serves as one electrode of the capacitor device of a semiconductor device adjacent in the A1 direction, that is, on the left side of the semiconductor device 600 in FIG. 31B. Also, the same configuration applies to the cells in the A2 direction on the right side of the semiconductor device 601, that is, in FIG. 31B. That is, a cell array (also referred to as a memory device layer) can be configured. By adopting such a configuration of the cell array, the interval between adjacent cells can be reduced, so that the projected area of the cell array can be reduced and high integration becomes possible. Also, by arranging the cell array configuration shown in FIG. 31B in a matrix, a matrix-shaped cell array can be configured.

[0465] As described above, by forming the transistor 200a, the transistor 200b, the capacitive device 292a, and the capacitive device 292b with the configuration shown in this embodiment, the area of the cell can be reduced, and miniaturization or high integration of the semiconductor device having the cell array can be achieved.

[0466] Also, the cell array may be configured to be stacked not only in a plane but also in layers. FIG. 32 shows a cross-sectional view of a configuration in which the cell array 610 is stacked in n layers. As shown in FIG. 32, by stacking a plurality of cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the occupied area of the cell array. That is, a 3D cell array can be configured.

[0467] <Modified Example 3 of Memory Device> FIG. 33 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0468] The memory device layers 415_1 to 415_4 each have a plurality of memory devices 420.

[0469] The memory device 420 is electrically connected to the memory device 420 included in different memory device layers 415 and the transistor 200T included in the transistor layer 413 via a conductor 424 and a conductor 205.

[0470] The memory unit 470 is sealed by an insulator 212, an insulator 214, an insulator 282, and an insulator 283 (hereinafter referred to as a sealing structure for convenience). An insulator 274 is provided around the insulator 283. A conductor 440 is provided on the insulator 274, the insulator 283, and the insulator 212 and is electrically connected to the element layer 411.

[0471] In addition, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen by heating. Or, the insulator 280 has an excess oxygen region.

[0472] Note that the insulator 212 and the insulator 283 are preferably made of a material having a high hydrogen blocking property. Also, the insulator 214 and the insulator 282 are preferably made of a material having a function of capturing or fixing hydrogen.

[0473] For example, materials having a high hydrogen blocking property include silicon nitride or silicon oxynitride. Also, materials having a function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0474] Note that there is no particular limitation on the crystal structure of the materials used for the insulator 212, the insulator 214, the insulator 282, and the insulator 283, but it may have an amorphous or crystalline structure. For example, it is preferable to use an amorphous aluminum oxide film as a material having a function of capturing or fixing hydrogen. Amorphous aluminum oxide may capture and fix a larger amount of hydrogen than highly crystalline aluminum oxide.

[0475] Here, the following model can be considered for the excess oxygen in the insulator 280 with respect to the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.

[0476] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. Due to the diffusion of the hydrogen, excess oxygen in the insulator 280 reacts with the hydrogen in the oxide semiconductor to form OH bonds and diffuses through the insulator 280. When the hydrogen atoms with OH bonds reach a material (typically, the insulator 282) having a function of capturing or fixing hydrogen, the hydrogen atoms react with the oxygen atoms bonded to the atoms (e.g., metal atoms, etc.) in the insulator 282 and are captured or fixed in the insulator 282. On the other hand, the oxygen atoms of the excess oxygen having OH bonds are presumed to remain in the insulator 280 as excess oxygen. That is, in the diffusion of the hydrogen, it is highly probable that the excess oxygen in the insulator 280 plays a bridging role.

[0477] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0478] As an example, an insulator 280 having excess oxygen is formed on the oxide semiconductor, and then the insulator 282 is formed. After that, it is preferable to perform a heat treatment. Specifically, the heat treatment is performed at a temperature of 350 °C or higher, preferably 400 °C or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.

[0479] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280 and the insulator 282. That is, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0480] After the above heat treatment, an insulator 283 is formed. Since the insulator 283 is a material having a high function of blocking hydrogen, it is possible to suppress the hydrogen diffused outward or the hydrogen existing outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0481] Regarding the above heat treatment, although an example of the configuration in which it is performed after forming the insulator 282 has been illustrated, the present invention is not limited thereto. For example, after forming the transistor layer 413, or after forming the memory device layers 415_1 to 415_3, the above heat treatment may be performed respectively. Further, when hydrogen is diffused outward by the above heat treatment, hydrogen is diffused upward or laterally above the transistor layer 413. Similarly, when the heat treatment is performed after forming the memory device layers 415_1 to 415_3, hydrogen is diffused upward or laterally.

[0482] Note that by adopting the above manufacturing process, the insulator 214 and the insulator 283 adhere to each other, thereby forming the above-described sealing structure.

[0483] As described above, by adopting the above structure and the above manufacturing process, a semiconductor device using an oxide semiconductor with a reduced hydrogen concentration can be provided. Therefore, a semiconductor device with good reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided.

[0484] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with other configurations, methods shown in the present embodiment, configurations, methods shown in other embodiments, or configurations, methods shown in examples.

[0485] (Embodiment 3) In the present embodiment, with reference to FIGS. 34A, 34B, 35A to 35H, a transistor using an oxide as a semiconductor according to one aspect of the present invention (hereinafter sometimes referred to as an OS transistor), and a storage device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) will be described. The OS memory device is a storage device having at least a capacitive element and an OS transistor that controls charging and discharging of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.

[0486] <Configuration Example of Memory Device> FIG. 34A shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0487] The column circuit 1430 has, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. The above wiring is the wiring connected to the memory cells included in the memory cell array 1470, which will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 has, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0488] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside. Also, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the memory device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

[0489] The control logic circuit 1460 processes the control signals (CE, WE, RE) input from the outside and generates control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0490] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cells MC in one column, and the like. Also, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in one row, and the like.

[0491] In FIG. 34A, an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane is shown, but the present embodiment is not limited to this. For example, as shown in FIG. 34B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a configuration may be adopted in which a sense amplifier is provided so as to overlap below the memory cell array 1470.

[0492] Examples of the configuration of a memory cell applicable to the above-described memory cell MC will be described with reference to FIGS. 35A to 35H.

[0493] [DOSRAM] Circuit configuration examples of memory cells of DRAM are shown in FIGS. 35A to 35C. In this specification and the like, a DRAM using a 1OS transistor 1 capacitor type memory cell may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) (registered trademark). The memory cell 1471 shown in FIG. 35A has a transistor M1 and a capacitor element CA. Note that the transistor M1 has a gate (which may be referred to as a top gate) and a back gate.

[0494] The first terminal of the transistor M1 is connected to the first terminal of the capacitor element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitor element CA is connected to the wiring LL.

[0495] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, the wiring LL may be at the ground potential or at a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0496] Here, the memory cell 1471 shown in FIG. 35A corresponds to the storage device shown in FIGS. 30A and 30B. That is, the transistor M1 corresponds to the transistor 200, and the capacitive element CA corresponds to the capacitive device 292.

[0497] Also, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 35B. Further, for example, the memory cell MC may be a memory cell composed of a transistor M1 having a single gate structure, that is, a transistor without a back gate, as in the memory cell 1473 shown in FIG. 35C.

[0498] When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitive element 100 can be used as the capacitive element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Or, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very small, multi-valued data or analog data can be held for the memory cells 1471, 1472, and 1473.

[0499] Also, in the DOSRAM, as described above, when the sense amplifier is provided so as to overlap below the memory cell array 1470, the bit lines can be shortened. As a result, the bit line capacitance is reduced, and the holding capacitance of the memory cell can be decreased.

[0500] [NOSRAM] FIGS. 35D to 35G show circuit configuration examples of a gain cell type memory cell of a 2-transistor 1-capacitor element. The memory cell 1474 shown in FIG. 35D includes a transistor M2, a transistor M3, and a capacitor element CB. Note that the transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor for the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM) (registered trademark).

[0501] The first terminal of the transistor M2 is connected to the first terminal of the capacitor element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the capacitor element CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor element CB.

[0502] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor element CB. It is preferable to apply a high-level potential to the wiring CAL during data writing and data reading. Also, during data retention, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0503] Here, the memory cell 1474 shown in FIG. 35D corresponds to the storage device shown in FIGS. 28 and 29. That is, the transistor M2 corresponds to the transistor 200, the capacitor element CB corresponds to the capacitor element 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0504] Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 35E. Also, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 35F. Also, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 35G.

[0505] When using the semiconductor device shown in the above embodiment for a memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor element 100 can be used as the capacitor element CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely small. As a result, the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. Or, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is extremely small, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0506] Note that the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter sometimes referred to as an Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than the OS transistor. Therefore, an Si transistor may be used as the transistor M3 that functions as a read transistor. Also, by using an Si transistor for the transistor M3, the transistor M2 can be provided laminated on the transistor M3, so that the occupied area of the memory cell can be reduced and high integration of the storage device can be achieved.

[0507] Also, the transistor M3 may be an OS transistor. When OS transistors are used for the transistor M2 and the transistor M3, the memory cell array 1470 can be configured with a circuit using only n-type transistors.

[0508] Further, FIG. 35H shows an example of a gain cell type memory cell of a three-transistor one-capacitor element. The memory cell 1478 shown in FIG. 35H includes transistors M4 to M6 and a capacitor element CC. The capacitor element CC is provided as appropriate. The memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that provides a low-level potential. Note that the memory cell 1478 may be electrically connected to wiring RBL and wiring WBL instead of wiring BIL.

[0509] Transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to wiring BGL. Note that the back gate and the gate of transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a back gate.

[0510] Note that each of transistors M5 and M6 may be an n-channel type Si transistor or a p-channel type Si transistor. Alternatively, transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured with only n-type transistors.

[0511] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitor element 100 can be used as capacitor element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be made very small.

[0512] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, etc. shown in this embodiment are not limited to the above. The arrangement or function of these circuits, the wiring connected to the circuits, circuit elements, etc. may be changed, deleted, or added as necessary. The memory device according to one aspect of the present invention has a high operating speed and can retain data for a long period of time.

[0513] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with other configurations, methods shown in this embodiment, configurations, methods shown in other embodiments, or configurations, methods shown in examples.

[0514] (Embodiment 4) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using FIGS. 36A and 36B. A plurality of circuits (systems) are mounted on the chip 1200. The technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as System on Chip (SoC).

[0515] As shown in FIG. 36A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0516] Bumps (not shown) are provided on the chip 1200 and connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 36B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connected to a motherboard 1203.

[0517] The motherboard 1203 may be provided with memory devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for the flash memory 1222.

[0518] The CPU 1211 preferably has a plurality of CPU cores. Also, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The NOSRAM or DOSRAM described above can be used for the memory. Also, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and sum-of-products calculation. By providing an image processing circuit or a sum-of-products calculation circuit using the oxide semiconductor of the present invention in the GPU 1212, it becomes possible to execute image processing and sum-of-products calculation with low power consumption.

[0519] Also, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the calculation result from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed at high speed.

[0520] The analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the sum-of-products calculation circuit may be provided in the analog arithmetic unit 1213.

[0521] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0522] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0523] The network circuit 1216 has a network circuit such as a LAN (Local Area Network). Further, it may have a circuit for network security.

[0524] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0525] The PCB 1201 provided with the chip 1200 having the GPU 1212, the motherboard 1203 provided with the DRAM 1221 and the flash memory 1222 can be called a GPU module 1204.

[0526] Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. Also, since it is excellent in image processing, it is preferably used in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. Further, due to the multiplication-accumulation circuit using the GPU 1212, methods such as deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann machine (DBM), and deep belief network (DBN) can be executed. Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0527] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with other configurations, methods shown in this embodiment, configurations, methods shown in other embodiments, or configurations, methods shown in examples.

[0528] (Embodiment 5) This embodiment shows an example of an electronic component and an electronic device in which a storage device or the like shown in the above embodiment is incorporated.

[0529] <Electronic component> First, an example of an electronic component in which a storage device 720 is incorporated will be described with reference to FIGS. 37A and 37B.

[0530] FIG. 37A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 37A has a storage device 720 in a mold 711. FIG. 37A omits a part in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the storage device 720 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0531] The storage device 720 has a drive circuit layer 721 and a memory circuit layer 722.

[0532] FIG. 37B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.

[0533] In the electronic component 730, an example is shown in which the memory device 720 is used as a high bandwidth memory (HBM). Also, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.

[0534] As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. can be used. As the interposer 731, a silicon interposer, a resin interposer, etc. can be used.

[0535] The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Also, the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate". Also, in some cases, a through electrode is provided on the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as the through electrode.

[0536] It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult in a resin interposer.

[0537] In HBM, in order to realize a wide memory bandwidth, it is necessary to connect many wirings. For this reason, the interposer for mounting HBM requires the formation of fine and high-density wirings. Therefore, it is preferable to use a silicon interposer as the interposer for mounting HBM.

[0538] In addition, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer is less likely to occur. Also, since the silicon interposer has high surface flatness, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0539] Also, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 730. When providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 731 uniform. For example, in the electronic component 730 shown in the present embodiment, it is preferable to make the heights of the storage device 720 and the semiconductor device 735 uniform.

[0540] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. FIG. 37B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix form at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix form at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0541] The electronic component 730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0542] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with other configurations, methods shown in this embodiment, configurations, methods shown in other embodiments, or configurations, methods shown in the examples.

[0543] (Embodiment 6) In this embodiment, an application example of a memory device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment can be applied to, for example, memory devices of various electronic devices (such as information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large-scale computers...

Claims

1. an oxide, a first conductor and a second conductor on the oxide, a first insulator on the first conductor, a second insulator on the second conductor, a third insulator on the first insulator and on the second insulator, a fourth insulator on the third insulator, a fifth insulator on the oxide and disposed between the first conductor and the second conductor, a sixth insulator on the fifth insulator, a third conductor on the sixth insulator, a seventh insulator on the third conductor, an eighth insulator having a region in contact with the upper surface of the seventh insulator and a region in contact with the side surface of the fourth insulator, the third conductor has a region overlapping with the oxide, the fifth insulator has regions in contact with the oxide, the first conductor, the second conductor, and the first insulator to the fourth insulator respectively, the fifth insulator contains nitrogen, oxygen, and silicon, a semiconductor device.

2. In claim 1, the sixth insulator contains hafnium, a semiconductor device.

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