Electronic component package and method for manufacturing the same

Abstract

The present invention relates to an electronic component package and a method for manufacturing the same. In one embodiment, the electronic component package includes a first metal layer, a high-voltage transistor semiconductor bare chip, a first mold compound layer, a second metal layer, a first vertical connection structure, a second vertical connection structure, a control circuit bare die, and a second mold compound layer. The electronic component package of the present invention uses the metal layer and the vertical connection structure instead of the lead frame and electrical leads, which makes the location of the electrical connection of the chip more flexible and improves the heat dissipation effect. Compared with the lead frame and electrical leads, the electronic component package of the present disclosure is more suitable for packaging high-voltage or high-current chips.

Description

Technical Field

[0001] The present invention relates to an electronic component package and a method for manufacturing the same, and more specifically, to an electronic component package having a high-voltage transistor semiconductor bare chip and a control circuit bare die.

Background Art

[0002] In an electronic component (such as a chip or an integrated circuit (IC)) package, a lead frame package technology can be used, and electrical connection of the chip ends can be provided by electrical lead wires. As the density and miniaturization of the package technology progress, the number of input / output (I / O) connection pins of the package and its internal interconnections increase and become more complex. Since the lead frame can provide only one-layer wiring, the position of the electrical connection of the chip is limited, and this spatial limitation has become a technical bottleneck for the multi-chip package. Also, the heat dissipation problem becomes serious and may affect the performance of the chip.

[0003] Although the flip-chip package technology can also realize a multi-chip package, this is to place the surface of the chip downward and interconnect it through a package substrate. Compared with using a lead frame, the flip-chip package technology may increase the manufacturing cost, and moreover, the manufacturing process is quite complex, so its throughput may also decrease.

Summary of the Invention

[0004] Embodiments of the present disclosure relate to an electronic component package. The electronic component package includes a first metal layer including a first external terminal, a second external terminal, and a third external terminal that are not in direct contact with each other, a high-voltage transistor semiconductor bare chip having a gate electrode, a source electrode, and a drain electrode, wherein the drain electrode is located on one side of the high-voltage transistor semiconductor bare chip, the gate electrode and the source electrode are located on the opposite other side of the high-voltage transistor semiconductor bare chip, and the high-voltage transistor semiconductor bare chip is disposed on the first metal layer, and the drain electrode is connected to the second external terminal; a first mold compound layer having a first side and a second side facing each other, the first mold compound layer covering the high-voltage transistor semiconductor bare chip and further covering at least a part of the first metal layer, wherein the first external terminal, the second external terminal, and the third external terminal are exposed from the first side of the first mold compound layer; a second metal layer including a first metal layer portion and a second metal layer portion that are not in direct contact with each other, wherein the second metal layer is disposed on the second side of the first mold compound layer; a first vertical continuation structure penetrating the first mold compound layer and connecting the first metal layer portion to the first external terminal; a second vertical continuation structure penetrating a part of the first mold compound layer and connecting the second metal layer portion to the gate electrode of the high-voltage transistor semiconductor bare chip; a control circuit bare die having an active surface facing the gate electrode and the source electrode of the high-voltage transistor semiconductor bare chip, the active surface including a first control terminal and a second control terminal that are correspondingly connected to the first metal layer portion and the second metal layer portion; and a second mold compound layer having a first side and a second side facing each other, the second mold compound layer being disposed on the first mold compound layer, and the first side thereof being bonded to the second side of the first mold compound layer to cover the control circuit bare die and the second metal layer, whereinThe first control terminal of the control circuit bare die is connected to the first external terminal by the first metal layer portion and the first vertical connection structure, and among them, the second control terminal of the control circuit bare die is connected to the gate electrode of the high-voltage transistor semiconductor bare chip by the second metal layer portion and the second vertical connection structure, and among them, the source electrode of the high-voltage transistor semiconductor bare chip is connected to the third external terminal.

[0005] Embodiments of the present disclosure relate to a method for manufacturing an electronic component package. The method includes providing a temporary carrier; forming, on the temporary carrier, a first metal layer including a first external terminal, a second external terminal, and a third external terminal that are not in direct contact with each other; placing, on the first metal layer, a high-voltage transistor semiconductor bare chip having a gate electrode, a source electrode, and a drain electrode, wherein the drain electrode is located on one side of the high-voltage transistor semiconductor bare chip and is connected to the second external terminal, and the gate electrode and the source electrode are located on the opposite other side of the high-voltage transistor semiconductor bare chip; forming, on the temporary carrier, a first mold compound layer having a first side and a second side facing each other to cover at least a part of the high-voltage transistor semiconductor bare chip and the first metal layer; forming, on the second side of the first mold compound layer, a second metal layer including a first metal layer portion and a second metal layer portion that are not in direct contact with each other; connecting the first metal layer portion to the first external terminal; connecting the second metal layer portion to the gate electrode of the high-voltage transistor semiconductor bare chip; placing, on the first mold compound layer, a control circuit bare die having an active surface facing the gate electrode and the source electrode of the high-voltage transistor semiconductor bare chip, the active surface including a first control terminal and a second control terminal that are correspondingly connected to the first metal layer portion and the second metal layer portion; forming, on the first mold compound layer, a second mold compound layer having a first side and a second side facing each other, and the first side of the second mold compound layer is bonded to the second side of the first mold compound layer to cover the control circuit bare die and the second metal layer; connecting the source electrode of the high-voltage transistor semiconductor bare chip to the third external terminal; and removing the temporary carrier to expose the first external terminal, the second external terminal, and the third external terminal from the first side of the first mold compound layer.

[0006] Some embodiments of the present disclosure can be optimally understood by reading the following detailed description in conjunction with the drawings. It should be noted that the various structures do not have to be drawn to scale. In fact, for the sake of clarity of the discussion, the sizes of the various structures can be arbitrarily enlarged or reduced.

Brief Description of the Drawings

[0007]

Figure 1A

Figure 1B

Figure 1C

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Embodiments for Carrying Out the Invention

[0008] The same or similar components are denoted by the same reference numerals in the drawings and the detailed description. Some embodiments of the present disclosure can be readily understood from the following detailed description and the drawings.

[0009] In the following disclosure, numerous different embodiments or examples are provided for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, a reference to forming a first feature above or on a second feature can include embodiments where the first and second features form a direct contact, and can also include embodiments where another feature is formed between the first and second features such that the first and second features do not form a direct contact. Also, in the present disclosure, reference numerals and / or letters may overlap within each embodiment. This overlap is done for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements being discussed.

[0010] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in various specific environments. The specific embodiments discussed are illustrative and not intended to limit the scope of the present disclosure.

[0011] The present disclosure provides an electronic component package and a method for manufacturing the same. Since the electronic component package of the present disclosure integrates a high-voltage transistor semiconductor bare chip and a control circuit bare die in one package, it can not only meet the demand for miniaturization, but also reduce the circuit wiring area on a printed circuit board (PCB) or a template. Further, in the electronic component package of the present disclosure, by using a metal layer (e.g., a redistribution layer (RDL)) and a vertical connection structure (e.g., a conductive pillar or a conductive via) instead of a lead frame and electrical lead wires, the electrical connection position of the chip becomes more flexible, and the heat dissipation effect is also further improved. Compared with a lead frame and electrical lead wires, the electronic component package of the present disclosure is more suitable for packaging high-voltage or high-current chips. Furthermore, since the active surface (or active region) of the chip of the present disclosure can be butted face-to-face through the metal layer, the transmission path between the chips can be shortened and the transmission speed can be increased.

[0012] Referring to FIG. 1A, FIG. 1A shows a cross-sectional view of an electronic component package 1 according to some embodiments of the present application. The electronic component package 1 may include electronic components 10 and 12, encapsulants 11 and 13, a first metal layer (including external terminals m11, m12, and m13), and a second metal layer (including metal layer portions m21, m22, and m23).

[0013] The external terminals m11, m12, and m13 of the first metal layer do not have to be in direct contact with each other. For example, the external terminals m11, m12, and m13 can be separated from each other by the encapsulant 11. For example, the external terminals m11, m12, and m13 do not have to be directly connected to each other. The external terminal m12 can be located between the external terminals m11 and m13.

[0014] The sizes (e.g., width, thickness, area, etc.) of the external terminals m11, m12, and m13 may be the same as each other or different. As shown in FIG. 1A, the width of the external terminal m12 may be greater than the width of the external terminal m11 or m13. In some embodiments, the area of the external terminal m12 may be about 1 to 2 times the area (e.g., surface area) of the electronic component 10. Also, as shown in FIG. 1A, the thicknesses of the external terminals m11, m12, and m13 may be the same as each other. The external terminals m11, m12, and m13 can each include a conductive material such as a metal or a metal alloy. Examples of the conductive material can include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or a combination of two or more of them. The external terminals m11, m12, and m13 can provide an electrical connection between the electronic component package 1 and an external device (e.g., a PCB, other package, or other electronic component).

[0015] The electronic component 10 can include a semiconductor chip (or bare chip). The chip can include circuit components such as transistors, resistors, capacitors, and interconnect structures for forming an integrated circuit (IC). In some embodiments, the electronic component 10 can include (but is not limited to) a metal-oxide-semiconductor field-effect transistor (MOSFET), e.g., NMOS, PMOS, CMOS, a voltage feedback device, and / or a switch.

[0016] In some embodiments, the electronic component 10 can include a high-voltage transistor having a relatively high breakdown voltage (or withstand voltage), and can also be applied to circuits with high input voltage and / or high output voltage. Furthermore, the electronic component 10 can include various types of integrated circuits, such as a memory device including a dynamic random access memory (DRAM), a static random access memory (SRAM), and various types of non-volatile memories (including programmable read-only memory (PROM) and flash memory), an optoelectronic device, a logic device, a communication device, and other types of devices.

[0017] The electronic component 10 can have a surface 101, a surface 102 facing the surface 101, and a surface (or side surface) 103 extending between the surface 101 and the surface 102. One or more electrical terminals can be exposed from the surface 101 and / or the surface 102 of the electronic component 10. For example, the gate electrode and the source electrode of the electronic component 10 can be located on the same side of the electronic component 10, and the drain electrode can be located on the opposite side. The drain electrode of the electronic component 10 can be located on the surface 101, and the gate electrode and the source electrode can be located on the surface 102.

[0018] The electronic component 10 can be located on the first metal layer. The drain electrode of the electronic component 10 can be connected (or electrically connected) to the external terminal m12 of the first metal layer. The drain electrode of the electronic component 10 can be in contact with the external terminal m12 of the first metal layer. The drain metal layer (i.e., the external terminal m12) of the drain electrode is located on the surface 101, and the gate metal layer 10e1 of the gate electrode and the source metal layer 10e2 of the source electrode can be located on the surface 102.

[0019] The encapsulant 11 can cover at least a part of the electronic component 10 and the first metal layer. The encapsulant 11 can include a molding compound (e.g., an epoxy molding compound) or other suitable materials, which include, but are not limited to, epoxy resins, phenolic resins, silicon-containing resins, etc., or combinations thereof.

[0020] The encapsulant 11 can have a surface 111 and a surface 112 facing the surface 111. The external terminals m11, m12, and m13 of the first metal layer can be exposed from the surface 111. In some embodiments, the external terminals m11, m12, and m13 of the first metal layer can be flush or coplanar with the surface 111, respectively.

[0021] The metal layer portions m21, m22, and m23 of the second metal layer can be located on the surface 112 of the encapsulant 11. In other words, the first metal layer and the second metal layer are located on opposite sides of the encapsulant 11. The first metal layer can be partially embedded in the encapsulant 11, and the second metal layer can protrude from the surface 112 of the encapsulant 11.

[0022] The metal layer portions m21, m22, and m23 of the second metal layer do not have to be in direct contact with each other. For example, the metal layer portions m21, m22, and m23 can be separated from each other by the encapsulant 13. For example, the metal layer portions m21, m22, and m23 may be directly connected to each other. The metal layer portion m22 can be located between the metal layer portions m21 and m23.

[0023] The sizes (e.g., width, thickness, area, etc.) of the metal layer portions m21, m22, and m23 may be the same as each other or different. As shown in FIG. 1A, the width of the metal layer portion m23 may be larger than the width of the metal layer portion m21 or the metal layer portion m22. Also, as shown in FIG. 1A, the thicknesses of the metal layer portions m21, m22, and m23 may be the same as each other. The metal layer portions m21, m22, and m23 can each include a conductive material such as a metal or a metal alloy. Examples of the conductive material can include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or a combination of two or more of them.

[0024] The second metal layer can be encapsulated between the encapsulants 11 and 13. The second metal layer can be part of the interconnect structure inside the electronic component package 1. The second metal layer can include a redistribution layer. The second metal layer can provide an electrical connection between the electronic components 10 and 12, provide an electrical connection between the electronic component 10 and the first metal layer, and provide an electrical connection between the electronic component 12 and the first metal layer.

[0025] In some embodiments, the metal layer portion m21 can provide an electrical connection between the electronic component 12 and the external terminal m11. For example, the metal layer portion m21 can be connected to the external terminal m11 by a vertical continuous structure that penetrates at least a part of the encapsulant 11. As shown in FIG. 1A, the vertical continuous structure can include a conductive via v1 and a conductive pillar p1. The conductive pillar p1 can be disposed between the external terminal m11 and the conductive via v1. The conductive pillar p1 can extend from one side (e.g., its bottom) of the conductive via v1 toward the surface 111 of the encapsulant 11 and can contact the external terminal m11. The conductive pillar p1 can include a first side (e.g., its bottom) that contacts the external terminal m11 and a second side (e.g., its top) that contacts the conductive via v1. The diameter of the conductive pillar p1 can remain unchanged from the second side toward the first side. For example, the top diameter and the bottom diameter of the conductive pillar p1 are equal. The conductive via v1 can be disposed between the conductive pillar p1 and the metal layer portion m21. The conductive via v1 can include a first side (e.g., its bottom) that contacts the conductive pillar p1 and a second side (e.g., its top) that contacts the metal layer portion m21. The diameter of the conductive via v1 can be reduced from the second side toward the first side. For example, the diameter of the conductive via v1 is larger on the side closer to the metal layer portion m21 than on the side closer to the conductive pillar p1. For example, the top diameter of the conductive via v1 is larger than the bottom diameter. The conductive via v1 can extend from the surface 112 of the encapsulant 11 toward the surface 111. The first side (e.g., its bottom) of the conductive via v1 does not have to be coplanar with the surface 111, and the second side (e.g., its top) of the conductive via v1 can be coplanar with the surface 112.

[0026] In some embodiments, the metal layer portion m22 can provide an electrical connection between the electronic components 10 and 12. For example, the metal layer portion m22 can be connected to the gate metal layer 10e1 of the gate electrode of the electronic component 10 by a vertical continuous structure that penetrates at least a part of the encapsulant 11. As shown in FIG. 1A, the vertical continuous structure can include a conductive via v2. The conductive via v2 can be disposed between the gate metal layer 10e1 and the metal layer portion m22. The conductive via v2 can include a first side (e.g., its bottom) that contacts the gate metal layer 10e1 and a second side (e.g., its top) that contacts the metal layer portion m22. The diameter of the conductive via v2 can decrease from the second side toward the first side. For example, the diameter of the conductive via v2 is larger on the side closer to the metal layer portion m22 than on the side closer to the gate metal layer 10e1. For example, the top diameter of the conductive via v2 is larger than the bottom diameter. The conductive via v2 can extend from the surface 112 of the encapsulant 11 toward the surface 111. The first side (e.g., its bottom) of the conductive via v2 may not be coplanar with the surface 111, and the second side (e.g., its top) of the conductive via v2 may be coplanar with the surface 112.

[0027] In some embodiments, the metal layer portion m23 can provide an electrical connection between the electronic component 10 and the external terminal m13. For example, the metal layer portion m23 can be connected to the source metal layer 10e2 of the source electrode of the electronic component 10 by a vertical continuous structure that penetrates at least a part of the encapsulant 11. As shown in FIG. 1A, the vertical continuous structure can include a conductive via v3. The conductive via v3 can be disposed between the source metal layer 10e2 and the metal layer portion m23. The conductive via v3 can include a first side (e.g., its bottom) in contact with the source metal layer 10e2 and a second side (e.g., its top) in contact with the metal layer portion m23. The diameter of the conductive via v3 can decrease from the second side toward the first side. For example, the diameter of the conductive via v3 is larger on the side closer to the metal layer portion m23 than on the side closer to the source metal layer 10e2. For example, the top diameter of the conductive via v3 is larger than the bottom diameter. The conductive via v3 can extend from the surface 112 of the encapsulant 11 toward the surface 111. The first side (e.g., its bottom) of the conductive via v3 may not be coplanar with the surface 111, and the second side (e.g., its top) of the conductive via v3 may be coplanar with the surface 112.

[0028] In some embodiments, the metal layer portion m23 can be connected to the external terminal m13 by a vertical continuous structure that penetrates at least a part of the encapsulant 11. As shown in FIG. 1A, the vertical continuous structure can include a conductive via v4 and a conductive pillar p2. The conductive pillar p2 can be disposed between the external terminal m13 and the conductive via v4. The conductive pillar p2 can extend from one side (e.g., its bottom) of the conductive via v4 toward the surface 111 of the encapsulant 11 and can contact the external terminal m13. The conductive pillar p2 can include a first side (e.g., its bottom) that contacts the external terminal m13 and a second side (e.g., its top) that contacts the conductive via v4. The diameter of the conductive pillar p2 can remain unchanged from the second side toward the first side. For example, the top diameter and the bottom diameter of the conductive pillar p2 are equal. The conductive via v4 can be installed between the conductive pillar p2 and the metal layer portion m23. The conductive via v4 can include a first side (e.g., its bottom) that contacts the conductive pillar p2 and a second side (e.g., its top) that contacts the metal layer portion m23. The diameter of the conductive via v4 can be reduced from the second side toward the first side. For example, the diameter of the conductive via v4 is larger on the side closer to the metal layer portion m23 than on the side closer to the conductive pillar p2. For example, the top diameter of the conductive via v4 is larger than the bottom diameter. The conductive via v4 can extend from the surface 112 of the encapsulant 11 toward the surface 111. The first side (e.g., its bottom) of the conductive via v4 may not be coplanar with the surface 111, and the second side (e.g., its top) of the conductive via v4 may be coplanar with the surface 112.

[0029] In some embodiments, the height p1h of the conductive pillar p1 may be equal to the height p2h of the conductive pillar p2. The first side (e.g., its bottom) that contacts the external terminal m11 of the conductive pillar p1 and the first side (e.g., its bottom) that contacts the external terminal m13 of the conductive pillar p2 may be coplanar. The second side (e.g., its top) that contacts the conductive via v1 of the conductive pillar p1 and the second side (e.g., its top) that contacts the conductive via v4 of the conductive pillar p2 may be coplanar. In some embodiments, the second side (e.g., its top) that contacts the conductive via v1 of the conductive pillar p1 may be coplanar with one surface of the gate metal layer 10e1 (or the source metal layer 10e2). In some embodiments, the second side (e.g., its top) that contacts the conductive via v4 of the conductive pillar p2 may be coplanar with one surface of the gate metal layer 10e1 (or the source metal layer 10e2).

[0030] In some embodiments, the height v1h of the conductive via v1, the height v2h of the conductive via v2, the height v3h of the conductive via v3, and the height v4h of the conductive via v4 may be equal. The first side (e.g., its bottom) that contacts the conductive pillar p1 of the conductive via v1, the first side (e.g., its bottom) that contacts the gate metal layer 10e1 of the conductive via v2, the first side (e.g., its bottom) that contacts the source metal layer 10e2 of the conductive via v3, and the first side (e.g., its bottom) that contacts the conductive pillar p2 of the conductive via v4 may be coplanar. The second side (e.g., its top) that contacts the metal layer portion m21 of the conductive via v1, the second side (e.g., its top) that contacts the metal layer portion m22 of the conductive via v2, the second side (e.g., its top) that contacts the metal layer portion m23 of the conductive via v3, and the second side (e.g., its top) that contacts the metal layer portion m23 of the conductive via v4 may be coplanar.

[0031] The electronic component 12 can be located on the surface 112 of the encapsulant 11. The electronic component 12 can be located on the second metal layer. The electronic component 12 can include a semiconductor chip (or bare chip). The chip can include circuit components such as transistors, resistors, capacitors, and interconnect structures for forming an integrated circuit (IC). In some embodiments, the electronic component 12 can include a control circuit. Further, the electronic component 12 can include any type of control circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a micro processing unit (MPU), an application-specific integrated circuit (ASIC), a field-programmable gate or grid array (FPGA), a microcontroller, a system-on-chip (SoC), etc. The electronic component 12 can be connected to the electronic component 10 to control the electronic component 10.

[0032] The electronic component 12 can have a surface 121 and a surface 122 facing the surface 121. The surface 121 can include an active surface, and the surface 122 can include a non-active surface or a backside surface. The surface 121 of the electronic component 12 can face the surface 102 of the electronic component 10. The surface 121 of the electronic component 12 can face the gate electrode and the source electrode of the electronic component 10. One or more control terminals (or electrical terminals) can be exposed from the surface 121 of the electronic component 12. For example, the metal layers 12e1 and 12e2 of the control terminal (or electrical terminal) can be located on the surface 121.

[0033] The metal layer 12e1 can be connected to the metal layer portion m21 of the second metal layer via the electrical connection member 12s1 and further connected to the external terminal m11. The metal layer 12e2 can be connected to the metal layer portion m22 of the second metal layer via the electrical connection member 12s2 and further connected to the gate metal layer 10e1 of the gate electrode of the electronic component 10.

[0034] In some embodiments, the electrical connection members 12s1 and 12s2 can each include solder balls such as, for example, controlled collapse chip connection (C4) bumps, ball grid array (BGA), or land grid array (LGA).

[0035] The encapsulant 13 can cover at least a part of the electronic component 12, the electrical connection members 12s1 and 12s2, and the second metal layer. The encapsulant 13 can be bonded to the surface 112 of the encapsulant 11. In some embodiments, the encapsulant 13 can include the materials listed for the encapsulant 11. In some embodiments, there may be an interface between the encapsulant 13 and the encapsulant 11. However, in other embodiments, there may be no interface between the encapsulant 13 and the encapsulant 11.

[0036] FIG. 1B shows a perspective view of an electronic component package according to some embodiments of the present application. In some embodiments, the electronic component package shown in FIG. 1B can have a cross-sectional view as shown in FIG. 1A. In FIG. 1B, the encapsulants 11 and 13 are omitted for simplicity. In the electronic component package shown in FIG. 1B, elements that are the same or similar to the electronic component package 1 shown in FIG. 1A are denoted by the same reference numerals, and detailed descriptions of the same or similar elements will not be repeated.

[0037] The electronic component package shown in FIG. 1B is disposed on a temporary carrier 40. The temporary carrier 40 can include a substrate such as a ceramic substrate, a semiconductor substrate, a dielectric substrate, or a glass substrate. The temporary carrier 40 can be conductive, for example, include a metal substrate, or have a metal layer or a conductive layer thereon. The first metal layer is disposed on the temporary carrier 40.

[0038] The first metal layer can include a plurality of external terminals m11 and a plurality of external terminals m13. The plurality of external terminals m11 can be arranged along one side surface of the electronic component 10. Five external terminals m11 are depicted in FIG. 1B, but the number of external terminals m11 is not limited thereto. In some embodiments, any number of external terminals m11 may be present according to design requirements. For example, the number of external terminals m11 can correspond to the number of control terminals on the surface 121 of the electronic component 12. For example, by disposing a plurality of electrical connection members 12s1, a plurality of metal layer portions m21, and a plurality of vertical connection structures (each including a conductive via v1 and a conductive pillar p1) on the corresponding external terminals m11, the corresponding control terminals can be connected to the corresponding external terminals m11.

[0039] The plurality of external terminals m13 can be arranged along another side surface (e.g., the surface 103) of the electronic component 10. Five external terminals m13 are depicted in FIG. 1B, but the number of external terminals m13 is not limited thereto and may be different from the number of external terminals m11. In some embodiments, any number of external terminals m13 may be present according to design requirements. For example, as the current of the source electrode of the electronic component 10 increases, the number of external terminals m13 and the vertical connection structures (each including a conductive via v4 and a conductive pillar p2) above them increases, thereby providing more current paths and enhancing the heat dissipation effect.

[0040] In some embodiments, as shown in FIG. 2, the conductive pillars p1 and p2 can be omitted, and the conductive via v1 can be directly connected to the external terminal m11, and the conductive via v4 can be directly connected to the external terminal m13. However, adding conductive vias to the conductive pillars to form a vertical connection structure on the external terminals m11 and m13 can improve the electrical conductivity compared to using only conductive vias.

[0041] The first metal layer can include a single-layer external terminal m12 located on the surface 101 of the electronic component 10 and in contact with the drain electrode. Thus, in the present disclosure, the external terminal m12 can also be referred to as the drain metal layer of the electronic component 10. As described above, the area of the external terminal m12 can be about 1 to 2 times the area (e.g., surface area) of the electronic component 10. The plurality of external terminals m11 and the plurality of external terminals m13 can be located on opposite sides of the external terminal m12, respectively.

[0042] The electronic component 10 can include a plurality of gate electrodes and a plurality of gate metal layers 10e1. In some embodiments, the electronic component 10 can include a single source electrode and a single layer of source metal layer 10e2. However, the number of gate electrodes or source electrodes of the electronic component 10 is not limited thereto. For example, the number of gate electrodes of the electronic component 10 can correspond to the number of control terminals on the surface 121 of the electronic component 12. For example, a plurality of electrical connection members 12s2, a plurality of metal layer portions m22, and a plurality of conductive vias v2 can be arranged on the corresponding gate metal layer 10e1 to connect the corresponding control terminals to the corresponding gate electrodes.

[0043] The second metal layer can include a plurality of metal layer portions m21 and a plurality of metal layer portions m22. As described above, the number of the metal layer portions m21 and m22 can correspond to the number of control terminals on the surface 121 of the electronic component 12. The metal layer portion m21 can be located between one electrical connection member 12s1 and one conductive via v1, respectively. The metal layer portion m22 can be located between one electrical connection member 12s2 and one conductive via v2, respectively.

[0044] The second metal layer can include a single-layer metal layer portion m23. The metal layer portion m23 can connect the source electrode of the electronic component 10 to a plurality of external terminals m13. However, the number of the metal layer portions m23 is not limited thereto. For example, when the electronic component 10 includes a plurality of source electrodes, the source electrodes can be connected to the corresponding external terminals m13 via a plurality of metal layer portions m23.

[0045] FIG. 1C shows a perspective view of an electronic component package according to some embodiments of the present application. In some embodiments, the electronic component package shown in FIG. 1C can have a cross-sectional view as shown in FIG. 1A. In FIG. 1C, for the sake of simplicity, the encapsulants 11 and 13 are omitted. Since the electronic component package shown in FIG. 1C is similar to the electronic component package shown in FIG. 1B, the differences therebetween will be described below.

[0046] The plurality of external terminals m13 and the vertical continuation structure above them (each including a conductive via v4 and a conductive post p2) can be arranged along three sides of the electronic component 10. For example, the plurality of external terminals m13 and the vertical continuation structure above them can surround three sides of the electronic component 10. The metal layer portion m23 can cover the electronic component 10 and extend beyond three sides of the electronic component 10. As described above, the larger the current of the source electrode of the electronic component 10, the more the external terminals m13 and the vertical continuation structure above them, thereby providing more current paths and enhancing the heat dissipation effect.

[0047] FIG. 2 shows a cross-sectional view of an electronic component package 2 according to some embodiments of the present application. Since the electronic component package 2 shown in FIG. 2 is similar to the electronic component package 1 shown in FIG. 1A, the same or similar components are denoted by the same reference numerals, and the detailed description of the same or similar components will not be repeated. The differences therebetween will be described below.

[0048] The electronic component package 2 omits the conductive posts p1 and p2, directly connects (or contacts) the conductive via v1 to the external terminal m11, and directly connects (contacts) the conductive via v4 to the external terminal m13. The height v1h of the conductive via v1 and the height v4h of the conductive via v4 may be equal. The height v1h of the conductive via v1 and the height v4h of the conductive via v4 may be greater than the height v2h of the conductive via v2 and the height v3h of the conductive via v3, respectively.

[0049] In some embodiments, the width (e.g., maximum width) v2w of the conductive via v2 may be smaller than any of the width v1w of the conductive via v1, the width v3w of the conductive via v3, and the width v4w of the conductive via v4. The width v2w of the conductive via v2 can be between about 50 and 200 micrometers (μm). In some embodiments, the width (e.g., maximum width) v4w of the conductive via v4 may be greater than any of the width v1w of the conductive via v1, the width v2w of the conductive via v2, and the width v3w of the conductive via v3.

[0050] In some embodiments, since the conductive posts p1 and p2 are omitted, the number of steps in the manufacturing process of the electronic component package 2 can be significantly reduced. Also, since only conductive vias are used compared to using conductive posts, it is easier to adjust the size of the vertical connection structure based on the magnitude of the current. For example, as the current increases, a larger current can be transmitted by widening the conductive vias.

[0051] FIG. 3 shows a cross-sectional view of an electronic component package 3 based on some embodiments of the present application. Since the electronic component package 3 shown in FIG. 3 is similar to the electronic component package 2 shown in FIG. 2, the same or similar components are denoted by the same reference numerals, and detailed descriptions of the same or similar components will not be repeated. The differences are described below.

[0052] The electronic component package 3 uses an integrated conductive member 30 instead of the conductive vias v3, the metal layer portion m23, and the conductive via v4 to connect the source metal layer 10e2 to the external terminal m13. The integrated conductive member 30 can overlap with the source metal layer 10e2 and have an end portion extending outward from the electronic component 10, for example, extending beyond the surface 103. For example, the integrated conductive member 30 can have a portion 301 that extends horizontally outward from the source metal layer 10e2. The horizontally extending portion 301 can have one end overlapping with the source metal layer 10e2 and the other end not overlapping with the source metal layer 10e2. Also, the integrated conductive member 30 can have another portion 302 that connects the horizontally extending portion 301 to the external terminal m13. The portion 302 can extend non-vertically and non-horizontally between one end of the portion 301 and the external terminal m13. In some embodiments, the integrated conductive member 30 may be covered by the encapsulant 13.

[0053] In some embodiments, compared with the electronic component package 2, the number of steps in the manufacturing process of the electronic component package 3 can be reduced. Moreover, compared with connecting the source metal layer 10e2 to the external terminal m13 using conductive posts or conductive vias, the current path of the electronic component package 3 can be made shorter. In some embodiments, when including a plurality of external terminals m13 (for example, in FIG. 1B), the integrated conductive member 30 can connect the source electrode (regardless of one or more) of the electronic component 10 to the plurality of external terminals m13.

[0054] Referring to FIGS. 4A - 4F, FIGS. 4A - 4F show one or more stages in a method of manufacturing an electronic component package according to some embodiments of the present application. At least some of these drawings have been simplified to better understand the form of the present disclosure.

[0055] Referring to FIG. 4A, the manufacturing method includes providing a temporary carrier 40. The temporary carrier 40 can include substrates such as ceramic substrates, semiconductor substrates, dielectric substrates, glass substrates, etc. The temporary carrier 40 can be conductive, for example, include a metal substrate or have a metal layer or a conductive layer thereon.

[0056] The manufacturing method includes disposing a first metal layer on the temporary carrier 40. The first metal layer can be formed by electroplating or chemical vapor deposition (CVD). The first metal layer can form external terminals m11, m12, and m13 by patterning.

[0057] Next, conductive pillars p1, electronic component 10, and conductive pillar p2 are respectively disposed on external terminals m11, m12, and m13. The drain electrode of the electronic component 10 can contact the external terminal m12 downward. The gate metal layer 10e1 of the gate electrode and the source metal layer 10e2 of the source electrode can be located on the surface 102. In some embodiments, the height p1h of the conductive pillar p1 can be equal to the height p2h of the conductive pillar p2. In some embodiments, the top of the conductive pillar p1 can be coplanar with one surface of the gate metal layer 10e1 (or the source metal layer 10e2). In some embodiments, the top of the conductive pillar p2 can be coplanar with one surface of the gate metal layer 10e1 (or the source metal layer 10e2).

[0058] Referring to FIG. 4B, a sealing material 11 is formed on the temporary carrier 40 to cover at least a part of the conductive pillar p1, the electronic component 10, the conductive pillar p2, and the first metal layer. In some embodiments, the sealing material 11 is formed by a molding technique such as transfer molding or compression molding.

[0059] Next, a part of the encapsulant 11 can be removed to form openings 11t1, 11t2, 11t3, and 11t4. The openings 11t1, 11t2, 11t3, and 11t4 expose a part of the conductive pillar p1, the gate metal layer 10e1, the source metal layer 10e2, and the conductive pillar p2, respectively.

[0060] In some embodiments, the openings 11t1, 11t2, 11t3, and 11t4 can have upper and lower portions with different slopes. The upper portion can be wider than the lower portion. The upper portion can gradually narrow towards the lower portion. The upper portion can gradually narrow towards the temporary carrier 40. In some embodiments, the openings 11t1, 11t2, 11t3, and 11t4 can be formed by a laser drilling process.

[0061] Referring to FIG. 4C, conductive vias v1, v2, v3, and v4 can be formed by forming a conductive material in the openings 11t1, 11t2, 11t3, and 11t4. In some embodiments, the conductive material can be formed by physical vapor deposition (PVD) such as sputtering or spraying. In some embodiments, the conductive material can be formed by electroplating or CVD. In some embodiments, the tops of the conductive vias v1, v2, v3, and v4 can be made coplanar by a planarization operation, a polishing operation, or another suitable removal operation.

[0062] Referring to FIG. 4D, a second metal layer is disposed on the surface 112 of the encapsulant 11. The second metal layer can be formed by electroplating or CVD. The second metal layer can form metal layer portions m21, m22, and m23 by patterning.

[0063] Referring to FIG. 4E, the electronic component 12 is disposed on the second metal layer. The metal layer 12e1 of the control terminal (or electrical terminal) is connected to the metal layer portion m21 of the second metal layer via the electrical connection member 12s1. The metal layer 12e2 of the control terminal is connected to the metal layer portion m22 of the second metal layer via the electrical connection member 12s2.

[0064] Referring to FIG. 4F, by forming the encapsulant 13 on the encapsulant 11, at least a part of the electronic component 12, the electrical connection members 12s1 and 12s2, and the second metal layer is covered. In some embodiments, the encapsulant 13 is formed by a molding technique such as transfer molding or compression molding. Thereafter, the temporary carrier 40 is removed to expose the external terminals m11, m12, and m13.

[0065] The semiconductor structure formed through the above steps may be the same as the electronic component package 1 shown in FIG. 1A.

[0066] Referring to FIGS. 5A - 5F, FIGS. 5A - 5F show one or more stages in a method for manufacturing an electronic component package according to some embodiments of the present application. At least some of these drawings have been simplified to better understand the form of the present disclosure.

[0067] Referring to FIG. 5A, the manufacturing method includes providing a temporary carrier 40. The temporary carrier 40 can include a substrate such as a ceramic substrate, a semiconductor substrate, a dielectric substrate, or a glass substrate. The temporary carrier 40 can be conductive, for example, including a metal substrate or having a metal layer or a conductive layer thereon.

[0068] The manufacturing method includes disposing a first metal layer on the temporary carrier 40. The first metal layer can be formed by electroplating or CVD. The first metal layer can form the external terminals m11, m12, and m13 by patterning.

[0069] Next, the electronic component 10 is disposed on the external terminal m12. The drain electrode of the electronic component 10 can be in downward contact with the external terminal m12. The gate metal layer 10e1 of the gate electrode and the source metal layer 10e2 of the source electrode can be located on the surface 102.

[0070] Referring to FIG. 5B, a sealing material 11 is formed on the temporary carrier 40 to cover at least a part of the electronic component 10 and the first metal layer. In some embodiments, the sealing material 11 is formed by a molding technique such as transfer molding or compression molding.

[0071] Next, a part of the sealing material 11 can be removed to form openings 11t1, 11t2, 11t3, and 11t4. The openings 11t1, 11t2, 11t3, and 11t4 expose a part of the external terminal m11, the gate metal layer 10e1, the source metal layer 10e2, and the external terminal m13, respectively.

[0072] In some embodiments, the openings 11t1, 11t2, 11t3, and 11t4 can have upper and lower portions with different slopes. The upper portion can be wider than the lower portion. The upper portion can gradually become narrower toward the lower portion. The upper portion can gradually become narrower toward the temporary carrier 40. In some embodiments, the openings 11t1, 11t2, 11t3, and 11t4 can be formed by a laser drilling operation.

[0073] Referring to FIG. 5C, conductive vias v1, v2, v3, and v4 can be formed by forming a conductive material in the openings 11t1, 11t2, 11t3, and 11t4. In some embodiments, the conductive material can be formed by PVD such as sputtering or spraying. In some embodiments, the conductive material can be formed by electroplating or CVD. In some embodiments, the tops of the conductive vias v1, v2, v3, and v4 can be made coplanar by a planarization operation, a polishing operation, or another suitable removal operation.

[0074] Since the steps in FIGS. 5D to 5F are the same as those in FIGS. 4D to 4F, they will not be described repeatedly here. Thereafter, the temporary carrier 40 is removed to expose the external terminals m11, m12, and m13.

[0075] The semiconductor structure formed through the above steps may be the same as the electronic component package 2 shown in FIG. 2.

[0076] Referring to FIGS. 6A to 6F, FIGS. 6A to 6F show one or more stages in a method for manufacturing an electronic component package according to some embodiments of the present application. At least some of these drawings have been simplified to better understand the form of the present disclosure.

[0077] Referring to FIG. 6A, the manufacturing method includes providing a temporary carrier 40. The temporary carrier 40 can include a substrate such as a ceramic substrate, a semiconductor substrate, a dielectric substrate, or a glass substrate. The temporary carrier 40 can be conductive. For example, it includes a metal substrate or has a metal layer or a conductive layer thereon.

[0078] The manufacturing method includes disposing a first metal layer on the temporary carrier 40. The first metal layer can be formed by electroplating or CVD. The first metal layer can form the external terminals m11, m12, and m13 by patterning. The electronic component 10 is disposed on the external terminal m12. The drain electrode of the electronic component 10 can be in downward contact with the external terminal m12. The gate metal layer 10e1 of the gate electrode and the source metal layer 10e2 of the source electrode can be located on the surface 102.

[0079] Subsequently, the source metal layer 10e2 is connected to the external terminal m13 by the integral conductive member 30.

[0080] Subsequently, a sealing material 11 is formed on the temporary carrier 40 to cover at least a part of the electronic component 10, the integral conductive member 30, and the first metal layer.

[0081] Referring to FIG. 6B, a part of the sealing material 11 can be removed to form openings 11t1 and 11t2. The openings 11t1 and 11t2 respectively expose a part of the external terminal m11 and the gate metal layer 10e1.

[0082] In some embodiments, the openings 11t1 and 11t2 can have upper and lower portions with different slopes. The upper portion can be wider than the lower portion. The upper portion can gradually become narrower towards the lower portion. The upper portion can gradually become narrower towards the temporary carrier 40. In some embodiments, the openings 11t1 and 11t2 can be formed by a laser drilling operation.

[0083] Referring to FIG. 6C, conductive vias v1 and v2 can be formed by forming a conductive material in the openings 11t1 and 11t2. In some embodiments, the conductive material can be formed by PVD such as sputtering or spraying. In some embodiments, the conductive material can be formed by electroplating or CVD. In some embodiments, the tops of the conductive vias v1 and v2 can be made coplanar by a planarization operation, a polishing operation or another suitable removal operation.

[0084] Since the steps of FIGS. 6D to 6F are the same as those of FIGS. 4D to 4F, they will not be described repeatedly here. Thereafter, the temporary carrier 40 is removed to expose the external terminals m11, m12 and m13.

[0085] The semiconductor structure formed through the above steps can be the same as the electronic component package 3 shown in FIG. 3.

[0086] In this document, for the sake of easy description, terms corresponding to spaces such as "below", "lower surface", "lower part", "above", "upper part", "left side", and "right side" are used to describe the relationship between one component or feature shown in the drawings and one or more other components or features. In addition to the directions shown in the drawings, terms corresponding to spaces may also cover different directions during the use or operation of the device. The direction of the device (90-degree rotation, or other orientations) can be determined in other ways, and similarly, the terms corresponding to spaces used in this document can be interpreted in the corresponding ways. It should be understood that when a component is written as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components.

[0087] As used herein, the terms "substantially", "essentially", "nearly", and "about" are used to describe and interpret small variations. When used in connection with an event or situation, these terms can refer to instances where the event or situation has definitely occurred, as well as instances where the event or situation is about to occur. When used herein with respect to a given value or range, the term "about" means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range as a whole. In this document, ranges are expressed from one endpoint to another endpoint, or between two endpoints. All ranges disclosed in this document include the endpoints unless otherwise expressly stated. The term "substantially coplanar" can refer to the difference in position where two surfaces are positioned along the same plane being within a few micrometers (μm), for example, the difference in position being within 10 μm, 5 μm, 1 μm, or 0.5 μm along the same plane. When a numerical value or characteristic is said to be "essentially" the same, the term can refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average value of the said value.

[0088] The foregoing content outlines the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures in order to implement the same or similar purposes and / or achieve the same or similar advantages of the embodiments introduced in the text. Various modifications, substitutions, and changes can be made without departing from the spirit and scope of the present disclosure and in situations where such equivalent structures do not deviate from the spirit and scope of the present disclosure.

Claims

1. In an electronic component package, a first metal layer including a first external terminal, a second external terminal, and a third external terminal that do not directly contact each other; a high-voltage transistor semiconductor bare chip having a gate electrode, a source electrode, and a drain electrode, wherein the drain electrode is located on one side of the high-voltage transistor semiconductor bare chip, the gate electrode and the source electrode are located on the opposite other side of the high-voltage transistor semiconductor bare chip, and the high-voltage transistor semiconductor bare chip is installed on the first metal layer, and the drain electrode is connected to the second external terminal; a first mold compound layer having a first side and a second side facing each other, the first mold compound layer covering the high-voltage transistor semiconductor bare chip and further covering at least a part of the first metal layer, and the first external terminal, the second external terminal, and the third external terminal being exposed from the first side of the first mold compound layer; a second metal layer including a first metal layer portion and a second metal layer portion that do not directly contact each other, the second metal layer being disposed on the second side of the first mold compound layer; a first vertical connection structure penetrating the first mold compound layer and connecting the first metal layer portion to the first external terminal; a second vertical connection structure penetrating a part of the first mold compound layer and connecting the second metal layer portion to the gate electrode of the high-voltage transistor semiconductor bare chip; a control circuit bare die having an active surface facing the gate electrode and the source electrode of the high-voltage transistor semiconductor bare chip, the active surface including a first control terminal and a second control terminal that are correspondingly connected to the first metal layer portion and the second metal layer portion; a second mold compound layer having a first side and a second side facing each other, installed on the first mold compound layer, and the first side thereof being bonded to the second side of the first mold compound layer to cover the control circuit bare die and the second metal layer; the first control terminal of the control circuit bare die is connected to the first external terminal by the first metal layer portion and the first vertical connection structure, The second control terminal of the control circuit bare die is connected to the gate electrode of the high-voltage transistor semiconductor bare chip by the second metal layer portion and the second vertical connection structure, characterized in that the source electrode of the high-voltage transistor semiconductor bare chip is connected to the third external terminal, an electronic component package.

2. The first vertical connection structure includes a first conductive via, and the second vertical connection structure includes a second conductive via. The first conductive via includes a first side and a second side, and the second conductive via includes a first side and a second side. The diameter of the first conductive via decreases from the second side of the first conductive via toward the first side of the first conductive via, and the diameter of the second conductive via decreases from the second side of the second conductive via toward the first side of the second conductive via. The electronic component package according to claim 1.

3. The second conductive via extends from the second side of the first mold compound layer toward the first side of the first mold compound layer, and the second side of the second conductive via and the second side of the first mold compound layer are coplanar. The first side of the second conductive via is in contact with the gate metal layer of the gate electrode of the high-voltage transistor semiconductor bare chip. The electronic component package according to claim 2.

4. The first conductive via extends from the second side of the first mold compound layer toward the first side of the first mold compound layer, and the second side of the first conductive via and the second side of the first mold compound layer are coplanar. The first side of the first conductive via and the first side of the first mold compound layer are not coplanar. The electronic component package according to claim 3.

5. The first side of the first conductive via is in contact with the first external terminal. The electronic component package according to claim 4.

6. The first vertical connection structure further includes a first conductive pillar disposed between the first conductive via and the first external terminal. The first conductive pillar includes a first side and a second side, and the diameter of the first conductive pillar remains unchanged from the second side to the first side of the first conductive pillar. The first side of the first conductive via is in contact with the second side of the first conductive pillar. By extending the first conductive pillar from the first side of the first conductive via toward the first side of the first molding compound layer, the first side of the first conductive pillar is brought into contact with the first external terminal. The electronic component package according to claim 4.

7. The electronic component package according to claim 6, wherein the first side of the first conductive via is coplanar with the first side of the second conductive via.

8. The second metal layer further includes a third metal layer portion that does not directly contact the first metal layer portion and the second metal layer portion, and the second metal layer portion is located between the first metal layer portion and the third metal layer portion. The electronic component package according to claim 1.

9. A third vertical connection structure that penetrates a part of the first molding compound layer and connects the third metal layer portion to the source electrode of the high-voltage transistor semiconductor bare chip; A fourth vertical connection structure that penetrates the first molding compound layer and connects the third metal layer portion to the third external terminal to connect the source electrode of the high-voltage transistor semiconductor bare chip to the third external terminal. The electronic component package according to claim 8 further includes. The electronic component package according to claim 8.

10. The third vertical connection structure includes a third conductive via, and the fourth vertical connection structure includes a fourth conductive via. The third conductive via includes a first side and a second side, the fourth conductive via includes a first side and a second side, and the diameter of the third conductive via decreases from the second side to the first side of the third conductive via. The diameter of the fourth conductive via decreases from the second side to the first side of the fourth conductive via. The electronic component package according to claim 9.

11. The third conductive via extends from the second side of the first mold compound layer toward the first side of the first mold compound layer, and the second side of the third conductive via and the second side of the first mold compound layer are coplanar, and the first side of the third conductive via is in contact with the source metal layer of the source electrode of the high-voltage transistor semiconductor bare chip. The electronic component package according to claim 10.

12. The fourth conductive via extends from the second side of the first mold compound layer toward the first side of the first mold compound layer, and the second side of the fourth conductive via and the second side of the first mold compound layer are coplanar, and the first side of the fourth conductive via and the first side of the first mold compound layer are not coplanar. The electronic component package according to claim 11.

13. The first side of the fourth conductive via is in contact with the third external terminal. The electronic component package according to claim 12.

14. The fourth vertical connection structure further includes a second conductive pillar disposed between the fourth conductive via and the third external terminal. The second conductive pillar includes a first side and a second side, and the diameter of the second conductive pillar remains unchanged from the second side of the second conductive pillar toward the first side of the second conductive pillar. The first side of the fourth conductive via is in contact with the second side of the second conductive pillar, and the second conductive pillar extends from the first side of the fourth conductive via toward the first side of the first mold compound layer, so that the first side of the second conductive pillar is brought into contact with the third external terminal. The electronic component package according to claim 12.

15. The first side of the fourth conductive via is coplanar with the first side of the third conductive via. The electronic component package according to claim 14.

16. Further comprising an integral conductive member, the integral conductive member being a first portion disposed on the source metal layer of the source electrode of the high-voltage transistor semiconductor bare chip, As seen in the above figure, the first part of the integral conductive member extends from the source metal layer of the source electrode outwardly beyond the high-voltage transistor semiconductor bare chip, so that the first end of the first part of the integral conductive member overlaps the high-voltage transistor semiconductor bare chip, and the second end of the first part of the integral conductive member is a first part that does not overlap the high-voltage transistor semiconductor bare chip, and a second part that is connected non-vertically and non-horizontally between the second end of the first part of the integral conductive member and the third external terminal. The electronic component package according to claim 1.

17. The electronic component package according to claim 16, wherein the integral conductive member is coated by the first mold compound layer.

18. A first solder ball disposed on the first metal layer portion and connecting the metal layer on the first control terminal of the control circuit bare die to the first metal layer portion, and a second solder ball disposed on the second metal layer portion and connecting the metal layer on the second control terminal of the control circuit bare die to the second metal layer portion. The electronic component package according to claim 1.

19. The electronic component package according to claim 18, wherein the second mold compound layer coats the first solder ball and the second solder ball.

20. In a method for manufacturing an electronic component package, providing a temporary carrier, forming a first metal layer including a first external terminal, a second external terminal, and a third external terminal that do not directly contact each other on the temporary carrier, a high-voltage transistor semiconductor bare chip having a gate electrode, a source electrode, and a drain electrode, wherein the drain electrode is located on one side of the high-voltage transistor semiconductor bare chip and is connected to the second external terminal, and the gate electrode and the source electrode are located on the opposite other side of the high-voltage transistor semiconductor bare chip installing on the first metal layer, forming a first mold compound layer having a first side and a second side facing each other on the temporary carrier to coat at least a part of the high-voltage transistor semiconductor bare chip and the first metal layer, forming a second metal layer including a first metal layer portion and a second metal layer portion that do not directly contact each other on the second side of the first mold compound layer. Connecting the first metal layer portion to the first external terminal; Connecting the second metal layer portion to the gate electrode of the high-voltage transistor semiconductor bare chip; Providing a control circuit bare die having an active surface facing the gate electrode and the source electrode of the high-voltage transistor semiconductor bare chip, the active surface including first and second control terminals connected corresponding to the first and second metal layer portions, on the first mold compound layer; Forming a second mold compound layer on the first mold compound layer to cover the control circuit bare die and the second metal layer, the second mold compound layer having first and second sides facing each other and the first side being bonded to the second side of the first mold compound layer; Connecting the source electrode of the high-voltage transistor semiconductor bare chip to the third external terminal; Removing the temporary carrier to expose the first external terminal, the second external terminal, and the third external terminal from the first side of the first mold compound layer, characterized by including: Manufacturing method.

21. Disposing a first conductive pillar including first and second sides on the first external terminal, wherein the first side of the first conductive pillar contacts the first external terminal and the diameter of the first conductive pillar remains unchanged from the second side to the first side of the first conductive pillar; Disposing a second conductive pillar including first and second sides on the third external terminal, wherein the first side of the second conductive pillar contacts the third external terminal and the diameter of the second conductive pillar remains unchanged from the second side to the first side of the second conductive pillar; Forming the first mold compound layer on the temporary carrier to cover the first and second conductive pillars; Further including exposing a part of the first conductive pillar, a part of the second conductive pillar, a part of the gate metal layer of the gate electrode, and a part of the source metal layer of the source electrode by forming a plurality of openings in the first mold compound layer; The manufacturing method according to claim 20.

22. A first conductive via including a first side and a second side, wherein the first side of the first conductive via contacts the second side of the first conductive pillar, and the diameter of the first conductive via decreases from the second side of the first conductive via toward the first side of the first conductive via, and forming the first conductive via on the first conductive pillar; A second conductive via including a first side and a second side, wherein the first side of the second conductive via contacts the gate metal layer, and the diameter of the second conductive via decreases from the second side of the second conductive via toward the first side of the second conductive via, and forming the second conductive via on the gate metal layer; A third conductive via including a first side and a second side, wherein the first side of the third conductive via contacts the source metal layer, and the diameter of the third conductive via decreases from the second side of the third conductive via toward the first side of the third conductive via, and forming the third conductive via on the source metal layer; A fourth conductive via including a first side and a second side, wherein the first side of the fourth conductive via contacts the second side of the second conductive pillar, and the diameter of the fourth conductive via decreases from the second side of the fourth conductive via toward the first side of the fourth conductive via, and forming the fourth conductive via on the second conductive pillar; A third metal layer portion that does not directly contact the first metal layer portion and the second metal layer portion, wherein the second metal layer portion is located between the first metal layer portion and the third metal layer portion, and connecting the third metal layer portion to the third conductive via and the fourth conductive via, thereby connecting the source electrode of the high-voltage transistor semiconductor bare chip to the third external terminal, and forming the third metal layer portion on the first mold compound layer; The manufacturing method according to claim 21.

23. The manufacturing method according to claim 22, wherein the second sides of the first conductive via, the second conductive via, the third conductive via, and the fourth conductive via are coplanar with the second side of the first mold compound layer.

24. The manufacturing method according to claim 22, wherein the first sides of the first conductive via, the second conductive via, the third conductive via, and the fourth conductive via are not coplanar with the first side of the first mold compound layer.

25. The manufacturing method according to claim 22, wherein the first sides of the first conductive via, the first side of the second conductive via, the first side of the third conductive via, and the first side of the fourth conductive via are coplanar.

26. Forming the first mold compound layer on the temporary carrier to cover the first external terminal and the third external terminal; Forming a plurality of openings in the first mold compound layer to expose a part of the first external terminal, a part of the third external terminal, a part of the gate metal layer of the gate electrode, and a part of the source metal layer of the source electrode; Forming a first conductive via including a first side and a second side, wherein the first side of the first conductive via is in contact with the first external terminal, and the diameter of the first conductive via decreases from the second side of the first conductive via toward the first side of the first conductive via, on the first external terminal; Forming a second conductive via including a first side and a second side, wherein the first side of the second conductive via is in contact with the gate metal layer, and the diameter of the second conductive via decreases from the second side of the second conductive via toward the first side of the second conductive via, on the gate metal layer; Forming a third conductive via including a first side and a second side, wherein the first side of the third conductive via is in contact with the source metal layer, and the diameter of the third conductive via decreases from the second side of the third conductive via toward the first side of the third conductive via, on the source metal layer; Forming a fourth conductive via including a first side and a second side, wherein the first side of the fourth conductive via is in contact with the third external terminal, and the diameter of the fourth conductive via decreases from the second side of the fourth conductive via toward the first side of the fourth conductive via, on the third external terminal; Forming a third metal layer portion that does not directly contact the first metal layer portion and the second metal layer portion, wherein the second metal layer portion is located between the first metal layer portion and the third metal layer portion, and connecting the third metal layer portion to the third conductive via and the fourth conductive via to connect the source electrode of the high-voltage transistor semiconductor bare chip to the third external terminal, on the first mold compound layer; The manufacturing method according to claim 20.

27. To form an integral conductive member, the integral conductive member being a first portion disposed on the source metal layer of the source electrode of the high-voltage transistor semiconductor bare chip, when viewed from a top view, the first portion of the integral conductive member extends outward from the source metal layer of the source electrode toward the outside of the high-voltage transistor semiconductor bare chip, so that a first end of the first portion of the integral conductive member overlaps the high-voltage transistor semiconductor bare chip, and a second end of the first portion of the integral conductive member is a first portion that does not overlap the high-voltage transistor semiconductor bare chip, forming an integral conductive member including a second portion non-vertically and non-horizontally connected between the second end of the first portion of the integral conductive member and the third external terminal; forming the first mold compound layer on the temporary carrier to cover the integral conductive member and a part of the source metal layer; forming a plurality of openings in the first mold compound layer to expose a part of the first external terminal and a part of the gate metal layer of the gate electrode; forming a first conductive via including a first side and a second side on the first external terminal, wherein the first side of the first conductive via is in contact with the first external terminal, and the diameter of the first conductive via decreases from the second side of the first conductive via toward the first side of the first conductive via; further including forming a second conductive via including a first side and a second side on the gate metal layer, wherein the first side of the second conductive via is in contact with the gate metal layer, and the diameter of the second conductive via decreases from the second side of the second conductive via toward the first side of the second conductive via; The manufacturing method according to claim 20.

28. The electronic component package according to claim 1, wherein a plurality of the first external terminals are arranged along a first side surface of the electronic component package, and a plurality of the third external terminals are arranged along a second side surface different from the first side surface of the electronic component package.

29. The manufacturing method according to claim 20, wherein a plurality of the first external terminals are arranged along a first side surface of the electronic component package, and a plurality of the third external terminals are arranged along a second side surface different from the first side surface of the electronic component package.

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