3-color 3D DRAM stack and method of manufacturing the same

Abstract

A method for reducing wafer bow in a 3D DRAM device is described using a three-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks including two doped SiGe layers with different dopant amounts and / or Si:Ge ratios and a doped silicon layer. A 3D DRAM device is also described.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to 3D DRAM stacks and methods for forming 3D DRAM devices. In particular, embodiments of the present disclosure relate to methods for forming 3D DRAM devices using a 3-color process.

Background Art

[0002] The semiconductor manufacturing industry is interested in increasing the bit density of memory devices. One approach to manufacturing 3D DRAM devices involves epitaxially growing a multilayer stack that includes an epitaxial silicon channel layer and two or more sacrificial epitaxial layers. Subsequent process steps require providing recesses in the sacrificial layers to form access gates and capacitors.

[0003] To scale 3D DRAM beyond the 10nm node, the number of stacks of silicon channels and sacrificial layers needs to be increased to over 100, which can result in 400 epitaxial layers. One problem associated with the increase in the number of layers is wafer bow when the stack exceeds 150μm. The lattice mismatch-induced stress in the silicon channel / sacrificial layer stack is thought to cause this wafer bow. Generally, wafer bow exceeding 150μm of the wafer will prevent subsequent processes such as lithography from being performed accurately.

[0004] During device formation, the sacrificial layer is selectively etched with respect to the silicon channel. Conventional designed layer stacks designed to reduce wafer bow result in a decrease in the etching selectivity ratio.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The current state-of-the-art process requires the additional deposition of a stress-relief film on the backside of the wafer to counteract wafer bow. This only partially alleviates the wafer bow problem because the bow returns when the upper stack is etched or during a thermal process. In addition, the removal of the backside film increases process complexity and cost.

[0006] Accordingly, there is a need for 3D DRAM devices and methods of forming 3D DRAM devices in which wafer bow is reduced and / or etch selectivity is improved.

Means for Solving the Problem

[0007] One or more embodiments of the present disclosure are directed to a method for reducing wafer bow in a 3D DRAM device. A plurality of film stacks are formed on a substrate surface. Each of the film stacks includes a first doped SiGe layer, a second doped SiGe layer, and a doped silicon layer. The first doped SiGe layer has experimental Si 1-x Ge x where x is in the range greater than 0 (>0) to 0.5. The second doped SiGe layer is on the first doped SiGe layer and has experimental Si 1-y Ge y where y is in the range >0 to 0.5. The doped silicon layer is on the second doped SiGe layer. The first doped SiGe layer and the second doped SiGe layer have one or more of different doping amounts or different Si:Ge ratios.

[0008] Additional embodiments of the present disclosure are directed to a method of fabricating a 3D DRAM device. At least 100 film stacks are formed on a substrate surface. Each of the film stacks includes a first doped SiGe layer, a second doped SiGe layer, and a doped silicon layer. The first doped SiGe layer has experimental Si 1-x Ge xhas, where x is in the range greater than 0 (>0) to 0.5. The second doped SiGe layer is on the first doped SiGe layer, with the empirical formula Si 1-y Ge y has, where y is in the range greater than 0 (>0) to 0.5. The first doped SiGe layer and the second doped SiGe layer have one or more of different doping amounts or different Si:Ge ratios. The doped silicon layer is on the second doped SiGe layer. A channel is formed through the film stack to the substrate. One or more of the first doped SiGe layer or the second doped SiGe layer are selectively removed through the channel.

[0009] A further embodiment of the present disclosure is directed to a method of fabricating a 3D DRAM device with reduced wafer warpage. At least 100 film stacks are formed on a substrate surface. Each of the film stacks includes an epitaxially grown first doped SiGe layer, an epitaxially grown second doped SiGe layer, and an epitaxially grown doped silicon layer. The epitaxially grown first doped SiGe layer has the empirical formula Si 1-x Ge x has, where x is in the range greater than 0 (>0) to 0.5. The epitaxially grown second doped SiGe layer is on the first doped SiGe layer, with the empirical formula Si 1-y Ge yhaving, where y is in the range of >0 to 0.5. The first doped SiGe layer and the second doped SiGe layer have one or more of different doping amounts or different Si:Ge ratios. The epitaxially grown doped silicon layer is on the second doped SiGe layer. The first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer each independently contain a dopant selected from carbon or boron in the range of 0.5 to 2.5%. The stress of the second doped SiGe layer is more tensile than the stress of the first doped SiGe layer, and the stress of the first doped SiGe layer is more tensile than the stress of the Si layer. Each of the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer has an etching selectivity greater than 200:1 with respect to other layers when using a halide-based etchant. The channel is formed through the entire stack to the substrate surface by lithography. One or more of the first doped SiGe layer or the second doped SiGe layer are selectively etched from all of the film stack through the channel.

[0010] For the features of the present disclosure to be understood in detail, a more detailed description of the present disclosure, briefly summarized above, may be made by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure and, therefore, the present disclosure should not be considered to be limited to the scope of the present disclosure because other equally effective embodiments can be recognized. The embodiments described herein are shown by way of example and are not limited to the figures of the accompanying drawings in which like reference designations indicate like elements.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Mode for Carrying Out the Invention

[0012] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure can have other embodiments and can be practiced or carried out in various ways.

[0013] As used in this specification and the appended claims, the term "substrate" refers to the surface or a portion of the surface on which the process acts. Those skilled in the art will understand that a reference to a substrate can also refer to only a portion of the substrate, unless the context clearly indicates otherwise. In addition, a reference to depositing on a substrate can mean both a bare substrate and a substrate on which one or more films or features have been deposited or formed thereon.

[0014] As used herein, "substrate" refers to any substrate on which film processing is performed during the manufacturing process or the surface of a material formed on a substrate. For example, the substrate surface on which processing can be performed can be made of materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, etc., and any other materials such as metals, metal nitrides, alloys, and other conductive materials. The substrate includes, without limitation, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV-cure, electron-beam cure, and / or bake the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate, as will be disclosed in more detail below, and the term "substrate surface" is intended to include such an underlying layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface for further processes.

[0015] According to one or more embodiments, the term "on" with respect to a film or a layer of a film includes the film or layer being directly present on a surface, such as a substrate surface, and one or more underlying layers being present between the film or layer and the surface, such as the substrate surface. Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlying layers. In other embodiments, the phrase "directly on" refers to a layer or film that contacts a surface, such as a substrate surface, without an intervening layer. Thus, the phrase "a layer directly on the substrate surface" refers to a layer that directly contacts the substrate surface without an intermediate layer.

[0016] One or more embodiments of the present disclosure advantageously provide a three-color method for forming a 3D DRAM device having a membrane stack with reduced or neutral warpage. When used in this way, the three-color process means that three etching selectivity materials are used. Some embodiments advantageously include epitaxial silicon (Si) and silicon germanium (SiGe) and provide a 3D DRAM membrane stack with reduced or neutral warpage. Some embodiments advantageously provide an epi-Si / SiGe stack with reduced warpage using carbon (C) or boron (B) doping.

[0017] Referring to FIGS. 1-3, one or more embodiments of the present disclosure are directed to a method for reducing wafer warpage in a 3D DRAM device 100 using a three-color process. A plurality of membrane stacks 120 are formed on a substrate 110 having a substrate surface 112. The membrane stack 120 may also be referred to as a three-color stack. The embodiment shown in FIG. 1 shows five membrane stacks 120 (including membrane stacks 120a, 120b). Those skilled in the art will recognize that this is merely representative and that more or fewer membrane stacks 120 may be present. In some embodiments, there are 50, 100, 150, or more than 200 membrane stacks 120.

[0018] At least a portion of the membrane stack 120, or each of the membrane stacks 120, includes a first doped SiGe layer 122, a second doped SiGe layer 124, and a doped silicon layer 126. Those skilled in the art will recognize that the first doped SiGe layer 122 in the first stack 120a is formed on or directly on the substrate surface 112. The first doped SiGe layer 122 of the subsequent membrane stack 120b is formed on or directly on the surface 127 of the doped silicon layer 126 of the previous membrane stack 120a.

[0019] The first doped SiGe layer 122 is experimental Si 1-x Ge x having. In some embodiments, x ranges from greater than 0 (>0) to 0.5. In some embodiments, x ranges from greater than 0 to 0.4, or from greater than 0 to 0.3, or from greater than 0 to 0.2. In some embodiments, x ranges from 0.05, 0.1, 0.15, 0.2, or 0.25 to 0.5.

[0020] The first doped SiGe layer 122 contains a dopant having a concentration in the range of 0.5 atomic % to 2.5 atomic %. In some embodiments, the first doped SiGe layer 122 has a dopant concentration in the range of 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, or 1.5 atomic % to 2.5 atomic %. In some embodiments, the first doped SiGe layer 122 has a dopant concentration in the range of 0.5 atomic % to 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, or 2.5 atomic %.

[0021] The second doped SiGe layer 124 is experimental Si 1-y Ge y having. In some embodiments, y ranges from greater than 0 to 0.5. In some embodiments, y ranges from greater than 0 to 0.4, or from greater than 0 to 0.3, or from greater than 0 to 0.2. In some embodiments, x ranges from 0.05, 0.1, 0.15, 0.2, or 0.25 to 0.5. In some embodiments, x and y of the second doped layer 124 from the first doped layer 122 differ by 0.1, 0.2, 0.3, 0.4, or 0.5 or more. In some embodiments, x is greater than y. In some embodiments, y is greater than x.

[0022] The second doped SiGe layer 124 includes a dopant having a concentration in the range of 0.5 atomic % to 2.5 atomic %. In some embodiments, the second doped SiGe layer 124 has a dopant concentration in the range of 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, or 1.5 atomic % to 2.5 atomic %. In some embodiments, the second doped SiGe layer 124 has a dopant concentration in the range of 0.5 atomic % to 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, or 2.5 atomic %.

[0023] The doped silicon layer 126 includes a dopant having a concentration in the range of 0.5 atomic % to 2.5 atomic %. In some embodiments, the doped silicon layer 126 has a dopant concentration in the range of 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, or 1.5 atomic % to 2.5 atomic %. In some embodiments, the doped silicon layer 126 has a dopant concentration in the range of 0.5 atomic % to 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, or 2.5 atomic %.

[0024] The dopant in any of the first doped SiGe layer 122, the second doped SiGe layer 124, or the doped silicon layer 126 can be any suitable dopant known to those skilled in the art. In some embodiments, the dopant includes group III-V elements. In some embodiments, the dopant includes one or more of carbon or boron. In some embodiments, the dopant consists essentially of one or more of carbon or boron. The term "consisting essentially of" as used in this way means that the composition of the subject component is 95%, 98%, 99%, or 99.5% or more of the described material. For example, a dopant consisting essentially of carbon and / or boron means that 95% or more of all dopant atoms are carbon or boron. In some embodiments, the dopant includes carbon or consists essentially of carbon. In some embodiments, the dopant includes boron or consists essentially of boron.

[0025] In some embodiments, the first doped SiGe layer and the second doped SiGe layer independently include a dopant in the range of 0.5 to 2.5%. In some embodiments, the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer independently include a dopant in the range of 0.5 to 2.5%. The dopant may be the same or different in different layers.

[0026] In some embodiments, x of the first doped SiGe layer 122 and y of the second doped SiGe layer 124 are the same or within 0.1 of each other, and the dopant concentration of each of the first doped SiGe layer 122 and the second doped SiGe layer 124 differs by 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, or 1.0 atomic percent or more.

[0027] The various layers described can be formed by any suitable technique known to those skilled in the art. For example, one or more of the films can be formed by epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, ion implantation, etc. In some embodiments, each of the first doped SiGe layer 122, the second doped SiGe layer 124, and the doped silicon layer 126 is epitaxially grown. In some embodiments, each of the first doped SiGe layer 122, the second doped SiGe layer 124, and the doped silicon layer 126 is independently grown at a temperature in the range of 500°C to 800°C.

[0028] The stress of the film stack 120 is adjusted by the doped layers. In some embodiments, the stress of the second doped SiGe layer 124 is more tensile than the stress of the first doped SiGe layer 122. The stress of the film stack 120 is adjusted by the doped layers. In some embodiments, the stress of the second doped SiGe layer 124 is more tensile than the stress of the first doped SiGe layer 122, and the stress of the first doped SiGe layer 122 is more tensile than the stress of the doped silicon layer 126. In some embodiments, the stress of the first doped SiGe layer 122 and the second doped SiGe layer 124 is more tensile than the stress of the doped silicon layer 126.

[0029] In some embodiments, the overall warp of the wafer is neutral after the formation of 100 film stacks 120. In some embodiments, the overall warp of the wafer is neutral after the formation of 125, 150, 175, or 200 film stacks 120. The term "neutral" as used herein means that the warp across the wafer surface is 150 μm, 125 μm, 100 μm, 75 μm, 50 μm, or 25 μm or less. Some embodiments provide a method of doping an epi film in a controlled manner to reduce the warp of a 1 μm thick stack wafer to about 30 μm in order to enable a DRAM stack of 5 μm or more.

[0030] In the three-color process shown in the figures, the first doped SiGe layer 122 and the second doped SiGe layer 124 are different from each other in terms of how to make the two etchings selective to each other. In some embodiments, the first doped SiGe layer 122 and the second doped SiGe layer 124 have a similar Si:Ge ratio at different doping levels. In some embodiments, the first doped SiGe layer 122 and the second doped SiGe layer 124 have different Si:Ge ratios at similar doping levels. In other words, in some embodiments, the first doped SiGe layer 122 and the second doped SiGe layer 124 have one or more of different doping amounts or different Si:Ge ratios.

[0031] The first doped SiGe layer 122, the second doped SiGe layer 124, and the doped silicon layer 126 are etch-selective relative to each other. In some embodiments, the first doped SiGe layer 122 and the doped silicon layer 126 have an etching selectivity greater than 200:1 when using a halide-based etchant (e.g., 1% HF, NF3 plasma). Halide-based etchants include wet etchants or vapor-phase etchants. In some embodiments, the halide-based etchant is a vapor-phase etchant containing fluorine atoms. In some embodiments, the second doped SiGe layer 124 and the doped silicon layer 126 have an etching selectivity greater than 200:1 when using a halide-based etchant. In some embodiments, the first doped SiGe layer 122 and the second doped SiGe layer 124 have an etching selectivity greater than 200:1 when using a halide-based etchant. In some embodiments, each of the first doped SiGe layer 122, the second doped SiGe layer 124, and the doped silicon layer 126 has an etching selectivity greater than 200:1 with respect to the other layers when using a halide-based etchant.

[0032] The embodiments and the explanatory figures discuss a three - color method, but those skilled in the art will recognize that the doped Si layer and the doped SiGe layer can be configured to provide a system of four or more colors. The additional color (SiGe layer) is etch - selective by one or more of a different dopant amount or a different Si:Ge ratio compared to the first doped SiGe layer 122, the second doped SiGe layer 124, and the doped silicon layer 126.

[0033] Figures 2 and 3 show a portion in region II of the 3D DRAM device 100 of FIG. 1. In some embodiments, this method further includes forming the channel 140 by lithography all the way through the film stack 120 to the substrate surface 112 (or a certain distance within the substrate 110). Those skilled in the art will understand how to form the channel 140 using lithography. After the formation of the channel 140, one or more of the first doped SiGe layer 122 or the second doped SiGe layer 124 are selectively etched from the film stack 120 through the channel 140. FIG. 3 shows that the first doped SiGe layer 122 has been removed and the second doped SiGe layer 124 and the doped silicon layer 126 remain. Those skilled in the art will understand that it is possible to remove the second doped SiGe layer 124 through the channel 140 while leaving the first doped SiGe layer 122 and the doped silicon layer 126.

[0034] References throughout this specification to "one embodiment", "a particular embodiment", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0035] The disclosure of this specification has been described with reference to particular embodiments, but those skilled in the art will understand that the described embodiments are merely examples of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various changes and modifications may be made to the methods and apparatuses of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure can include changes and modifications within the scope of the appended claims and their equivalents.

Claims

1. A method for reducing wafer warpage in a 3D DRAM device, the method comprising: forming a plurality of film stacks on a substrate surface, each of the film stacks comprising: a first doped SiGe layer having experimental Si1-xGex, where x is in the range greater than 0 (>0) to 0.5, the first doped SiGe layer; a second doped SiGe layer on the first doped SiGe layer, the second doped SiGe layer having experimental Si1-yGey, where y is in the range >0 to 0.5, the second doped SiGe layer; a doped silicon layer on the second doped SiGe layer and forming the first doped SiGe layer and the second doped SiGe layer to have one or more of different doping amounts or different Si:Ge ratios. A method comprising.

2. The method according to claim 1, wherein the first doped SiGe layer comprises a dopant in the range of 0.5 atomic % to 2.5 atomic %.

3. The method according to claim 2, wherein the dopant is a group III-V element.

4. The method according to claim 3, wherein the dopant is one or more of carbon or boron.

5. The method according to claim 1, wherein the second doped SiGe layer comprises a dopant in the range of 0.5 atomic % to 2.5 atomic %.

6. The method according to claim 5, wherein the dopant is a group III-V element.

7. The method according to claim 6, wherein the dopant is one or more of carbon or boron.

8. The method according to claim 1, wherein the doped silicon layer comprises a dopant in the range of 0.5 atomic % to 2.5 atomic %.

9. The method according to claim 1, wherein each of the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer is epitaxially grown.

10. The method according to claim 9, wherein each of the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer is independently grown at a temperature in the range of 500 °C to 800 °C.

11. The method according to claim 1, wherein the stress of the second doped SiGe layer has a greater tensile stress than the stress of the first doped SiGe layer, and the stress of the first doped SiGe layer has a greater tensile stress than the stress of the doped silicon layer.

12. The method according to claim 1, wherein when there are 100 film stacks, the wafer warps by an amount less than 150 μm.

13. The method according to claim 1, wherein each of the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer has an etching selectivity greater than 200:1 with respect to other layers when using a halide-based etchant.

14. The method according to claim 1, further comprising forming a channel through all of the film stack to the substrate surface by lithography, and selectively etching one or more of the first doped SiGe layer or the second doped SiGe layer through the channel from all of the film stack.

15. A method of fabricating a 3D DRAM device, the method comprising: forming at least 100 film stacks on a substrate surface, each of the film stacks comprising: a first doped SiGe layer having experimental Si1-xGex, where x is in the range greater than 0 (>0) to 0.5, a first doped SiGe layer; a second doped SiGe layer on the first doped SiGe layer, the second doped SiGe layer having experimental Si1-yGey, where y is in the range >0 to 0.5, and the first doped SiGe layer and the second doped SiGe layer having one or more of different doping amounts or different Si:Ge ratios, a second doped SiGe layer; a doped silicon layer on the second doped SiGe layer including forming forming a channel through the film stack to the substrate; selectively removing one or more of the first doped SiGe layer or the second doped SiGe layer through the channel including the method.

16. The method according to claim 15, wherein the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer each independently contain a dopant in the range of 0.5 atomic % to 2.5 atomic %.

17. The method according to claim 15, wherein each of the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer is epitaxially grown.

18. The method according to claim 15, wherein the stress of the second doped SiGe layer has a greater tensile force than the stress of the first doped SiGe layer, and the stress of the first doped SiGe layer has a greater tensile force than the stress of the doped silicon layer.

19. The method according to claim 1, wherein when there are 100 film stacks, the wafer warps by an amount less than 150 μm.

20. A method of manufacturing a 3D DRAM device with reduced wafer warpage, the method comprising: forming at least 100 film stacks on a substrate surface, each of the film stacks comprising: Experimental formula Si 1-x Ge x An epitaxially grown first doped SiGe layer having, where x is in the range greater than 0 (>0) to 0.5, the epitaxially grown first doped SiGe layer and, An epitaxially grown second doped SiGe layer on the first doped SiGe layer, wherein the second doped SiGe layer has the empirical formula Si 1-y Ge y where y is in the range of >0 to 0.5, and the first doped SiGe layer and the second doped SiGe layer have one or more of different doping amounts or different Si:Ge ratios, an epitaxially grown second doped SiGe layer, and an epitaxially grown doped silicon layer on the second doped SiGe layer; and the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer each independently contain a dopant selected from carbon or boron in the range of 0.5 atomic % to 2.5 atomic %; the stress of the second doped SiGe layer has a greater tensile force than the stress of the first doped SiGe layer, and the stress of the first doped SiGe layer has a greater tensile force than the stress of the silicon layer; forming each of the first doped SiGe layer, the second doped SiGe layer, and the doped silicon layer to have an etching selectivity greater than 200:1 with respect to other layers when using a halide-based etchant; forming a channel through all of the film stacks to the substrate surface by lithography; selectively etching one or more of the first doped SiGe layer or the second doped SiGe layer through the channel from all of the film stacks; and.

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