Die-level cavity heat sink

Abstract

A die level cavity heat sink that can be used in current and emerging packaging technologies to improve die level thermal performance within a package. Alternatively or additionally, a selective heat sink element can be provided to further manage thermal performance within the package by providing a thermal pad from the interior of the package to the surface of the mold cap, allowing additional thermal cooling mechanisms to be utilized to further remove heat from the package area.

Description

Technical Field

[0001]

[0001] This disclosure relates to electronic system packaging. More specifically, in one example, this disclosure relates to heat dissipation techniques and technologies for electronic system packaging. Specifically, in another example, this disclosure relates to integrated circuit packaging technologies having improved heat dissipation performance.

Background Art

[0002]

[0002] Electronic system technology is a field that is being driven towards microelectronics by high performance and miniaturization and is developing rapidly. In particular, it is desirable to reduce the size of electronic systems to smaller, more compact packaging. Thus, the field of microelectronics generally focuses on creating the smallest form factor that fits into the smallest package while providing consistent or improved electronic performance.

[0003]

[0003] These functional electronic systems are generally included in a single package such as a System in Package (SiP) or incorporated into a single integrated circuit known as a System in Chip package (SiC). As technology improves, the improvement in the performance of electronic system circuits and other components, combined with the reduction in size and the nature of both packaging methods, tends to create a heat load that exceeds the capabilities of conventional package heat dissipation techniques and / or technologies. In particular, the higher performance requirements of electronic components in modern electronic systems drive the local heat load in individual integrated circuits, which can create an excessive accumulation of local heat that exceeds the temperature rating of the device. This can potentially cause degradation of the performance and / or early failure of the integrated circuit.

[0004]

[0004] Furthermore, focusing on reducing the size and weight limitations of current SiP and SiC packaging technologies, when combined with the improvement in the performance of the electronic systems contained therein, further worsens the limited ability to control thermal performance.

Summary of the Invention

[0005]

[0005] In one aspect, the present disclosure addresses these and other problems by providing a die level cavity heat sink that can be used within current and new packaging technologies to improve die level thermal performance within a package. Alternatively or in addition, a selective heat sink element is provided to further manage thermal performance within the package by providing a thermal pad from the interior of the package to the surface of the mold cap, and an additional thermal cooling mechanism can be utilized to further remove heat from the package area.

[0006]

[0006] In one aspect, an exemplary embodiment of the present disclosure provides an electronic system package comprising: at least one die operably communicating with a substrate; and a heat sink defining a cavity that includes the at least one die therein, the heat sink being carried by the substrate, wherein the heat sink is operable to direct heat generated from the at least one die into the substrate. This exemplary embodiment or another exemplary embodiment may further provide a first thermal interface material layer between the heat sink and the substrate, and a second thermal interface material layer between the heat sink and the at least one die. This exemplary embodiment or another exemplary embodiment may further provide that the at least one die further comprises a flip chip die. This exemplary embodiment or another exemplary embodiment may further provide a second substrate above the heat sink, wherein the heat sink is further operable to direct heat generated from the at least one die into the second substrate. This exemplary embodiment or another exemplary embodiment may further provide a second die above the second substrate and operably communicating with the second substrate. This exemplary embodiment or another exemplary embodiment may further provide that the second die further comprises one of a flip chip die and a wire bond die. This exemplary embodiment or another exemplary embodiment may further provide an encapsulation layer surrounding the second die. This exemplary embodiment or another exemplary embodiment may further provide that heat generated from the second die is dispersed within the encapsulation layer. This exemplary embodiment or another exemplary embodiment may further provide one or more selective heat sinks within the encapsulation layer surrounding the second die. This exemplary embodiment or another exemplary embodiment may further provide that heat generated from the second die is dispersed within the one or more selective heat sinks and out of the encapsulation layer.This exemplary embodiment or another exemplary embodiment may further provide that the heat sink further includes a thermal interface surface surrounding the die and a thermal interface material layer between the thermal interface surface and the substrate. This exemplary embodiment or another exemplary embodiment may further provide that the heat sink is a first heat sink, and the package further includes a second heat sink extending over the first heat sink and in thermal communication with the first heat sink, and a thermal interface material layer between the first heat sink and the second heat sink.

[0007]

[0007] In another aspect, an exemplary embodiment of the present disclosure includes generating heat with at least one die included in an electronic system package, using a heat sink that defines a cavity internally containing the at least one die to absorb at least a portion of the heat generated by the at least one die, directing a portion of the heat from the heat sink through a thermal interface surface toward a substrate that supports the heat sink thereon, and dissipating a portion of the heat from the die. This exemplary embodiment or another exemplary embodiment may further provide directing at least a part of a portion of the heat toward the substrate that supports the heat sink and directing at least another part of the portion of the heat toward a second substrate that is above the heat sink and in thermal communication with the heat sink. This exemplary embodiment or another exemplary embodiment may further include generating heat with at least one additional die within the electronic system package, wherein the at least one additional die is above the heat sink and is supported by a second substrate in thermal communication with the heat sink, and directing at least a portion of the heat generated by the at least one additional die toward a encapsulation layer surrounding the at least one additional die.

[0008]

[0008] In yet another aspect, an exemplary embodiment of the present disclosure is enclosing a first die carried on a first substrate of an electronic system package within a first heat sink that defines a cavity, the cavity including enclosing the first die therein, generating heat with the first die, generating heat with a second die carried by a second substrate that is above the first heat sink and in thermal communication with the first heat sink, absorbing at least a portion of the heat generated by the first die with the first heat sink, absorbing at least a portion of the heat generated by the second die with a second heat sink within an encapsulation layer surrounding the second die, and directing a portion of the heat from the first die and a portion of the heat from the second die away from the first and second dies, which may provide a method of dissipating heat. This exemplary embodiment or another exemplary embodiment may further provide that directing a portion of the heat away from the first and second dies includes directing a first portion of a portion of the heat from the first die toward the first substrate, directing a second portion of a portion of the heat from the first die toward and into the second heat sink, and dissipating a second portion of the heat from the first die and a portion of the heat from the second die away from the second heat sink and away from the first and second dies. This exemplary embodiment or another exemplary embodiment may further provide generating heat with a third die carried by the second substrate, absorbing at least a portion of the heat generated by the third die with the second heat sink within an encapsulation layer surrounding the third die, and directing a portion of the heat from the third die away from the first, second, and third dies. This exemplary embodiment or another exemplary embodiment may further provide that directing a portion of the heat from the third die away from the first, second, and third dies further includes dissipating a portion of the heat from the third die away from the first, second, and third dies through the second heat sink.This exemplary embodiment or another exemplary embodiment may further provide that the second heat sink further comprises at least one of a heat conductive material slug on the second die, a heat conductive material slug on the third die, and at least one heat conductive material slug within an encapsulation layer between the second die and the third die.

[0009]

[0009] In yet another aspect, an exemplary embodiment of the present disclosure provides an electronic system package comprising a first die operably communicating with a first substrate, a second die operably communicating with a second substrate that is above the first substrate and in thermal communication with the first substrate, an encapsulation layer surrounding the second die, and at least one heat sink within the encapsulation layer surrounding the second die, wherein the at least one heat sink is operable to direct heat generated from the first and second dies out of the package and away from the first and second dies. This exemplary embodiment or another exemplary embodiment may further provide a thermal interface material layer between each of the at least one heat sink and the second substrate. This exemplary embodiment or another exemplary embodiment may further provide that the at least one heat sink further comprises at least one of a heat conductive material slug on the second die and at least one heat conductive material slug adjacent to the second die within the encapsulation layer. This exemplary embodiment or another exemplary embodiment may further provide a third die operably communicating with the second substrate. This exemplary embodiment or another exemplary embodiment may further provide that the at least one heat sink further comprises at least one of a heat conductive material slug on the second die, a heat conductive material slug on the third die, and at least one heat conductive material slug within the encapsulation layer between the second die and the third die. This exemplary embodiment or another exemplary embodiment may further provide that the first die further comprises a flip chip die. This exemplary embodiment or another exemplary embodiment may further provide that the second die further comprises one of a flip chip die and a wire bond die. This exemplary embodiment or another exemplary embodiment may further provide that the third die further comprises one of a flip chip die and a wire bond die. This exemplary embodiment or another exemplary embodiment may further provide a second heat sink between the first die and the second substrate.This exemplary embodiment or another exemplary embodiment may further provide that the second heat sink further includes a cavity defined in the second heat sink, and the cavity includes the first die therein. This exemplary embodiment or another exemplary embodiment may further provide that the second heat sink further includes a thermal interface surface surrounding the first die and a thermal interface material layer between the thermal interface surface and the substrate. This exemplary embodiment or another exemplary embodiment may further provide that heat generated from the first die is dispersed into the first substrate through the second heat sink and through the thermal interface surface.

[0010]

[0010] In yet another aspect, an exemplary embodiment of the present disclosure includes generating heat with a first die carried by a first substrate included in an electronic system package, generating heat with a second die carried by a second substrate above the first die, absorbing at least a portion of the heat generated by the first and second dies with at least one heat sink within an encapsulation layer surrounding the second die, and directing a portion of the heat from the first and second dies away from the first and second dies through the at least one heat sink. This exemplary embodiment or another exemplary embodiment may further include directing a portion of the heat from the first and second dies, wherein directing a first portion of a portion of the heat from the first die is directed towards the first substrate, a second portion of a portion of the heat from the first die is directed into a second heat sink through the second substrate, a first portion of a portion of the heat from the first die is dissipated away from the first and second dies through the first substrate, and a second portion of a portion of the heat from the first die and a portion of the heat from the second die are dissipated away from the first and second dies through the second heat sink. This exemplary embodiment or another exemplary embodiment may further include generating heat with a third die carried by the second substrate and directing at least a portion of the heat generated by the third die towards the at least one heat sink. This exemplary embodiment or another exemplary embodiment may further include dissipating a portion of the heat from the third die away from the first, second, and third dies through the at least one heat sink.

[0011]

[0011] In yet another aspect, an exemplary embodiment of the present disclosure includes a first die operably communicating with a first substrate, and a first heat sink defining a cavity that includes the first die therein, the first heat sink being carried by the first substrate, a second die operably communicating with a second substrate that is above the first substrate and in thermal communication with the first substrate, an encapsulation layer surrounding the second die, and a second heat sink within the encapsulation layer surrounding the second die, wherein the first heat sink is operable to direct heat generated from the first die into the first and second substrates, and the second heat sink is operable to direct heat generated from the second substrate and the second die out of and away from the first and second dies. This exemplary embodiment or another exemplary embodiment may further provide that the first heat sink further includes a thermal interface surface surrounding the first die and a thermal interface material layer between the thermal interface surface and the first substrate. This exemplary embodiment or another exemplary embodiment may further provide a third die operably communicating with the second substrate. This exemplary embodiment or another exemplary embodiment may further provide that the second heat sink further includes at least one of a heat conductive material slug on the second die, a heat conductive material slug on the third die, and at least one heat conductive material slug within the encapsulation layer between the second die and the third die.

Brief Description of the Drawings

[0012]

[0012] The exemplary embodiments of the present disclosure are described in the following description, shown in the drawings, and particularly and distinctly shown and described in the appended claims.

Figure 1

[0013] FIG. 1 is a schematic side view of an exemplary electronic system package that includes a die level cavity heat seat therein, according to one aspect of the present disclosure.

Figure 2

[0014] FIG. 2 is a schematic side view of an electronic system package of an exemplary stacked flip chip package on package (PoP) configuration that includes a die-level cavity heat sheet therein, according to one aspect of the present disclosure.

Figure 3

[0015] FIG. 3 is a schematic side view of an electronic system package of an exemplary thermal flip chip configuration that includes a die-level cavity heat sheet therein, according to one aspect of the present disclosure.

Figure 4

[0016] FIG. 4 is a schematic side view of an electronic system package of an exemplary stacked flip chip PoP configuration that includes a die-level cavity heat sheet and a selective heat sink element therein, according to one aspect of the present disclosure.

Figure 5

[0017] FIG. 5 is a schematic side view of an exemplary electronic system package from FIG. 4 showing an exemplary heat dissipation path, according to one aspect of the present disclosure.

[0013]

[0018] Like numbers refer to like parts throughout the drawings. Detailed description

[0014]

[0019] An electronic system (ES) package is shown and is generally designated by reference numeral 10 in the figures provided with this specification. The ES package 10 is first generally described herein before being provided with the following additional details. The ES package 10 can be any suitable package or packaging technology that includes a functional electronic system contained within a single package known as a system in package (SiP) or a single integrated circuit (IC) known as a system in chip package (SiC). These ES packages are becoming increasingly smaller and more compact, so conventional package-level heat dissipation techniques and technologies can be used to further improve the capabilities of the ES package 10 and dissipate heat from the individual ICs to prevent IC failure.

[0015]

[0020] Thus, referring to FIG. 1, an exemplary ES package 10 is shown and will generally be described as having one or more chip dies 12, hereinafter referred to as one or more dies 12, a flip chip substrate 14, a cavity heat sink 16, one or more thermal interface material layers 18, and a plurality of solder balls 20. As best shown in FIG. 2, the ES package 10 may further include a mold or encapsulation material 22 and a host board 24. As further described herein, the ES package 10 may be suitable for use in stacked packaging configurations as well as individual packaging configurations.

[0016]

[0021] Although described herein as having a component “on top of” or “above” another element or component, it will be understood that the ES package solution may be provided in any suitable orientation. Thus, as used herein, directional or positional terms will be understood to be relative to other components and to the orientation illustrated in the figures. For example, referring to FIG. 1, the host board 24 may be at the bottom of the ES package 10, while the substrate 14 and the cavity heat 16 may be stacked “on top of” or “above” the host board 24. In a real-world application, the host board 24 may be the “top” and the other layers may be provided thereunder.

[0017]

[0022] Die 12 can be an integrated circuit of any suitable material, such as electronic grade silicon, gallium arsenide, or any other suitable semiconductor material. Die 12 can include one or more functional circuits fabricated thereon by any suitable manufacturing means, such as photolithography or the like. The circuits printed on die 12 can be of any suitable or desired purpose, as determined by the desired implementation. Further, as described herein, ES package 10 can be scaled to any suitable size, including die 12, as desired. Die 12 can be considered a six-sided die having a single active surface. The active surface of die 12 can be the surface of die 12 having printed circuits thereon, while the opposite side can be referred to as the back side.

[0018]

[0023] Flip chip substrate 14 (and / or substrate 30 described below) can be any suitable substrate including a printed circuit board (PCB) having ball grid array (BGA) capabilities, and can include any suitable connections or traces, including solder balls or the like, thereon for housing one or more dies 12 used in an integrated circuit or electronic system.

[0019]

[0024] As will be described in further detail below, the cavity heat sink 16 can be a die 12 level cavity heat sink that can be formed from any suitable thermally conductive material. According to one aspect, the cavity heat sink 16 can be formed from copper. The cavity heat sink 16 can include one or more surfaces for interaction with the thermal interface material layer 18, as will be described in further detail below. The cavity heat sink 16 can be made in any suitable size and can include a central cavity 26 that can house one or more dies 12 therein. The cavity heat sink 16 can be a five-sided heat sink in that it can enclose five sides of the six-sided die 12, and the remaining non-enclosed side is the active surface of the die 12. The cavity heat sink 16 can extend over the back surface of the die 12 such that the active surface of the die 12 interacts freely with the substrate 14 while the back and side surfaces are in thermal contact with or in proximity to the heat sink.

[0020]

[0025] The thermal interface material layer 18 can be any suitable material that is inserted between one or more components of the ES package 10 to enhance the thermal coupling between adjacent components. These thermal interface material layers 18 can be any suitable material including, but not limited to, thermal paste, thermal adhesive, thermal gap filler, thermally conductive pad, thermal tape, phase change material, or metallic thermal interface material, as determined by the desired embodiment. These thermal interface material layers 18 can be provided at the intersections of any or all of the components of the ES package 10, as determined by the desired embodiment and as will be described in further detail below. According to one aspect, the thermal interface material 18 can be provided at all intersections between the heat generating element (i.e., die 12) and the heat sink elements (e.g., cavity heat sink 16 and / or selective heat sink 28), as well as between all heat sink elements and the surrounding structures (e.g., substrates 14, 30). The thermal interface material 18 can function as an adhesive between such layers in addition to its role in heat dissipation.

[0021]

[0026] The solder ball 20 can be formed from any suitable solder material such as copper, nickel, and / or gold materials, or combinations thereof, and is soldered to the flip-chip substrate 14 as determined by the desired implementation form, and underfilled with epoxy to enable electrical communication between any integrated circuit, die 12, PCB, or other components of the ES package 10. The solder balls 20 can be strategically placed on the flip-chip substrate 14 and / or between the stacked layers of the ES package 10, as further described below.

[0022]

[0027] The molding material 22 can encapsulate one or more components of the ES package 10 as desired and can be formed from any suitable material including epoxy, epoxy resin, etc. The mold / encapsulant 22 can surround or enclose most of the ES package 10 when the other components of the ES package 10 are assembled.

[0023]

[0028] The host board 24 can be an additional board that can be electrically connected to the flip-chip substrate 14, and components are carried thereon to enable electrical communication between them. The host board 24 can serve any suitable purpose or be any suitable type of host board as determined by the desired implementation. According to one aspect, as illustrated herein, the host board 24 can be connected to the flip-chip substrate 14 via a plurality of solder balls 20.

[0024]

[0029] Continuing to refer to FIG. 1, the cavity heat sink 12 can be utilized within current and new packaging technologies to improve the thermal performance of die 12 within the ES package 10. The cavity heat sink 16 can completely enclose one or more dies 12 within the cavity. As shown in FIG. 1, die 12 can be a flip-chip die having epoxy underfill, which can be a die flipped such that the active surface faces the flip-chip substrate 14. In such a configuration, the cavity heat sink 16 can extend across the non-active surface of die 12 and can be thermally bonded thereto by the thermal interface material layer 18. The cavity 26 can further enable the cavity heat sink 16 to enclose die 12 therein, and at the same time, provide a thermal interface surface (designated by reference numeral 16A) where the heat sink 16 and the flip-chip substrate 14 can contact the layer of thermal interface material 18 therebetween. Although the thermal interface material layer 18 is shown on both sides of die 12 and at the junction of the cavity heat sink 16 and the flip-chip substrate 14, it is understood that the cavity heat sink can surround the outer edge of die 12 such that the thermal interface surface 16A and the thermal interface material layer 18 can be a continuous layer that surrounds die 12 and interacts with the flip-chip substrate 14 through the thermal interface material layer 18.

[0025]

[0030] This thermal interface surface 16A and the thermal interface material layer 18 can facilitate the cavity heat sink 16 in extracting excessive heat from die 12 and directing it into the flip-chip substrate 14 in order to reduce the junction temperature of the die as compared to existing heat dissipation techniques. Further, the cavity heat sink 16 can have a thermal interface surface 16A having a thermal interface material layer 18 that connects the heat sink 16 to the laminate substrate 30, as further described below.

[0026]

[0031] The cavity heat sink 16 can be scaled to a die 12 of any size and / or can be made to fit, if not all, then most of the current packaging constraints. As will be appreciated, the greatest thermal benefit of the cavity heat sink 16 is that it allows the largest surface area of the die 12 to be in thermal communication with the cavity heat sink 16 and thus draw the most heat from the die 12, and can thus be best realized when used with a flip-chip packaging solution.

[0027]

[0032] Referring to FIG. 2, according to one aspect, an exemplary ES package 10 is shown in a stacked flip-chip package-on-package configuration (shown as ES package 10A). This configuration may be similar to the flip-chip packaging solution provided in FIG. 1, but includes an additional stacked substrate 30 and die(s) 12 on the cavity heat sink 16. The stacked substrate 30 may be substantially similar to the flip-chip substrate 14 except for its location on top of the flip-chip substrate 14 and may be a PCB or any other suitable substrate material. The stacked substrate 30 may include an additional mold / encapsulant layer 22. The stacked substrate 30 may further include or carry one or more additional die(s) 12 thereon, as described below.

[0028]

[0033] The stacked substrate 30 may be substantially similar to the solder balls 20 between the flip-chip substrate 14 and the host board 24, but additional solder balls 20 may be used as stacked solder balls disposed between the flip-chip substrate 14 and the stacked substrate 30 and fixed to the flip-chip substrate 14.

[0029]

[0034] Further, the stacked substrate 30 can be adjacent to the cavity heat sink 16 and can be thermally connected to the cavity heat sink 16 by an additional layer of thermal interface material 18, as desired or as determined by the desired implementation form. In this configuration, the first die indicated at 12A can be a flip-chip die 12 as previously described herein. Thus, the first die 12A can be the die 12A included within the cavity 26 of the cavity heat sink 16. The second die 12B can be a die 12 operably connected to the stacked substrate 30. The second die 12B can be a flip-chip die 12 (as shown in FIG. 2) or a wire-bonded die 12, as desired. In this stacked assembly, as further described below, heat can dissipate from the first die 12A through the cavity heat sink 16 into the flip-chip substrate 14 and the stacked substrate 30. Heat can further dissipate into the host board 24 through the mold / capsulation material 22 extending over the second die 12B and through the solder balls 20.

[0030]

[0035] Modeling data for a stacked flip-chip package-on-package configuration utilizing the cavity heat sink 16 indicates that the thermal performance is improved by up to 5 percent based on the maximum junction temperature, compared to the current approach where only the mold material 22 encapsulates the first die 12A between the flip-chip substrate 14 and the stacked substrate 30. Further, the placement of the cavity heat sink 16, with the entire die 12A included within the cavity 26 of the cavity heat sink 16, can further improve the thermal performance by 2 - 3 percent compared to a flat heat sink that extends over the die 12A but has no thermal interface and no layer of thermal interface material 18 between the cavity heat sink 16 and the flip-chip substrate 14.

[0031]

[0036] Referring to FIG. 3, a second exemplary ES package 10B is shown in a thermal flip chip package ball grid array (BGA) configuration. The thermal flip chip BGA package is a current or industry standard heat sink and may include an additional heat sink 32 that can extend over the die, but by including a cavity heat sink 16 between the die 12 and the standard heat sink 32, the thermal performance can be improved by more than 10% compared to current thermal flip chip packages that utilize only the standard heat sink 32. In this configuration, the die 12 can be thinned and extended horizontally to provide additional surface area and / or thermal contact between the die 12 and the cavity heat sink 16 that can further improve the thermal performance of the ES package 10.

[0032]

[0037] This particular configuration, namely a thermal flip chip package that includes a standard heat sink 32, is considered a major industry standard package for flip chip die applications and is often currently recognized as one of the best packaging styles for high heat dissipation within the electronics system industry. Including the cavity heat sink 16 along with the thin die 12 contained within the cavity 26 improves the thermal performance by more than 10% with minimal manufacturing changes and allows this approach to maintain its position as an industry-wide solution while improving its heat dissipation performance. As previously explained herein, the die 12 and the cavity heat sink 16 can be scaled to any suitable size, further enabling flexibility in their use.

[0033]

[0038] Referring to FIG. 4, a package-on-package configuration of an ES package 10C similar to the ES package 10A of FIG. 2 is shown, which has a first die 12, 12A utilizing a cavity heat sink 16 and second and third dies 12B and 12C stacked thereon. As shown, the ES package 10C includes the same elements or components as described previously herein, namely, die 12, base flip-chip substrate 14, cavity heat sink 16, several thermal interface material layers 18, a plurality of solder balls 20, mold / encapsulant 22, host board 24, and stacked substrate 30. Further, the ES package 10C may include components of one or more optional heat sinks 28, which will be described in more detail below.

[0034]

[0039] In particular, compared to the ES package 10A of FIG. 2, the ES package 10C of FIG. 4 may be substantially similar in that it includes flip-chip dies 12, 12A on a base flip-chip substrate 14 having a cavity heat sink 16 that includes die 12A within its cavity 26. On top of the cavity heat sink 16, there may similarly be a stacked substrate 30 having one or more additional dies 12, shown here as dies 12B and 12C, which may be flip-chip dies 12 or alternatively, wire-bond dies 12, as will be further described below. The ES package 10C may be electrically connected to the host board 24 through one or more solder balls 20, as determined by its desired implementation.

[0035]

[0040] ES package 10C may be different from ES package 10A in that it may further include one or more selectable heat sink 28 elements that may be or include one or more thermally conductive material slugs disposed on die 12B and / or 12C when die 12B and 12C are flip chip dies. When die 12B and 12C are wire bond dies, one or more selectable heat sinks 28 may be selectively disposed within the mold / encapsulant 22 in the free space between die 12B and 12C. Similarly, the selectable heat sink 28 may be disposed in both regions, i.e., between and on die 12, if space and / or installation parameters permit.

[0036]

[0041] The selectable heat sink 28 can function as a conductive heat path that absorbs heat from or otherwise extracts heat from the main regions within the ES package 10C and can exit out through the top of the ES package 10C, as further described below. According to one aspect, the selectable heat sink 28 can extract sufficient heat from die 12, draw it into the mold / encapsulant 22, and dissipate it there. According to another aspect, the components of the selectable heat sink 28 can be at the same height as the mold / encapsulant 22 (or can extend slightly outside the mold / encapsulant 22) so as to be exposed outside the ES package 10C, which can further enable other thermal cooling mechanisms, such as a fan included within the electronic system, to further dissipate heat from die 12 and other critical regions within the ES package 10C.

[0037]

[0042] The selective heat sink 28 can be formed of any suitable thermally conductive material including, but not limited to, copper, gold, etc. The selective heat sink 28, similar to the cavity heat sink 16, can be scaled to any die size or available package area and can be placed or configured at any suitable location determined by the individual package configuration. Thus, the selective heat sink 28 can be easily incorporated into existing packaging techniques through placement in the empty space or void regions between components to further enhance the heat dissipation of the entire package.

[0038]

[0043] The selective heat sink 28 can be further utilized in packages that do not have the cavity heat sink 16 or, alternatively, can be included in packages that utilize the cavity heat sink 16 therein. Similarly, the ES package 10 can include the cavity heat sink 16 but, depending on its particular implementation and configuration, may omit the use of the selective heat sink 28 or, otherwise, may not be required. Including only the selective heat sink 28 can improve the thermal performance by about 2.5 percent compared to packages that strictly utilize a molding compound on the die 12 and substrates 14, 30. Overall, the ES package 10 that utilizes both the cavity heat sink 16 and the selective heat sink 28 can further improve the flow of heat away from key areas of the ES package 10.

[0039]

[0044] Referring to FIG. 5, the ES package 10C of FIG. 4 is shown with additional arrows indicating various paths that heat can take after being generated by die 12. As shown in the figure, the wavy lines / arrows represent heat when it is generated, while the standard arrows represent the paths that heat can take as it leaves a major area such as die 12. These arrows are generally arranged to represent the paths by which heat can move through the various components of ES package 10C and are intended as representative examples. Thus, heat can move in any or all directions or dissipate in other ways, but by including cavity heat sink 16 and / or selective heat sink 28, a path of least resistance for heat to leave the major components or dissipate in other ways can be provided, thereby further improving this heat dissipation.

[0040]

[0045] The improvement in thermal performance provided by cavity heat sink 16, selective heat sink 28, or a combination thereof is intended and further understood to remove heat from package 10, dissipate heat within package 10 from the major components, and / or keep die 12 below the critical operating temperature for as long as possible. When ES package 10 is adapted for steady-state type electronic equipment, including cavity heat sink 16 and / or selective heat sink 28 can make it possible to draw heat into an area where it can be further dissipated through other heat removal components such as a fan or other cooling components. For example, in a computer or personal electronic device, by adding cavity heat sink 16 and / or selective heat sink 28, heat can be directed towards the cooling fan or vents contained therein. In short-lived electronic systems such as those found in many military applications, including cavity heat sink 16 and / or selective heat sink 28 can function to dissipate heat within or outside package 10 and provide the longest temporary lifespan of die 12 while maintaining high performance throughout the life of die 12.

[0041]

[0046] According to one example, an ES package 10 including a cavity heat sink 16 and / or a selective heat sink 28 can be used as a processor or memory in a GPS guidance system that can be utilized in military applications. The lifespan of such applications may require peak performance of the die 12, but that is only for a short period, often less than a few minutes. Therefore, including the cavity heat sink 16 and / or the selective heat sink 28 can be important as it may enable maximum performance levels throughout the lifespan of the ES package 10.

[0042]

[0047] According to one aspect, it will be understood that additional cavity heat sinks and / or selective heat sinks can be included beyond those illustrated and described herein while remaining within the scope of the present disclosure when additional substrate layers and additional layers including dies are utilized.

[0043]

[0048] Having thus described the elements and components of the exemplary ES package 10, the method of use will now be described.

[0044]

[0049] As described herein, the method of use is described with reference to FIG. 5, but the described method(s) are representative examples and it will be understood that they can be applied to all embodiments of the ES package 10 having a cavity heat sink 16 and / or a selective heat sink 28 therein. In particular, due to the scalability of the cavity heat sink 16 and the selective heat sink 28, it will be understood that the methods described herein can similarly include other packaging solutions not explicitly described herein.

[0045]

[0050] Thus, referring to FIG. 5, in one example, the ES package 10 can be assembled in any suitable configuration (such as a stacked flip chip package on package configuration as shown) according to standard manufacturing techniques. The ES package 10 can further be installed as a component thereof in other electronic systems and operated therewith. For example, if the ES package 10 is part of a navigation or GPS system, it can be installed as a component of a larger system. Similarly, any number of ES packages 10 can be utilized in a larger system as desired or as determined by the desired implementation.

[0046]

[0051] Once installed and entering normal operation, it is understood that the die 12 begins to generate heat and its temperature level rapidly rises. As shown by the waveform arrow in FIG. 5, when heat is generated, the heat is radiated outward from the die 12 in substantially all directions. The active surface of the die 12 engaged with the substrates 14, 30 can reflect heat through the back and side surfaces of the die 12 or otherwise more easily disperse the heat. The heat exiting the first die 12A can be easily absorbed by the heat sink 16. Similarly, the heat generated by the second and third dies 12B and 12C can be easily absorbed by the selective heat sink 28. As described above, these heat sinks 16 and 28 represent the path of least resistance to the heat generated by the die 12 and thus function to draw heat therefrom and direct the heat elsewhere.

[0047]

[0052] In particular, when the first die 12A is fully encapsulated within the ES package 10, the cavity heat sink 16 can draw heat from the die 12A and disperse that heat into the substrate 14 through the heat interface surface 16A and the thermal interface material layer 18. Similarly, if the ES package 10 is a stacked package (such as package 10C), the cavity heat sink can further dissipate heat into the stacked substrate 30.

[0048]

[0053] Similar to the cavity heat sink 16, the selective heat sink 28 can absorb the heat generated by the second die 12B and the third die 12C and, again, draw heat therefrom as the path of least resistance. This heat can be dissipated out of the ES package 10 or at least partially into the mold / capsulant 22 surrounding the heat sink 28. Further, any heat transmitted through the cavity heat sink 16 to the laminated substrate 30 can similarly follow the least restrictive path through the selective heat sink 28, as shown.

[0049]

[0054] Ultimately, the goal of all ES packaging techniques is to extract heat from the main area, i.e., the die 12, and dissipate that heat to other remote structures and / or to the external environment of the package. As shown and described herein, including the cavity heat sink 16 and / or the selective heat sink 28 can provide a more efficient and longer-lasting solution while maintaining size scalability and minimizing the impact on cost and manufacturing considerations as compared to current packaging techniques.

[0050]

[0055] Various inventive concepts can be embodied as one or more methods, and an example thereof is provided. The operations executed as part of the method can be ordered in any suitable manner. Accordingly, embodiments can be configured in which the operations are executed in an order different than that illustrated, including performing some operations simultaneously, even though shown as sequential operations in the exemplary embodiments.

[0051]

[0056] Although various embodiments of the present invention have been described and illustrated herein, those skilled in the art will readily envision various other means and / or structures for performing the functions described herein and / or for obtaining one or more of the results and / or advantages described herein, and each such variation and / or modification is to be regarded as within the scope of the embodiments of the invention described herein. More generally, those skilled in the art will understand that all parameters, dimensions, materials, and configurations described herein are illustrative, and that actual parameters, dimensions, materials, and / or configurations will depend on the particular application or applications for which the teachings of the invention are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described herein. Accordingly, the foregoing embodiments are presented by way of example only, and it is to be understood that the embodiments of the invention may be practiced otherwise than as specifically described and claimed within the scope of the appended claims and their equivalents. Embodiments of the invention of the present disclosure are directed to each of the individual features, systems, articles, materials, kits, and / or methods described herein. Additionally, any combination of two or more such features, systems, articles, materials, kits, and / or methods is included within the scope of the invention of the present disclosure if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent.

[0052]

[0057] All definitions defined and used herein are to be understood as governing over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of defined terms.

[0053]

[0058] As used in this specification and the claims, the articles "a" and "an" should be understood to mean "at least one" unless the contrary is clearly indicated. The phrase "and / or" as used in this specification and the claims (if any) should be understood to mean "either or both" of the elements so combined, i.e., elements that may be present conjunctively in some cases and disjunctively in other cases. A plurality of elements listed with "and / or" should likewise be construed as "one or more" of the elements so combined. Other elements may optionally be present, whether or not they are related to the specifically identified elements, other than those specifically identified by the "and / or" clause. Thus, by way of non-limiting example, a reference to "A and / or B" when used with open-ended language such as "comprising" may, in one embodiment, refer to only A (optionally including elements other than B), in another embodiment, refer to only B (optionally including elements other than A), and in yet another embodiment, refer to both A and B (optionally including other elements), etc. As used in this specification and the claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" is inclusive, i.e., it includes at least one of some elements or a list of elements, but also includes more than one, and optionally, additional items not listed. In contrast, terms that clearly indicate the contrary, such as "only one of" or "exactly one of", or "consisting of" when used in the claims, refer to exactly one element of some elements or a list of elements. Generally, the term "or" as used in this specification should be construed as indicating exclusive alternatives (i.e., "either one or the other, but not both") only when preceded by exclusive terms such as "either", "one of", "only one of", or "exactly one of"."Consisting essentially of", when used in a claim, shall have its ordinary meaning as used in the field of patent law.

[0054]

[0059] As used herein and in the claims, the phrase "at least one", referring to a list of one or more elements, means at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of every element specifically recited within the list of elements, and is to be understood not to exclude any combination of elements in the list of elements. This definition also allows for elements to optionally exist, whether or not related to the specifically recited elements, in addition to those specifically recited elements within the list of elements to which the phrase "at least one" refers. Thus, by way of non-limiting example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently, "at least one of A and / or B") can, in one embodiment, refer to at least one including two or more A's where B optionally does not exist (and optionally includes elements other than B), in another embodiment, can refer to at least one including two or more B's where A optionally does not exist (and optionally includes elements other than A), and in yet another embodiment, can refer to at least one optionally including two or more A's, and at least one optionally including two or more B's (and optionally including other elements), etc.

[0055]

[0060] When a feature or element is referred to in this specification as being "above" another feature or element, it can be directly above that other feature or element, or intervening features and / or elements may be present. In contrast, when a feature or element is referred to as being "directly above" another feature or element, no intervening features or elements are present. When a feature or element is referred to as being "connected", "attached", or "coupled" to another feature or element, it will be understood that it can be directly connected, attached, or coupled to that other feature or element, or intervening features or elements may be present. In contrast, when a feature or element is referred to as being "directly connected", "directly attached", or "directly coupled" to another feature or element, no intervening features or elements are present. Although described or illustrated with respect to one embodiment, the features and elements so described or illustrated can be applied to other embodiments. Also, those skilled in the art will understand that a reference to a structure or feature being "adjacent" to another feature can have portions that overlap or are present under the adjacent feature.

[0056]

[0061] Spatially relative terms, such as "under", "below", "lower", "over", "upper", "above", "behind", "in front of", and the like, may be used herein for ease of explanation to describe the relationship of one element or feature illustrated in the figures to another element(s) or feature(s). It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is inverted, an element described as "under" or "beneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary term "under" can encompass both an orientation of over and under. The device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein will be interpreted accordingly. Similarly, terms such as "upwardly", "downwardly", "vertical", "horizontal", "lateral", "transverse", "longitudinal", and the like are used herein for purposes of description only, unless otherwise indicated.

[0057]

[0062] The terms "first" and "second" may be used herein to describe various features / elements, but these features / elements should not be limited by these terms unless the context indicates otherwise. These terms may be used to distinguish one feature / element from another. Thus, without departing from the teachings of the present invention, the first feature / element described herein may be referred to as the second feature / element, and similarly, the second feature / element described herein may be referred to as the first feature / element.

[0058]

[0063] One embodiment is an implementation or example of the present disclosure. References to "one embodiment", "an embodiment", "some embodiments", "one particular embodiment", "exemplary embodiment", or "other embodiments" in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some embodiments of the invention, but not necessarily all embodiments. The various occurrences of "one embodiment", "an embodiment", "some embodiments", "one particular embodiment", "exemplary embodiment", or "other embodiments" do not necessarily all refer to the same embodiment.

[0059]

[0064] When a component, feature, structure, or characteristic is described in this specification as "may be included", "may be contained", or "can be included", that particular component, feature, structure, or characteristic need not be included. When this specification or the claims refer to "one" element, it does not mean that there is only one such element. When this specification or the claims refer to "additional" elements, it does not exclude the presence of two or more additional elements.

[0060]

[0065] As used in this specification and the claims, including when used in examples, unless otherwise specified, all numbers may be read as if the term "about" or "approximately" preceded them, even if the term does not explicitly appear. The phrases "about" or "approximately" can be used to indicate that the value and / or position being described is within a reasonable expected range of the value and / or position when describing size and / or position. For example, a numerical value can have a value that is + / −0.1% of the recited value (or range of values), + / −1% of the recited value (or range of values), + / −2% of the recited value (or range of values), + / −5% of the recited value (or range of values), + / −10% of the recited value (or range of values), etc. Any numerical range recited in this specification is intended to include all sub-ranges subsumed therein.

[0061]

[0066] In addition, the methods of carrying out the present disclosure may be performed in an order different from that described herein. Accordingly, the order of the methods should not be read as limiting unless explicitly stated. It will be recognized that similar results can be achieved by performing some of the method steps in a different order.

[0062]

[0067] In the claims, and in the above specification, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "accompanying," "holding," "consisting of," and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" are to be considered closed or semi-closed transitional phrases, respectively, as set forth in the Manual of Patent Examining Procedure of the United States Patent and Trademark Office for patent examination procedures.

[0063]

[0068] In the foregoing description, certain terms have been used for the sake of brevity, clarity, and understanding. Such terms are used for explanatory purposes and are not intended to imply any unnecessary limitations beyond the requirements of the prior art.

[0064]

[0069] Further, the descriptions and illustrations of the various embodiments of the present disclosure are examples, and the present disclosure is not limited to the exact details shown or described. The invention described in the claims of the present application at the time of filing is appended below. [C1] An electronic system package, comprising: at least one die operably communicating with a substrate; a heat sink defining a cavity that internally contains the at least one die, the heat sink being supported by the substrate; wherein the heat sink is operable to direct heat generated from the at least one die into the substrate; A package comprising the above. [C2] A first thermal interface material layer between the heat sink and the substrate; A second thermal interface material layer between the heat sink and the at least one die; The package according to C1, further comprising the above. [C3] The at least one die further comprises: a flip chip die The package according to C1, further comprising the above. [C4] The package according to C3, further comprising a second substrate above the heat sink, wherein the heat sink is further operable to direct heat generated from the at least one die into the second substrate. [C5] The package according to C4, further comprising a second die above the second substrate and operably communicating with the second substrate. [C6] The second die further comprises: one of a flip chip die and a wire bond die The package according to C5, further comprising the above. [C7] The package according to C5, further comprising an encapsulation layer surrounding the second die. [C8] The package according to C7, wherein heat generated from the second die is dispersed within the encapsulation layer. [C9] The package according to C7, further comprising one or more selective heat sinks within the encapsulation layer surrounding the second die. [C10] The package according to C9, wherein heat generated from the second die is dispersed within the one or more selective heat sinks and dispersed out of the encapsulation layer. [C11] The heat sink further comprises: a thermal interface surface surrounding the die; a thermal interface material layer between the thermal interface surface and the substrate; The package according to C1, further comprising the above. [C12] The heat sink is a first heat sink, and the package further comprises: a second heat sink extending over the first heat sink and in thermal communication with the first heat sink; a thermal interface material layer between the first heat sink and the second heat sink; The package according to C1, further comprising the above. [C13] A method of dissipating heat, comprising: Generating heat with at least one die included within an electronic system package, and using a heat sink that defines a cavity containing the at least one die therein to absorb at least a portion of the heat generated by the at least one die, Directing the portion of the heat from the heat sink through a thermal interface surface toward a substrate on which the heat sink is carried, Dispersing the portion of the heat from the die, A method comprising. [C14] Directing at least a part of the portion of the heat toward the substrate carrying the heat sink, Directing at least another part of the portion of the heat toward a second substrate that is above the heat sink and in thermal communication with the heat sink, The method according to C13, further comprising. [C15] Generating heat with at least one additional die within the electronic system package, the at least one additional die being above the heat sink and carried by a second substrate in thermal communication with the heat sink, Directing at least a portion of the heat generated by the at least one additional die toward an encapsulation layer surrounding the at least one additional die, The method according to C13, further comprising. [C16] A method of dispersing heat, Encapsulating a first die carried on a first substrate of an electronic system package within a first heat sink that defines a cavity, the cavity containing the first die therein, Generating heat with the first die, Generating heat with a second die that is above the first heat sink and carried by a second substrate in thermal communication with the first heat sink, Absorbing at least a portion of the heat generated by the first die with the first heat sink, Using a second heat sink within an encapsulation layer surrounding the second die to absorb at least a portion of the heat generated by the second die, Directing the portion of the heat from the first die and the portion of the heat from the second die away from the first and second dies, A method comprising. [C17] Directing the portion of the heat away from the first and second dies, Directing a first portion of the portion of the heat from the first die toward the first substrate, directing a second portion of the heat from the first die to the second substrate and into the second heat sink; dissipating, from the second heat sink, the second portion of the heat from the first die and the portion of the heat from the second die, dissipating away from the first and second dies; The method of claim C16, further comprising: [C18] generating heat with a third die carried by the second substrate; absorbing at least a portion of the heat generated by the third die with the second heat sink within the encapsulation layer surrounding the third die; directing a portion of the heat from the third die away from the first, second, and third dies; The method of claim C16, further comprising: [C19] Directing a portion of the heat from the third die away from the first, second, and third dies comprises: dissipating a portion of the heat from the third die away from the first, second, and third dies through the second heat sink; The method of claim C18, further comprising: [C20] The second heat sink comprises: at least one of a heat conductive material slug over the second die, a heat conductive material slug over the third die, and at least one heat conductive material slug within the encapsulation layer between the second die and the third die; The method of claim C18, further comprising:

Claims

1. An electronic system package, comprising: at least one die operably communicating with a substrate; a heat sink defining a cavity that includes the at least one die therein, the heat sink being carried by the substrate; a second substrate above the heat sink; wherein the heat sink is operable to direct heat generated from the at least one die into the substrate and into the second substrate. A package comprising the above.

2. A first thermal interface material layer between the heat sink and the substrate; and a second thermal interface material layer between the heat sink and the at least one die. The package according to claim 1, further comprising the above.

3. The at least one die further comprises a flip chip die. The package according to claim 1, further comprising the above.

4. The package according to claim 1, further comprising a second die above the second substrate and operably communicating with the second substrate.

5. The second die further comprises one of a flip chip die and a wire bond die. The package according to claim 4, further comprising the above.

6. The package according to claim 4, further comprising an encapsulation layer surrounding the second die.

7. For the package according to claim 6, heat generated from the second die is dispersed within the encapsulation layer.

8. The package according to claim 6, further comprising one or more selective heat sinks within the encapsulation layer surrounding the second die.

9. For the package according to claim 8, heat generated from the second die is dispersed within the one or more selective heat sinks and dispersed out of the encapsulation layer.

10. The heat sink further comprises a thermal interface surface surrounding the die; and a thermal interface material layer between the thermal interface surface and the substrate. The package according to claim 1, further comprising the above.

11. The heat sink is a first heat sink, and the package further comprises a second heat sink extending over the first heat sink and in thermal communication with the first heat sink; and a thermal interface material layer between the first heat sink and the second heat sink. The package according to claim 1, further comprising the above.

12. A method of dissipating heat, comprising: generating heat with at least one die included within an electronic system package; Using a heat sink that defines a cavity containing the at least one die therein, absorbing at least a portion of the heat generated by the at least one die, directing the portion of the heat from the heat sink through a thermal interface surface toward a substrate on which the heat sink is carried, and dispersing the portion of the heat from the die A method comprising.

13. directing at least a part of the portion of the heat toward the substrate carrying the heat sink, directing at least another part of the portion of the heat toward a second substrate that is above the heat sink and in thermal communication with the heat sink The method according to claim 12, further comprising.

14. generating heat with at least one additional die within the electronic system package, the at least one additional die being above the heat sink and carried by a second substrate in thermal communication with the heat sink, directing at least a portion of the heat generated by the at least one additional die toward an encapsulation layer surrounding the at least one additional die The method according to claim 12, further comprising.

15. A method of dissipating heat, comprising: encapsulating a first die carried on a first substrate of an electronic system package within a first heat sink that defines a cavity, the cavity containing the first die therein, generating heat with the first die, generating heat using a second die that is above the first heat sink and carried by a second substrate in thermal communication with the first heat sink, absorbing at least a portion of the heat generated by the first die with the first heat sink, absorbing at least a portion of the heat generated by the second die using a second heat sink within an encapsulation layer surrounding the second die, and directing the portion of the heat from the first die and the portion of the heat from the second die away from the first and second dies A method comprising.

16. Directing the portion of the heat away from the first and second dies comprises: directing a first portion of the portion of the heat from the first die toward the first substrate, directing a second portion of the portion of the heat from the first die to the second substrate and into the second heat sink; dissipating, from the second heat sink, the second portion of the portion of the heat from the first die and the portion of the heat from the second die, dissipating away from the first and second dies; The method of claim 15, further comprising. **Claim 17** generating heat with a third die carried by the second substrate; absorbing at least a portion of the heat generated by the third die with the second heat sink within the encapsulation layer surrounding the third die; directing the portion of the heat from the third die away from the first, second, and third dies; The method of claim 15, further comprising. **Claim 18** Directing the portion of the heat from the third die away from the first, second, and third dies comprises: dissipating the portion of the heat from the third die away from the first, second, and third dies through the second heat sink; The method of claim 17, further comprising. **Claim 19** The second heat sink comprises: at least one of a heat conductive material slug on the second die, a heat conductive material slug on the third die, and at least one heat conductive material slug within the encapsulation layer between the second die and the third die; The method of claim 17, further comprising.

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