Oxide semiconductor film, method for manufacturing the same, transistor, semiconductor device, electronic circuit, electric device, electronic device, vehicle, and power unit

Abstract

To provide an oxide semiconductor film having a high mobility. An oxide semiconductor film containing indium as a main component, wherein the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface opposite to the lower surface is 0.06 nm or less.

Description

Technical Field

[0001] The present disclosure relates to an oxide semiconductor film, a method for manufacturing the same, a transistor, a semiconductor device, an electronic circuit, an electric device, an electronic device, a vehicle, and a power unit.

Background Art

[0002] In recent years, transistors using an oxide semiconductor film have been tried to be applied not only to display applications but also to memory applications (e.g., DRAM, NAND, ReRAM, FeRAM, and FeFET), logic IC applications (e.g., CPU, MPU, BEOL, 3D-LSI, CMOS), sensor applications (e.g., CMOS image sensor), and the like. Research has been conducted to further improve the performance of the oxide semiconductor film including for display applications.

[0003] For example, Patent Document 1 discloses a field effect device having an insulating film layer, a channel layer laminated on the insulating film layer, and three electrodes as a gate electrode, a source electrode, and a drain electrode, wherein the channel layer has a surface roughness of 0.2 nm or more and 1.3 nm or less, and the channel layer is made of an amorphous oxide semiconductor containing one or more elements selected from In, Ga, Sn, and Zn. According to Patent Document 1, by setting the surface roughness to 0.2 nm or more and 1.3 nm or less, good mobility and a large on / off ratio are achieved.

[0004] By the way, currently, as a method for forming an oxide semiconductor film, a sputtering method is widely used. In recent years, a method for forming an oxide semiconductor film by atomic layer deposition (hereinafter sometimes referred to as "ALD") instead of the sputtering method has attracted attention (for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] Currently, higher-performance transistors are demanded, and for this purpose, an oxide semiconductor film with high mobility is desired. Therefore, an object in one aspect of the present disclosure is to provide an oxide semiconductor film having a high field-effect mobility.

[0007] The inventors of the present invention have conducted intensive research and found that when the difference between the roughness of the interface between the substrate and the oxide semiconductor film and the roughness of the surface of the oxide semiconductor film (or the interface with a protective film formed on the oxide semiconductor film) is within a predetermined range, the field-effect mobility of the oxide semiconductor film becomes high, and thus the present invention has been completed. [Means for Solving the Problems]

[0008] The present invention is as follows. [1] An oxide semiconductor film containing indium as a main component, wherein the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface opposite to the lower surface is 0.06 nm or less, oxide semiconductor film. [2] wherein the film thickness of the oxide semiconductor film is 20.0 mm or less, The oxide semiconductor film according to [1]. [3] wherein the film thickness of the oxide semiconductor film is less than 10.0 mm, The oxide semiconductor film according to [1] or [2]. [4] wherein the roughness 1 of the lower surface is less than 0.2 nm, The oxide semiconductor film according to any one of [1] to [3]. [5] The atomic ratio of indium to all the metal elements contained in the oxide semiconductor film is 62.0 at% or more. The oxide semiconductor film according to any one of [1] to [4]. [6] The atomic ratio of indium to all the metal elements contained in the oxide semiconductor film is 100.0 at% or less. The oxide semiconductor film according to any one of [1] to [5]. [7] Further containing gallium. The oxide semiconductor film according to any one of [1] to [6]. [8] The atomic ratio of gallium to all the metal elements contained in the oxide semiconductor film is 20.0 at% or less. The oxide semiconductor film according to any one of [1] to [7]. [9] The atomic ratio of gallium to all the metal elements contained in the oxide semiconductor film is 0.1 at% or more. The oxide semiconductor film according to any one of [1] to [8].

[10] The electron diffraction spot or cross-section in electron diffraction shows a Bixbyite structure. The oxide semiconductor film according to any one of [1] to [9].

[11] The mobility is 70.0 cm2 / Vs or more. The oxide semiconductor film according to any one of [1] to

[10] .

[12] Formed by atomic layer deposition. The oxide semiconductor film according to any one of [1] to

[11] .

[13] An oxide semiconductor film containing indium as a main component, The difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface opposite to the lower surface is 0.06 nm or less. The film thickness of the oxide semiconductor film is less than 10.0 mm. The roughness 1 of the lower surface is less than 0.2 nm. Oxide semiconductor film.

[14] The atomic ratio of gallium to all the metal elements contained in the oxide semiconductor film is 0.1 at% or more. The oxide semiconductor film according to

[13] .

[15] The mobility is 50.0 cm2 / Vs or more. The oxide semiconductor film according to

[14] .

[16] Formed by atomic layer deposition The oxide semiconductor film according to

[15] .

[17] On a substrate, comprising a layer made of the oxide semiconductor film according to any one of [1] to

[16] , an insulating layer, and an electrode. Transistor

[18] Bottom gate - top contact type or top gate - top contact type The transistor according to

[17] .

[19] Three - dimensional vertical channel type The transistor according to

[17] .

[20] The transistor according to any one of

[17] to

[19] , wherein the insulating layer contains at least one selected from the group consisting of gallium oxide, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.

[21] Further comprising a first insulating film and a second insulating film. The electrode is a gate electrode. The first insulating film is located between the gate electrode and the layer made of the oxide semiconductor film. The second insulating film is located on the opposite side of the layer made of the oxide semiconductor film with respect to the first insulating film and is in contact with the layer made of the oxide semiconductor film. The second insulating film contains gallium oxide. The transistor according to any one of

[17] to

[20] .

[22] The electrode contains at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), chromium (Cr), gold (Au), zinc (Zn), niobium (Nb), manganese (Mn), and titanium nitride (TiN). The transistor according to any one of

[17] to

[21] .

[23] A semiconductor device including the transistor according to any one of

[17] to

[22] .

[24] The semiconductor device according to

[23] , which is a semiconductor memory device.

[25] An electronic circuit including the semiconductor device according to

[23] or

[24] .

[26] An electric device, an electronic device, a vehicle, or a power unit including the electronic circuit according to

[25] .

[27] A method for manufacturing an oxide semiconductor film according to any one of [1] to

[16] , the method including a film formation step of forming a film by an atomic layer deposition method using an indium-containing precursor.

[28] Using triethylindium as the indium-containing precursor. The method for manufacturing an oxide semiconductor film according to

[27] .

[29] Using a gallium-containing precursor in the film formation step. The method for manufacturing an oxide semiconductor film according to

[27] or

[28] .

[30] A method for analyzing the quality of an oxide semiconductor film containing indium as a main component, Determining whether the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface is 0.06 nm or less, Method.

[31] When it is determined that the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface is 0.06 nm or less, further including evaluating that the quality of the oxide semiconductor film is good, The method according to

[30] .

Effect of the Invention

[0009] An effect of one aspect of the present invention is to provide an oxide semiconductor film having a high field-effect mobility.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2A

Figure 2B

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Figure 2D

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 4A

Figure 4B

Figure 4C

Figure 5

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments for carrying out the present invention (hereinafter simply referred to as "the present embodiment") will be described in detail with reference to the drawings as necessary. However, the present invention is not limited to the following present embodiment. The present invention can be variously modified without departing from its gist. In the drawings, the same reference numerals are assigned to the same elements, and redundant explanations are omitted. Also, the positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios.

[0012] 1. Oxide semiconductor film The oxide semiconductor film of the present embodiment is an oxide semiconductor film containing indium as a main component, and the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface opposite to the lower surface is 0.06 nm or less.

[0013] Here, the lower surface of the oxide semiconductor film means the interface with the surface formed prior to the oxide semiconductor film, that is, the surface to be formed with the oxide semiconductor film, and the interface on the opposite side is referred to as the upper surface. Specifically, for example, in the oxide semiconductor film of the embodiments described later, the interface between the gate insulating film and the oxide semiconductor film is the lower surface, and the interface between the protective film and the oxide semiconductor film is the upper surface. The lower surface and the upper surface only need to be continuous surfaces, which may be flat surfaces, multi-step surfaces, or curved surfaces. Even if the lower surface and the upper surface are macroscopically curved surfaces, they can be regarded as flat surfaces in microscopic observations such as when performing TEM observations described later.

[0014] The roughness analysis is not particularly limited. For example, a TEM image is binarized with a predetermined threshold value, and an interface for performing the roughness analysis is obtained from the binarized image. Specifically, the method described in the embodiments can be used, and thereby the arithmetic mean roughness (Ra) can be calculated.

[0015] The mechanism by which the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface (hereinafter, also simply referred to as "roughness difference") is 0.06 nm or less and the field-effect mobility of the oxide semiconductor film (hereinafter, also simply referred to as "mobility") increases is not particularly limited, but is considered as follows. The fact that the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface is 0.06 nm or less means that the film formed from the lower surface toward the upper surface has grown in a layered manner. Due to the layered growth, each layer grows uniformly, so it is considered that the stress and irregularities generated during the film formation process are minimized. For this reason, the defects and impurities in the crystal are reduced, and a high-quality film with few crystal defects can be obtained, so the mobility of the oxide semiconductor film is improved. Also, the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface only needs to be 0.06 nm or less, and discussions on the effects based on the difference in roughness difference within the range of 0.06 nm or less are difficult because they are affected by the resolution of the measuring device and sample processing. Also, although the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface has not been focused on in conventional studies, as a result of intensive studies, it has been found that it is a parameter representing the film quality of an oxide semiconductor thin film that can improve the mobility of the oxide semiconductor film without being affected by the roughness of the underlying layer.

[0016] It is preferable that the roughness 1 of the lower surface is less than 1.0 nm, more preferably 0.5 nm or less, still more preferably 0.2 nm or less, and still more preferably 0.15 nm or less. Also, the roughness of the lower surface is not particularly limited, but for example, it may be 0.1 nm or more. The mobility does not change only depending on the value of the roughness 1 of the lower surface, but when it is 1.0 nm or less, the factors that hinder the layered growth are reduced, and as a result, the mobility tends to be easily improved.

[0017] From the viewpoint of further improving the mobility, the surface roughness 2 of the upper surface is preferably less than 1.0 nm, more preferably 0.5 nm or less, and even more preferably 0.2 nm or less. Further, the surface roughness of the upper surface is not particularly limited, and may be, for example, 0.1 nm or more.

[0018] The roughnesses 1 and 2 (hereinafter, also simply referred to as "roughness") are calculated based on the cross-sectional TEM observation image after obtaining the cross-sectional TEM observation image. The method for obtaining the cross-sectional TEM observation image is specifically performed by the method described in the examples. The method for calculating the roughness based on the obtained image is obtained by the following method. First, the contour lines (interface profiles) of the upper and lower surfaces are digitized as x-z coordinate data using digital image processing software, and then the roughness Ra can be obtained as the average of the absolute values of the heights with respect to the reference line which is the average height. Specifically, it can be calculated by the following formula (1). Formula 1

[0019] TIFF0007711340000001.tif25170 In formula (1), x is the position on the reference line, z(x) is the vertical height with respect to the reference line at position x, and L means the total length of the reference line of the interface. Note that the height of the reference line is the average height of z(x).

[0020] When the oxide semiconductor film of this embodiment is used for various memory applications such as densification, for example, the film thickness is preferably small. From such a viewpoint, the film thickness is preferably 20.0 nm or less, more preferably 15.0 nm or less, still more preferably 10.0 nm or less, even more preferably less than 10.0 nm, still more preferably 6.0 nm or less, and even more preferably 5.0 nm or less. Note that the lower limit of the film thickness may usually be 1.0 nm or more, 2.0 nm or more, or 3.0 nm or more.

[0021] The film thickness of the oxide semiconductor film of this embodiment can be measured by cross-sectional TEM. Specifically, it is measured by the method described in the examples. The measurement of the film thickness by cross-sectional TEM is carried out based on the cross-sectional TEM observation image.

[0022] In the measurement of the film thickness using cross-sectional TEM observation, the interface line that is the basis for calculating the film thickness does not necessarily have to be parallel to the surface to be measured (for example, the surface of the crystalline oxide semiconductor film), but it may be parallel to the underlying layer of the crystalline oxide semiconductor film. The crystalline oxide semiconductor film is defined as the distance between the two interfaces above and below it in the region where the metal indium composition is 50 at% or more of the total metal composition. Also, when the upper surface in contact with the atmosphere is the upper layer surface of the crystalline oxide semiconductor film, the upper layer surface may be defined as the surface, or when the upper layer surface and the underlying layer are not parallel, the distance from the perpendicular line from the lower layer surface to the point where it intersects the upper layer surface may be used as the film thickness. It is preferable to use the average value obtained from three or more thinned cross-sectional TEM samples for the film thickness. Also, when obtaining the film thickness from the thinned cross-sectional TEM samples, it is preferable that the image scales in the vertical and horizontal directions of the two-dimensional TEM image are 10 times or more and 100 times or less with respect to the film thickness.

[0023] The oxide semiconductor constituting the oxide semiconductor film of this embodiment is not particularly limited as long as it contains indium as a main component, and any oxide that can function as a semiconductor may be used. Specifically, examples of the oxide semiconductor include metal oxides.

[0024] In this specification, "containing indium as a main component" means that the atomic ratio of indium (hereinafter also simply referred to as "In") to all metal elements contained in the oxide semiconductor film ([In] / ([In] + [all metal elements other than In]) × 100) is 50 at% or more. The atomic ratio of indium to all metal elements contained in the oxide semiconductor film may be 55.0 at% or more, 60.0 at% or more, 62.0 at% or more, 65.0 at% or more, 70.0 at% or more, 75.0 at% or more, 80.0 at% or more, 85.0 at% or more, 90.0 at% or more, 95.0 at% or more, 97.0 at% or more, or 98.0 at% or more from the viewpoint of more preferably crystallizing the oxide semiconductor film. The upper limit of the atomic ratio is 100.0 at% or less, and may be 99.9 at% or less, 99.5 at% or less, 99.0 at% or less, or 98.5 at% or less.

[0025] Note that the content (atomic ratio) of each metal element in the crystalline oxide semiconductor film of this embodiment is not particularly limited, but can be analyzed, for example, by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0026] In the oxide semiconductor film of this embodiment, when In and metal elements other than In described later are contained, the atomic ratio of indium to all metal elements contained in the oxide semiconductor film is preferably 80.0 at% or more and 99.9 at% or less, more preferably 85.0 at% or more and 99.5 at% or less, and still more preferably 90.0 at% or more and 99.0 at% or less from the viewpoint of more preferably crystallizing the oxide semiconductor film.

[0027] In addition to In, the oxide semiconductor film of the present embodiment may contain a metal element. Such metal elements are not particularly limited, and examples thereof include Mg, Al, Si, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ce, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln (lanthanoid element), Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb, Yb, and Bi. The metal element is preferably selected from Ga, Al, Sn, and Zn, and more preferably selected from Ga, Al, and Sn. Other elements that may be included include, for example, H, B, C, N, O, F, S, Cl, and Ar. The metal oxides that the oxide semiconductor film of the present embodiment may contain are not particularly limited, and examples thereof include indium oxide (IO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium aluminum oxide (IGAO), indium gallium tin zinc oxide (IGTZO), and indium tin zinc oxide (ITZO).

[0028] The oxide semiconductor film of the present embodiment preferably contains a trivalent metal. As the trivalent metal, gallium (also simply referred to as "Ga") and aluminum (also simply referred to as "Al") are preferable, and Ga is more preferable. When the oxide semiconductor film of the present embodiment contains gallium, the atomic ratio of gallium to all the metal elements contained in the oxide semiconductor film ([Ga] / ([Ga]+[all metal elements other than Ga])×100) is preferably 0.1 at% or more and 20.0 at% or less, 0.5 at% or more and 15.0 at% or less, and 1.0 at% or more and 10.0 at% or less from the viewpoint of more suitably crystallizing the oxide semiconductor film. When the oxide semiconductor film of the present embodiment contains aluminum, the atomic ratio of aluminum to all the metal elements contained in the oxide semiconductor film ([Al] / ([Al]+[all metal elements other than Al])×100) is preferably 0.1 at% or more and 20.0 at% or less, 0.5 at% or more and 15.0 at% or less, and 1.0 at% or more and 10.0 at% or less from the viewpoint of more suitably crystallizing the oxide semiconductor film.

[0029] In this embodiment, it is preferable that the oxide semiconductor film contains In and Ga and their atomic ratios satisfy the following formula (11). In the formula regarding the atomic ratio, "[ ]" indicates the concentration of each element (for example, atom / cm 3 ). 0.1 at% ≦ [Ga] / ([In] + [Ga]) ≦ 20 at% …(11) Here, in addition to unavoidable impurities and O (oxygen atoms), it may contain C (carbon atoms), N (nitrogen atoms), F (fluorine atoms), or H (hydrogen atoms). By setting the composition range as described above, the ratio of In increases, and Ga tends to substitute for In sites at an annealing temperature of about 300° C. and crystallize into a bixbyite structure. Furthermore, by adding Ga, which has a strong binding force with oxygen, oxygen deficiency after annealing can be suppressed, and a stable film as a semiconductor can be formed.

[0030] In this embodiment, the oxide semiconductor film preferably contains at least one element X selected from the group consisting of B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu, and the total atomic ratio of these elements satisfies the following formula (12). [X] / ([In] + [X]) < 15 at% …(12) Here, in addition to unavoidable impurities and O, it may contain C, N, F, or H. By setting the composition range as described above, the ratio of In increases, and it can crystallize into a bixbyite structure in which X substitutes for In sites at an annealing temperature of about 300° C. Furthermore, by adding element X, which has a strong binding force with oxygen, oxygen deficiency after annealing can be suppressed, and a stable film as a semiconductor can be formed.

[0031] In this embodiment, the oxide semiconductor film is composed of In, Ga, and at least one element X selected from the group consisting of B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu. When a metal element other than In and Ga is used as the additive element X, the atomic ratio may satisfy the following formulas (13) and (14). [Ga] / ([In]+[Ga]+[X])<22.5at% …(13) [X] / ([In]+[Ga]+[X])<8.0at% …(14) Here, in addition to inevitable impurities and O, it may contain C, N, F, or H. By setting the composition range as described above, the ratio of In increases, and crystallization can occur into a bixbyite structure in which Ga is substituted for In sites at an annealing temperature of about 300°C. Further, by adding the additive element X having a strong binding force with oxygen, oxygen deficiency after annealing can be further suppressed, and a stable film can be formed as a semiconductor.

[0032] In this embodiment, the oxide semiconductor film is composed of In, Sn, and at least one element X selected from the group consisting of B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu. When a metal element other than In and Sn is used as the element X, the atomic ratio may satisfy the following formulas (15) and (16). [Sn] / ([In]+[Sn]+[X])<20at% …(15) [X] / ([In]+[Sn]+[X])<8.0at% …(16) Here, in addition to inevitable impurities and O, it may contain C, N, F, or H. By setting such a composition range, the ratio of In increases, and even at a low annealing temperature such as 300 °C, it can crystallize into a bixbyite structure in which Sn is substituted for the In site. Since Sn has a large ionic radius and a large orbital overlap with In, it can maintain high mobility. Further, by adding an element X having a strong binding force with oxygen, oxygen deficiency after annealing can be further suppressed, and a stable film as a semiconductor can be formed.

[0033] In this embodiment, the oxide semiconductor film is composed of In as a metal element, Zn, and at least one element X selected from the group consisting of B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb, and Lu. When a metal element other than In and Zn is used as the element X, the atomic ratio may satisfy the following formulas (17) and (18). [Zn] / ([In]+[Zn]+[X])<12at% …(17) [X] / ([In]+[Zn]+[X])<8.0at% …(18) Here, in addition to inevitable impurities and O, it may contain C, N, F, or H. By setting the above composition range, the ratio of In increases, and it can crystallize into a bixbyite structure in which Zn is substituted for the In site at an annealing temperature of about 300 °C. By adding Zn, the film immediately after film formation can be made into an amorphous state, and it can be processed without residue during semiconductor patterning with an acid when manufacturing a semiconductor device such as a transistor. Further, by adding an element X having a strong binding force with oxygen, oxygen deficiency after annealing can be suppressed, and a stable film as a semiconductor can be formed.

[0034] In this embodiment, in the oxide semiconductor film, it is preferable that the electron beam diffraction spot or cross section in electron beam diffraction shows a bixbyite structure. Regarding the electron beam diffraction spot in electron beam diffraction, it is obtained by the method and conditions described in the examples, and the presence or absence of a bixbyite structure is determined.

[0035] In addition, in this embodiment, the determination of the presence or absence of the bicrystal structure may be made using an X-ray diffraction pattern in X-ray diffraction (XRD). In that case, even if the X-ray diffraction pattern does not show a bicrystal structure, if the electron diffraction spot shows a bicrystal structure, it can be determined that the bicrystal structure is present.

[0036] By the oxide semiconductor film of this embodiment showing a bicrystal structure, there is a tendency to obtain an effect that the carrier concentration is further reduced and the mobility is higher.

[0037] From the viewpoint of operating well as a transistor, the mobility of the oxide semiconductor film of this embodiment is preferably 70.0 cm 2 / Vs or more, more preferably 80 cm 2 / Vs or more, still more preferably 100 cm 2 / Vs or more, particularly preferably 120 cm 2 / Vs or more. The mobility of the oxide semiconductor film is measured by the method described in the examples. The upper limit of the mobility is not particularly limited, but for example, it may be 300 cm 2 / Vs or less.

[0038] 2. Method for manufacturing an oxide semiconductor film The manufacturing method of the oxide semiconductor film of this embodiment is not particularly limited, but a conventionally known method can be used. Such methods include, for example, DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, ALD (atomic layer deposition method), PLD, MO-CVD, ICP-CVD, sol-gel method, coating method, and mist CVD. Among them, it is preferable to use a step of forming an oxide semiconductor film by a sputtering method or an atomic layer deposition method (ALD), and it is more preferable to use a step of forming a film by the atomic layer deposition method (ALD). That is, in this embodiment, it is more preferable that the oxide semiconductor film is formed by the atomic layer deposition method (ALD). Further, the manufacturing method of the oxide semiconductor film of this embodiment preferably includes a film forming step of forming an oxide semiconductor film by an atomic layer deposition method using an indium-containing precursor. First, the manufacturing method of the oxide semiconductor film by ALD will be described, and the sputtering method will be described later.

[0039] 2.1. Atomic layer deposition method The atomic layer deposition method (ALD) is a thin film forming method in which a process of alternately exposing a substrate surface to a raw material (sometimes referred to as a precursor or a precurser) containing a metal element constituting an oxide semiconductor film and an oxidizing agent is defined as one cycle, and one atomic layer is formed in one cycle, and this cycle is repeated until a desired film thickness is obtained to form an oxide semiconductor film. The specific process of ALD will be described later.

[0040] According to ALD, it is possible to deposit an ultrathin film of several nm by an accurately controlled method. Therefore, ALD is a film forming method of an oxide semiconductor film suitable for the manufacture of three-dimensional vertical channel type transistor memories and the like developed in recent years.

[0041] Generally, one atomic layer deposition cycle of ALD includes the following four steps (1) to (4). (1) Vaporize the precursor, which is the raw material, in a container containing the precursor, introduce it into the chamber, apply a predetermined system pressure, react it with the OH groups on the substrate surface or film surface for a predetermined time, and adsorb single molecules. When the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization. When the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization for adjustment. (2) Remove unreacted raw materials and by-produced gases from the chamber by purging with an inert gas, and deposit one layer of atomic layer. (3) Introduce a reactive gas into the chamber, and oxidize the metal of the precursor using heat, plasma, etc. (4) Remove unreacted oxidizing agents and by-produced gases by purging with an inert gas. After step (4), return to step (1), and repeat steps (1) to (4) until the desired film thickness is obtained.

[0042] In this embodiment, a well-known ALD apparatus can be used. Specifically, for example, an apparatus capable of bubbling and supplying a precursor, an apparatus having a vaporization chamber, etc. can be mentioned. Also, an apparatus capable of performing plasma treatment, etc. on a reactive gas (oxidizing agent) can be mentioned. Note that not only a single-wafer apparatus equipped with a film formation chamber but also an apparatus capable of simultaneously processing multiple wafers using a batch furnace can be used.

[0043] Examples of the types of ALD precursors include organometals (e.g., AlMe3), metal hydrides (e.g., AsH3), metal alkoxides (e.g., Ti(OCHMe2)4), metal amides (e.g., Ti(NMe2)4), β-diketonates (e.g., Co(acac)2, cobalt(II) acetylacetonate), metallocenes (e.g., MgCp2), and metal amidinates. Various metal compounds are commercially available as ALD precursors. A precursor and an oxidizing agent that can form the target oxide semiconductor film may be selected. If a precursor capable of forming the target oxide semiconductor film is not commercially available, it may be newly synthesized.

[0044] Examples of indium-containing precursors (precursors) used for depositing a layer containing indium (for example, a layer of indium oxide (In2O3)) by ALD include, for example, indium trichloride (InCl3), trimethylindium (TMI), triethylindium (TEIn), cyclopentadienylindium(I) (InCp), ethylcyclopentadienylindium(I) (InEtCp), indium acetylacetonate (In(acac)3), indium 2,2,6,6-tetramethyl-3,5-heptanedionate (In(tmhd)3), indium-tris-guanidinate (for example, tris-N,N-dimethyl-N’,N’’-diisopropylguanidinate indium (In[(i-PrN)2CNR2]3, R = Me), diethyl [bis-(trimethylsilyl)amide]indium (Et2InN(TMS)2), diethyl [1,1,1-trimethyl-N-(trimethylsilyl)silanaminato]indium (INCA), [3-(dimethylamino)propyl]dimethylindium (DADI), N,N-dimethylbutylamine trimethylindium (DATI), (1-dimethylamino-2-methyl-2-propoxy)indium (In(dmamp)3), dimethyl(N-ethoxy-2,2-dimethylpropanamide)indium (Me2In(EDPA)), and tris(N,N’-diisopropylacetamidinate)indium(III). These ALD precursors may be used alone or in combination of two or more.

[0045] Examples of gallium-containing precursors (precursors) used for depositing a gallium-containing layer (e.g., a gallium oxide layer) by ALD include trimethylgallium (TMG), triethylgallium (TEG), gallium triisopropoxide (Ga(OCH(CH3)2)3), gallium trimethoxide (Ga(OCH3)3), gallium trichloride (GaCl3), gallium dichloride dimethylamide (GaCl2(N(CH3)2)), gallium acetylacetonate (Ga(acac)3), gallium triimide (Ga(NR)3 where R is an organic group), gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) (Ga(tmhd)3), cyclopentadienylgallium ethylcyclopentadienyl (GaEcCp), cyclopentadienylgallium(I) (GaCp), and ethylcyclopentadienylgallium(I) (GaEtCp). These ALD precursors may be used alone or in combination of two or more.

[0046] From the viewpoints of the vapor pressure and decomposition temperature (ALD window) of the precursor, it is preferable to use triethyl indium as the indium-containing precursor (precursor).

[0047] Furthermore, for the metal cations constituting the oxide semiconductor film, when In is the main component, a thin film may be formed using a precursor containing other metal cations as an additive.

[0048] Examples of the precursor include at least one compound selected from the group consisting of compounds used as organic ligands such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, and organic amine compounds, and a compound of indium or a metal cation.

[0049] Examples of the metal cation include lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0050] Furthermore, examples of the compound that coordinates to the metal cation containing indium include the following. Depending on the valence of the central metal, a plurality of the following coordination species coordinate, and the plurality of coordination species may be the same compound, or a plurality of different coordination species may be combined.

[0051] Examples of the alkyl compound include methyl, ethyl, propyl, isopropyl, butyl, sec-butyl, isobutyl, tert-butyl, pentyl, isopentyl, and tert-pentyl.

[0052] Examples of the alcohol compound include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, sec-butyl alcohol, isobutyl alcohol, tert-butyl alcohol, pentyl alcohol, isopentyl alcohol, and tert-pentyl alcohol; ether alcohols such as 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, 2-butoxy-1,1-dimethylethanol, 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; and dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, and diethylamino-2-methyl-2-pentanol.

[0053] Examples of the glycol compound include 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol.

[0054] Examples of β-diketone compounds include alkyl-substituted β-diketones such as acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethylheptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethylnonane-4,6-dione, 2-methyl-6-ethyldecane-3,5-dione, and 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione, and 1,3-diperfluorohexylpropane-1,3-dione; and ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione, and 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione.

[0055] Examples of cyclopentadiene compounds include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, sec-butylcyclopentadiene, isobutylcyclopentadiene, tert-butylcyclopentadiene, dimethylcyclopentadiene, and tetramethylcyclopentadiene.

[0056] Examples of the organic amine compound include methylamine, ethylamine, propylamine, isopropylamine, butylamine, sec-butylamine, tert-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, and isopropylmethylamine.

[0057] In addition, chloride or fluoride may coordinate with the metal cation, or a combination of chloride or fluoride and a compound that coordinates with the metal cation may be used. Also, part or all of the hydrogen of the compound that coordinates with the metal cation may be replaced with chlorine or fluorine.

[0058] Among these precursors, trimethylaluminum, trimethylgallium, triethylgallium, dimethylzinc, and diethylzinc can form a more excellent oxide semiconductor film when combined with an indium-based precursor.

[0059] The precursors coordinated with the above-described compounds are known in the art, and their production methods are also known. For example, when an alcohol compound is used as the organic ligand, a precursor can be produced by reacting the above-described metal inorganic salt or its hydrate with the alkali metal alkoxide of the alcohol compound. Here, examples of the metal inorganic salt or its hydrate include metal halides and nitrates. Examples of the alkali metal alkoxide include sodium alkoxide, lithium alkoxide, and potassium alkoxide.

[0060] Examples of the oxidizing agent used in ALD include H2O, O2, O3, O2 plasma, H2O plasma, and hydrogen peroxide (H2O2). These oxidizing agents may be used alone or in combination of two or more.

[0061] When using two or more oxidizing agents, the two or more oxidizing agents may be used simultaneously, or they may be used individually while changing the two or more oxidizing agents. For example, by using two types of O2 plasma and H2O plasma as oxidizing agents, both advantages can be utilized: the high mobility obtained when using O2 plasma and the effect of reducing the carbon concentration and improving the stability of mobility against heat treatment obtained when using H2O plasma. By using two or more oxidizing agents, high mobility and low carbon concentration can be adjusted. Depending on the intended effect, the usage ratio, usage order, number of cycles, etc. of O2 plasma and H2O plasma may be appropriately selected.

[0062] The types of precursors and oxidizing agents are as described above. From the viewpoints of the electrical characteristics and functionality of the oxide semiconductor thin film, in the present embodiment, in addition to the indium-containing precursor, it is preferable to use a gallium-containing precursor, and more preferably to use a gallium-containing precursor in addition to triethylindium.

[0063] The pressure of the system (inside the film formation chamber) in step (1) may be appropriately set according to the type of precursor, substrate temperature, etc., and is usually 1 Pa or more and 10,000 Pa or less, preferably 10 Pa or more and 1,000 Pa or less, more preferably 50 Pa or more and 500 Pa or less, and still more preferably 80 Pa or more and 120 Pa or less.

[0064] To vaporize the precursor, the container containing the precursor may be heated to a temperature at which the precursor is sufficiently vaporized as necessary. When using a precursor with a high vapor pressure, the container containing the precursor may be cooled as necessary. In one embodiment, the container containing the indium-containing precursor (for example, triethylindium) is heated in the range of usually 25°C or more and 150°C or less. The above temperature is preferably 50°C or more and 150°C or less, and more preferably 75°C or more and 125°C or less.

[0065] In this embodiment, the substrate temperature during film formation is usually in the range of 50°C or higher and 600°C or lower, preferably 85°C or higher and 500°C or lower, more preferably 80°C or higher and 350°C or lower, and still more preferably 100°C or higher and 250°C or lower.

[0066] Note that the growth amount of the oxide semiconductor film per ALD process cycle varies depending on the precursor used during film formation, the types of reactive gases, and the substrate temperature during film formation. Fig. 1 shows the growth amount of the oxide semiconductor film when H2O plasma and O2 plasma are used and the substrate temperature is changed. The substrate temperature during film formation is preferably in a range where the growth amount of the film is stable. From the graph in Fig. 1, it can be seen that when using H2O plasma and O2 plasma, the growth amount is stable and suitable in the range of 100°C or higher and 150°C or lower for the substrate temperature during film formation. Also, this temperature range where the growth amount is stable is called the ALD window.

[0067] The growth amount per ALD process cycle is called Growth per cycle (GPC), and can be calculated, for example, by measuring the film thickness of the oxide semiconductor after repeating 30 cycles of ALD cycles. Here, GPC varies depending on the combination of the precursor, the oxidizing agent, and the substrate temperature, and also varies depending on the substrate type or the condition of the underlying layer. Therefore, since the above number of cycles varies depending on many factors such as the types of the precursor and the oxidizing agent and their combination, the substrate type, the substrate temperature during film formation, and the desired film thickness, it can be appropriately set considering these factors.

[0068] Also, when using O3 as the oxidizing agent, the substrate temperature during film formation is preferably above 100°C, more preferably 110°C or higher and 250°C or lower, still more preferably 120°C or higher and 230°C or lower, and even more preferably 130°C or higher and 220°C or lower.

[0069] Examples of the inert gas for purging unreacted raw materials and unreacted oxidizing agents include argon and nitrogen. In this embodiment, argon or nitrogen is preferred.

[0070] In the above step (3), in this embodiment, it is preferable to generate plasma of a reactive gas (oxidant).

[0071] 2.2. Sputtering method As an example of the method for manufacturing an oxide semiconductor film according to this embodiment, there is a manufacturing method including a step of forming an oxide semiconductor film by sputtering using a sputtering target. In the film formation step by sputtering, at least one gas selected from the group consisting of argon, oxygen, hydrogen, water vapor, and nitrogen, which substantially does not contain an impurity gas, is used as a sputtering gas. The "impurity" contained in the sputtering gas means a trace element that is not intentionally added and does not substantially affect the sputtering performance.

[0072] The atomic composition ratio of the oxide film obtained by the sputtering method reflects the atomic composition ratio of the oxide sintered body in the sputtering target. Therefore, it is preferable to form a film using a sputtering target including an oxide sintered body having an atomic composition ratio similar to the desired atomic composition ratio of the oxide film. Accordingly, the description of the content of each atom in the oxide semiconductor film according to this embodiment can be cited as the description of the content of each atom in the oxide sintered body in the sputtering target.

[0073] The target used in the sputtering method preferably has an impurity metal content of 500 ppm or less, more preferably 100 ppm or less. In particular, for tetravalent Sn, by setting the content in the target to 500 ppm or less, more preferably 100 ppm or less, even if the Sn contained in the target remains as an impurity in the oxide film, it does not become an electron scattering source in the oxide semiconductor film of the present embodiment, and good TFT characteristics can be obtained. The content of the impurity metal in the target can be measured by ICP (Inductive Coupled Plasma)-MS (Mass Spectrometry). The "impurities" contained in the target are elements that are mixed in during the raw material or manufacturing process and are not intentionally added, and are trace elements that do not substantially affect the performance of the target and the semiconductor. "Impurity metal" means a metal element among the elements as "impurities".

[0074] In the film formation process by the sputtering method, for example, it can be manufactured by forming an oxide semiconductor film mainly composed of In on the lower layers constituting the TFT, such as a substrate, a buffer layer, and an insulating layer. The film formation method is not particularly limited, and examples include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, and reactive sputtering. When forming a film by sputtering, it is preferable to form an oxide semiconductor film by sputtering using at least one gas selected from the group consisting of argon, oxygen, hydrogen, water vapor, and nitrogen that substantially does not contain impurity gas, by means of a planar sputtering cathode device or a rotary sputtering cathode device using the sputtering target according to the present embodiment.

[0075] When the sputtering gas "substantially does not contain impurity gas", it means that except for the inclusion of adsorbed water accompanying the insertion of the gas and inevitable gases that cannot be excluded such as chamber leaks and adsorbed gases (inevitable impurity gases), no impurity gas other than the gas used is actively introduced. In the present embodiment, as the sputtering gas, for example, a mixed gas of commercially available high-purity argon and high-purity oxygen can be used. If possible, it is preferable to exclude impurities from the sputtering gas.

[0076] The proportion of impurity gas in the sputtering gas is preferably 0.10% by volume or less, and more preferably 0.05% by volume or less. If the proportion of impurity gas is 0.10% by volume or less, the crystallization of the oxide film proceeds without problems. The purity of high-purity argon and high-purity oxygen is preferably 99.00% by volume or more, more preferably 99.90% by volume or more, and still more preferably 99.99% by volume or more.

[0077] As an example, when using argon and oxygen, the oxygen partial pressure in the mixed gas is preferably more than 0.00% by volume and 30.00% by volume or less, and more preferably more than 0.00% by volume and 10.00% by volume or less. If the oxygen partial pressure is more than 0.00% by volume and 30.00% by volume or less, it easily crystallizes and becomes semi-conductive during heating. By changing the oxygen partial pressure, the degree of oxidation of the oxide film, that is, the degree of crystallization, can be adjusted. The oxygen partial pressure may be appropriately selected as needed.

[0078] As an example, when using argon and water vapor, the water vapor pressure in the mixed gas is preferably more than 0.03% by volume and 10.00% by volume or less, and more preferably more than 0.03% by volume and 5.00% by volume or less. If the water vapor pressure is more than 0.03% by volume and 5.00% by volume or less, it easily crystallizes and becomes semi-conductive during heating. Also, a mixed gas of hydrogen and oxygen may be used instead of water.

[0079] The magnetic flux density during sputtering is preferably 300 G or more, and more preferably 700 G or more. If the magnetic flux density during sputtering is 700 G or more, the density of the plasma during sputtering film formation can be further increased, the density of the oxide film is further increased, and a better oxide semiconductor film can be obtained by heat treatment after patterning. Even if the magnetic flux density during sputtering is less than 700 G, the output density during sputtering is set to 2.5 kW / cm 2 or more, whereby the density of the plasma during sputtering film formation can be increased, and as a result, a good oxide semiconductor film can be obtained.

[0080] In the film formation step by sputtering, it is preferable to perform sputtering by mounting a sputtering target on an RF magnetron sputtering apparatus or a DC magnetron sputtering apparatus.

[0081] In the method for manufacturing a crystalline oxide semiconductor film of the present embodiment, after forming an oxide semiconductor film by the above atomic layer deposition method or sputtering method, etc., post-annealing for heating the oxide semiconductor film may be performed. In the method for manufacturing a crystalline oxide semiconductor film of the present embodiment, after forming an amorphous oxide semiconductor film by a film formation step, post-annealing may be performed to crystallize the oxide semiconductor film. Alternatively, a crystalline oxide semiconductor may be formed without post-annealing, or after forming a crystalline oxide semiconductor, post-annealing may be performed to adjust the crystallinity of the crystalline oxide semiconductor.

[0082] Post-annealing may be performed after forming the oxide semiconductor film, or may be performed after forming another layer (for example, an insulating film described later) on the oxide semiconductor film. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The post-annealing atmosphere may contain nitrogen or oxygen, and may be under vacuum or in the atmosphere. The post-annealing temperature is preferably 250°C or more and 600°C or less, more preferably 300°C or more and 500°C or less, and still more preferably 350°C or more and 450°C or less. The post-annealing time is 5 minutes or more and 3 hours or less, preferably 30 minutes or more and 2 hours or less.

[0083] 3. Transistor The transistor of this embodiment includes a layer made of the oxide semiconductor film of this embodiment (hereinafter, also simply referred to as "oxide semiconductor layer"), an insulating film, and an electrode on a substrate. The oxide semiconductor layer of this embodiment functions as a channel layer in the transistor.

[0084] As long as the transistor has an oxide semiconductor layer, the transistor may have any structure. Examples of the transistor include the structures shown in FIGS. 2A to 2D, FIGS. 3A and 3B, and FIGS. 4A and 4B.

[0085] In one embodiment, the transistor is of a bottom gate - top contact type. In one embodiment, the transistor is of a top gate - top contact type. In one embodiment, the transistor is of a three - dimensional vertical channel type.

[0086] Examples of the bottom gate - top contact type include the bottom gate - bottom contact (BGBC) type transistor shown in the schematic cross - sectional view of FIG. 2A and the bottom gate - top contact (BGTC) type transistor shown in the schematic cross - sectional view of FIG. 2B. Examples of the top gate - top contact type include the top gate - bottom contact (TGBC) type transistor shown in the schematic cross - sectional view of FIG. 2C and the top gate - top contact (TGTC) type transistor shown in the schematic cross - sectional view of FIG. 2D. Also, dual (double) gate type or multi - gate type transistors having a plurality of gate electrodes are included, and they can exhibit the same effects as the transistors described in this specification.

[0087] As shown in the schematic cross-sectional views of FIGS. 2A to 2D, these transistors usually include a substrate 1, a gate electrode 2, a first insulating film 3, a source electrode 4, a drain electrode 5, and an oxide semiconductor layer 6. Further, these transistors may include a second insulating layer film 7 (not shown in FIGS. 2C and 2D). In these transistors, the source electrode 4 may be used as the drain electrode 5, and the drain electrode 5 may be used as the source electrode 4.

[0088] The first insulating film 3 is located between the gate electrode 2 and the oxide semiconductor layer 6. The first insulating film 3 functions as a gate insulating film. The source electrode 4 and the drain electrode 5 are in contact with at least the oxide semiconductor layer 6. The oxide semiconductor layer 6 functions as a channel. When the second insulating layer film 7 is provided, the second insulating layer 7 is located on the side opposite to the crystalline oxide semiconductor layer 6 with respect to the first insulating film 3 and is in contact with the crystalline oxide semiconductor layer 7. The second insulating layer film 7 can function as a protective film for the oxide semiconductor layer 6. The second insulating layer 7 preferably contains gallium oxide.

[0089] The transistor includes an oxide semiconductor layer 6, a first insulating film 3, a second insulating film 7, and a gate electrode 2. The first insulating film 3 is located between the gate electrode 2 and the oxide semiconductor layer 6. The second insulating film 7 is located on the side opposite to the oxide semiconductor layer 6 with respect to the first insulating film 3 and is in contact with the oxide semiconductor layer 6. The second insulating film 7 preferably contains gallium oxide.

[0090] Examples of the three-dimensional vertical channel type include, for example, the three-dimensional vertical channel all-around type transistor shown in the schematic cross-sectional views of FIGS. 3A and 3B, and the three-dimensional vertical gate all-around type transistor shown in the schematic cross-sectional views of FIGS. 4A and 4B. In FIGS. 3A and 3B, and FIGS. 4A and 4B, the same reference numerals as in FIGS. 2A to 2D denote the same configurations, and unless otherwise specified, the descriptions of FIGS. 2A to 2D are incorporated herein. Further, unless otherwise specified, the descriptions of FIGS. 3A and 3B, and FIGS. 4A and 4B are also incorporated in FIGS. 2A to 2D. Further, other examples of the three-dimensional vertical channel type include, for example, FinFET type, trench gate type, or CFET type transistors, which can exhibit the same effects as the transistors described in this specification.

[0091] As shown in FIGS. 3A and 3B, the three-dimensional vertical channel all-around type transistor generally includes a gate electrode 2, a source electrode 4, a drain electrode 5, an oxide semiconductor layer 6, a first insulating film 3, and a second insulating film 7. In these transistors, the source electrode 4 may be used as the drain electrode 5, and the drain electrode 5 may be used as the source electrode 4.

[0092] At least a part of the gate electrode 2 is located between the source electrode 4 and the drain electrode 5. At least a part of the gate electrode 2 may be located on the side opposite to the drain electrode 5 of the source electrode 4, or on the side opposite to the source electrode 4 of the drain electrode 5. The second insulating film 7 is located between the source electrode 4 and the drain electrode 5. Here, the source electrode 4 and the drain electrode 5 are stacked via the second insulating film 7. Thereby, the source electrode 4 and the drain electrode 5 are electrically insulated by the second insulating film 7. Here, the second insulating film 7 functions as an interlayer insulating film. The gate electrode 2 is provided adjacent to the oxide semiconductor layer 6 without contact therewith. Specifically, the gate electrode 2 is adjacent to the oxide semiconductor layer 6 via the first insulating film 3. The first insulating film 3 may be provided between the gate electrode 2 and the oxide semiconductor layer 6 to insulate the gate electrode 2 and the oxide semiconductor layer 6.

[0093] The oxide semiconductor layer 6 penetrates at least the second insulating film 7 and is provided so as to connect the source electrode 4 and the drain electrode 5. Here, the oxide semiconductor layer 6 penetrates the source electrode 4 and the second insulating film 7 in this order and is provided in a columnar shape. A concave portion is formed in the columnar oxide semiconductor layer 6 from one end side (the upper side in FIGS. 3A and 3B) toward the other end side (the lower side in FIGS. 3A and 3B), and the first insulating film 3 is formed on the inner peripheral surface and the bottom surface of the concave portion. The gate electrode 2 is provided so as to fill the concave portion in which the first insulating film 3 is formed.

[0094] As shown in FIGS. 4A and 4B, a three-dimensional vertical gate all-around type transistor generally includes a gate electrode 2, a source electrode 4, a drain electrode 5, an oxide semiconductor layer 6, a first insulating film 3, a second insulating film 7a, and a third insulating film 7b. The source electrode 4 and the drain electrode 5 are stacked via at least the second insulating film 7a (here, the second insulating film 7a and the third insulating film 7b). The gate electrode 2 is located between the source electrode 4 and the drain electrode 5. In these transistors, the source electrode 4 may be used as the drain electrode 5, and the drain electrode 5 may be used as the source electrode 4.

[0095] Among the second insulating film 7a and the third insulating film 7b, the second insulating film 7a is located between the source electrode 4 and the gate electrode 2. Thereby, the source electrode 4 and the gate electrode 2 are electrically insulated by the second insulating film 7a. Also, the third insulating film 7b is located between the drain electrode 5 and the gate electrode 2. Thereby, the drain electrode 5 and the gate electrode 2 are electrically insulated by the third insulating film 7b. That is, the second insulating film 7a and the third insulating film 7b function as an interlayer insulating film.

[0096] Note that, in the region shown in FIG. 4B, the gate electrode 2 is disposed between the second insulating film 7a and the third insulating film 7b. However, outside the region shown in FIG. 4B, the second insulating film 7a and the third insulating film 7b may be in contact with each other to form a single layer. In this case, the gate electrode 2 may not be disposed between the second insulating film 7a and the third insulating film 7b in this region.

[0097] The oxide semiconductor layer 6 penetrates at least the second insulating film 7a and is provided so as to connect the source electrode 4 and the drain electrode 5. The oxide semiconductor layer 6 may penetrate the gate electrode 2 in addition to the second insulating film 7a and the third insulating film 7b. Here, the oxide semiconductor layer 6 penetrates the second insulating film 7a, the gate electrode 2, and the third insulating film 7b in this order and is provided in a columnar shape. In this case, the gate electrode 2 preferably surrounds the side of the oxide semiconductor layer 6 (the periphery in the direction perpendicular to the length direction) over the entire circumference at a part in the length direction of the oxide semiconductor layer 6 (the central part in the example of FIG. 4B) via the first insulating film 3 described later. Thereby, even if the channel length of the oxide semiconductor layer 6 described later becomes short, it becomes easy to prevent leakage current. At the same time, it is also advantageous in terms of miniaturization.

[0098] The first insulating film 3 is provided between the gate electrode 2 and the oxide semiconductor layer 6. The oxide semiconductor layer 6, the first insulating film 3, and the gate electrode 2 are arranged in this order. The first insulating film 3 may insulate the gate electrode 2 and the oxide semiconductor layer 6 by being provided between the gate electrode 2 and the oxide semiconductor layer 6. The first insulating film 3 is also provided between the second insulating film 7a and / or the third insulating film 7b and the oxide semiconductor layer 6 in addition to between the gate electrode 2 and the oxide semiconductor layer 6. The first insulating film 3 is provided so as to surround the side surface of the columnar oxide semiconductor layer 6 over the entire circumference.

[0099] The oxide semiconductor layer 6 can function as a channel (current path) of the transistor. For example, when a gate voltage is applied to the gate electrode 2 which is a gate electrode, the source electrode 4 and the drain electrode 5 are electrically connected by the oxide semiconductor layer 6, and the transistor 10 is in an ON state. Also, when no gate voltage is applied, the electrical connection between the source electrode 4 and the drain electrode 5 by the oxide semiconductor layer 6 is released, and the transistor 10 is in an OFF state.

[0100] In the transistor, the oxide semiconductor layer 6 is provided so as to connect the source electrode 4 and the drain electrode 5. "Provided so as to connect the source electrode 4 and the drain electrode 5" means that it is provided in a state where the source electrode 4 and the drain electrode 5 can be electrically connected. Therefore, the oxide semiconductor layer 6 does not necessarily have to be in physical contact with the source electrode 4 and the drain electrode 5. For example, a conductive material may be provided between the oxide semiconductor layer 6 and the source electrode 4 and / or the drain electrode 5.

[0101] In the transistor structure described above, the materials of each layer may be appropriately selected except that the oxide semiconductor film of the present embodiment is used as the oxide semiconductor layer 6. Examples of the base material 1 include a glass substrate and a silicon substrate.

[0102] Each of the gate electrode 2, the source electrode 4, and the drain electrode 5 is not particularly limited as long as it is a conductor. The electrodes include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), chromium (Cr), gold (Au), zinc (Zn), niobium (Nb), manganese (Mn), and titanium nitride (TiN). The gate electrode 2, the source electrode 4, and the drain electrode 5 may be the same or different from each other.

[0103] When the electrode contains at least one selected from the group consisting of nickel, titanium nitride, and tungsten as a main component, a reduction effect of contact resistance, which is a parasitic resistance, can be obtained with respect to the crystalline oxide semiconductor film. Further, by selecting at least one selected from the group consisting of nickel, titanium nitride, and tungsten as the material of the electrode, film formation in ALD is also possible.

[0104] Each of the first insulating film 3, the second insulating film 7, the second insulating film 7a, and the third insulating film 7b is not particularly limited as long as it is a film containing an insulator or made of an insulator. As the insulating film, it contains at least one selected from the group consisting of gallium oxide, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The second insulating film 7, the second insulating film 7a, and / or the third insulating film 7b preferably contains gallium oxide. Also, each of the first insulating film 3, the second insulating film 7, the second insulating film 7a, and the third insulating film 7b may be a laminated film of the above materials. Note that the insulating film may contain La, N, Zr, etc. The insulators contained in the first insulating film 3, the second insulating film 7, the second insulating film 7a, and the third insulating film 7b may be the same as or different from each other.

[0105] When the first insulating film 3 functions as a gate insulating film, an insulating film containing at least one selected from the group consisting of gallium oxide, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used for the gate insulating film. The insulating film preferably contains at least one selected from the group consisting of gallium oxide, hafnium oxide, silicon oxide, and aluminum oxide as a main component. Also, the insulating film may be a laminate of the above materials. Note that the insulating film may contain La, N, Zr, etc. as impurities.

[0106] Hafnium oxide and aluminum oxide have a higher relative dielectric constant compared to silicon oxide and silicon oxynitride. Therefore, when hafnium oxide and aluminum oxide are used to achieve the same insulating film capacitance as when using silicon oxide, the film thickness of the insulating film can be increased, and thus the leakage current due to tunneling current can be reduced. That is, a transistor with a small off-current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant compared to hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic and cubic systems, but are not limited thereto.

[0107] In one embodiment, the insulating film contains hafnium oxide as a main component. In this specification, "containing hafnium oxide as a main component" means that more than 50% by mass of the material constituting the insulating film layer is hafnium oxide. The insulating layer may contain hafnium oxide in an amount of 55% by mass or more, 60% by mass or more, 70% by mass or more, 80% by mass or more, 90% by mass or more, 95% by mass or more, 97% by mass or more, 98% by mass or more, or 99% by mass or more, or may contain 100% by mass. When the main component of the insulating film is hafnium oxide, there is an advantage that the dielectric constant of the insulating film can be increased.

[0108] The second insulating film 7 may function as a protective film or an interlayer insulating film. As the insulating film that functions as the second insulating film 7, an insulating film containing at least one selected from the group consisting of gallium oxide, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be used. In particular, when the second insulating film 7 functions as a protective film, it preferably contains gallium oxide, and more preferably contains gallium oxide as a main component. Here, the meaning of "containing as a main component" is the same as that of hafnium oxide described above. The second insulating film 7 may be a laminate of the above materials. Note that the insulating film may contain La, N, Zr, etc. as impurities. When gallium oxide is used for the second insulating film 7, the mobility of the oxide semiconductor channel is likely to be improved when a transistor is formed.

[0109] (Method for manufacturing a transistor) The transistor of this embodiment can be manufactured in the same manner as a normal transistor, except that the oxide semiconductor film constituting the oxide semiconductor layer is formed by the ALD method or the sputtering method. The formation of the oxide semiconductor layer, that is, the oxide semiconductor film, in transistor manufacturing can be performed by the method described in the examples. The components other than the channel layer in the transistor and their manufacturing methods are not particularly limited, and known materials, configurations, and manufacturing methods can be used.

[0110] Transistors having various structures as shown in FIGS. 2A to 2D can be manufactured, for example, as follows. For example, first, a silicon substrate with a thermal oxide film is prepared. The silicon substrate functions as a gate electrode, and the thermal oxide film functions as a gate insulating layer. An oxide semiconductor layer is formed thereon by ALD method and patterned. The oxide semiconductor layer functions as a channel layer. Next, a metal film for forming source and drain electrodes is formed on the oxide semiconductor layer. Thereafter, a lift-off process or the like is used to form source and drain electrodes to obtain a transistor. If necessary, a protective film may be further formed.

[0111] <Fabrication process of bottom gate type transistor> As a method for manufacturing a transistor substrate having an oxide semiconductor layer, a bottom gate type transistor will be described as an example. The bottom gate-top contact type transistor shown in FIG. 2B can be manufactured, for example, as follows. First, a gate electrode 2 is patterned on a substrate 1 made of glass or the like. Next, a gate insulating layer 3 is formed on the gate electrode 2. The gate insulating layer 3 is formed, for example, by the PE-CVD method. The thickness of the gate insulating layer 3 is usually 10 nm or more and 300 nm or less. A silicon substrate with a thermal oxide film (substrate resistance of 0.1 Ωcm or less) may be regarded as a substrate with a gate insulating layer 3 with a gate electrode. Next, an oxide semiconductor layer 6 is formed on the gate insulating layer 3. As a method for forming the oxide semiconductor layer 6, for example, a sputtering method in which a sputtering target having the same composition as the oxide semiconductor film is formed by DC sputtering or RF sputtering, an ALD method in which a film is formed using an organometal or the like as a precursor, a precursor solution such as a metal alkoxide, a metal organic acid salt, and a chloride, or a liquid phase method in which an oxide semiconductor layer is formed by applying and firing a dispersion of oxide semiconductor nanoparticles can be mentioned. In the bottom gate-top contact type transistor crystal shown in FIG. 2B, after the oxide semiconductor layer 6 is formed, patterns of the source electrode 4 and the drain electrode 5 are formed. After forming the source electrode and the drain electrode, a protective film or a second insulating film may be formed so as to cover them. For the protective film, for example, SiO2 or aluminum oxide formed by the ALD method or the CVD method may be used, aluminum oxide formed by the RF sputtering method may be used, or aluminum oxide formed by introducing oxygen during DC sputtering may be used.

[0112] Note that in the bottom gate-bottom contact type transistor crystal shown in FIG. 2A, in the bottom gate-top contact type transistor shown in FIG. 2B, after forming the patterns of the source electrode 4 and the drain electrode 5, the oxide semiconductor layer 6 is formed.

[0113] <Manufacturing process of top gate type transistor> The top gate-top contact type transistor shown in FIG. 2D can be manufactured, for example, as follows. First, a second insulating film is formed on a substrate 1 made of glass, silicon, or the like. The substrate 1 may be cleaned in advance. Using a liquid (Sulfuric acid-Hydrogen Peroxide Mixture, abbreviated as SPM solution) in which 0.25 volume or more and 1.00 volume or less of hydrogen peroxide solution is mixed with respect to one volume of concentrated sulfuric acid, while heating at around 130°C, the substrate is brought into contact with the SPM solution to remove organic substances and the like from the substrate. Subsequently, the substrate can be cleaned with a 1% hydrofluoric acid aqueous solution to remove the oxide film on the substrate surface. After that, for example, after heating the substrate to 250°C, the second insulating film can be formed by ALD. For example, when forming a hafnium oxide film as the second insulating film by an ALD apparatus, a first source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, hafnium amide such as tetrakis(dimethylamido)hafnium (TDMAHf), etc.) and a second source gas such as ozone (O3) and oxygen (O2) as an oxidizing agent are used. When using TDMAHf as the hafnium precursor compound in the first source gas, the first source gas may be supplied from the source gas supply unit, and further, oxygen, which is an oxidizing agent, may be supplied as the second source gas from the source gas supply unit. When using oxygen as the oxidizing agent, the first source gas may be oxidized by plasma-excited oxygen. When forming a hafnium oxide film using TDMAHf, the substrate temperature is preferably 100°C or higher and 600°C or lower, more preferably 150°C or higher and 500°C or lower, and from the viewpoint of damage to the device, even more preferably 200°C or higher and 400°C or lower, and even more preferably around 250°C (for example, 250°C ± 5°C).

[0114] When forming a second insulating film on a substrate in a processing container by ALD, specifically, a step of supplying a first source gas containing a precursor of a material constituting the second insulating film (for example, when the above material is a metal oxide, an organic complex of the metal) into the processing container, a step of removing residual gas remaining in the processing container after the step of supplying the first source gas, a step of subsequently supplying a second source gas which is an oxidizing agent for oxidizing the first source gas into the processing container, and a step of removing residual gas remaining in the processing container after the step of supplying the second source gas may be sequentially performed.

[0115] In one embodiment, in order to form hafnium oxide with a thickness of 5 nm using TDMAHf, when the substrate temperature is set to 250 °C and plasma-excited oxygen is used as the oxidizing agent, the plasma oxidation time may be set to 20 seconds, and the above steps may be sequentially repeated 54 cycles.

[0116] In the top gate-top contact type transistor shown in FIG. 2D, after optionally forming a second insulating film, an oxide semiconductor layer 6 is formed. The oxide semiconductor layer 6 may be formed as described above.

[0117] The oxide semiconductor layer 6 is preferably formed in a film thickness range of 1 Å or more and 100 nm or less, more preferably in a film thickness range of 1 nm or more and 50 nm or less. Further, in a micro device, since the parasitic capacitance of the oxide semiconductor layer 6 becomes a problem, the film thickness of the oxide semiconductor layer 6 is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 10 nm or less, and still more preferably 1 nm or more and 5 nm or less.

[0118] If the formed oxide semiconductor layer 6 is amorphous, it is easy to pattern by wet etching. Referring to the description of the bottom gate above, patterning can be performed using a photoresist. As the etching agent, it is desirable to use one that can dissolve the oxide semiconductor layer 6 and is insoluble in the second insulating layer. Examples of the etching agent include hydrochloric acid solution and oxalic acid solution. When the crystalline component is dominant in the oxide semiconductor layer 6 immediately after film formation, a hydrochloric acid solution is preferred. When the amorphous component is dominant, an oxalic acid solution with less residue formation is desirable.

[0119] The oxide semiconductor layer 6 formed into a desired shape by patterning can then have its crystallinity improved by a thermal process such as annealing. The annealing atmosphere is generally vacuum, nitrogen, or air. In the case of an air atmosphere, the annealing temperature is preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 500°C or lower, and still more preferably 350°C or higher and 450°C or lower. The annealing time is usually 5 minutes or more and 3 hours or less, preferably 30 minutes or more and 2 hours or less.

[0120] Subsequently, a first insulating film 3 is formed on the upper layer of the oxide semiconductor layer 6. The first insulating film 3 can be formed using the same materials and methods as the second insulating film. When the first insulating film 3 is used as the gate insulating film of a microelement, it is desirable to make it as thin as possible so that the capacitance of the gate insulating film does not become a parasitic component. In the case of an element with an element size of 50 nm or less, the film thickness of the first insulating film 3 is preferably 1 Å or more and 10 nm or less, more preferably 5 Å or more and 5 nm or less, and still more preferably 10 Å or more and 2 nm or less.

[0121] In one embodiment, similar to the second insulating film, hafnium oxide can be formed as the first insulating film 3 using TDMAHf. Subsequently, contact holes can be formed in the first insulating film 3 by dry etching. When the first insulating film 3 is hafnium oxide, dry etching is possible using a mixed gas of chlorine gas and argon gas.

[0122] Subsequently, the gate electrode 2, the source electrode 4, and the drain electrode 5 can be formed. Specifically, the source electrode 4 and the drain electrode 5 are patterned on the first insulating film 3 having the above-described contact hole, and then the first insulating film 3 is formed thereon, and the gate electrode 2 is patterned on the first insulating film 3.

[0123] In one embodiment, the gate electrode 2, the source electrode 4, and the drain electrode 5 are formed of titanium nitride formed by sputtering on a lift-off resist, and further patterned to form electrodes.

[0124] Finally, the fabricated top-gate transistor can be annealed to stabilize the device characteristics. The annealing atmosphere is generally vacuum, nitrogen, or air. In the case of an air atmosphere, the annealing temperature is preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 500°C or lower, and still more preferably 350°C or higher and 450°C or lower. The annealing time is usually 5 minutes or longer and 2 hours or shorter, preferably 30 minutes or longer and 1 hour or shorter.

[0125] In one embodiment, the annealing treatment can be performed at 300°C in an argon atmosphere or 350°C in an air atmosphere.

[0126] In the top-gate-bottom-contact transistor shown in FIG. 2C, in the manufacturing process of the top-gate-top-contact transistor shown in FIG. 2D, instead of forming the oxide semiconductor layer 6 after forming the first insulating film on the substrate 1, after forming the first insulating film 3 on the substrate 1, the source electrode 4 and the drain electrode 5 are patterned. Thereafter, a second insulating film having a contact hole is optionally formed, and then the oxide semiconductor layer 6 is formed, and then the gate insulating layer 3 and the gate electrode 2 are formed. Regarding the formation method and materials of the first insulating film 3, the source electrode 4 and the drain electrode 5, the second insulating film, the oxide semiconductor layer 6, and the gate electrode 2 in the top-gate-bottom-contact transistor shown in FIG. 2C, reference may be made to the manufacturing of the top-gate-top-contact transistor shown in FIG. 2D.

[0127] <Fabrication Process of Three-Dimensional Vertical Channel Transistor> The manufacturing method of the three-dimensional vertical channel all-around transistor shown in FIGS. 3A and 3B can be manufactured by a known method with reference to the manufacturing method of the three-dimensional vertical gate all-around transistor shown in FIGS. 4A and 4B described later. For example, a three-dimensional vertical channel all-around transistor may be manufactured as follows. After forming a laminate of a gate electrode 2, a second insulating film 7, and a source electrode 4, a through hole is formed so as to penetrate the source electrode 4 and the second insulating film 7. After forming an oxide semiconductor layer 6, a first insulating film 3 and a gate electrode 2 are formed.

[0128] When manufacturing a three-dimensional vertical channel all-around transistor or a three-dimensional vertical gate all-around transistor, it is more preferable that the oxide semiconductor layer is formed by an atomic layer deposition method (ALD). For example, when manufacturing a three-dimensional vertical channel all-around transistor, if an oxide semiconductor layer as a channel layer is to be formed on a base layer partitioned by a first insulating film, a source electrode, and a drain electrode by a sputtering method, the opening of the base layer to be coated with the oxide semiconductor layer is narrow and tends to be a vertically long cylindrical shape. Therefore, as shown in FIG. 3C, the oxide semiconductor layer tends to be formed only near the opening of the cylindrical base layer. On the other hand, according to the manufacturing method of a transistor using an oxide semiconductor layer formed by the ALD method, since the oxide semiconductor layer (channel layer) is formed by the ALD method, even if the opening of the base layer is narrow and has a vertically long cylindrical shape, as shown in FIG. 3D, the entire inner surface of the base layer can be uniformly coated with the oxide semiconductor layer. Therefore, as shown in FIG. 3D, a gate insulating layer and a gate electrode can be easily formed thereon, and a highly reliable transistor memory tends to be easily obtained.

[0129] The three-dimensional vertical gate all-around transistor shown in FIGS. 4A and 4B can be manufactured, for example, as shown in FIG. 4C. Note that FIG. 4C is a diagram for explaining an example of a method for manufacturing a transistor.

[0130] FIG. 4C(a) shows a state in which a drain electrode 5 and an insulating film 8 supporting the drain electrode 5 are formed. Although not shown in FIG. 4C(a), the drain electrode 5 and the insulating film 8 may be further formed on another substrate. Also, the drain electrode 5 may be connected to an element outside the transistor. The insulating film 8 and the drain electrode 5 can be formed by known methods.

[0131] Next, as shown in FIG. 4C(b), a third insulating film 7b, a gate electrode 2, and a second insulating film 7a are formed in this order. At this time, as will be described later, the gate electrode 2 may be formed so as to be connected to a word line. Alternatively, the gate electrode 2 itself may be used as a word line.

[0132] The third insulating film 7b is formed, for example, by forming a film containing an insulator as described above by various methods such as chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, and coating method, or by forming a film containing an insulator as described above by various methods such as plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, and coating method.

[0133] The gate electrode 2 is formed, for example, by forming a conductor as described above such as nickel, titanium nitride, and tungsten. The gate electrode 2 may be patterned into an arbitrary shape. The gate electrode 2 may form a pattern during film formation, or may form a pattern by etching after film formation.

[0134] The second insulating film 7a is formed by forming a film containing an insulator as described above by various methods such as chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, coating method, etc.

[0135] Next, as shown in FIG. 4C(c), a through hole H is formed by etching so as to penetrate the second insulating film 7a, the gate electrode 2, and the third insulating film 7b. Etching for forming the through hole H may use various methods such as dry etching and wet etching. Also, before etching, a resist for defining the region where the through hole H is to be formed may be formed on the second insulating film 7a.

[0136] Next, as shown in FIG. 4C(d), the first insulating film 3 containing an insulator as described above is formed by various methods such as chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, coating method, etc.

[0137] Next, as shown in FIG. 4C(e), an oxide semiconductor layer 6 is formed in the through hole H on which the first insulating film 3 is formed. Examples of the method for forming the oxide semiconductor layer 6 include chemical vapor deposition (CVD) method, plasma CVD (PECVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, sol-gel method, coating method, etc. Note that CVD methods include metalorganic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), mist CVD, etc. PVD methods include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, etc. The oxide semiconductor layer 6 may be formed as an oxide semiconductor by performing post-annealing, which will be described later, after forming an amorphous oxide semiconductor. By performing post-annealing after forming the amorphous oxide semiconductor, an oxide semiconductor may be formed, and post-annealing may be further performed after the oxide semiconductor is crystallized to form the oxide semiconductor. Alternatively, an oxide semiconductor may be formed without post-annealing, and post-annealing may be performed after forming the oxide semiconductor to adjust the crystallinity of the oxide semiconductor.

[0138] It is preferable to perform post-annealing on the oxide semiconductor layer 6 formed in the process shown in FIG. 4C(e). Post-annealing can be performed, for example, after forming the subsequent source electrode 4 or before forming the source electrode 4 after forming the oxide semiconductor film. The state of the oxide semiconductor before post-annealing may be amorphous or crystalline. The annealing atmosphere may contain nitrogen or oxygen, and may be under vacuum or in air. The annealing temperature is preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 500°C or lower, and still more preferably 350°C or higher and 450°C or lower. The annealing time is within 5 minutes to 2 hours, preferably within 30 minutes to 1 hour. The oxide semiconductor layer 6 can reduce grain boundaries by being formed by atomic layer deposition (ALD). Also, by performing post-annealing, a polycrystalline or single-crystalline oxide semiconductor can be formed.

[0139] Next, as shown in FIG. 4C(f), a source electrode 4 is formed on the upper layer of the oxide semiconductor layer 6. The source electrode 4 may be patterned into an arbitrary shape. The source electrode 4 may form a pattern during film formation, or may form a pattern by etching after film formation.

[0140] As described above, a transistor as shown in FIGS. 4A and 4B can be obtained.

[0141] In this embodiment, the case where the first insulating film 3 entirely surrounds the side circumferential surface of the columnar oxide semiconductor layer 6 has been shown, but it is not necessarily limited to this. For example, the first insulating film 3 may surround at least a part of the columnar oxide semiconductor layer 6.

[0142] <Annealing process> Regarding the annealing treatment described above, annealing may be performed immediately after forming the oxide semiconductor layer, or annealing of the formed oxide semiconductor layer may be performed to form a crystalline oxide semiconductor layer, or annealing treatment may be performed on the transistor. The number of annealing times may be single or plural. When performing multiple times, the temperature and annealing atmosphere may be different. When forming a protective film in an element including the crystalline oxide semiconductor layer 6, the formation includes, for example, film formation by PVD or CVD, pattern processing by dry etching or wet etching, and a resist stripping process. At this time, since the performance of the transistor may deteriorate, it is desirable to recover the performance and adjust the carrier concentration by annealing treatment. In this embodiment, for example, by performing annealing treatment at 250°C or higher, even when the performance of the transistor once decreases during patterning, the performance can be recovered. In particular, in this embodiment, even when the characteristics of the transistor are significantly deteriorated, significant performance recovery can occur by annealing in the presence of oxygen-containing substances. Also, depending on the degree of deterioration of the crystalline oxide semiconductor layer 6, the performance recovery of the transistor and the reliability of the element can be improved by increasing the annealing temperature or lengthening the annealing time. The annealing temperature is preferably 250°C or higher and 500°C or lower, more preferably 300°C or higher and 450°C or lower. The annealing time is usually 30 minutes or more, preferably 60 minutes or more. Annealing is preferably performed in the presence of oxygen. However, annealing in the presence of oxygen is preferably performed at 400°C or lower in consideration of the effects such as oxidation of the electrode and coloring due to oxidation of the protective film of this embodiment. Annealing treatment may be performed in a nitrogen atmosphere.

[0143] <Patterning> When patterning the above-mentioned oxide semiconductor layer, electrodes, and protective film, a photoresist may be applied and light may be irradiated onto its surface. As the light source used for light irradiation, any light source conventionally used in the patterning method can be used. Examples of such light sources include lamps such as high-pressure mercury lamps, low-pressure mercury lamps, metal halides, xenon, etc., laser diodes, LEDs, etc. As the irradiation light, ultraviolet rays such as g-line, h-line, and i-line may be used.

[0144] In order to irradiate light in a pattern, a general photomask can be used. Such a photomask can be arbitrarily selected from well-known ones. The environment during irradiation is not particularly limited, but generally, the ambient atmosphere (in air) or nitrogen atmosphere may be used. Also, when forming a film over the entire surface of the substrate, light may be irradiated onto the entire surface of the substrate.

[0145] After exposure, in order to promote the reaction between polymers in the film by the reaction initiator generated at the exposed locations, post-exposure baking may be performed as necessary. This heat treatment is not performed to completely cure the photoresist, but is performed so that only the desired pattern remains on the substrate after development, and the other parts can be removed by development.

[0146] After exposure, and after performing post-exposure baking as necessary, the photoresist may be developed. As the developer used during development, any developer conventionally used for developing known photosensitive polymer materials and photosensitive siloxane compositions can be used. A pattern can be obtained by development. After development is performed with the developer, it is preferable to perform water washing. In such a manufacturing method, the drain electrode and the transparent electrode (pixel electrode) formed on the protective film can also be electrically connected through the contact holes formed by development.

[0147] When using a positive-type composition and using the formed protective film as a transparent film, light irradiation called bleaching exposure may be performed. By performing bleaching exposure, unreacted diazonaphthoquinone derivatives remaining in the film are photodecomposed, and the light transparency of the film is further improved. As a method of bleaching exposure, a high-pressure mercury lamp, a low-pressure mercury lamp, etc. are used, and depending on the film thickness, 100 mJ / cm 2 or more and 2,000 mJ / cm 2 or less (in terms of exposure energy converted to a wavelength of 365 nm) is used to expose the entire surface. Also, when using a negative-type composition, by activating the curing aid in the remaining film after development by light irradiation, subsequent heat curing can be performed more easily. In this case, depending on the film thickness, 100 mJ / cm 2 or more and 2,000 mJ / cm 2 or less (in terms of exposure energy converted to a wavelength of 365 nm) is used to expose the entire surface.

[0148] 4. Semiconductor Device A semiconductor device according to one aspect includes the transistor of this embodiment. A semiconductor device according to one aspect is preferably the semiconductor memory device of this embodiment. The semiconductor device and the semiconductor memory device of this embodiment include the transistor of this embodiment, and thus have excellent electrical characteristics and high reliability.

[0149] The type of the semiconductor device is not particularly limited, but from the viewpoint of significantly exhibiting the above-described effects, a semiconductor memory device such as a volatile memory such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM); a mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR type flash memory, NAND type flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), ReRAM (Resistive RAM), etc. non-volatile memory. Alternatively, the semiconductor device may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), MPU (Microprocessor Unit), etc.

[0150] In addition, since the transistor according to one aspect can apply the vertical structure as shown in each embodiment, it is suitable for arranging a plurality of transistors at high density in a semiconductor memory device, and also contributes to miniaturization of the semiconductor memory device. In addition, since the transistor according to one aspect uses an oxide semiconductor film as a channel, the leakage current tends to be small. Therefore, by using it in a semiconductor memory device, the capacitance of the capacitor can be reduced or the capacitor can be omitted. As a result, by using the transistor according to one aspect of the present invention, the semiconductor memory device can be miniaturized.

[0151] 5. Electronic Circuit The electronic circuit of this embodiment includes the semiconductor device of this embodiment. By including the semiconductor device of this embodiment, the electronic circuit of this embodiment has excellent electrical characteristics and high reliability. The electronic circuit of this embodiment may have the same configuration as a known electronic circuit except that it includes the semiconductor device of this embodiment.

[0152] 6. Electrical equipment, electronic equipment, vehicles, or power engines The electrical equipment, electronic equipment, vehicles, or power engines of this embodiment include the electronic circuit of this embodiment. By including the electronic circuit of this embodiment, the electrical equipment, electronic equipment, vehicles, or power engines of this embodiment have excellent electrical characteristics and high reliability. The electrical equipment, electronic equipment, vehicles, or power engines of this embodiment may have the same configuration as known electrical equipment, electronic equipment, vehicles, or power engines except that they include the electronic circuit of this embodiment.

[0153] 7. Method for analyzing the quality of an oxide semiconductor film The method for analyzing the quality of an oxide semiconductor film of this embodiment is a method for analyzing the quality of an oxide semiconductor film containing indium as a main component, and includes determining whether the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface is 0.06 nm or less, and may include other steps as long as the effects of the present invention are not inhibited.

[0154] The method for analyzing the quality of an oxide semiconductor film of this embodiment preferably further includes evaluating that the quality of the oxide semiconductor film is good when it is determined that the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface on the side opposite to the lower surface is 0.06 nm or less. The quality of the oxide semiconductor film being good is not particularly limited, but for example, it may mean that when the oxide semiconductor film is mounted on a device, the performance of the device is high. Alternatively, it may mean that the mobility of the oxide semiconductor film is high.

[0155] The method for measuring the difference between the roughness 1 of the lower surface of the oxide semiconductor film and the roughness 2 of the upper surface opposite to the lower surface is not particularly limited. For example, the method described in the examples can be used.

Examples

[0156] Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples, but the present invention is not limited thereto.

[0157] <Manufacture of crystalline oxide semiconductor film> An oxide semiconductor film was formed by sputtering or ALD as follows. The formed oxide semiconductor film was annealed in air at 450 ° C for 2 hours to obtain a crystalline oxide semiconductor film. It was confirmed that all the thin films were crystallized after annealing. In addition, except for the measurement of the film thickness by ellipsometry, each evaluation in the examples and comparative examples was carried out using the crystalline oxide semiconductor film obtained as described above.

[0158] <Film formation by sputtering (Comparative Examples 1 and 2)> An oxide semiconductor film (oxide semiconductor layer) was formed by a sputtering method using InGaO (Ga: 7.2 at%) as a sputtering target. Specifically, using a sputtering target, an oxide semiconductor film (oxide semiconductor layer) of Comparative Example 1 was formed by sputtering on a silicon wafer (gate electrode) with a 100 nm thick thermal oxide film (gate insulating film) according to the following film formation conditions. In Comparative Example 2, an oxide semiconductor film (oxide semiconductor layer) was formed in the same manner as above, except that indium oxide was used as the sputtering target. In addition, as the film forming apparatus, a revolving sputtering apparatus with a target size of 100 mm in diameter was used. (Film formation conditions) · Atmosphere gas: Add 2% water vapor to the argon atmosphere · Back pressure before film formation (Pa): 3×10 -4 Film formation was started when it reached Pa or less · Pressure during film formation (Pa): 0.5 Pa · Oxygen flow ratio during film formation (%): 0% · Moisture pressure during film formation (%): 2% · Output (W): DC400 W

[0159] <Film formation of indium gallium oxide by ALD (O2 plasma)> Using an ALD apparatus (apparatus name: Fiji F200; manufactured by Veeco), an oxide semiconductor film (oxide semiconductor layer) of Example 1 was produced on a silicon wafer (gate electrode) with a thermal oxide film (gate insulating film) having a thickness of 80 to 85 nm by the ALD method according to the following steps. Specifically, using triethylindium (TEI) as a precursor, the steps (1) to (4) described in the following (indium film formation step) were repeated 5 times to obtain Film 1. On Film 1, using trimethylgallium (TMG) as a precursor, the steps (1) to (4) described in the following (gallium film formation step) were performed once to obtain Film 2. On Film 2, using triethylindium (TEI) as a precursor, the steps (1) to (4) described in the following (indium film formation step) were performed 5 times to obtain Film 3. Furthermore, each step related to the film formation of Films 1 to 3 was defined as a sub-cycle, and a super-cycle in which Films 1 to 3 were successively formed was repeated 8 times to obtain an oxide semiconductor film. This film formation corresponded to performing a series of cycles consisting of a first step of forming a layer containing indium by atomic layer deposition using an indium-containing precursor as a raw material and a second step of forming a layer containing gallium by atomic layer deposition using a gallium-containing precursor as a raw material, where the number of sub-cycles 1 was 5 times and the number of sub-cycles 2 was 1 time, and then performing a series of cycles consisting of a first step where the number of sub-cycles 1 was 10 (5×2) times and the number of sub-cycles 2 was 1 time 7 times, and finally performing an additional first step where the number of sub-cycles 1 was 5 times. Note that the conditions shown in Table 1 were adopted as the manufacturing conditions.

[0160] (Indium film formation step) A series of steps consisting of the following (1) to (4) was repeated for a predetermined number of cycles with one cycle being defined as follows. (1) The vapor of the precursor vaporized under the condition that the heating temperature of the raw material container was 85°C was introduced into the chamber with the valve open for 0.06 seconds, exposed to the substrate surface or film surface at a system pressure of 100 Pa, and reacted and adsorbed. (2) Unreacted raw materials were removed by argon purging for 15 seconds. (3) Oxygen (O2) gas was introduced into the chamber with the valve open at a flow rate of 50 sccm and used as an oxidant. The oxygen gas was fed into the film formation chamber from the inlet of the film formation chamber, but was introduced into the film formation chamber after passing through a quartz tube capable of remote plasma discharge. After that, the introduced oxygen gas was allowed to stabilize for 10 seconds, and then a plasma was generated for 20 seconds by applying an output of 300 W to the coil of the quartz tube portion capable of remote plasma discharge using an RF power supply. The generated plasma spread into the film formation chamber. Then, the RF power supply was turned off and the gas supply valve was closed. (4) Unreacted raw materials were removed by argon purging for 30 seconds. During the film formation period of (1) to (4), 100 sccm of argon gas was allowed to flow from the inlet of the film formation chamber through the plasma chamber into the film formation chamber, and in addition, 30 sccm of argon gas was constantly supplied as a carrier gas from the side surface of the film formation chamber into the film formation chamber. In addition, the opening degree of the APC valve for gas exhaust in the film formation chamber was set to 11%.

[0161] (Gallium film formation process) A series of steps consisting of the following (1) to (4) was repeated for a predetermined number of cycles with one cycle being defined as follows. (1) With the raw material container at room temperature of 25°C, the vapor of the vaporized precursor was introduced into the chamber with the valve open for 0.02 seconds, exposed to the substrate surface or film surface at a system pressure of 100 Pa, and reacted and adsorbed. (2) Unreacted raw materials were removed by argon purging for 15 seconds. (3) Oxygen (O₂) gas was introduced into the chamber with the valve open at a flow rate of 50 sccm and used as an oxidizing agent. The oxygen gas was fed into the film deposition chamber from the inlet of the film deposition chamber, but was introduced into the film deposition chamber after passing through a quartz tube capable of remote plasma discharge. Then, after waiting for 10 seconds for the introduced oxygen gas in the film deposition chamber to stabilize, an RF power supply was used to apply an output of 300 W to the coil of the quartz tube part capable of remote plasma discharge for 20 seconds to generate plasma. The generated plasma spread into the film deposition chamber. Then, the RF power supply was turned off and the gas supply valve was closed. (4) Unreacted raw materials were removed by argon purging for 30 seconds. During the film deposition period of (1) to (4), while flowing 100 sccm of argon gas from the inlet of the film deposition chamber through the plasma chamber into the film deposition chamber, 30 sccm of argon gas was constantly supplied as a carrier gas to the film deposition chamber from the side of the film deposition chamber. In addition, the opening degree of the APC valve for gas exhaust in the film deposition chamber was set to 11%.

[0162] <Film Deposition of Indium Oxide Film by ALD (O₂ Plasma)> Using an ALD apparatus (apparatus name: Fiji F200; manufactured by Veeco), the oxide semiconductor films (oxide semiconductor layers) of Examples 2 and 3 were manufactured on a silicon wafer (gate electrode) with a thermal oxide film (gate insulating film) having a thickness of 80 to 85 nm by the ALD method according to the following steps. Triethylindium (TEI) shown in Table 1 was used as a precursor, and the conditions shown in Table 1 were adopted as manufacturing conditions.

[0163] (Process) A series of steps consisting of the following (1) to (4) was defined as one cycle and repeated to reach a predetermined number of cycles. (1) The vapor of the precursor vaporized under the condition that the heating temperature of the raw material container was 85°C was introduced into the chamber with the valve open for 0.06 seconds, exposed to the substrate surface or the film surface at a system pressure of 100 Pa, and reacted and adsorbed. (2) Unreacted raw materials were removed by argon purging for 15 seconds. (3) Oxygen (O2) gas was introduced into the chamber with the valve open at a flow rate of 50 sccm and used as an oxidizing agent. The oxygen gas was fed into the film deposition chamber from the inlet of the film deposition chamber, but was introduced into the film deposition chamber after passing through a quartz tube capable of remote plasma discharge. Then, after waiting for 10 seconds for the introduced oxygen gas to stabilize, an RF power supply was used to apply an output of 300 W to the coil of the quartz tube capable of remote plasma discharge for 20 seconds to generate plasma. The generated plasma spread into the film deposition chamber. Then, the RF power supply was turned off and the gas supply valve was closed. (4) Unreacted raw materials were removed by argon purging for 30 seconds. During the film deposition period of (1) to (4), while flowing 100 sccm of argon gas from the inlet of the film deposition chamber through the plasma chamber into the film deposition chamber, 30 sccm of argon gas was constantly supplied as a carrier gas from the side of the film deposition chamber into the film deposition chamber. In addition, the opening degree of the APC valve for gas exhaust of the film deposition chamber was set to 11%.

[0164] In Table 1, "film deposition temperature" means the substrate temperature during the above film deposition.

[0165] <Physical Property Evaluation> The crystalline oxide semiconductor films in the examples and comparative examples were evaluated as follows. The results are shown in Table 1. In Table 1, "-" means that the measurement was not performed. (Measurement of Gallium Concentration) The obtained thin film was measured by Rutherford Back-Scattering Spectroscopy (RBS) to determine the Ga concentration. The measurement conditions of RBS are as follows. <Measurement Conditions of RBS> (Equipment Used) Pelletron manufactured by National Electrostatics Corporation. (Analysis Conditions) Incident ion: 4He ++, Incident energy: 2300 keV, incident angle: 102 deg, scattering angle: 0 deg, sample current: 12 nA, beam diameter: 2 mm φ, in-plane rotation: none, exposure dose: 140 μC.

[0166] (Measurement of film thickness by TEM) Using an electron microscope (JEOL Ltd. "JEM-2800 type"), cross-sectional TEM images of the oxide semiconductor films of the examples and comparative examples were observed respectively. From these TEM images, the film thickness (nm) of each oxide semiconductor layer was measured.

[0167] (Calculation of roughness by TEM image analysis) The arithmetic mean roughness (Ra) was calculated based on the following TEM image analysis.

[0168] First, for each transistor obtained from the oxide semiconductor films of the examples and comparative examples, thinning by focused ion beam (FIB) was performed at an acceleration voltage of 40 kV using "FB-2100" manufactured by Hitachi, Ltd. according to the micro-sampling method, and thin film processing was performed under the conditions of an acceleration voltage of 10 kV to 30 kV using "JIB-4700F" manufactured by JEOL Ltd. to prepare a TEM observation sample. The cross-sectional images of the upper and lower surfaces of the sample were acquired under an acceleration voltage of 200 kV using an electron microscope (JEOL Ltd. "JEM-F200"), and then TEM observation, FFT image acquisition, and electron diffraction image acquisition were performed.

[0169] Here, in Table 1, the "protective film / oxide semiconductor film interface" is the interface on the protective film side of the oxide semiconductor film and corresponds to the upper surface. The "oxide semiconductor film / SiO2 interface" is the interface on the substrate side of the oxide semiconductor film and corresponds to the lower surface.

[0170] (Roughness analysis) The roughness analysis in this example was performed by the following method. 1. Binarization of the image and extraction of interface information 1.1. Binarization of the image The obtained TEM images were binarized using the following threshold values. When the influence of the image contrast was observed, the threshold value was appropriately adjusted according to the contrast. · Protective film / oxide semiconductor interface: 40 · Oxide semiconductor / SiO2 interface: 130 · SiO2 / Si substrate interface: 130 1.2. Extraction of interface information From the images binarized above, pixel information in the vertical direction was extracted for each interface for 1 pixel in the horizontal direction. For the horizontal direction, extraction was performed 1 pixel at a time from the left end to the right end based on the left end of the TEM image. For the vertical direction, the number of pixels from the upper end to each interface was extracted based on the upper end of the TEM image.

[0171] 2. Calculation of roughness value (1) The interface positions used for calculating the roughness value were calculated as the following normalized interface positions for each horizontal interface from the pixel information in the vertical direction obtained above. However, the normalized interface position was calculated as a value obtained by converting the unit from the number of pixels to the order of nm. In the case of the protective film / oxide semiconductor interface, the normalized interface position was calculated by subtracting the number of pixels of the SiO2 / Si substrate interface from the number of pixels of the said interface. Similarly, in the case of the oxide semiconductor / SiO2 interface, the normalized interface position was calculated by subtracting the number of pixels of the SiO2 / Si substrate interface from the number of pixels of the said interface. (2) The average value of the vertically normalized film thickness derived in (1) above with respect to the horizontal direction was calculated. (3) Using Equation (1), the arithmetic mean roughness (Ra) of the protective film / oxide semiconductor interface and the oxide semiconductor / SiO2 interface was calculated. The calculation results of roughness by TEM image analysis for Example 3 and Comparative Example 2 are shown in FIG. 5.

[0172] <Manufacture and evaluation of a transistor including a crystalline oxide semiconductor film> (Manufacture of a bottom gate - top contact type transistor) A conductive n-type silicon substrate with a thermal oxide film was used as the substrate. The thickness of the thermal oxide film corresponds to the thickness described in the above examples (80 to 100 nm). This thermal oxide film functions as a gate insulating film, and the conductive silicon portion functions as a gate electrode. First, the surface of the gate insulating film (thermal oxide film) was treated with SPM solution and UV / O3 treatment to obtain a cleaned surface. On the gate insulating film, the crystalline oxide semiconductor layers in each example and each comparative example were formed by the film formation method described in the above <Manufacture of crystalline oxide semiconductor film>. In addition, in order to enhance the adhesion between the crystalline oxide semiconductor layer and the positive photoresist, hexamethyldisilazane (HMDS) was applied to the surface of the crystalline oxide semiconductor layer. In order to pattern the crystalline oxide semiconductor layer, a positive photoresist was used, applied, pre-baked (90 °C, 1 minute 30 seconds), and exposed. After exposure, heating was performed at 110 °C for 1 minute 30 seconds. After development, post-baking (110 °C, 1 minute 30 seconds) was performed, and etching was performed with a 500 mM oxalic acid aqueous solution to pattern it into a desired shape. When etching does not proceed or residues are generated when using the oxalic acid aqueous solution, dilute hydrochloric acid heated to 50 °C was used as the etchant. Thereafter, the photoresist was removed, and in order to clean the surface of the crystalline oxide semiconductor layer, UV / O3 treatment at 115 °C for 10 minutes was performed. The patterned oxide semiconductor film was heat-treated (annealed) at 450 °C for 120 minutes in a hot air heating furnace.

[0173] Thereafter, a lift-off resist was formed, tungsten (80 nm) and platinum (20 nm) were sequentially formed by RF sputtering, and patterned into a desired shape as source / drain electrodes by the lift-off method. Thereafter, the surface of the crystalline oxide semiconductor layer was cleaned again by UV / O3 treatment at 115 °C for 10 minutes. Thereafter, a lift-off resist was formed for opening the contact hole portion, 200 nm of gallium oxide was formed by RF sputtering, and it was used as a protective film after lift-off. Finally, annealing was performed at 350 °C in a nitrogen atmosphere to obtain a transistor.

[0174] (Characteristics of the transistor) For the transistor obtained above, the threshold voltage, S value, and reliability were evaluated. The results are shown in Table 1. Specifically, for the transistors obtained in Examples 1 to 3 and Comparative Examples 1 and 2 above, a semiconductor device analyzer ("B1500A" manufactured by Agilent Technologies) was used to measure them at room temperature in a light-shielded environment (inside a shield box). The drain voltage (Vd) was set to 0.1 V. For each applied Vd, with a constant Vd applied, the gate voltage (Vg) was swept from -20 V to 20 V or from -0.5 V / nm to 0.5 V / nm in steps of 0.05 V or 0.002 V / nm, and the current value Id was measured to obtain the Id-Vg characteristics. Here, the unit V / nm of the applied voltage is the value obtained by dividing the applied voltage by the EOT (equivalent oxide thickness) of the gate insulating film. The EOT is the value obtained by converting the high-k dielectric film thickness into the equivalent electrical film thickness of an SiO2 film, and is expressed as EOT = [thickness of the target insulating film] × [relative permittivity of SiO2 film] / [thickness of the target insulating film]. That is, it is not the physical high-k dielectric film thickness, but the equivalent film thickness representation when converted to the SiO2 film thickness with the same capacitance value. For example, since the hafnium oxide film has a relative permittivity of 20, the equivalent film thickness is 5.1 times the thickness of an SiO2 film (relative permittivity 3.9). Various parameters calculated from the Id-Vg characteristics are shown in Table 1. The calculation method for each parameter is as described below.

[0175] (a) Maximum value of linear mobility (μlin-Max) The maximum value of the linear mobility when Vd = 0.1 V was obtained by creating a graph of the Id-Vg characteristics, calculating the transconductance (Gm) for each Vg, and deriving the linear mobility (μlin) using the equation for the linear region. Specifically, Gm was calculated by ∂(Id) / ∂(Vg). Furthermore, μlin was calculated by the following equation (a) for the linear region. μlin=(Gm·L) / (W·Ci·Vd)…(a) Ci in equation (a) is the capacitance of the gate insulating film, and Ci [F / cm -14 was calculated based on the gate insulating film thickness, the relative permittivity 3.9 of SiO2, and the permittivity of vacuum 8.85×102 The value of ] was used. In formula (a), L is the channel length (L length), and W is the channel width (W length). Furthermore, from each graph of Vg-μlin, the maximum value of μlin (linear mobility) at Vg = -20 V to 20 V or -0.5 V / nm to 0.5 V / nm was calculated and designated as "μlin-Max [cm 2 / Vs] (Av. / Dev)". Also, in Table 1, the mobility at the gate voltage where Vg-Vth = 18 V was defined as "μlin-Max [cm 2 / Vs] at Vg-Vth = 18 V (Av. / Dev)". Here, "Av." means the average value, and "Dev" means the standard deviation. The threshold voltage Vth was defined as follows. Here, "Av." means the average value, and "Dev" means the standard deviation.

[0176] (b) S value and threshold voltage Vth From the graph of each Id-Vg characteristic, the S value (SS [mV / decade] (Av. / Dev)) and the threshold voltage (Nomarized Vth [V] (Av. / Dev)) were evaluated. Specifically, in the current value range of Id = 100 pA to 10 nA or 5×10 -7 ~5×10 -6 [mA / mm], the value obtained by the following formula (b) was calculated as the S value. Furthermore, the value of Vg at the current value of Id = 1 nA or 5×10 -6 [mA / mm] was calculated as the threshold voltage (Vth). Here, the unit of the current value Id is the value obtained by dividing the measured current value by the channel width W for normalization.

[0177]

Equation

[0178] (c) Reliability The reliability of the transistor was evaluated by a stress test. A positive bias stress test (PBS) and a negative bias stress test (NBS) were performed. The PBS was applied with Vg = +20 V at 25°C, and after 10,000 seconds had elapsed, the threshold voltage (Vth) was compared with that before the test, and the difference was defined as ΔVth. The NBS was applied with Vg = -20 V at 25°C, and after 10,000 seconds had elapsed, the threshold voltage (Vth) was compared with that before the test, and the difference was defined as ΔVth. Note that the threshold voltage (Vth) was defined as the gate voltage value at which the current value Id = 1 nA. Regarding the above, in Table 1, they were described as "PBS shift ΔVth [V] Vg at Id = 1 nA" and "NBS shift ΔVth [V] Vg at Id = 1 nA", respectively.

[0179] <Measurement Method of Intrinsic Mobility and Parasitic Resistance> Next, in the same manner as <Manufacture and Evaluation of Transistor Provided with Crystal Oxide Semiconductor Film>, a bottom-gate / top-contact type transistor having a plurality of channel lengths was fabricated. Using this transistor, the intrinsic mobility [cm 2 / Vs], which is the mobility due to the semiconductor channel excluding the contact resistance of the electrodes calculated by the transfer length method (TLM method), was measured. To perform the TLM method, the bottom-gate / top-contact type transistors described in the above Examples and Comparative Examples having a plurality of channel lengths were prepared. The drain voltage Vd in each FET element was set to 0.1 V. A constant voltage was applied for each Vd application, and the Id-Vg characteristics were obtained by measuring the current value Id while sweeping the gate voltage Vg from -20 V to 40 V in 0.1 V steps. Next, the Vg of the Id-Vg characteristics of each obtained element was normalized by the threshold voltage Vth of each element, and a graph of the Id-(Vg-Vth) characteristics was created. Then, the total resistance Rtotal at the source / drain ends was calculated from the current value Id and the value of Vd obtained when each Vg-Vth was applied. Next, a graph (TLM plot) was created with the channel length of the bottom-gate / top-contact type transistor having a plurality of channel lengths on the horizontal axis and the total resistance Rtotal at each Vg-Vth application on the vertical axis. This TLM plot can be linearly approximated by the following equation (c). Rtotal = rch·L + Rs / d ···(c) In formula (c), rch is the channel resistivity, and Rs / d is the parasitic resistance / contact resistance in the source / drain region. Based on formula (c), the channel resistivity rch can be obtained from the slope of the TLM plot. rch is given by the following formula (d). rch = 1 / (μFEi·Ci·W·(Vg - Vth)) ···(d) Here, μFEi is the intrinsic mobility, and a value obtained by correcting the voltage drop component of the drain voltage Vd due to the deviation of the channel length L and the parasitic resistance in the transistor can be obtained. Next, the reciprocal of rch was taken, and a graph with the vertical axis 1 / rch and the horizontal axis Vg - Vth was created. Based on formula (d), the (1 / rch)-(Vg - Vth) characteristics when a high Vg - Vth is applied can be linearly approximated, and its slope corresponds to μFEi·Ci·W. Therefore, μFEi was derived by dividing the calculated slope by Ci and W. In the case of a crystalline oxide semiconductor with a large absolute value of mobility, the field-effect linear mobility μlin may be greatly underestimated / overestimated due to parasitic resistance and channel length deviation. Therefore, it is preferable to use the intrinsic mobility μFEi derived by this method for evaluation. Also, the parasitic resistance can be derived from the TLM plot and formula (c) when each Vg - Vth is applied. In this example, Rs / d·W, which is a value normalized by the channel width W, is defined as the parasitic resistance, and it was calculated using the value when Vg - Vth = +40V was applied.

[0180]

Table 1

[0181] From the results in Table 1, it can be seen that the oxide semiconductor film according to this embodiment is excellent in field-effect mobility.

Industrial Applicability

[0182] The oxide semiconductor film of this embodiment is suitable as a channel layer of a transistor and can be used in various semiconductor devices. In particular, it can be suitably used in transistors for displays, FETs for memories (DRAM, NAND, ReRAM, FeRAM, and FeFET), FETs for logic ICs (CPU, MPU, BEOL, 3D-LSI, CMOS), FETs for sensors (CMOS image sensors), and transistors (MOSFET, power transistor, MESFET), etc.

Explanation of symbols

[0183] 1... Substrate, 2... Gate electrode, 3... First insulating film, 4... Source electrode, 5... Drain electrode, 6... Oxide semiconductor layer, 7, 7a... Second insulating film, 7b... Third insulating film, 8... Insulating film, H... Through hole.

Claims

1. An oxide semiconductor film containing indium as a main component, wherein a difference between roughness 1 of a lower surface of the oxide semiconductor film and roughness 2 of an upper surface opposite to the lower surface is 0.06 nm or less. Oxide semiconductor film.

2. The oxide semiconductor film according to Claim 1, wherein a film thickness of the oxide semiconductor film is 20.0 mm or less. The oxide semiconductor film according to Claim 1.

3. The oxide semiconductor film according to Claim 1, wherein the film thickness of the oxide semiconductor film is less than 10.0 mm. The oxide semiconductor film according to Claim 1.

4. The oxide semiconductor film according to Claim 1, wherein the roughness 1 of the lower surface is less than 0.2 nm. The oxide semiconductor film according to Claim 1.

5. The oxide semiconductor film according to Claim 1, wherein an atomic ratio of indium to all metal elements contained in the oxide semiconductor film is 62.0 at% or more. The oxide semiconductor film according to Claim 1.

6. The oxide semiconductor film according to Claim 1, wherein the atomic ratio of indium to all metal elements contained in the oxide semiconductor film is 100.0 at% or less. The oxide semiconductor film according to Claim 1.

7. The oxide semiconductor film according to Claim 1, further containing gallium. The oxide semiconductor film according to Claim 1.

8. The oxide semiconductor film according to Claim 1, wherein an atomic ratio of gallium to all metal elements contained in the oxide semiconductor film is 20.0 at% or less. The oxide semiconductor film according to Claim 1.

9. The oxide semiconductor film according to Claim 1, wherein an atomic ratio of gallium to all metal elements contained in the oxide semiconductor film is 0.1 at% or more. The oxide semiconductor film according to Claim 1.

10. The oxide semiconductor film according to Claim 1, wherein an electron diffraction spot or cross section in electron beam diffraction shows a Bixbyite structure. The oxide semiconductor film according to Claim 1.

11. The mobility is 70.0 cm ２ / Vs or more, The oxide semiconductor film according to Claim 1.

12. The oxide semiconductor film according to Claim 1, formed by atomic layer deposition. The oxide semiconductor film according to Claim 1.

13. An oxide semiconductor film containing indium as a main component, wherein a difference between roughness 1 of a lower surface of the oxide semiconductor film and roughness 2 of an upper surface opposite to the lower surface is 0.06 nm or less, wherein the film thickness of the oxide semiconductor film is less than 10.0 mm, and wherein the roughness 1 of the lower surface is less than 0.2 nm. Oxide semiconductor film.

14. The oxide semiconductor film according to Claim 13, wherein an atomic ratio of gallium to all metal elements contained in the oxide semiconductor film is 0.1 at% or more. The oxide semiconductor film according to Claim 13.

15. The mobility is 50.0 cm ２ / Vs or more, The oxide semiconductor film according to Claim 14.

16. The oxide semiconductor film according to Claim 15, formed by atomic layer deposition. The oxide semiconductor film according to Claim 15.

17. A transistor provided with a layer made of an oxide semiconductor film according to any one of claims 1 to 16, an insulating layer, and an electrode, on a substrate. Transistor.

18. The transistor according to claim 17, which is of a bottom gate - top contact type or a top gate - top contact type. The transistor according to claim 17.

19. The transistor according to claim 17, which is of a three - dimensional vertical channel type. The transistor according to claim 17.

20. The transistor according to claim 17, wherein the insulating layer contains at least one selected from the group consisting of gallium oxide, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.

21. Further comprising a first insulating film and a second insulating film, wherein the electrode is a gate electrode, the first insulating film is located between the gate electrode and the layer made of the oxide semiconductor film, the second insulating film is located on the opposite side of the layer made of the oxide semiconductor film with respect to the first insulating film and is in contact with the layer made of the oxide semiconductor film, the second insulating film contains gallium oxide. The transistor according to claim 17.

22. The transistor according to claim 17, wherein the electrode contains at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), chromium (Cr), gold (Au), zinc (Zn), niobium (Nb), manganese (Mn), and titanium nitride (TiN). The transistor according to claim 17.

23. A semiconductor device including the transistor according to claim 17.

24. The semiconductor device according to claim 23, which is a semiconductor memory device.

25. An electronic circuit including the semiconductor device according to claim 23.

26. An electric device, an electronic device, a vehicle, or a power unit including the electronic circuit according to claim 25.

27. A method for manufacturing an oxide semiconductor film according to any one of claims 1 to 16, the method comprising a film-forming step of forming a film by atomic layer deposition using an indium-containing precursor.

28. using triethylindium as the indium-containing precursor, A method for manufacturing an oxide semiconductor film according to claim 27.

29. further using a gallium-containing precursor in the film-forming step, A method for manufacturing an oxide semiconductor film according to claim 27.

30. A method for analyzing the quality of an oxide semiconductor film containing indium as a main component, the method including determining whether a difference between roughness 1 of a lower surface of the oxide semiconductor film and roughness 2 of an upper surface opposite to the lower surface is 0.06 nm or less. Method.

31. further including, when it is determined that the difference between roughness 1 of a lower surface of the oxide semiconductor film and roughness 2 of an upper surface opposite to the lower surface is 0.06 nm or less, evaluating that the quality of the oxide semiconductor film is good, A method according to claim 30.

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