Amplifier

Abstract

To suppress the increase in power losses.SOLUTION: An amplifier includes a first transistor in which a gate terminal is connected to a signal input port and a source terminal is grounded, a second transistor in which a gate terminal is grounded and a source terminal is connected to a drain terminal of the first transistor, and a harmonic control circuit that is connected to the gate terminal of the second transistor and controls harmonic components generated when amplifying a signal input from the input port.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an amplifier.

Background Art

[0002] In recent years, the trend towards high-capacity transmission in the field of communications has advanced, and for example, this has also had an impact on the field of wireless communications. Specifically, for example, in the fifth-generation mobile communication system (5G), broadbanding of wireless communication devices has been required. In addition, the frequency of the carriers used has increased, resulting in an increase in the power loss of the amplifier that amplifies the signal, and thus the power efficiency of the wireless communication device has deteriorated.

[0003] One of the causes of the increase in the power loss of the amplifier is considered to be that power gains such as the unilateral power gain and the maximum available power gain of the transistor used for signal amplification, as well as the current gain, decrease as the frequency of the signal increases.

[0004] By the way, recently, the performance of metal-oxide-semiconductor (MOS) transistors using silicon (Si) material has improved and they are also actively used in the field of wireless communications. For example, when an Si-MOS transistor is applied to an amplifier of a wireless communication device, it is required that the maximum oscillation frequency or the high-frequency cut-off frequency of this transistor be about 3 to 5 times the carrier frequency. For this reason, a transistor with a shortened gate length may be used, but as the gate length is shortened, the power supply voltage that can be applied to the transistor decreases. Therefore, in order to obtain a desired output power, a cascode configuration in which a source-grounded transistor and a gate-grounded transistor are connected in series may be adopted to configure an amplifier that can utilize a high power supply voltage.

Prior Art Documents

Patent Documents

[0005] Patent Document 1 Japanese Patent Publication No. 2004-516737 Summary of the Invention Problems to be Solved by the Invention

[0006] However, in an amplifier having a cascode configuration, there is a problem that power loss increases. Specifically, when the signal power input to the transistor increases, harmonics having frequencies that are integer multiples of the carrier frequency are generated depending on the non-linearity of the current-voltage characteristics of the transistor. Since harmonics are unwanted signals, a filter circuit or the like for blocking the transmission of the harmonic signal may be provided on the signal path. Such a filter circuit or the like is usually formed using passive elements having electrical resistance such as capacitors and inductors. Therefore, when the signal passes through the filter circuit, the signal power is converted into heat and power loss occurs.

[0007] When a circuit for blocking the transmission of a high-frequency signal is formed on the signal path in this way, in addition to the power loss due to the increase in the carrier frequency described above, a larger power loss occurs, and the power efficiency of the wireless communication device is significantly reduced.

[0008] The disclosed technology has been made in view of such points, and an object thereof is to provide an amplifier capable of suppressing an increase in power loss. Means for Solving the Problems

[0009] In one aspect, the amplifier disclosed in the present application includes a first transistor having a gate terminal connected to a signal input port and a source terminal grounded, a second transistor having a gate terminal grounded and a source terminal connected to the drain terminal of the first transistor, and a harmonic control circuit connected to the gate terminal of the second transistor and controlling harmonic components generated during amplification of a signal input from the input port. Effects of the Invention

[0010] According to one aspect of the amplifier disclosed in the present application, it has the effect of suppressing an increase in power loss.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Before describing the embodiments of the amplifier disclosed in the present application, an amplifier adopting a cascode configuration will be described. FIG. 1 is a diagram showing the configuration of a cascode amplifier. The cascode amplifier shown in FIG. 1 amplifies a signal input from the input port 115 and outputs it from the output port 116. On the signal path, the source-grounded transistor 101 and the gate-grounded transistor 104 are connected in series, and a cascode configuration is adopted.

[0013] The signal input from the input port 115 passes through the capacitor 110, the input matching circuit 113, the source-grounded transistor 101, the gate-grounded transistor 104, the output matching circuit 114, and the capacitor 111 and is output from the output port 116. The gate voltage of the source-grounded transistor 101 is supplied from the power supply 103 via the resistor 102, and the gate voltage of the gate-grounded transistor 104 is supplied by connecting the node 108 where the voltage of the power supply 105 is divided by the resistors 106 and 107 to the gate terminal of the gate-grounded transistor 104.

[0014] The positive terminal of the gate DC power supply 103, whose negative terminal is grounded and supplies a gate voltage, is connected to the gate terminal of the source-grounded transistor 101 via the resistor 102. Also, the source terminal of the source-grounded transistor 101 is grounded, and the drain terminal is connected to the source terminal of the gate-grounded transistor 104. One terminal of the inductor 109 for blocking the AC signal is connected to the drain terminal of the gate-grounded transistor 104, and the other terminal of the inductor 109 is connected to the positive terminal of the power supply 105 and the resistor 106. The gate terminal of the gate-grounded transistor 104 is connected to the node 108 between the resistors 106 and 107 and is further connected to the capacitor 112 for short-circuiting the AC signal.

[0015] Further, the input matching circuit 113 is connected to the gate terminal of the source - grounded transistor 101, and a signal input from the input port 115 is input to the input matching circuit 113 via the DC - blocking capacitor 110. On the other hand, the output matching circuit 114 is connected to the drain terminal of the gate - grounded transistor 104, and the signal output from the output matching circuit 114 is output from the output port 116 via the DC - blocking capacitor 111.

[0016] When a signal is input from the input port 115, this signal is input to the input matching circuit 113 via the DC - blocking capacitor 110. In the input matching circuit 113, matching is performed so that the gain obtained at a desired frequency is maximized, and the signal output from the input matching circuit 113 is input to the gate terminal of the source - grounded transistor 101.

[0017] The signal input to the gate terminal of the source - grounded transistor 101 changes the potential of the drain terminal of the source - grounded transistor 101 and changes the current flowing in and out of the drain terminal. Since the drain terminal of the source - grounded transistor 101 is connected to the source terminal of the gate - grounded transistor 104, the change in the potential of the drain terminal of the source - grounded transistor 101 causes a change in the potential between the gate terminal and the source terminal of the gate - grounded transistor 104. At this time, because the capacitor 112 is connected to the gate terminal of the gate - grounded transistor 104, the AC signal can be short - circuited.

[0018] As a result of the change in the potential between the gate terminal and the source terminal of the gate - grounded transistor 104, the potential of the drain terminal of the gate - grounded transistor 104 changes, and the drain current is input to the output matching circuit 114 as a signal. In the output matching circuit 114, matching is performed so that the gain obtained at a desired frequency is maximized, and the signal output from the output matching circuit 114 is output from the output port 116 via the DC - blocking capacitor 111.

[0019] Here, when the power of the input signal increases, the voltage dependence of the drain currents of the source-grounded transistor 101 and the gate-grounded transistor 104 becomes non-linear, and the signal output from the output port 116 contains harmonic components and the waveform is distorted. In order to suppress the harmonic components, it is conceivable to insert a filter circuit or a harmonic control circuit, for example, into the output matching circuit 114 on the signal path. However, when these circuits are inserted on the signal path through which the drain current flows as a signal, the signal power is converted into heat and power loss occurs. That is, in the cascode amplifier, there is a problem that the power loss increases.

[0020] Hereinafter, an embodiment of the amplifier disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited by this embodiment.

[0021] FIG. 2 is a diagram showing the configuration of an amplifier according to an embodiment. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals. The amplifier shown in FIG. 2 has a configuration in which a harmonic control circuit 120 is added to the cascode amplifier shown in FIG. 1. The harmonic control circuit 120 is connected to the gate terminal of the gate-grounded transistor 104, not on the signal path. That is, the harmonic control circuit 120 is provided between the capacitor 112 and the node 108.

[0022] The amplifier shown in FIG. 2 is an amplifier that amplifies a signal having a frequency of, for example, 28 GHz. The characteristics of the source-grounded transistor 101 and the gate-grounded transistor 104 at this time are shown in FIGS. 3 and 4. That is, FIG. 3 shows the drain current-voltage characteristics for each gate voltage. Also, the upper diagram in FIG. 4 shows the mutual conductance for each gate voltage, the middle diagram in FIG. 4 shows the cut-off frequency for each gate voltage, and the lower diagram in FIG. 4 shows the terminal capacitance for each gate voltage. In the lower diagram of FIG. 4, the solid line indicates the capacitance between the gate-source terminals, the broken line indicates the capacitance between the gate-drain terminals, and the one-dot chain line indicates the capacitance between the drain-source terminals. Furthermore, the maximum oscillation frequency of the source-grounded transistor 101 and the gate-grounded transistor 104 is 270 GHz.

[0023] By connecting the source - grounded transistor 101 and the gate - grounded transistor 104 having such characteristics in series, it becomes possible to amplify a signal with a frequency of 28 GHz.

[0024] Returning to FIG. 2, the input matching circuit 113 is configured by connecting a shunt capacitor to a node between, for example, a serially - connected capacitor and inductor. Similarly, the output matching circuit 114 is configured by connecting a shunt capacitor to a node between, for example, a serially - connected capacitor and inductor.

[0025] The harmonic control circuit 120 is configured by combining a series circuit in which an inductor as an inductive element and a capacitor as a capacitive element are serially connected, and a parallel circuit in which the inductor and the capacitor are parallely connected. Then, the harmonic control circuit 120 controls the gate voltage of the gate - grounded transistor 104 so as to output a fundamental wave having the same frequency as the input signal and suppress the second - harmonic wave and partially suppress the third - harmonic wave. Specifically, the harmonic control circuit 120 has, for example, the configuration shown in FIG. 5. That is, the harmonic control circuit 120 includes a second - harmonic wave removal filter 120a, a third - harmonic wave series resonance circuit 120b, a fundamental wave series resonance circuit 120c, and a second - harmonic wave parallel resonance circuit 120d.

[0026] The second harmonic removal filter 120a is a band-stop filter that suppresses second harmonic signals in an arbitrary frequency band at a frequency that is twice the center frequency (here, 56 GHz). The second harmonic removal filter 120a is configured by combining series and parallel circuits of capacitors and inductors that block the passage of second harmonic signals. That is, the second harmonic removal filter 120a is formed by connecting in series a parallel circuit of capacitor C1 and inductor L1, a parallel circuit of capacitor C3 and inductor L3, and a parallel circuit of capacitor C2 and inductor L2, and connecting in series between each parallel circuit a series circuit of capacitor C4 and inductor L4 and a series circuit of capacitor C5 and inductor L5. Note that the number of series and parallel circuits of capacitors and inductors is not limited to that shown in FIG. 5, and for example, the series circuit of capacitor C5 and inductor L5 and the parallel circuit of capacitor C2 and inductor L2 may be deleted, or other series and parallel circuits of capacitors and inductors may be added.

[0027] The third harmonic series resonance circuit 120b is a series resonance circuit that resonates at a frequency that is three times the center frequency (here, 84 GHz). That is, the third harmonic series resonance circuit 120b is configured by connecting capacitor C6 and inductor L6 in series. The third harmonic series resonance circuit 120b suppresses a part of the third harmonic signal and then allows it to pass.

[0028] The fundamental wave series resonance circuit 120c is a series resonance circuit that resonates at the fundamental wave frequency (here, 28 GHz). That is, the fundamental wave series resonance circuit 120c is configured by connecting capacitor C7 and inductor L7 in series. The capacitance and inductance of capacitor C7 and inductor L7 are each three times the capacitance and inductance of capacitor C6 and inductor L6. The fundamental wave series resonance circuit 120c suppresses a part of the fundamental wave signal and then allows it to pass.

[0029] The second harmonic parallel resonance circuit 120d is a parallel resonance circuit that resonates at the second harmonic frequency (here, 56 GHz). That is, the second harmonic parallel resonance circuit 120d is configured by connecting a capacitor C8 and an inductor L8 in parallel and connecting a capacitor C9 for removing DC components. The second harmonic parallel resonance circuit 120d adjusts the band edges of the second harmonic signal suppressed by the second harmonic removal filter 120a.

[0030] The frequency characteristics of the second harmonic removal filter 120a, the third harmonic series resonance circuit 120b, the fundamental wave series resonance circuit 120c, and the second harmonic parallel resonance circuit 120d, and the frequency characteristics of the harmonic control circuit 120 are shown in FIG. 6. FIG. 6 shows the reflection loss (S11 parameter) indicated by the solid line of each circuit and the insertion loss (S21 parameter) indicated by the broken line.

[0031] As shown in FIG. 6, the second harmonic is suppressed by the second harmonic removal filter 120a and the second harmonic parallel resonance circuit 120d, and the third harmonic and the fundamental wave are partially suppressed and passed by the third harmonic series resonance circuit 120b and the fundamental wave series resonance circuit 120c, respectively. As a result, as shown in the bottom diagram of FIG. 6, the harmonic control circuit 120 outputs a fundamental wave signal, suppresses the second harmonic signal, and partially suppresses the third harmonic signal. Then, when these signals are input to the gate terminal of the grounded-gate transistor 104, a fundamental wave is output at the drain terminal of the grounded-gate transistor 104, the second harmonic is suppressed, and the third harmonic is partially suppressed. As a result, the harmonic components of the output signal are suppressed, and the output power of the fundamental wave component can be increased. Further, since the harmonic control circuit 120 for suppressing the harmonic components is not provided on the signal path, power loss of the signal due to the harmonic control circuit 120 does not occur, and an increase in power loss can be suppressed.

[0032] Note that the harmonic control circuit 120 can be configured using a distributed constant line, for example, as shown in FIG. 7, instead of being configured using passive elements such as capacitors and inductors.

[0033] Next, the output signals of the cascode amplifier shown in FIG. 1 and the amplifier shown in FIG. 2 will be described with reference to FIGS. 8 to 10.

[0034] FIG. 8 is a diagram showing a specific example of an input waveform and an output waveform of an amplifier. In FIG. 8, the solid line indicates the output waveform of the amplifier shown in FIG. 2, and the broken line indicates the output waveform of the cascode amplifier shown in FIG. 1.

[0035] The uppermost diagram in FIG. 8 shows the input waveform. The frequency of this input waveform is 28 GHz. When a signal having such an input waveform is input to the amplifier, as shown by the broken line in the third and fourth diagrams of FIG. 8, the cascode amplifier shown in FIG. 1 without the harmonic control circuit 120 outputs harmonic components such as the second harmonic and the third harmonic without being suppressed. On the other hand, in the amplifier shown in FIG. 2 having the harmonic control circuit 120, the second harmonic is suppressed, and a part of the third harmonic is suppressed, and the power of the fundamental wave increases accordingly. That is, the amplifier having the harmonic control circuit 120 can achieve high gain.

[0036] FIG. 9 is a diagram showing a specific example of the output power characteristics of an amplifier. In FIG. 9, the solid line indicates the output power of the amplifier shown in FIG. 2, and the broken line indicates the output power of the cascode amplifier shown in FIG. 1. Also, the line without marks indicates the power of the output signal, the line with circles indicates the output power of the fundamental wave, the line with triangles indicates the output power of the second harmonic, the line with squares indicates the output power of the third harmonic, and the line with crosses indicates the power added efficiency (PAE: Power Added Efficiency).

[0037] As shown in FIG. 9, by providing the harmonic control circuit 120, in particular, the second harmonic is greatly suppressed (~12 dB), and the linear region in which the power of the input signal and the power of the output signal have linearity is widened. That is, the harmonic control circuit 120 suppresses the harmonic components, thereby reducing the distortion of the output signal. Also, by providing the harmonic control circuit 120, the power added efficiency is improved to about 1.5 times.

[0038] FIG. 10 is a diagram showing a specific example of gain-output power characteristics. In FIG. 10, the solid line indicates the gain and output power of the amplifier shown in FIG. 2, and the dashed line indicates the gain and output power of the cascode amplifier shown in FIG. 1.

[0039] As shown in FIG. 10, at any output power, the gain of the amplifier having the harmonic control circuit 120 is high, and the gain difference 201 is, for example, about 1.5 dB. Also, the 1 dB gain compression point (P1dB) is improved by the amplifier having the harmonic control circuit 120, and the improvement width 202 is, for example, about 1.6 dBm.

[0040] As described above, according to the present embodiment, in an amplifier having a cascode configuration in which a source-grounded transistor and a gate-grounded transistor are connected in series, a harmonic control circuit is connected to the gate terminal of the gate-grounded transistor. Then, the harmonic control circuit controls the gate voltage of the gate-grounded transistor so that a fundamental wave is output and the second harmonic is suppressed and a part of the third harmonic is suppressed. For this reason, harmonic components can be suppressed and the distortion of the output signal can be reduced, and since no harmonic control circuit is provided on the signal path, no power loss of the signal occurs. Therefore, an increase in power loss can be suppressed.

[0041] It is also possible to adjust the linearity of the output power by adjusting the suppression amount of the third harmonic by the harmonic control circuit 120. Specifically, FIGS. 11 and 12 are diagrams showing modified examples of the harmonic control circuit 120. In FIGS. 11 and 12, the same parts as those in FIG. 5 are denoted by the same reference numerals. The harmonic control circuit 120 shown in FIG. 11 has a third harmonic series resonance circuit 121b instead of the third harmonic series resonance circuit 120b of the harmonic control circuit 120 shown in FIG. 5. Also, the harmonic control circuit 120 shown in FIG. 12 has a third harmonic series resonance circuit 122b instead of the third harmonic series resonance circuit 120b of the harmonic control circuit 120 shown in FIG. 5.

[0042] The third-harmonic series resonance circuit 121b is configured by connecting a resistor Rx in series with a capacitor C6 and an inductor L6. On the other hand, the third-harmonic series resonance circuit 122b is configured by connecting a transistor in series with a capacitor C6 and an inductor L6. This transistor is driven by an external voltage Vx connected via inductors L9 and L10 and operates as a variable resistor.

[0043] In this way, by adding a resistive element to the third-harmonic series resonance circuits 121b and 122b and adjusting the resistance of this resistive element, the suppression amount of the third harmonic can be controlled. Specifically, for example, Fig. 13 shows the frequency characteristics near the third harmonic when the resistor Rx in Fig. 11 is set to 1Ω, 10Ω, 100Ω, and 10kΩ. Fig. 13 shows the reflection loss (S11 parameter) indicated by the solid line and the insertion loss (S21 parameter) indicated by the dashed line when the value of the resistor Rx is 1Ω, 10Ω, 100Ω, and 10kΩ.

[0044] That is, curves 211 and 221 show the insertion loss and reflection loss when the resistor Rx is 1Ω, curves 212 and 222 show the insertion loss and reflection loss when the resistor Rx is 10Ω, curves 213 and 223 show the insertion loss and reflection loss when the resistor Rx is 100Ω, and curves 214 and 224 show the insertion loss and reflection loss when the resistor Rx is 10kΩ. As shown in Fig. 13, by changing the value of the resistor Rx, the suppression amount of the third harmonic changes, and the gate voltage applied to the gate-grounded transistor 104 also changes. Therefore, the power of the output signal of the amplifier can be adjusted, and the linearity of the output power can be adjusted.

[0045] In the above-described embodiment, one gate-grounded transistor 104 is connected to the source-grounded transistor 101 to form an amplifier. However, it is also possible to connect a plurality of gate-grounded transistors 104 to the source-grounded transistor 101 to form an amplifier. FIG. 14 is a diagram showing the configuration of an amplifier when n (n is an integer of 2 or more) gate-grounded transistors 104-1 to 104-n are connected to the source-grounded transistor 101. As shown in FIG. 14, harmonic control circuits 120-1 to 120-n are connected to the gate terminals of the n gate-grounded transistors 104-1 to 104-n together with capacitors 112-1 to 112-n for short-circuiting the AC signals, respectively. The gate voltages of the gate-grounded transistors 104-1 to 104-n are supplied by dividing the voltage of the power supply 105 by resistors 106-1 to 106-n and 107-1 to 107-n, respectively.

Explanation of Signs

[0046] 101 Source-grounded transistor 102, 106, 107 Resistors 103, 105 Power supplies 104 Gate-grounded transistor 106, 107 Resistors 109 Inductor 110, 111, 112 Capacitors 113 Input matching circuit 114 Output matching circuit 115 Input port 116 Output port 120 Harmonic control circuit 120a Second harmonic removal filter 120b, 121b, 122b Third harmonic series resonance circuits 120c Fundamental wave series resonance circuit 120d Second harmonic parallel resonance circuit

Claims

1. A first transistor having a gate terminal connected to a signal input port and a source terminal grounded; A second transistor having a gate terminal grounded and a source terminal connected to the drain terminal of the first transistor; A harmonic control circuit connected to the gate terminal of the second transistor for controlling harmonic components generated during amplification of a signal input from the input port. The amplifier is characterized by comprising: The harmonic control circuit includes: A series circuit in which an inductive element and a capacitive element are connected in series; A parallel circuit in which an inductive element and a capacitive element are connected in parallel; An amplifier characterized by having the above.

2. A first transistor having a gate terminal connected to a signal input port and a source terminal grounded; A second transistor having a gate terminal grounded and a source terminal connected to the drain terminal of the first transistor; A harmonic control circuit connected to the gate terminal of the second transistor for controlling harmonic components generated during amplification of a signal input from the input port. The amplifier is characterized by comprising: The harmonic control circuit includes: A second harmonic removal filter for suppressing the second harmonic of the signal input from the input port; A third harmonic series resonance circuit that resonates with the third harmonic of the signal input from the input port and has an inductive element and a capacitive element connected in series; A fundamental wave series resonance circuit that resonates with the fundamental wave of the signal input from the input port and has an inductive element and a capacitive element connected in series; A second harmonic parallel resonance circuit that resonates with the second harmonic of the signal input from the input port and has an inductive element and a capacitive element connected in parallel; An amplifier characterized by having the above.

3. The third harmonic series resonance circuit includes: An inductive element, a capacitive element, and a resistive element connected in series; The amplifier according to claim 2, characterized by the above.

4. The third harmonic series resonance circuit includes: An inductive element, a capacitive element, and a third transistor connected in series; The amplifier according to claim 2, characterized by the above.

5. The second harmonic removal filter includes: A first parallel circuit in which an inductive element and a capacitive element are connected in parallel; A second parallel circuit connected in series with the first parallel circuit, the second parallel circuit being a parallel circuit in which an inductive element and a capacitive element are connected in parallel; A series circuit in which an inductive element and a capacitive element are connected in series, one end of which is grounded and the other end of which is connected between the first parallel circuit and the second parallel circuit; The amplifier according to claim 2, characterized by having the above.

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