Wiring Substrate and Method for Manufacturing the Same

Abstract

To provide a wiring board in which an outer edge of a pad for external connection is located inside an outer edge of an opening of an insulating layer in a plan view.SOLUTION: A wiring board has a pad for external connection and an insulating layer. A part of a lower surface of the pad is coated with the insulating layer. An upper surface of the pad is provided at a position lower than an upper surface of the insulating layer. The insulating layer comprises a groove located around the pad in a plan view and opened toward the upper surface side of the insulating layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the same.

Background Art

[0002] A wiring board has, for example, pads exposed from an insulating layer disposed on the outermost layer. These pads serve as pads for external connection for electrically connecting to, for example, a motherboard or the like. The manufacturing process of this wiring board includes, for example, a step of forming pads for external connection on the upper surface of a support, a step of forming an insulating layer covering the pads for external connection on the upper surface of the support, and a step of removing the support.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when the area of the upper surface of the pad is large, the capacitance may increase and the electrical signal may deteriorate. Therefore, in recent years, there has been a demand to reduce the area of the upper surface of the pad in order to reduce the capacitance. On the other hand, from the viewpoint of ensuring compatibility with a conventional wiring board regarding a socket or the like used for connection to the wiring board, there is a demand that even if the pad is miniaturized, the size of the opening of the insulating layer around the pad should not be changed.

[0005] In order to meet these demands, it is necessary to move the outer edge of the pad inward from the outer edge of the opening of the insulating layer around the pad without moving the outer edge of the opening of the insulating layer around the pad in plan view. However, in the above-described wiring board, it is difficult to move only the outer edge of the pad inward from the outer edge of the opening of the insulating layer.

[0006] The present invention has been made in view of the above points, and an object thereof is to provide a wiring board in which the outer edge of a pad for external connection is located inside the outer edge of an opening of an insulating layer in a plan view.

Means for Solving the Problems

[0007] This wiring board has a pad for external connection and an insulating layer. A part of the lower surface of the pad is covered by the insulating layer, and the upper surface of the pad is said at a position lower than the upper surface of the insulating layer. The insulating layer is provided with a groove that is located around the pad in a plan view and opens to the upper surface side of the insulating layer. the bottom surface of the groove is at a position lower than the lower surface of the pad .

Effects of the Invention

[0008] According to the disclosed technology, it is possible to provide a wiring board in which the outer edge of a pad for external connection is located inside the outer edge of an opening of an insulating layer in a plan view.

Brief Description of the Drawings

[0009] [Figure 1] It is a diagram illustrating a wiring board according to a first embodiment. [Figure 2] It is a diagram (part 1) illustrating a manufacturing process of a wiring board according to a first embodiment. [Figure 3] It is a diagram (part 2) illustrating a manufacturing process of a wiring board according to a first embodiment. [Figure 4] It is a diagram (part 3) illustrating a manufacturing process of a wiring board according to a first embodiment. [Figure 5] It is a diagram illustrating a wiring board according to a modification 1 of the first embodiment. [Figure 6] It is a diagram illustrating a wiring board according to a second embodiment. [Figure 7] It is a diagram illustrating a wiring board according to a third embodiment.

Modes for Carrying Out the Invention

[0010] Hereinafter, embodiments for implementing the invention will be described with reference to the drawings. In each drawing, the same reference numerals are assigned to the same components, and redundant descriptions may be omitted.

[0011] 〈First Embodiment〉 [Structure of Wiring Substrate] FIG. 1 is a diagram illustrating a wiring substrate according to the first embodiment. FIG. 1(a) is a partial plan view, and FIG. 1(b) is a partial cross-sectional view taken along line A-A of FIG. 1(a).

[0012] Referring to FIG. 1, the wiring substrate 1 has a pad 10, an insulating layer 20, a wiring layer 30, an insulating layer 40, and a wiring layer 50. In the wiring substrate 1, a larger number of insulating layers and wiring layers may be laminated.

[0013] In this embodiment, for convenience, the insulating layer 20 side of the wiring substrate 1 in FIG. 1(b) is defined as the upper side or one side, and the insulating layer 40 side is defined as the lower side or the other side. Also, the surface on the insulating layer 20 side of each part is defined as the upper surface or one surface, and the surface on the insulating layer 40 side is defined as the lower surface or the other surface. However, the wiring substrate 1 can be used in an upside-down state or arranged at an arbitrary angle. Also, a plan view refers to viewing an object from the normal direction of the upper surface 20a of the insulating layer 20, and a planar shape refers to the shape of an object viewed from the normal direction of the upper surface 20a of the insulating layer 20.

[0014] The pad 10 is a pad for external connection. The pad 10 can be used, for example, to electrically connect to a mounting substrate (not shown) such as a motherboard. The pad 10 has a laminated structure. For example, the metal layer 13, which is the lowermost layer in contact with the insulating layer 20, is a copper layer (Cu layer), and the metal layer 12, which is the uppermost layer, is a gold layer (Au layer). The thickness of the metal layer 13 is, for example, about 10 to 30 μm.

[0015] Incidentally, the metal layer 12 may have a laminated structure with the uppermost layer being an Au layer. The metal layer 12 can be, for example, a Ni / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order on the metal layer 13), a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order on the metal layer 13), and the like. When the metal layer 12 is a Ni / Pd / Au layer, for example, the thickness of the Ni layer is about 5 to 10 μm, the thickness of the Pd layer is about 0.015 to 0.065 μm, and the thickness of the Au layer is about 0.030 to 0.090 μm.

[0016] The planar shape of the pad 10 is, for example, a circle with a diameter of about 600 μm to 800 μm. However, the planar shape of the pad 10 may be an ellipse, a rectangle, or any other arbitrary shape.

[0017] The pad 10 is exposed on the upper surface 20a side of the insulating layer 20. As the material of the insulating layer 20, for example, an insulating resin mainly composed of an epoxy resin can be used. The insulating layer 20 may contain a filler such as silica (SiO2). The thickness of the insulating layer 20 can be, for example, about 10 to 70 μm.

[0018] A part of the lower surface of the pad 10 (the part excluding the part connected to the via wiring) is covered by the insulating layer 20. Also, the upper surface 10a of the pad 10 is at a position lower than the upper surface 20a of the insulating layer 20. The distance between the upper surface 10a of the pad 10 and the upper surface 20a of the insulating layer 20 is, for example, about 5 to 20 μm. The insulating layer 20 is provided with a groove 20g that is located around the pad 10 in a plan view and opens on the upper surface 20a side of the insulating layer 20. When the planar shape of the pad 10 is circular, the groove 20g can be formed in a ring shape such that, for example, in a plan view, the inner edge and the outer edge are circles with different diameters. The width of the groove 20g can be, for example, about 80 μm to 100 μm.

[0019] The bottom surface of the groove 20g is, for example, at a position deeper than the lower surface of the pad 10 (the lower surface of the metal layer 13). However, the bottom surface of the groove 20g may be at the same position as the lower surface of the pad 10 (the lower surface of the metal layer 13), or may be at a position shallower than the lower surface of the pad 10 (the lower surface of the metal layer 13). The bottom surface of the groove 20g is, for example, at a position of ±30 μm with respect to the lower surface of the pad 10 (the lower surface of the metal layer 13). That is, although the side surface of the pad 10 is exposed from the insulating layer 20, there are cases where the entire side surface of the pad 10 is exposed from the insulating layer 20, and cases where the side closer to the upper surface 10a of the side surface of the pad 10 is exposed and the side closer to the lower surface is covered by the insulating layer 20.

[0020] The wiring layer 30 is formed on the other side of the insulating layer 20. The wiring layer 30 includes, for example, via wirings filled in via holes 20x that penetrate the insulating layer 20 and expose the lower surface of the pad 10, via receiving pads formed on the lower surface of the insulating layer 20, and wiring patterns. The via wiring penetrates the insulating layer 20 and contacts the lower surface of the pad 10. The via hole 20x can be a frustum-shaped recess in which the diameter of the opening on the insulating layer 40 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the pad 10. As the material of the wiring layer 30, for example, copper or the like can be used. The thickness of the via receiving pads and the wiring patterns constituting the wiring layer 30 can be, for example, about 10 to 30 μm.

[0021] The insulating layer 40 is formed so as to cover the wiring layer 30 on the lower surface of the insulating layer 20. The material and thickness of the insulating layer 40 can be, for example, the same as those of the insulating layer 20. The insulating layer 40 may contain a filler such as silica (SiO2).

[0022] The wiring layer 50 is formed on the other side of the insulating layer 40. The wiring layer 50 includes, for example, via wirings filled in via holes 40x that penetrate the insulating layer 40 and expose the lower surface of the via receiving pads of the wiring layer 30, pads formed on the lower surface of the insulating layer 40, and wiring patterns. The via holes 40x can be frustum-shaped recesses in which the diameter of the opening on the lower surface side of the insulating layer 40 is larger than the diameter of the bottom surface of the opening formed by the lower surface of the via receiving pads of the wiring layer 30. The material of the wiring layer 50, the thickness of the via receiving pads and the wiring patterns constituting the wiring layer 50 can be the same as those of the wiring layer 30, for example.

[0023] Thus, in the wiring substrate 1, the insulating layer 20 is provided with grooves 20g that are located around the pads 10 in a plan view and open to the upper surface 20a side of the insulating layer 20. As a result, the outer edge of the pad 10 can be located inside the outer edge of the opening of the insulating layer 20 (the outer edge of the groove 20g) in a plan view, so that the area of the upper surface 10a of the pad 10 can be reduced. By reducing the area of the upper surface 10a of the pad 10, it is possible to reduce the capacitance of the pad 10 and suppress the degradation of the electrical signal passing through the pad 10.

[0024] Also, if the grooves 20g are not provided, the position of the opening of the insulating layer 20 that exposes the upper surface 10a of the pad 10 will be as shown in FIG. 4(a) described later. That is, in a plan view, the outer edge of the opening and the outer edge of the pad 10 are at the same position. In this case, if the area of the upper surface 10a of the pad 10 is made smaller than before, the size of the opening will also become smaller, and the compatibility with the conventional wiring substrate cannot be ensured.

[0025] That is, when connecting the pad 10 to a mounting substrate such as a motherboard, a socket is used. However, the opening of the insulating layer 20 that exposes the upper surface 10a of the pad 10 is sized such that the socket does not contact the insulating layer 20. Therefore, in order to reduce the capacitance of the pad 10 while ensuring compatibility with a conventional wiring board, it is necessary to reduce the area of the upper surface 10a of the pad 10 without changing the size of the opening of the insulating layer 20. By providing a groove 20g that is located around the pad 10 in a plan view and opens to the upper surface 20a side of the insulating layer 20, it becomes possible to reduce the area of the upper surface 10a of the pad 10 while ensuring compatibility with a conventional wiring board.

[0026] Also, when connecting the pad 10 and a mounting substrate such as a motherboard via solder, excess solder flows into the groove 20g from the upper surface 10a of the pad 10, so short - circuits between adjacent pads can be suppressed. Further, since the solder enters the groove 20g, the upper surface 10a and the side surface of the pad 10 are three - dimensionally joined to the solder, so the joining strength between the pad 10 and the solder can be improved. Also, in the wiring board 1, since the upper surface 10a of the pad 10 is at a position lower than the upper surface 20a of the insulating layer 20, the center of gravity of the entire solder is positioned closer to the center of the wiring board 1, so the stability of the connection between the pad 10 and the solder can be improved. In particular, the durability of the solder against forces applied in the horizontal direction (the direction parallel to the upper surface 10a) of the wiring board 1 can be significantly improved. These effects regarding joining with the solder become greater when the bottom surface of the groove 20g is at the same position as the lower surface of the pad 10 or at a position lower than the lower surface of the pad 10.

[0027] [Manufacturing method of wiring board] Next, a manufacturing method of the wiring board according to the first embodiment will be described. FIGS. 2 to 4 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. In this embodiment, a process of forming a single wiring board is shown, but it may also be a process of manufacturing a plurality of parts that will become the wiring board and then separating them into individual wiring boards.

[0028] First, in the process shown in FIG. 2(a), a support 300 with a flat upper surface is prepared. As the support 300, a metal plate, a metal foil, etc. can be used, but in this embodiment, an example of using a copper foil as the support 300 is shown. The thickness of the support 300 can be, for example, about 18 to 100 μm.

[0029] Next, a resist layer 400 (for example, a dry film resist, etc.) having an opening 400x at a predetermined position on the upper surface of the support 300 at a portion where the pad 10 is to be formed is formed. Then, by an electrolytic plating method or the like that uses the support 300 as a plating power supply layer, the sacrificial layer 11 and the pad 10 for external connection are sequentially laminated on the upper surface of the support 300 exposed within the opening 400x of the resist layer 400. Thereafter, the resist layer 400 is removed.

[0030] The pad 10 can have, for example, a laminated structure in which a metal layer 12 and a metal layer 13 are sequentially laminated from the sacrificial layer 11 side. The metal layer 12 itself may have a laminated structure. Here, as an example, the sacrificial layer 11 and the metal layer 13 are copper layers. Also, the metal layer 12 has a laminated structure of a gold layer, a nickel layer, and a palladium layer from the sacrificial layer 11 side. The thickness of each metal layer is as described above. Note that the sacrificial layer 11 is a metal layer that is finally removed by etching.

[0031] Next, in the process shown in FIG. 2(b), a semi-cured film-like epoxy resin or the like is laminated on the upper surface of the support 300 so that the lower surface is in contact with the upper surface of the support 300 and covers the side surface of the sacrificial layer 11 and the upper surface and side surface of the pad 10, and then cured to form the insulating layer 20. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and then cured to form the insulating layer 20. The thickness etc. of the insulating layer 20 are as described above.

[0032] Next, in the process shown in FIG. 3(a), a via hole 20x that penetrates the insulating layer 20 and exposes the upper surface of the pad 10 is formed in the insulating layer 20. The via hole 20x can be formed by, for example, a laser processing method using a CO2 laser or the like. Thereafter, a desmear treatment may be performed to remove resin residues adhering to the upper surface of the pad 10 exposed at the bottom of the via hole 20x.

[0033] Next, in the process shown in FIG. 3(b), a wiring layer 30 is formed on the insulating layer 20. The wiring layer 30 includes, for example, via wirings filled in the via holes 20x, via receiving pads formed on the insulating layer 20, and wiring patterns. The wiring layer 30 is electrically connected to the pad 10 exposed at the bottom of the via hole 20x. As the material of the wiring layer 30, for example, copper (Cu) or the like can be used. The wiring layer 30 can be formed using various wiring layer formation methods such as a semi-additive method or a subtractive method.

[0034] Next, in the process shown in FIG. 3(c), the same processes as those in FIGS. 2(b) to 3(b) are repeated to form an insulating layer 40 on the wiring layer 30, form a via hole 40x that exposes the upper surface of the via receiving pad of the wiring layer 30 in the insulating layer 40, and further form a wiring layer 50. The material and thickness of the insulating layer 40 can be the same as, for example, the material and thickness of the insulating layer 20. The material and thickness of the wiring layer 50 can be the same as, for example, the material and thickness of the wiring layer 30.

[0035] Next, in the process shown in FIG. 4(a), the support 300 is removed. The support 300 made of copper foil can be removed by, for example, wet etching using an aqueous hydrogen peroxide / sulfuric acid solution, an aqueous sodium persulfate solution, an aqueous ammonium persulfate solution, or the like. Since the sacrificial layer 11 is also a copper layer, the sacrificial layer 11 is removed simultaneously with the removal of the support 300.

[0036] On the other hand, since the re-surface of the metal layer 12 is a gold layer, it is not removed by the etching solution for removing the copper layer and serves as an etching stopper layer. The upper surface 10a of the pad 10 (the upper surface of the metal layer 12) is exposed at a position recessed from the upper surface 20a of the insulating layer 20. Note that Fig. 4(a) is drawn in a state where it is inverted vertically compared to Fig. 3(c) and the like. The same applies to Fig. 4(b) described later.

[0037] Next, in the process shown in Fig. 4(b), a groove 20g is formed in the insulating layer 20 so as to be located around the pad 10 in a plan view and open to the upper surface 20a side of the insulating layer 20. The groove 20g can be formed, for example, by a laser processing method. The groove 20g is formed in a ring shape such that, for example, in a plan view, the inner edge and the outer edge are circular with different diameters. The bottom surface of the groove 20g is formed, for example, at a position deeper than the lower surface of the pad 10 (the lower surface of the metal layer 13). However, the bottom surface of the groove 20g may be formed at the same position as the lower surface of the pad 10 (the lower surface of the metal layer 13), or may be formed at a position shallower than the lower surface of the pad 10 (the lower surface of the metal layer 13). The position of the bottom surface of the groove 20g can be adjusted by the power of the laser and is formed, for example, within a range of ±30 μm in the vertical direction with respect to the lower surface of the pad 10 (the lower surface of the metal layer 13). Thereby, the wiring board 1 is completed.

[0038] <Modification Example 1 of the First Embodiment> In Modification Example 1 of the first embodiment, an example in which the insulating layer covers the side surface of the pad is shown. In Modification Example 1 of the first embodiment, the description of the same components as those in the already described embodiment may be omitted.

[0039] Fig. 5 is a diagram illustrating a wiring board according to Modification Example 1 of the first embodiment, Fig. 5(a) is a partial plan view, and Fig. 5(b) is a partial cross-sectional view taken along line B-B of Fig. 5(a).

[0040] Referring to FIG. 5, the wiring board 1A is different from the wiring board 1 (see FIG. 1 etc.) in that the entire side surface of the pad 10 is covered with the insulating layer 20. That is, the insulating layer 20 has a ring-shaped covering portion 20r that covers the entire side surface of the pad 10 between the side surface of the pad 10 and the bottom surface of the groove 20g in a plan view. The width of the covering portion 20r is, for example, about 0.1 to 2 μm. The covering portion 20r can be formed by adjusting the position where the insulating layer 20 is irradiated with laser light when forming the groove 20g.

[0041] Thus, the side surface of the pad 10 does not necessarily have to be exposed from the insulating layer 20. Even with such a structure, it is possible to reduce the capacitance of the pad 10 by reducing the area of the upper surface 10a of the pad 10 while ensuring compatibility with the conventional wiring board.

[0042] 〈Second Embodiment〉 In the second embodiment, an example of a wiring board with a different layer structure of the pad is shown. In the second embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0043] FIG. 6 is a diagram illustrating a wiring board according to the second embodiment, FIG. 6(a) is a partial plan view, and FIG. 6(b) is a partial cross-sectional view taken along the line C-C of FIG. 6(a).

[0044] Referring to FIG. 6, the wiring board 2 is different from the wiring board 1 (see FIG. 1 etc.) in that the pad 10 has a single-layer structure. The pad 10 is, for example, a copper layer. The surface of the insulating layer 20 that covers the lower surface of the pad 10 has, for example, an extending portion 20s that extends in a ring shape between the side surface of the pad 10 and the bottom surface of the groove 20g in a plan view. The width of the extending portion 20s is, for example, about 0.5 to 3 μm. An organic film (not shown) is formed on the upper surface 10a of the pad 10. The organic film may cover the side surface of the pad 10. The organic film contains, for example, an azole compound or an imidazole compound.

[0045] The structures of the pad 10 and the insulating layer 20 shown in FIG. 6 can be formed, for example, as follows. First, in the process of FIG. 2(a), the sacrificial layer 11 is made of a copper layer and the metal layer 12 is made of a nickel layer. In this case, the metal layer 12 also serves as a sacrificial layer. Then, after performing the processes of FIGS. 2(b) to 3(c), in the process of FIG. 4(a), after removing the support 300 and the sacrificial layer 11, the sacrificial layer, i.e., the metal layer 12, is removed with an etching solution that can etch nickel but not copper.

[0046] Then, similar to FIG. 4(b), a groove 20g is formed. At this point, in a plan view, the inner edge of the groove 20g and the outer edge of the pad 10 are in the same position. Next, in order to remove the oxide film formed on the upper surface 10a and the side surface of the pad 10, the upper surface 10a and the side surface of the pad 10 are etched by about 2 to 3 μm. As a result, the surface covering the lower surface of the pad 10 of the insulating layer 20 has a structure with an extending portion 20s that extends in a ring shape between the side surface of the pad 10 and the bottom surface of the groove 20g in a plan view. Thereafter, an OSP (Organic Solderability Preservative) treatment is performed on the pad 10 to form an organic film.

[0047] Note that when the pad 10 has a single-layer structure and no organic film is formed, the etching process for removing the oxide film is unnecessary. In this case, in a plan view, the inner edge of the groove 20g and the outer edge of the pad 10 are in the same position, and the extending portion 20s is not formed.

[0048] Also, it is possible to combine the second embodiment and the first modification of the first embodiment. In this form, the side surface of the single-layer structure pad 10 is covered with the insulating layer 20. Therefore, when an organic film is formed, it is formed only on the upper surface 10a of the pad 10.

[0049] <Third Embodiment> The third embodiment shows an example of a wiring board having a plurality of pads. Note that in the third embodiment, the description of the same components as those in the embodiments already described may be omitted.

[0050] FIG. 7 is a diagram illustrating a wiring board according to the third embodiment, FIG. 7(a) is a partial plan view, and FIG. 7(b) is a partial cross-sectional view taken along line D-D of FIG. 7(a).

[0051] Referring to FIG. 7, the wiring board 3 has a plurality of pads 10. In FIG. 7, two adjacent pads 10 among the plurality of pads are shown. There are grooves 20g around each pad 10, and the grooves 20g around adjacent pads 10 communicate with each other.

[0052] Thus, the adjacent grooves 20g may communicate with each other. This is effective when the interval between adjacent pads 10 is narrow. The adjacent pads 10 may be pads having the same potential. For example, the adjacent pads 10 may be GND. In this case, there is no problem even if solder flows into the adjacent grooves 20g and the adjacent pads 10 are electrically connected. When the adjacent pads 10 have different potentials, for example, solder may be formed only on the upper surface 10a of each pad 10.

[0053] It is also possible to combine the third embodiment with Modification 1 of the first embodiment and / or the second embodiment.

[0054] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope described in the claims.

Description of Reference Numerals

[0055] 1, 1A, 2, 3 Wiring board 10 Pad 11 Sacrificial layer 12, 13 Metal layer 10a, 20a Upper surface 20, 40 Insulating layer 20g Groove 20r Coating portion 20s Extension portion 20x, 40x via hole 30, 50 Wiring layer 300 Support 400 resist layer 400x opening

Claims

1. having an external connection pad and an insulating layer, a part of the lower surface of the pad is covered by the insulating layer, the upper surface of the pad is located at a position lower than the upper surface of the insulating layer, the insulating layer is provided with a groove that is located around the pad in plan view and opens to the upper surface side of the insulating layer, a wiring board, wherein the bottom surface of the groove is located at a position lower than the lower surface of the pad.

2. The wiring board according to claim 1, wherein a side surface of the pad is exposed from the insulating layer.

3. The wiring board according to claim 1, wherein the insulating layer has a covering portion that covers the entire side surface of the pad between the side surface of the pad and the bottom surface of the groove in plan view.

4. the pad has a laminated structure, the lowermost layer in contact with the insulating layer is a copper layer, and the uppermost layer is a gold layer, the wiring board according to any one of claims 1 to 3.

5. the pad has a single-layer structure of a copper layer, an organic film is formed on a surface of the pad exposed from the insulating layer, the wiring board according to any one of claims 1 to 3.

6. The wiring board according to claim 5, wherein a surface of the insulating layer covering the lower surface of the pad has an extending portion that extends between the side surface of the pad and the bottom surface of the groove in plan view.

7. having a plurality of the pads, the groove is provided around each of the pads, the grooves around adjacent pads communicate with each other, the wiring board according to any one of claims 1 to 6.

8. having a wiring layer formed on the lower surface side of the insulating layer, the wiring layer includes via wiring that penetrates the insulating layer and contacts the lower surface of the pad, the wiring board according to any one of claims 1 to 7.

9. the lower surface of the pad is in direct contact with the insulating layer, a surface of the insulating layer in contact with the lower surface of the pad is located at a position higher than the bottom surface of the groove, the wiring board according to any one of claims 1 to 8.

10. a step of sequentially laminating a sacrificial layer and an external connection pad at a predetermined position on the upper surface of a support; a step of forming an insulating layer on the upper surface of the support, the first surface of which is in contact with the upper surface of the support and covers the sacrificial layer and the pad; a step of removing the support and the sacrificial layer; a step of forming a groove in the insulating layer that is located around the pad in plan view and opens to the first surface side of the insulating layer; and a method for manufacturing a wiring board, wherein in the step of forming the groove, the bottom surface of the groove is located at a position lower than the lower surface of the pad.

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