High-performance power integrated circuit semiconductor device

Abstract

To provide a high breakdown voltage large current power integrated circuit semiconductor device capable of achieving a structure of a large power capacity power integrated circuit semiconductor device which can mount a vertical type reverse conduction semiconductor element for high breakdown voltage large current output and a reduction in loss and chip area thereof, and capable of achieving high reliability by solving a snapback phenomenon specific to the reverse conduction semiconductor element and a specific on-voltage deterioration when using a SiC semiconductor.SOLUTION: A power integrated circuit semiconductor device chip 100 adopts a dielectric separation type integrated circuit structure, forms a considerable part of a thick insulation protection film under crossover wiring 116 as an embedded insulation film 106 under a front surface of a chip main body, and provides a front surface carrier concentration reduction magnetic field relaxation region (SCaDFRR121) just under the crossover wiring 116.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an integrated circuit semiconductor device, and more particularly to a high-performance power integrated circuit semiconductor device that is suitable for increasing the power capacity, i.e., increasing the breakdown voltage and increasing the current, and is also suitable for reducing the size and loss.

Background Art

[0002] In recent years, Si power integrated circuit semiconductor devices integrating output elements with a medium power capacity and a high breakdown voltage have been developed and commercialized for various applications. As this output element, Si-IGBTs and Si-MOSFETs, which are also used as main semiconductor devices as individual elements, are frequently used. However, although products of Si-IGBT individual elements are supplied up to a breakdown voltage of 6.5 kV·100 A class, as a power integrated circuit semiconductor device, due to various constraints, it only reaches a breakdown voltage of 0.7 kV and a current capacity of about 20 A, and an increase in power capacity is desired. On the other hand, Si-IGBTs expected as output elements of power integrated circuit semiconductor devices have been pursuing a reduction in on-resistance and a high turn-off speed for the purpose of high performance such as low loss in recent years as individual elements, and various devices have been made and remarkable progress has been made. As a typical example, there are Si reverse-conducting IGBTs of the prior art example 1 shown in FIG. 7 and the prior art example 2 shown in FIG. 8, which are being commercialized as power elements for electric vehicles, and are disclosed in Non-Patent Documents 1 and 2, respectively. A brief explanation will be given below. For the sake of simplicity in the explanation, an n-channel element will be taken as an example. In the collector short-circuit Si-IGBT (n-channel type) of the prior art example 1, the - drift layer is short-circuited to the collector electrode by an n+ short-circuit portion provided in the p+ collector layer, and at the time of turn-off, the - carriers remaining in the drift layer are eliminated through this n+ short-circuit portion to shorten the turn-off time and achieve a significant reduction in loss.

[0003] By the way, in the case of the Si reverse-conducting IGBT including the disclosed prior art example 1, in the Ice-Vce characteristics between the output characteristics, i.e., the collector-emitter voltage (hereinafter referred to as Vce) and the collector-emitter current (hereinafter referred to as Ice), a snap-back phenomenon occurs where the collector-emitter voltage just before turning on is larger than the collector-emitter voltage just after turning on, inducing various transient phenomena and deteriorating the reliability. The collector-emitter voltage just before turning on is hereinafter referred to as the snap-back voltage and denoted as Vsb, and the collector-emitter current at this Vsb is referred to as the snap-back current and denoted as Isb. The Si reverse-conducting IGBT (n-channel type) of the prior art example 2 A plurality of Reverse-conducting Si-IGBT cell composed of Reverse-conducting Si-IGBT region and It is composed of a pilot IGBT region composed of one pilot IGBT cell. By making the width of the collector of the pilot IGBT cell significantly larger than the width of the collector of the reverse-conducting IGBT cell, the lateral resistance of the buffer layer between the short-circuit portions is significantly increased , suppresses the snap-back phenomenon that occurs when turning on such that the pilot IGBT region turns on prior to the reverse-conducting IGBT region with a small Isb, suppresses malfunction due to transient voltage and transient current, and aims to achieve high reliability. Note that since the n-drift layers of these disclosed IGBTs are short-circuited to the collector electrode by n+ short-circuit portions and thus have no blocking ability against reverse voltage, they are collectively referred to as reverse-conducting IGBTs. Therefore, hereinafter, all are referred to as reverse-conducting IGBTs.

[0004] On the other hand, prior art example 3 by the inventors etc. discloses a dielectric isolation type integrated circuit of the 650V 25A class in which a control low-voltage withstand vertical element and a lateral element and a high-voltage withstand vertical IGBT for output are integrated on the same chip. In the control element portion, while suggesting that a drive circuit and a protection circuit can be integrated to achieve high-density and high-integration of high-performance functions, the output IGBT has a vertical structure to greatly reduce the drift resistance to achieve low on-resistance and large current capacity, thereby achieving a significant increase in current, low loss, and high performance of the power integrated circuit semiconductor device.

[0005] In recent years, the development of high-voltage withstand large-power and medium power semiconductor devices using wide-gap semiconductors such as SiC semiconductors has been promoted, and SiC-MOSFET individual elements and SiC-IGBT Significant performance improvements have been made to semiconductor devices represented by individual elements. For example, in the prior art In Example 4, a 6.5 kV-class SiC-MOSFET individual element is disclosed. In this element a SiC Schottky diode is incorporated as a flywheel diode (hereinafter described as FWD) that is essential for applications such as inverters, and the on-voltage degradation peculiar to SiC semiconductor devices is suppressed to achieve high performance and high reliability. However, wide-gap semiconductors such as SiC semiconductors have many various problems in addition to the crystal quality and large-area fabrication of semiconductor chips, and are at a stage where the development of basic element circuits has just begun. There are no examples of development or practical applications of full-fledged power integrated circuit semiconductor devices integrating control circuits and high-voltage large-current output elements.

Prior Art Documents

Non-Patent Documents

[0006]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0007] As described above, as a power integrated circuit semiconductor device, due to various technical problems, the breakdown voltage is 0.7 kV and the current capacity is limited to about 25 A or less. In order to meet various new needs, increasing the power capacity is an important issue. To increase the power capacity, both increasing the breakdown voltage and increasing the current must be achieved. Moreover, it must be achieved with a chip size having reasonable economy (for example, about 20 mm x 20 mm or less). As described above, as an output element of a power integrated circuit semiconductor device, an IGBT individual element or a MOSFET individual element expected, in recent years, for the purpose of high performance such as low loss, low on-resistance and fast turn-on / off speed are pursued, and reverse-conducting IGBTs and reverse-conducting MOSFETs are attracting attention as suitable elements. In this specification, the reverse-conducting semiconductor element is construed more narrowly than the general term in

[0003] , and an element in which the high-voltage pn main junction in the element functions as an FWD indispensable for an inverter etc. during reverse bias is defined as a reverse-conducting semiconductor element. In this case, since the FWD is inherent in the element and does not need to be newly introduced or formed separately, the chip occupation area of the output element can be reduced to almost half, and cost reduction can be expected by significantly reducing the area of the integrated circuit semiconductor device chip. However, the reverse-conducting semiconductor element of this definition has various technical problems described below, and there is no example that has been mounted on a power integrated circuit semiconductor device and put into practical use. In various industrial fields represented by the mobile device field such as EVs, small, light and low loss are required. Therefore, there is a need for a semiconductor device that can meet these requirements.

[0008] In various industrial fields represented by the mobile device field such as EVs, small, light and low loss Moreover, the demand for semiconductor devices with a voltage of 1 kV and a current of 10 A or more at low cost is strong. Currently, semiconductor modules are used to meet this demand, but power integrated circuit semiconductor devices are expected to achieve further significant miniaturization, weight reduction, lower losses, and lower costs. Therefore, it is an important first task to solve the technical problems of the prior art and devise a structure that can mount reverse-conducting semiconductor elements such as reverse-conducting IGBTs and reverse-conducting MOSFETs, which are suitable for lower losses and higher performance (e.g., high reliability, etc.), and to realize a power integrated circuit semiconductor device with a high breakdown voltage of 1 kV or more and a large current capacity.

[0009] In Prior Art Example 3, the output IGBT of the dielectric integrated circuit semiconductor device is of a vertical structure to significantly reduce the drift resistance, and it has been successful in reducing the on-resistance and increasing the large current capacity. However, reverse-conducting semiconductor elements are not assumed and are not mentioned at all. In the structure of Prior Art Example 3, it is difficult to provide a short-circuit portion on the collector electrode side on the back surface of the element like the individual elements of Prior Art Examples 1 and 2 because a thick p+ collector is used. Therefore, it is not possible to achieve low losses based on a significant reduction in switching losses due to shortening the turn-off time by mounting a reverse-conducting semiconductor element, and it is also not possible to achieve the FWD function using the junction of the p-body inherent in the IGBT. Therefore, it is necessary to newly incorporate it inside the chip, which causes a significant increase in the chip area, or to externally attach it. Enabling the mounting of a reverse-conducting semiconductor element with a small occupied area and low losses is the second task to be solved in power integrated circuit semiconductor devices.

[0010] By the way, since the turn-on time of a reverse-conducting semiconductor device such as a reverse-conducting IGBT is short from just before to just after turning on, when the snap-back phenomenon occurs, a steep voltage change (hereinafter referred to as dV / dt) and a steep current change (hereinafter referred to as dI / dt) occur during turn-on. As a result, due to the parasitic capacitance existing in the circuit, a steep spike current (C· ​​ dv / dt) and a sharp overshoot voltage (L·dI / dt) caused by the parasitic reactor also occur, triggering a large overshoot phenomenon. Therefore, using a reverse-conducting semiconductor device such as this reverse-conducting IGBT in a circuit causes a large disturbance, resulting in malfunction or, in some cases, damage to the device or circuit, significantly impairing reliability. Therefore, suppressing or eliminating the snapback phenomenon is an extremely serious third issue in power integrated circuit semiconductor devices that integrate various circuits on a narrow chip area. Also, in the Si reverse-conducting IGBT of the prior art example 2, a pilot IGBT region is provided adjacent to the reverse-conducting IGBT region composed of a large number of reverse-conducting IGBT cells. By making the p+ collector width of the pilot IGBT region much larger than the p+ collector width of the IGBT cells in the reverse-conducting IGBT region, the lateral resistance of the buffer layer on the p+ collector is made very large. Therefore, the pilot IGBT region is first turned on with a small Isb. This suppresses the snapback phenomenon in the pilot IGBT region. However, in the case of this prior art example 2, the area of the pilot IGBT region in the entire IGBT chip area becomes quite large. For example, in the case of the prior art example 2, reading from the data, the p+ collector width of the Si reverse-conducting IGBT standard cell with a 3.3 kV design is 180 micrometers, while by making the p+ collector width of the pilot IGBT about 3.6 times, i.e., 650 micrometers or more, Vsb is made about 0.7 V, which is the built-in voltage, to eliminate the snapback phenomenon. The p+ collector width of the reverse-conducting IGBT standard cell is...

[0011] Moreover, in the Si reverse-conducting IGBT of the prior art example 2, a pilot IGBT region is provided adjacent to the reverse-conducting IGBT region composed of a large number of reverse-conducting IGBT cells. The p+ collector width of the pilot IGBT region is made much larger than the p+ collector width of the IGBT cells in the reverse-conducting IGBT region, thereby making the lateral resistance of the buffer layer on the p+ collector very large. Therefore, the pilot IGBT region is first turned on with a small Isb. This suppresses the snapback phenomenon in the pilot IGBT region. However, in the case of this prior art example 2, the area of the pilot IGBT region in the entire IGBT chip area becomes quite large. For example, in the case of the prior art example 2, reading from the data, the p+ collector width of the Si reverse-conducting IGBT standard cell with a 3.3 kV design is 180 micrometers, while the p+ collector width of the pilot IGBT is made about 3.6 times, i.e., 650 micrometers or more, thereby making Vsb about 0.7 V, which is the built-in voltage, to eliminate the snapback phenomenon. The p+ collector width of the reverse-conducting IGBT standard cell is... is... Making it much smaller and finer reduces the lateral resistance of the standard cell, so a larger current is required to obtain the built-in voltage Vbi of the collector junction. Therefore, the p+ collector width of the pilot IGBT also needs to be increased accordingly. As a result, the snap-back phenomenon is eliminated, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved. This results in the elimination of the snap-back phenomenon, but the area of the reverse-conducting IGBT standard cell region in the entire IGBT chip of a given area decreases, so the number of standard cells integrated in a given chip decreases, the on-resistance increases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. From the perspective of economic efficiency such as yield, with the current situation where the chip size of the device is set to about 20 mm x 20 mm or less, eliminating the snap-back phenomenon of the reverse-conducting semiconductor device with a small occupied area is an important issue in the power integrated circuit semiconductor device and is the fourth problem to be solved.

[0012] In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the prior art example 4, a SiC Schottky diode is incorporated as an FWD in the SiC-MOSFET, and it has been successful in suppressing the on-voltage degradation and improving the reliability, but the dedicated chip area increases significantly by about twice. When the temperature becomes higher or the breakdown voltage becomes higher, the drift resistance increases significantly, so a further significant increase in the area of the SiC Schottky diode is inevitable to achieve low loss. Also, like the reverse-conducting IGBT, when an excessive current arrives due to an accident or an excessive current is supplied, the IGBT cannot be operated to increase the current tolerance due to the low on-resistance caused by conductivity modulation. Therefore, in order to avoid damage to the device, it is necessary to further increase the dedicated chip areas of the SiC-MOSFET and the SiC-FWD corresponding to the assumed overcurrent. In the area of an integrated circuit semiconductor device chip currently restricted to about 20 mm x 20 mm, the increase in the exclusive area due to the above-mentioned FWD is an important issue and is the fifth problem to be solved.

[0013] In order to solve the problems of the prior art and increase the power capacity, the present invention aims to provide a structure of a power integrated circuit semiconductor device capable of mounting a constituent element with a large power capacity, that is, a constituent element with a high breakdown voltage and / or a large current capacity, particularly a reverse-conducting semiconductor element. Also, it aims to provide a power integrated circuit semiconductor device having a structure that can reduce the occupied area or loss of the constituent element with a large power capacity to be mounted. Further, it aims to provide a high-performance reverse-conducting power integrated circuit semiconductor device capable of reducing the chip size by achieving the FWD function without separately integrating the FWD. Furthermore, it aims to provide a highly reliable power integrated circuit semiconductor device that suppresses or eliminates the snap-back phenomenon of the output high-performance reverse-conducting power integrated circuit semiconductor device and can eliminate this in a smaller occupied area. Also, it aims to provide a highly reliable high-performance reverse-conducting power integrated circuit semiconductor device capable of eliminating or suppressing the on-voltage degradation by using a wide-gap semiconductor such as SiC.

Means for Solving the Problems

[0014] Solving Means

[0015] Prior to the description, Define some terms. In an integrated circuit semiconductor device, The semiconductor part obtained by removing electrodes, wirings, insulating protective films, etc. from an integrated circuit semiconductor device chip is defined as the chip body and described by this name. Also, the integrated circuit constituent elements are connected by wiring via a surface insulation protection film on the semiconductor chip body with other integrated circuit constituent elements, and a wiring portion that crosses over the separation region, the dielectric insulation separation film, and the inclined channel stopper between the constituent elements exposed on the surface within the semiconductor chip body is defined as a crossover wiring. The chip body is composed of a device integration substrate and a device support substrate stacked thereunder. The upper part of the chip body, which is composed of separation regions where single-crystalline islands formed with devices are spread via a dielectric isolation film, is defined as the device integration substrate. The lower part of the chip body that supports this substrate and all or part of which functions as a conductive path and a heat dissipation path for the devices is defined as the device support substrate, and these names will be used hereinafter for description. Also, in a semiconductor device integrated in a single crystal island, an element in which both the input electrode and the output electrode are formed on one main surface of the chip, that is, on surface A on the opposite side of the element support substrate on the above-mentioned element integration substrate, is defined as a lateral semiconductor element. Also, an element in which either one of the input electrode and the output electrode is formed on surface A of the element integration substrate and the other electrode is formed on the other main surface of the chip, that is, on surface B on the opposite side of the element integration substrate on the above-mentioned element support substrate, is defined as a vertical semiconductor element. In the following, for the sake of avoiding complexity and facilitating understanding, a power integrated circuit semiconductor device in which an n-channel type IGBT and an n-channel type MOSFET are used as large-power component elements (for example, output elements) will be described.

[0016] In order to solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device of is a dielectric isolation type integrated circuit semiconductor device, and its semiconductor chip body is formed in a separation region with single-crystalline islands spread via a dielectric isolation film. The side surface of the single-crystalline island has a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body. In the integrated circuit semiconductor device where the integrated circuit component elements in the single-crystalline island are connected by wiring via a surface insulating protection film to the integrated circuit component elements in other single-crystalline islands, the large-power component elements are provided with a novel surface carrier density decrease electric field reduction region (Surface Carrier density Decrease electric Field Reduction Region, abbreviated as SCaDFRR, pronounced as skad FRR) on the surface of the inclined channel stopper layer under the crossover wiring. This is the feature.

[0017] In order to solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device of A thick buried insulating protection film is provided between a component with a large power capacity and the surface of the chip body, between the surface carrier concentration reduction electric field relaxation region SCaDFRR on the surface of the inclined channel stopper layer, and a thick buried insulating protection film is provided, and the surface insulating protection film is provided on the surface of the chip body in contact with the thick buried insulating protection film.

[0018] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention is In a dielectric isolation type integrated circuit semiconductor device, the semiconductor chip body is composed of single crystal islands laid out via a dielectric isolation film in a separation region, the side surface of the single crystal island has a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit constituent elements in the single crystal island are connected by wiring via a surface insulating protective film on the semiconductor chip body to the integrated circuit constituent elements in other single crystal islands. It includes a lateral IGBT in a specific single crystal island as an integrated circuit constituent element, a buffer layer is provided in contact with the collector at least on the bottom surface of the collector of the lateral IGBT, and a part of the buffer layer is exposed on the semiconductor chip surface and connected to the collector electrode of the lateral IGBT to be short-circuited with the collector.

[0019] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention is In a dielectric isolation type integrated circuit semiconductor device, the semiconductor chip body is composed of single crystal islands laid out via a dielectric isolation film in a separation region, the side surface of the single crystal island has a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit constituent elements in the single crystal island are connected by wiring via a surface insulating protective film on the semiconductor chip body to the integrated circuit constituent elements in other single crystal islands. The semiconductor chip body of the dielectric isolation type integrated circuit semiconductor device is configured by laminating and bonding an element integrated substrate in which single crystal islands including the integrated circuit constituent elements are spread in the separation region, and an element support substrate having both a support function and a conductive path function of the element integrated substrate. The element integrated substrate is provided with a predetermined single crystal island in which the dielectric isolation film at the bottom of the single crystal island is removed in order to integrate vertical semiconductor elements. On the surface of the predetermined single crystal island The main functional part of the vertical semiconductor element connected to the first main electrode and the control electrode is formed between the island surface of the predetermined single crystal island and the buffer at the bottom of the island. The drain or collector of the vertical semiconductor element is connected to the buffer and formed to be exposed on the bonding surface of the element integrated substrate and bonded to the element support substrate. The vertical semiconductor element is configured by connecting the second main electrode on the back surface of the drain or collector of the element support substrate through the element support substrate. It is characterized by the above. The main functional part is a name that collectively indicates the remaining structural factors excluding the drain, collector, or short-circuit part from the structural factors in the chip body constituting the element.

[0020] In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention is In

[0019] , The vertical semiconductor element is a bipolar element, The first main electrode is formed on the surface of the predetermined single crystal island where the main functional part is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body. The third main electrode is formed on the surface of the separation region adjacent to the predetermined single crystal island through the dielectric isolation film, and a part of the separation region is connected to the buffer at the bottom of the island of the predetermined single crystal island and the collector. Of the main functional part The drift layer and the separation region of the element integrated substrate have the same polarity, but the element support substrate has the opposite polarity By electrically connecting the second main electrode and the third main electrode, the element between the first main electrode, the second main electrode, and the third main electrode constitutes a vertical reverse conduction semiconductor element. It is characterized by the above. In order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention is In

[0019] , The vertical semiconductor element is a unipolar element, The first main electrode is formed on the surface of the predetermined single crystal island where the main functional part is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body. The third main electrode is formed on the surface of the separation region adjacent to the predetermined single crystal island through the dielectric isolation film, and a part of the separation region is connected to the buffer at the bottom of the island of the predetermined single crystal island and the drain. Of the main functional part The drift layer and the element support substrate have the same polarity, but Separation region of the element integrated substrate has the opposite polarity Further, when the second main electrode and the third main electrode are electrically connected, the element between the first main electrode, the second main electrode, and the third main electrode constitutes a vertical reverse-conducting semiconductor element. It is characterized by the above.

[0021] To solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is characterized in that the reverse-conducting semiconductor element has a single buffer layer or a multi-buffer layer composed of two or more layers.

[0022] To solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention has a structure in which the bonding surfaces of the semiconductor chip body having a bonding surface with a mixed polycrystalline surface and single crystal surface and the element support substrate having a bonding surface with only a single crystal surface or only a polycrystalline surface are directly bonded to each other. Hereinafter, in order to clarify the difference from the bonding structure in various conventional dielectric isolation type power integrated circuit semiconductor devices and avoid confusion, when the element integration substrate has a bonding surface with a mixed polycrystalline surface and single crystal surface and the above-mentioned element support substrate has a bonding surface with only a single crystal surface, it is abbreviated as SP&S-DBS, which is Single and Poly mixed crystal surface & Single crystal surface Direct Bonding Structure. Also, when the element integration substrate is the same and the above-mentioned element support substrate has a bonding surface with only a polycrystalline surface, it is abbreviated as SP&P-DBS, which is Single and Poly mixed crystal surface & Poly crystal surface Direct Bonding Structure.

[0023] To solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is characterized in that the semiconductor device is composed of a SiC semiconductor. Also, in order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention The surface of the single-crystal island of the power integrated circuit semiconductor device composed of SiC semiconductor is formed using the C plane, i.e., the crystal plane of (000-1) plane, the side surface is formed of {0-33-8} plane, and the bottom surface of the single-crystal island is formed of Si plane, i.e., (0001) plane has a single crystal island crystal plane structure It is characterized by the above.

[0024] In order to solve the above problems and achieve the object of the present invention, the power integrated circuit semiconductor device according to the present invention is a dielectric isolation type integrated circuit semiconductor device, the semiconductor chip body of which is formed by laying single-crystal islands via a dielectric isolation film in a separation region, the side surface of the single-crystal island having a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components in the single-crystal island being connected to the integrated circuit components in other single-crystal islands and the wiring provided on the surface insulation protection film on the surface of the semiconductor chip body. In the integrated circuit semiconductor device the vertical semiconductor element is the surface carrier concentration reduction electric field relaxation region (SCaDFRR) has and a structure (SP&S-DBS or SP&P-DBS) in which the element integrated substrate having a mixed attachment surface of a polycrystalline surface and a single-crystalline surface is bonded to the element support substrate having an attachment surface of only a single-crystalline surface or only a polycrystalline surface also has It is characterized by the above.

[0025] Also, in order to solve the above problems and achieve the object of the present invention, a power integrated circuit semiconductor device according to the present invention a dielectric isolation type integrated circuit semiconductor device, the semiconductor chip body of which is formed by laying single-crystal islands via a dielectric isolation film in a separation region, the side surface of the single-crystal island having a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components in the single-crystal island being connected to the integrated circuit components in other single-crystal islands via the surface insulation protection film on the semiconductor chip body by wiring. In the integrated circuit semiconductor device built-in with an inverter circuit is characterized in that the upper arm of the inverter circuit is configured to include the vertical semiconductor element or the vertical reverse-conducting semiconductor element described in [Claim 4] to [Claim 11].

[0026] In the above-described invention, the power integrated circuit semiconductor device according to the present invention is provided with a novel surface electric field relaxation region (SCaDFRR) on the surface of the inclined channel stopper layer under the wiring across a constituent element having a large power capacitance, whereby high breakdown voltage can be achieved. Also, regardless of the thick element support substrate, the first main electrode is formed on the main surface, and the second main electrode and the third main electrode are electrically connected to realize a reverse-conducting semiconductor element having a vertical structure for output between the first main electrode, the second main electrode, and the third main electrode. As a result, compared with the case where an IGBT is configured in a horizontal structure within a dielectric isolation island, the drift resistance can be significantly reduced, and low on-resistance and large current capacity can be achieved. Therefore, by increasing the breakdown voltage and the current capacity, the capacity of the power integrated circuit semiconductor device can be increased.

[0027] In order to realize a high breakdown voltage of a power integrated circuit semiconductor device, it is necessary to install an electric field relaxation region to suppress surface dielectric breakdown of the semiconductor chip body under the crossover wiring and relax the surface peak electric field, and also to increase the thickness of the insulating protection film under the crossover wiring. When the breakdown voltage is high, only installing the electric field relaxation region will make the field region quite large, so the insulating protection film is also thickened, but this thickness will become very large. Although it depends on the composition of the electric field relaxation region and the insulating film to be installed, for example, estimating from Prior Art Document 3 using an electric field relaxation region called FRR and a silicon oxide film (hereinafter referred to as SiO2 film), when the breakdown voltage is 1.2 kV, an insulating protection film thickness of 12 μm or more is required, making it difficult to form. Also, when wiring and connecting to the wiring on the thin insulating protection film of the element inside the insulating isolation island, a large step is generated, and disconnection of the wiring occurs at this step portion. To avoid this, the insulating protection film is made stepped inside the element, and the step at each step is usually about 1 μm to 2 μm. However, for example, in the case of a high breakdown voltage where the insulating protection film thickness is 12 μm or more, it is necessary to increase the number of steps. As a result, the size of most of the constituent elements of the integrated circuit semiconductor device becomes large, and the chip becomes enlarged. For these reasons, there are no examples of high breakdown voltage integrated circuit semiconductor devices of 650 V or more, which has become a major obstacle to commercialization.

[0028] In the present invention, a novel surface carrier concentration reduction electric field relaxation region (SCaDFRR) is provided on the surface of the inclined channel stopper under the crossover wiring for a component with a large power capacitance, achieving a higher breakdown voltage. In Prior Art Document 3, an electric field relaxation region (FRR) was introduced on the surface of the drift region under the crossover wiring to increase the carrier concentration on the surface of the drift region and achieve a higher breakdown voltage. However, the entire surface of the inclined channel stopper with a high concentration also has an even higher concentration. As a result, the electric field concentration at the end of the drift region side on the surface of the inclined channel stopper becomes higher, and the breakdown voltage, that is, the maximum electric field at this electric field concentration part, is limited to a low value where it reaches the breakdown electric field strength of the semiconductor material. In the present invention, a novel SCaDFRR with a lower carrier concentration is provided on the surface of the drift region side of the inclined channel stopper under the crossover wiring. As a result, the low-concentration SCaDFRR region is depleted due to the potential difference with the crossover wiring, and the position where the surface electric field becomes maximum shifts to the vicinity of the boundary between the SCaDFRR and the surface of the inclined channel stopper that is not depleted. As a result, electric field relaxation can be achieved by the voltage sharing of the SCaDFRR, and the breakdown voltage can be increased. Therefore, it is preferable that the SCaDFRR is longer within the range where the surface of the inclined channel stopper maintains its function as a channel stopper. Since the SCaDFRR region is provided within the inclined channel stopper, there is a characteristic that the element size does not increase. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist. Since the breakdown voltage can be increased by the SCaDFRR in this way, when maintaining the breakdown voltage, the thickness of the insulation protection film under the crossover wiring can be reduced. Also, within the range of the maximum electric field reduction effect by the SCaDFRR, it is possible to reduce the thickness of the insulation protection film while increasing the breakdown voltage. As long as it is provided on the surface of the drift region side adjacent to the inclined channel stopper under the crossover wiring, since the FRR can effectively exhibit the electric field relaxation effect, it is also preferable to make the FRR and the SCaDFRR coexist.

[0029] As described in the above

[0027] , in order to achieve a higher breakdown voltage in the power integrated circuit semiconductor device it is necessary to thicken the insulating protection film under this crossover wiring to relax the electric field strength on the semiconductor element surface and make the maximum electric field strength equal to or less than the breakdown electric field strength of the semiconductor material. When the breakdown voltage is high, the thickness of this insulating protection film becomes very large. Therefore, in order to avoid disconnection of the wiring, the insulating protection film is made into a stepped shape to reduce the step difference at each step. As a result, it is necessary to increase the number of steps, and the sizes of most of the constituent elements of the integrated circuit semiconductor device become large, and the chip becomes enlarged, which is not practical. In the present invention, in order to solve this problem, a thick buried insulating film is provided under the surface of the chip body, the SCaDFRR is provided directly below it, and an insulating protection film is also separately provided on the surface of the chip body on the thick buried insulating film. For example, when the semiconductor material is Si and FRR is used and an SiO2 film is used as the insulating film, when the breakdown voltage is 1.2 kV, an insulating film thickness of 12 μm or more is required. Assuming that the insulating film thickness reduction effect of the above SCaDFRR is 2 μm, and when the thickness of the insulating protection film on the surface of the chip body is set to a realistic thickness of about 6 μm, this can be solved by making the thickness of the buried insulating film under the main surface 4 μm or more.

[0030] In the present invention, for a constituent element having a large power capacitance, the main functional part is formed on the single crystal island where the dielectric insulation separation film at the bottom of the single crystal island is removed and is configured as a vertical semiconductor element by connecting the main functional part to the conductive path of the element support substrate via a drain or a collector. As a result, compared with the horizontal semiconductor element of the conventional dielectric isolation type power integrated circuit semiconductor device, since the drain or the collector is formed below the main functional part instead of on the element surface, the drift thickness can be made small and the drift resistance can be significantly reduced to achieve low loss, and the current capacitance can be significantly increased without increasing the element area, enabling a large power capacitance. or the collector is formed below the main functional part instead of on the element surface, the drift thickness can be made small and the drift resistance can be significantly reduced to achieve low loss, and the current capacitance can be significantly increased without increasing the element area, enabling a large power capacitance. and the current capacitance can be significantly increased without increasing the element area, enabling a large power capacitance.

[0031] In the present invention, a first main electrode is formed on the surface of a single crystal island where the main functional part of the component with a large power capacitance is formed, and a second main electrode is formed on the back surface of the semiconductor chip body. A third main electrode is formed on the surface of a separation region that is sandwiched by a dielectric isolation film and adjacent to the single crystal island where the main functional part is formed. Since the second main electrode and the third main electrode are electrically connected, the element between the first main electrode, the second main electrode, and the third main electrode can be easily realized as a vertical structure reverse conduction semiconductor element.

[0032] In the present invention, when the vertical semiconductor element of the power integrated circuit semiconductor device is a bipolar element, the drift layer and the separation region of the element integration substrate are of the same polarity, and the element support substrate is of the opposite polarity so that a reverse conduction vertical bipolar semiconductor element such as a reverse conduction vertical IGBT can be easily provided. For example, in the case of this bipolar element, the drift layer and the separation region of the element integration substrate are of the same n-type, but the element support substrate is of the opposite polarity p-type. As a result, a vertical IGBT can be configured between the first main electrode and the second main electrodes, and the short circuit part can be configured between the first main electrode and the third main electrode and the second main electrode and the third main electrode are electrically connected, so a vertical reverse conduction IGBT can be realized between the first main electrode, the second main electrode, and the third main electrodes. As a result, due to the small on-resistance of the vertical element, a large current capacity and low loss can be achieved, and at the same time, low loss can be achieved due to the reduction of the turn-off time of the reverse conduction IGBT. Also, during reverse bias, the first main electrode and the third main electrode can be operated as an FWD composed of a p-body junction so that there is no need to separately integrate an FWD, and significant chip miniaturization can be achieved. In the structure of the prior art example 3, since it is connected to the collector electrode corresponding to the second main electrode through a thick p-collector layer, it was difficult to provide an n+ short circuit part, but in the present invention, by configuring the polarities of the element support substrate and the element integration substrate in this way, it is possible to accommodate The vertical IGBT and the short-circuit portion can be easily provided independently, and as a result, a vertical reverse-conducting IGBT structure can be provided. As a result, low loss and large current capacity due to verticalization, and further low loss can be achieved by significantly reducing the switching loss by shortening the turn-off time of the reverse-conducting semiconductor device.

[0033] In the present invention, when the vertical semiconductor element of the power integrated circuit semiconductor device is a unipolar element, the drift layer and the element support substrate have the same polarity, and the separation region of the element integration substrate has the opposite polarity, so that a reverse-conducting vertical unipolar semiconductor element can be easily provided. For example, when this vertical semiconductor element is a unipolar element such as a MOSFET, the drift layer and the element support substrate have the same n-type polarity, and the separation region of the element integration substrate has the opposite p-type polarity. As a result, a vertical MOSFET can be formed between the first main electrode and the second main electrode, and an IGBT can be formed between the first main electrode and the third main electrode. Since the second main electrode and the third main electrode are electrically connected, the first main electrode, the second main electrode, and the third main electrode function as a reverse-conducting IGBT during forward bias. Since there is no pn junction in the current path of the vertical MOSFET, a large current capacity and low loss due to a small on-resistance of the vertical structure can be achieved at a low applied voltage. On the other hand, at an applied voltage above the built-in voltage, the IGBT can also operate in parallel. As a result, low loss due to conductivity modulation of the IGBT and small temperature dependence of the on-resistance are effective, and an excessive current can be processed particularly at high temperatures. At this time, since a part of the vertical MOSFET functions as an n+ short-circuit portion, the IGBT functions as a reverse-conducting IGBT, and low loss can be achieved by significantly reducing the switching loss by shortening the turn-off time. Also, during reverse bias, the portion between the first main electrode and the second main electrode can be operated as a FWD composed of a p-body junction, eliminating the need to provide a separate FWD and achieving significant chip miniaturization.

[0034] In the present invention, the reverse-conducting semiconductor element of the power integrated circuit semiconductor device has a single-layer buffer layer or a multi-buffer layer having two or more layers. In the case of a single-layer configuration, by appropriately reducing the buffer layer thickness and the impurity concentration to a low level, even with a predetermined small p-collector layer width, the lateral resistance of the buffer layer above it is maximized so that even with a small Isb, Vsb is equal to or less than the built-in voltage Vbi of the p+-collector junction, eliminating the snap-back phenomenon. As a result, the chip area of the power integrated circuit semiconductor device is reduced with a reverse-conducting semiconductor element having a small p+-collector width, and the snap-back phenomenon is suppressed or eliminated, achieving high reliability. In the case of a multi-buffer layer having two or more layers, only the final layer is not completely depleted at the built-in voltage Vbi of the p+-collector junction, and the other layers are all set to be completely depleted. As a result, the buffer layer through which Isb flows can be further made highly resistive, the p+-collector width can be further reduced, the area of the reverse-conducting semiconductor element, and thus the chip area of the power integrated circuit semiconductor device can be further reduced, and the snap-back phenomenon can be further suppressed or eliminated, achieving high reliability.

[0035] In the present invention, for the lateral An integrated circuit semiconductor device composed only of semiconductor elements type, a semiconductor chip formation wafer is formed by bonding a wafer for an element integrated substrate having a polycrystalline attachment surface and a wafer for an element support substrate having a single-crystalline attachment surface. As a pretreatment before attaching the wafer for the element integrated substrate to the wafer for the element integrated substrate, for example, NH at 70 ° C 4 OH and H 2 O 2 Treat with a solution, rinse with ultrapure water, spin dry, then set a single crystal Si wafer for the element support substrate on this wafer for the element integrated substrate and perform a high-temperature heat treatment in an oxidizing atmosphere to bond them. Compared with the case where both wafers are integrated by conventional epitaxial growth, For forming the support substrate the high-temperature and long-time epitaxial growth process and the post-growth grinding and polishing processes for flattening large curvatures can be omitted, achieving a significant simplification of the power integrated circuit semiconductor device manufacturing process and a considerable cost reduction. On the other hand, for the vertical of an integrated circuit semiconductor device including semiconductor elements type formation, the insulating isolation oxide film is removed to form the vertical in the region for forming semiconductor elements ​A wafer for an element integrated substrate having an attachment surface where a single crystal surface and a polycrystalline surface formed on an insulating isolation oxide film are mixed, and a wafer for an element support substrate having an attachment surface with only a single crystal surface are attached to realize a wafer of a novel bonding structure (SP&S-DBS described in

[0022] ) for forming a semiconductor chip. The bonding surface between the single crystal planes has a higher bonding strength than the bonding surface between the single crystal plane and the polycrystal plane, In the bonding of single crystal surfaces, voids are generated at the bonding boundary, and the bonding strength to reduce tends to be affected. Therefore, efforts have been made in the bonding temperature, bonding pressure, bonding atmosphere gas, and the pretreatment process and its materials to overcome this. For example, As a pretreatment process, a wafer for an element integrated substrate having a bonding surface where a polished single crystal plane and a polycrystal plane are mixed and a wafer for an element support substrate having a bonding surface of only a single crystal plane Before bonding both wafers, perform heat treatment in a reducing atmosphere such as hydrogen annealing to bond hydrogen atoms to the dangling bonds of Si atoms on the bonding surface. Then, the bonding process of both wafers is performed in an oxidizing atmosphere, and these hydrogen atoms are combined with oxygen and removed as H 2 O, and at the same time, Si atoms on the bonding surfaces of both wafers are bonded together. In order to increase the bonding strength by this bonding, the bonding temperature and the bonding pressure applied to the wafer are as described at the beginning of this paragraph Compared with the bonding of a polycrystalline attachment surface and a single crystal attachment surface, there are more are increased. As a result, compared with the case of only the above horizontal semiconductor element, the bonding strength is high bonding parts between single crystal surfaces. of this part Since the bonding strength is improved, the bonding strength of the entire bonded wafer is improved. Therefore, in the subsequent element manufacturing process, due to partial peeling, etc. damage can be further reduced, and an improvement in the yield is expected.

[0036] The power integrated circuit semiconductor device according to the present invention is, in the above-described invention, configured with the integrated circuit semiconductor device made of a wide-gap semiconductor such as a SiC semiconductor. As a result, a semiconductor device with further high breakdown voltage, low loss, small chip size, and high heat resistance that far exceeds Si semiconductors can be realized. Also, the dielectric isolation type power integrated circuit semiconductor device has extremely low leakage current even at high temperatures compared to the pn isolation type power integrated circuit semiconductor device, so it is suitable for achieving high breakdown voltage and high heat resistance. Moreover, compared with element isolation by pn junctions, the width of the separation region between elements can be significantly narrowed, so it is also suitable for achieving miniaturization and low loss of the chip. Therefore, the SiC dielectric isolation type power integrated circuit semiconductor device configured by combining the two can be said to be an ideal power semiconductor device. In the case of an integrated circuit semiconductor device having an SP&S-DBS wafer structure composed of a SiC semiconductor, for example, as an example, as described in

[0035] , in order to increase the bonding strength A wafer for an element integrated substrate having an attachment surface with a mixed single crystal surface and polycrystal surface polished as a pretreatment process, and a wafer for an element support substrate having an attachment surface with only a single crystal surface Before pasting the two wafers, heat treatment is performed on both wafers in a reducing atmosphere such as hydrogen annealing to bond hydrogen atoms to the dangling bonds of Si atoms and carbon atoms (hereinafter referred to as C atoms) on the attachment surface. The subsequent pasting process is performed in an oxidizing atmosphere to bond this hydrogen atom with oxygen and remove it as H 2 O, and at the same time bond Si atoms and C atoms. In order to increase the bonding strength due to this bond, the pasting temperature and the pasting pressure applied to the wafer are set higher than those in the case of Si described in

[0035] . For the finish polishing of both wafers prior to this pretreatment, it is effective to apply a catalyst surface reference etching method (commonly known as the CARE method) having ultra-high-precision polishing accuracy at the atomic level. In addition, the heat treatment in the reducing atmosphere before the above pasting may be a nitriding treatment in a NO or N 2 O atmosphere. By performing the subsequent pasting process in an oxidizing atmosphere in the same manner, nitrogen atoms of the dangling bond are bonded with oxygen and removed, and at the same time, Si atoms and C atoms on the attachment surfaces of both wafers are bonded to complete the pasting.

[0037] In the present invention, in order to realize this SiC semiconductor dielectric isolation type integrated circuit semiconductor device, a novel single crystal island crystal plane structure is used in which each surface of the single crystal island is composed of crystal planes having crystal orientations peculiar to the present invention. That is, an n-type single crystal island is formed using 4H-SiC, and the surface of the single crystal island is composed of a C plane, that is, a crystal plane of the (000-1) plane, the side surface is composed of a {0-33-8} plane equivalent to the (0-33-8) plane, and the bottom surface of the single crystal island is composed of an Si plane, that is, a (0001) plane. As a result, the following advantages are obtained. A novel single crystal island crystal plane structure in which each surface of the single crystal island is composed of crystal planes having crystal orientations peculiar to the present invention is used. That is, an n-type single crystal island is formed using 4H-SiC, and the surface of the single crystal island is formed using a C plane, that is, a crystal plane of the (000-1) plane, the side surface is formed of a {0-33-8} plane equivalent to the (0-33-8) plane, and the bottom surface of the single crystal island is formed of an Si plane, that is, a (0001) plane. As a result, the following advantages are obtained. (1) When the Si plane is used with the catalyst surface reference etching method (CARE method) which is excellent as a planarization technique, flatness superior to that of the C plane can be obtained at the atomic level. Therefore, by making the bottom of the single crystal island the Si plane, a better bonding surface and a bonding surface with strong bonding strength can be obtained in bonding, and it is extremely suitable for the vertical elements formed by bonding the single crystal portions in the present invention. When the Si plane is used with the catalyst surface reference etching method (CARE method) which is excellent as a planarization technique, flatness superior to that of the C plane can be obtained at the atomic level. Therefore, by making the bottom of the single crystal island the Si plane, a better bonding surface and a bonding surface with strong bonding strength can be obtained in bonding, and it is extremely suitable for the vertical elements formed by bonding the single crystal portions in the present invention. By making the bottom of the single crystal island the Si plane, a better bonding surface and a bonding surface with strong bonding strength can be obtained in bonding, and it is extremely suitable for the vertical elements formed by bonding the single crystal portions in the present invention. By making the bottom of the single crystal island the Si plane, a better bonding surface and a bonding surface with strong bonding strength can be obtained in bonding, and it is extremely suitable for the vertical elements formed by bonding the single crystal portions in the present invention. is extremely suitable. (2) By configuring the side surface with a {0-33-8} plane equivalent to the (0-33-8) plane, it has an inclination angle of 54.7 degrees or (180 degrees - 54.7 degrees) with respect to the C plane on the surface. This crystal plane is suitable in that the oxidation rate is high and a thick insulating isolation oxide film for high breakdown voltage is easily formed. Furthermore, even if there are minute defects such as micropipes that cause breakdown voltage defects and an increase in leakage current in the drift region, it can be almost completely blocked during formation by a CVD method such as epitaxy, and it is also extremely suitable as a good quality and thin channel stopper forming crystal plane. (3) The C plane is suitable for obtaining the best MOS interface and fabricating a MOSFET with high channel mobility. It cuts. Furthermore, the C plane is the crystal plane with the fastest oxidation rate, and it is extremely suitable for high-voltage integrated circuit semiconductor devices that require a thick and high-quality insulating protection film under the crossover wiring. In addition, in the case of SiC semiconductors, the dielectric breakdown strength is about one order of magnitude higher than that of Si semiconductors. Therefore, as described in

[0027] and

[0029] , the insulating protection film under the crossover wiring can be made thinner even in the case of high voltage. As a result, the formation of the insulating protection film becomes easy, and the number of steps for avoiding disconnection of the wiring can be reduced, preventing the enlargement of the element area and enabling the miniaturization of the chip. On the other hand, in the case of SiC semiconductors, bipolar elements such as IGBTs and FWDs composed of p-body junctions have a problem that a specific on-voltage degradation phenomenon exists and the reliability is greatly impaired. However, with the reverse conduction structure of the present invention, only a large number of carriers can flow at the start or during the operation of the element, and the MaCH-TEDREC method (an operation method invented by the present inventor and disclosed in Japanese Patent No. 6232687), which raises the junction temperature above the on-voltage degradation suppression temperature to suppress or eliminate the on-voltage degradation, can be applied, and the on-voltage degradation phenomenon can be eliminated or significantly suppressed, achieving high reliability.

[0038] When the power integrated circuit semiconductor device according to this invention incorporates an inverter circuit, the upper arm of the inverter is configured to include the vertical semiconductor element. As a result, for example, in the case of an inverter having one or more phases of arms, the upper arm of each phase is electrically Since the collectors or drains of the reverse-conducting semiconductor elements of each phase are connected in parallel to the wiring of the high potential of the source, the element structure of the present invention in which a plurality of reverse-conducting semiconductor elements can be connected in parallel to the second main electrode (collector electrode or drain electrode) via the element support substrate is suitable. On the other hand, the lower arm of each phase has the first main electrode (emitter electrode or source electrode) connected in parallel to the wiring of the low and high potentials of the power supply, but since the potentials of the second main electrodes (collector electrode or drain electrode) change during the operation of the inverter, a reverse-conducting semiconductor element having a structure in which the second main electrodes (collector electrode or drain electrode) are independent of other phases is suitable. For this reason, the structures of Embodiments 7 to 9 are set as the preferred arm structure for one phase.

Advantages of the Invention

[0039] As described above, according to the present invention, in a dielectric isolation type power integrated circuit semiconductor device, by providing SCaDFRR on the surface of the inclined channel stopper of the output element, a high breakdown voltage of 700 V or more, which has been difficult in the past, can be achieved, and the vertical structure of the output reverse-conducting element can be realized, enabling a significant increase in the large current capacity and a reduction in loss. The large capacity and low loss of the power integrated circuit semiconductor device can be achieved. Furthermore, by optimizing and multiplexing the buffer layer, the snapback phenomenon can be eliminated with a small occupied area, and high reliability can be achieved. In addition, a dielectric isolation type integrated circuit semiconductor device wafer using a new wafer bonding structure SP&S-DBS can significantly reduce costs, improve the wafer bonding strength, and economize subsequent element manufacturing. Also, by applying a new SiC single crystal island crystal plane structure in addition to SCaDFRR and SP&S-DBS using SiC semiconductors, a further significant increase in capacity and reduction in loss can be achieved, and the on-voltage degradation can be eliminated, achieving an improvement in reliability. As a result, the application of the power integrated circuit semiconductor device of the present invention can greatly contribute to the miniaturization, weight reduction, low loss, high reliability, and economy of various power conversion circuit-mounted devices for home appliances, office equipment, vehicles, industries, etc.

Brief Description of the Drawings

[0040]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0041] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the dielectric isolation type power integrated circuit semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in the layers or regions marked with the polarity of the n or p semiconductor, electrons or holes are the majority carriers, respectively which means. In the case of the same layer or region, the numbers and arrows indicating the layers or regions in the drawings are, in principle, each Only one is shown to represent the rest are omitted. Also, each figure is a schematic cross-sectional view for explaining the invention while avoiding complexity, and there is no correlation such as size relationship or ratio between and among each structural factor in each figure. However, the numerical values of each structural factor in the description text are described as specifically as possible, so please understand from there. Also, to avoid complicating the figures, only 3 to 4 cells of the output element are drawn, and only 1 stage of the multi-stage surface protection film is schematically drawn. Further, the peripheral circuit components other than the output element are only schematically drawn about 2. In addition, each structural factor has no correlation such as size relationship or ratio within and between each figure. However, the numerical values of each structural factor in the description text are described as specifically as possible, so please understand from there. Also, to avoid complicating the figures, only 3 to 4 cells of the output element are drawn, and only 1 stage of the multi-stage surface protection film is schematically drawn. Furthermore, the peripheral circuit components other than the output element are only schematically drawn about 2. In a power integrated circuit semiconductor device, elements that constitute known gate drive circuits, various detection circuits such as voltage, current, and temperature, and various protection circuits of the output element are formed in each insulation isolation island according to the specifications of the power integrated circuit semiconductor device, either as single elements, multiple elements, or circuit units. In this specification, circuits and elements other than these output elements are collectively defined as peripheral circuits and peripheral circuit elements and are described by these names. In the following embodiments, the description focuses on the output element, particularly in the dielectric isolation type power integrated circuit semiconductor device chip, which is essential for understanding the present invention, and the description regarding the peripheral circuits and packages is omitted. (Embodiment 1) Figure 1 is a schematic cross-sectional view showing mainly the output element of the power integrated circuit semiconductor device chip 100 according to Embodiment 1. The semiconductor device chip 100 according to Embodiment 1 shown in Figure 1 is a dielectric isolation type power integrated circuit semiconductor device chip made using Si semiconductor, for example, with a design breakdown voltage of 1.2 kV and a rating of 3 A, and a little of the periphery of the output element is also shown in Figure 1. The output element is a reverse-conducting IGBT with a trench gate structure and a stripe shape. In a power integrated circuit semiconductor device, elements that constitute known gate drive circuits, various detection circuits such as voltage, current, and temperature, and various protection circuits of the output element are formed in each insulation isolation island according to the specifications of the power integrated circuit semiconductor device, either as single elements, multiple elements, or circuit units. In this specification, circuits and elements other than these output elements are collectively defined as peripheral circuits and peripheral circuit elements and are described by these names. In the following embodiments, the description focuses on the output element, particularly in the dielectric isolation type power integrated circuit semiconductor device chip, which is essential for understanding the present invention, and the description regarding the peripheral circuits and packages is omitted. (Embodiment 1) Figure 1 is a schematic cross-sectional view showing mainly the output element of the power integrated circuit semiconductor device chip 100 according to Embodiment 1. The semiconductor device chip 100 according to Embodiment 1 shown in Figure 1 is a dielectric isolation type power integrated circuit semiconductor device chip made using Si semiconductor, for example, with a design breakdown voltage of 1.2 kV and a rating of 3 A, and a little of the periphery of the output element is also shown in Figure 1. The output element is a reverse-conducting IGBT with a trench gate structure and a stripe shape.

[0042] (Embodiment 1) Figure 1 is a schematic cross-sectional view showing mainly the output element of the power integrated circuit semiconductor device chip 100 according to Embodiment 1. The semiconductor device chip 100 according to Embodiment 1 shown in Figure 1 is a dielectric isolation type power integrated circuit semiconductor device chip made using Si semiconductor, for example, with a design breakdown voltage of 1.2 kV and a rating of 3 A, and a little of the periphery of the output element is also shown in Figure 1. The output element is a reverse-conducting IGBT with a trench gate structure and a stripe shape. In the following embodiments, the description focuses on the output element, particularly in the dielectric isolation type power integrated circuit semiconductor device chip, which is essential for understanding the present invention, and the description regarding the peripheral circuits and packages is omitted. The output element is a reverse-conducting IGBT with a trench gate structure and a stripe shape. It is in a stripe shape. There are 25 stripe-shaped cells formed in the stripe-shaped single-crystal island, but for the sake of simplicity, only 3 cells are shown in the figure. The width of the single-crystal island is about 520 μm, and the length of the single-crystal island is 5 mm. Compared with the pn isolation type, the dielectric isolation type has extremely low leakage current even at high temperatures and requires a much smaller insulation separation region between elements, so it is easy to increase the breakdown voltage and reduce the chip size, and it is very suitable for high-voltage power integrated circuit semiconductor devices. The chip body of the first embodiment is composed of an element integration substrate 101 and an element support substrate 102, and the two substrates are bonded together by a wafer bonding technique. The wafer bonding technique used was developed by the inventors and disclosed in "Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, May 1992, p. 316 - 321" under the title "NEW DIELECTRIC ISOLATION FOR HIGH VOLTAGE ICS BY SINGLE SILICON POLY SILICON DIRECT (SPSDB) TECHNIQUE". The bonding structure by this wafer bonding technique should be called P&S-DBS following the naming method of

[0022] . By applying this structure, the high-temperature and long-time epitaxial growth process at 1200 °C or higher for forming a thick element support substrate in the conventional manufacturing process of dielectric isolation type power integrated circuit semiconductor devices can be omitted. As a result, a significant simplification of the manufacturing process of power integrated circuit semiconductor devices can be achieved, as well as a significant simplification of the manufacturing equipment and easier maintenance, and there is an advantage that a significant cost reduction can be achieved. Note that most of the various bonding structures of dielectric isolation type power integrated circuit semiconductor devices including SOI disclosed so far are P&S-DBS. The wafer bonding technology is disclosed in "Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, May 1992, p. 316 - 321" under the title "NEW DIELECTRIC ISOLATION FOR HIGH VOLTAGE ICS BY SINGLE SILICON POLY SILICON DIRECT (SPSDB) TECHNIQUE". The bonding structure using this wafer bonding technology should be called P&S-DBS following the naming method of

[0022] . By applying this structure, the high-temperature and long-time epitaxial growth process at 1200 °C or higher for forming a thick element support substrate in the conventional manufacturing process of dielectric isolation type power integrated circuit semiconductor devices can be omitted. As a result, a significant simplification of the manufacturing process of power integrated circuit semiconductor devices can be achieved, as well as a significant simplification of the manufacturing equipment and easier maintenance, and there is an advantage that a significant cost reduction can be achieved. Note that most of the various bonding structures of dielectric isolation type power integrated circuit semiconductor devices including SOI disclosed so far are P&S-DBS. BONDING The chip body of the first embodiment is composed of an element integration substrate 101 and an element support substrate 102, and the two substrates are bonded together by a wafer bonding technique. For example, it can be formed using the pasting method and its pretreatment described in lines 1 to 10 at the upper part of

[0035] . The wafer bonding technique used was developed by the inventors and disclosed in "Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, May 1992, p. 316 - 321" under the title "NEW DIELECTRIC ISOLATION FOR HIGH VOLTAGE ICS BY SINGLE SILICON POLY SILICON DIRECT (SPSDB) TECHNIQUE". The bonding structure by this wafer bonding technique should be called P&S-DBS following the naming method of

[0022] .

[0043] First, the configuration and features of Embodiment 1 in FIG. 1 will be described. Briefly describing the configuration of a conventional dielectric isolation type integrated circuit semiconductor device, the Si semiconductor chip body is configured such that single crystal islands are packed via a dielectric isolation film 106 in a separation region 117, and the side surfaces of the single crystal islands are inclined at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body. Therefore, since the channel stopper 125 extending along the dielectric isolation film 106 is inclined with respect to the front and back surfaces, it is hereinafter referred to as an inclined channel stopper. Also, the integrated circuit components in the single crystal islands are connected by wiring via a surface insulation protection film provided on the integrated circuit components in other single crystal islands and on the semiconductor chip body. As described in paragraph

[0015] , the wiring portion 116 that crosses over the separation region, the dielectric isolation film, and the inclined channel stopper exposed on the surface of the semiconductor chip body is defined as a crossover wiring. In this embodiment, the surface of the Si semiconductor chip body is composed of a (001) plane, and the side surfaces are composed of {111} planes. The predetermined angle determined by the crystal orientation with respect to the surface is about 54.7 degrees or (180 degrees - 54.7 degrees).

[0044] The p - collector 104 of the reverse - conducting IGBT in the single crystal island in the element integration substrate 101 is surrounded by an n - buffer layer 107 on the periphery, and is connected to the second main electrode (collector electrode) 103 via a short - circuit portion 10 5 located at a position farther from the n - emitter 110, forming a reverse - conducting structure. The n - buffer layer 107 has a double - buffer layer structure and has a higher lateral resistance compared to a single - buffer layer structure. Therefore, even if the extending p - collector width is short, with a small Isb, it is about 0.7V ​​​​Since the built-in voltage Vbi can be achieved and the IGBT can be turned on, the snap-back phenomenon can be significantly suppressed. That is, the snap-back phenomenon can be significantly suppressed with a small occupied area. The double buffer layer has its basic concept disclosed in Patent No. 6383971 by the inventor of the present invention. Also, the p-body 109 connected to the first main electrode (emitter electrode) 120 and the drift layer 108 form an FWD and are connected to the second main electrode (collector electrode) 103 via the n-short circuit portion 105. As a result, there is no need to separately integrate an FWD in the single crystal island, and a significant reduction in the element

[0045] The dielectric isolation type power integrated circuit semiconductor device chip in the present embodiment, which aims to achieve a significant increase in breakdown voltage, differs in configuration from the conventional dielectric isolation type integrated circuit semiconductor device chip in the following two points. The first difference is that, in addition to the conventional electric field relaxation high breakdown voltage technologies such as the field plate 123 for electric field relaxation at the bonding end and the surface electric field relaxation layer FRR (eff are) for electric field relaxation at the inclined channel stopper top portion, a new surface carrier density decrease electric field relaxation region (Surface Carrier An insulating film made of SiO2 with a thickness of about 5.4 μm is used. In the case of this embodiment, since a breakdown voltage of 1.2 kV or more is required, the surface insulating protection film 118 made of SiO2 needs to have a film thickness of about 12 μm or more, making it difficult to form. Therefore, in this embodiment, SCaDFRR121 is newly provided on the surface of the inclined channel stopper 125 to improve the breakdown voltage and reduce the thickness of the insulating film. The principle is described in

[0028] . Although it varies depending on the length, film quality of the insulating film, degree of coexistence with FRR, etc. due to the provision of SCaDFRR, a film thickness reduction of about 2 μm or more can be expected. When applied to the above prior art 3, it can be reduced to a film thickness of about 10 μm.

[0046] The second difference is that an embedded insulating film 140 is used in the chip body under the bypass wiring. When a voltage corresponding to the breakdown voltage is applied, surface electric field concentration occurs under this bypass wiring 116, causing the Si surface to undergo dielectric breakdown. Therefore, it is necessary to make the thickness of the surface insulating protection film that relaxes this surface electric field concentration and prevents dielectric breakdown. When the breakdown voltage is high, this thickness becomes very large. For example, when the breakdown voltage is 1.2 kV, an insulating film thickness of 12 μm or more is required as described above, making it difficult to form. Also, a large step is generated between the wiring 119 on the thin insulating film until the element is connected inside the insulating isolation island, and disconnection of the wiring occurs at the step portion. To avoid this, inside the element, the insulating film under the wiring is made stepped, with the step at each step usually being about 1 - 2 μm. However, in the case of high breakdown voltage, it is necessary to increase the number of steps, resulting in more tread portions between the steps. As a result, the size of most of the integrated circuit semiconductor device constituent elements becomes large, and the chip becomes hypertrophied. For this reason, there is no example of a high breakdown voltage integrated circuit semiconductor device of 650 V or more, which has become a major obstacle to commercialization.

[0047] In this embodiment, a thick embedded insulating film 140 is provided by embedding a part of the thick surface insulating protection film 118 under the bypass wiring, which has been formed on the surface of the chip body, under the surface of the chip body. The SCaDFRR121 is provided under it, and on the surface of the chip body, an embedded insulation It is configured to provide a separate surface insulating protective film 118 with a thickness obtained by subtracting the film thickness. For example, in the above Since the insulating film thickness reduction effect of SCaDFRR can be expected to be about 2 μm, in order to make the thickness of the surface insulating protective film on the surface of the chip body a realistic thickness of about 6 μm, the thickness of the buried insulating film under the main surface is set to about 4 μm. As a result, the number of steps of the insulating protective film on the surface of the chip body of the power integrated circuit semiconductor device can be reduced, and a reduction in chip area can be achieved.

[0048] Note that for the main structural specifications, for example, the drift layer has an impurity concentration of 1x10 14 cm -3 · and a thickness of 1 40 μm may be sufficient. The n+ emitter region has an impurity concentration and a thickness of 5x10 19 cm -3 · 1.5 μm, the p-body region has 3x10 17 cm -3 · a thickness of 4 μm from the surface, the n-b uffer layer has 2x10 16 cm -3 · 4 μm, and the p+ collector region has 1x10 19 cm -3 · 2 μm may be sufficient. The distance from the p-body region to the SiO2 dielectric isolation film may be 170 μm, and the thickness of the inclined channel stopper may be 5 μm. The thickness of the gate oxide film may be 1300 angstroms, and the thickness of the SiO2 dielectric isolation film may be 5 μm. Also, the thickness of the chip body is about 300 μm.

[0049] Next, the characteristics of the power integrated circuit semiconductor device of Embodiment 1 will be described. This power integrated circuit semiconductor element chip 100 was mounted on a high-voltage package for characteristic measurement and subjected to an operation test. With no gate voltage applied, a forward voltage is applied between the emitter electrode 120 and the collector electrode 103. ​​When pressure is applied, a leakage current flows, showing good forward blocking characteristics. The breakdown voltage at room temperature, that is the voltage showing avalanche breakdown is about 1.42 kV. Also, the leakage current before avalanche breakdown is 1×10 -6 A / cm 2 or less at room temperature. Even at a high temperature of 250 °C, it is 8×10 -6 A / cm 2 or less, which is good .

[0050] Also, when a gate voltage is applied and increased in the forward state, the reverse-conducting IGBT turns on. However, although the snapback phenomenon was observed, Vsb is as low as about 1.6 V, which is at a level without practical problems . Also, the on-voltage at room temperature when energized at a current density of 100 A / cm 2 is as low as about 2.5 V, which is good. Also, the turn-off time during energization at 100 A / cm is about 1 2 .2 μs, which is about 1 / 2 or less of that of Si-IGBTs in the same breakdown voltage class and is short. Thus, due to the reverse-conducting IGBT function, the turn-off time can be reduced and the speed can be increased. As a result, the switching loss can be significantly reduced and the loss can be decreased. Furthermore, the on-voltage at room temperature when energized at a current density of 100 A / cm 2 for FWD is as low as about 1.5 V, which is good.

[0051] As described above, according to this embodiment, as an output element of the Si power integrated circuit semiconductor device chip, a reverse-conducting IGBT with high breakdown voltage can be integrated by SCaDFRR and an embedded insulating film, and high breakdown voltage, reduction of chip occupation area, and low loss can be achieved, and large capacity of the power integrated circuit semiconductor device can also be achieved. Furthermore, the snap-back phenomenon can be significantly suppressed to a level where there is no practical problem, and high reliability can be achieved. Also, during the reflux of the inverter, the built-in diode composed of the p-body and the n-drift layer can be utilized as the FWD diode, eliminating the need to separately provide a new diode, significantly reducing the semiconductor chip size of the power integrated circuit semiconductor device, and achieving cost reduction.

[0052] (Embodiment 2) FIG. 2 is a cross-sectional view schematically showing the main part, which is the output element, of the Si power integrated circuit semiconductor device chip 200 according to Embodiment 2. The semiconductor device chip 200 according to Embodiment 2 shown in FIG. 2 is, for example, a dielectric isolation type power integrated circuit semiconductor device chip made of Si semiconductor with a designed breakdown voltage of 1.2 kV·60 A class, and the element integration substrate 201 and the element support substrate 202 are bonded together using a novel bonding structure (SP&S-DBS) according to the present invention. This configuration can be formed, for example, using the pasting method and its pretreatment described in lines 19 to 26 at the upper part of

[0035] . The output element is a vertical structure reverse-conducting IGBT with a trench gate structure, using a novel reverse-conducting IGBT structure according to the present invention, and is integrated in the dielectrically isolated single-crystal island and the adjacent isolation region 217 in the element integration substrate 201. Note that the output element has a stripe shape, the stripe-shaped single-crystal island width is about 6.5 mm, and the single-crystal island length is 5 mm. 500 stripe-shaped cells are formed in the stripe-shaped single-crystal island, but only 4 cells are schematically shown in the figure to avoid complication. As described above, compared with the pn isolation type, the dielectric isolation type has extremely low leakage current even at high temperatures and requires a significantly smaller isolation region, so it is easy to increase the breakdown voltage and reduce the chip size, and is suitable for high breakdown voltage power integrated circuit semiconductor devices.

[0053] First, the configuration and features of the first embodiment shown in FIG. 2 will be specifically described. In the second embodiment, the main functional part of the reverse conducting IGBT 200 of the output element is almost inductive. However, the insulating film 206 at the bottom of the dielectric isolation island is removed. The p+ collector 204 is connected to the p+ element support substrate 202. The supporting substrate 202 is connected to the collector electrode 203, which is the second main electrode. The element portion between the emitter electrode 220 and the collector electrode 203 is a vertical S type. On the other hand, the element portion between the first main electrode 220 and the third main electrode 215 can function as an i-IGBT. The n+ region (which also serves as a MOSFET) is connected to the n+ region (which is connected to the n+ short circuit portion) through the part where the insulating film at the bottom of the dielectric isolation island has been removed. The third main electrode 217 is connected to the drain of the first main electrode 205 of the first semiconductor laser 100 and the drain of the second semiconductor laser 101. 15. Therefore, the element between the first main electrode 220 and the third main electrode 215 is Si-M It can function as an OSFET. In addition, the third main electrode 215 is electrically connected to a metal part of the package to which the second main electrode 203 is die-bonded by wire bonding outside the chip, so the second main electrode 203 and the third main electrode 215 are electrically connected. Therefore, the elements between the first main electrode 220 and the second main electrode 203 and the third main electrode 215 function as a reverse conducting IGBT as a whole. Also, by adjusting the width of the n+ region 205 and the width of the above-mentioned p region 204, when the width of the n+ region 205 is large, the operation of the MOSFET becomes the main one, and when the width of the p+ region 205 is large, the operation of the IGBT can become the main one. In the case of this embodiment, in order to make the operation of the IGBT the main one, the ratio of the width of the above-mentioned p+ region 204 to the width of the above-mentioned n+ region 205 may be set to about 90 to 10, and the p+ region 204 may be made considerably large. On the other hand, since the above-mentioned n+ region 205 functions as a short-circuit portion of the p+ collector 204, the discharge of the residual carriers in the drift layer 208 can proceed rapidly at turn-off. As a result, the turn-off time is shortened and the turn-off loss can be reduced, so that the power integrated circuit semiconductor device chip can be made to have low losses. Note that since the width of the p+ collector 204 becomes large, a plurality of n+ regions 205 are also provided in the p+ collector 204 for each predetermined number of cells to efficiently and rapidly discharge the residual carriers. Only one is schematically shown in FIG. 2. The interval of this n+ region 205 is determined by the suppression condition of the snap-back phenomenon. Also, the n+ regions 205 provided in the p+ collector 204 divide the p+ collector 204 at predetermined positions in the depth direction of the drawing paper, and are connected to the n+ regions 205 on the left and right of the p+ collector 204 and the n+ regions inside each other to suppress the resistance and rapidly discharge the residual carriers. Also, when a voltage corresponding to the breakdown voltage is applied between the first main electrode and the second main electrode, electric field concentration occurs at the high breakdown voltage junction end inside the element. Therefore, a known terminal such as the field plate 223 in the figure

[0054] Also, when a voltage corresponding to the breakdown voltage is applied between the first main electrode and the second main electrode, electric field concentration occurs at the high breakdown voltage junction end inside the element. junction end causes electric field concentration, so a known terminal such as the field plate 223 in the figure It is suppressed by the -shion technology, and the channels generated on the chip surface are blocked by the inclined channel stopper technology. Furthermore, to prevent gate dielectric breakdown due to electric field concentration at the bottom of the trench gate, known technologies such as thickening the oxide film 212 at the bottom of the gate and installing a p-well for covering the bottom of the gate (not shown in the figure) are applied. When appropriate design is carried out using these technologies, the main factor determining the breakdown voltage is the electric field concentration occurring under the wiring, and in the case of this element structure, it is the surface electric field concentration in the inclined channel portion 225 under the crossover wiring 216. Since the Si surface undergoes dielectric breakdown at a voltage lower than the breakdown voltage due to this surface electric field concentration, it is necessary to mitigate the surface electric field concentration and thicken the insulation protection film to prevent this dielectric breakdown. When the breakdown voltage is high, this thickness becomes very large. For example, when the breakdown voltage is 1.2 kV, an insulation protection film thickness of 12 μ m or more is required, making it difficult to form. Also, a large step is generated between the wiring 219 on the thin insulation protection film until it is connected to the emitter 210 inside the insulation isolation island, and the wiring breaks at the step portion. To avoid this, inside the element, the insulation protection film under the wiring is made into a stepped shape, with the step at each step usually about 1 - 2 μm. However, in the case of high breakdown voltage, it is necessary to increase the number of these steps, resulting in more tread portions between the steps. As a result, the size of most of the constituent elements of the integrated circuit semiconductor device becomes large, and the chip becomes enlarged. For these reasons, there are no examples of high breakdown voltage integrated circuit semiconductor devices of 650 V or more, which has become a major obstacle to commercialization.

[0055] In this embodiment, a substantial portion of the thick insulating protective film 218 under the crossover wiring, which was conventionally formed on the chip surface, is embedded under the surface of the chip body to form the buried insulating film 240, thereby reducing the thickness of the surface insulating protective film 218 formed on the chip surface and reducing the step height and the number of steps. Also, a novel electric field relaxation region SCaDFRR221 described above in Embodiment 1 is formed under the buried insulating film 240, whereby the insulating film pressure can be reduced by about 2 μm or more. As a result, for example, the surface oxide film 218, which conventionally required 12 μm or more to achieve a breakdown voltage of 1.2 kV, may be made about 6 μm thick, and the buried insulating film 240 under the surface may be made about 4 μm thick, thereby achieving both a higher breakdown voltage of the power integrated circuit semiconductor device chip and a reduction in the chip area due to a reduction in the number of steps. When this chip is used in an inverter or the like, a pn junction diode composed of the p-body 209 and the n-drift layer 208 can be utilized as a FWD diode. That is, the reflux current flows through the route of the first electrode 220 → p-body 209 → n-drift 208 → n+ short circuit section 205 → isolation region 217 → third electrode 215 and functions as a FWD. As a result, there is no need to separately provide a new diode as a FWD. Since the FWD requires an almost equivalent current capacity to that of the IGBT, the semiconductor chip size of the power integrated circuit semiconductor device can be reduced by almost about half, enabling miniaturization and cost reduction of the power integrated circuit semiconductor device.

[0056] Regarding the snapback phenomenon associated with the reverse-conducting IGBT, since the single-crystal island width for the reverse-conducting IGBT is wide enough as described in

[0052] , the sheet resistance can be increased even with a single buffer layer, and the snapback voltage Vsb can be made less than or equal to the built-in voltage Vbi of Si with a small snapback current Isb, thus eliminating the snapback phenomenon and making it fully applicable. However, since the p+ collector 204 where the buffer layer extends becomes large, the interval between the short-circuit portions becomes large, and the discharge rate of the residual carriers during turn-off may be impaired. In this case, the application of a double buffer layer is preferable. By forming a double buffer layer, the sheet resistance of the non-depleted conduction path portion of the snapback current Isb in the buffer layer on the side in contact with the drift 208 can be increased, so that the p+ collector width capable of eliminating the snapback phenomenon can be reduced. That is, since the interval between the short-circuit portions can be reduced, the discharge rate of the residual carriers during turn-off can be increased, and the low-loss effect due to the improvement of the original switching speed of the reverse-conducting IGBT can be more effectively achieved, and the high reliability due to the elimination of the snapback phenomenon can also be fully achieved. Next, the manufacturing process flow of Embodiment 2 will be briefly described with reference to FIG. 3. It should be noted in advance that [5] and 6] in FIG. 3 are drawn with a slightly expanded right side for drawing convenience compared to the figures before [4].

[0057] First, a mask for forming isolation grooves is formed on the n single-crystal main substrate 230, and selective etching of the n single-crystal main substrate 230 is performed with a high-temperature molten KOH solution until the isolation grooves reach a predetermined depth. In this etching, the mask width of the third main electrode 215 forming portion is made wider than the mask widths of the other isolation V-groove forming portions. The depth of the isolation grooves may be 160 μm. When the etching depth of the V-groove portion reaches 160 μm, the etching is terminated, and the third main electrode 215 with a wide width is formed Note in advance that [5] and 6] in FIG. 3 are drawn with a slightly expanded right side for drawing convenience compared to the figures before [4]. First, a mask for forming isolation grooves is formed on the n single-crystal main substrate 230, and selective etching of the n single-crystal main substrate 230 is performed with a high-temperature molten KOH solution until the isolation grooves reach a predetermined depth. In this etching, the mask width of the third main electrode 215 forming portion is made wider than the mask widths of the other isolation V-groove forming portions. When performing this etching, the mask width of the third main electrode 215 forming portion is made wider than the mask widths of the other isolation V-groove forming portions. The depth of the isolation grooves may be 160 μm. When the etching depth of the V-groove portion reaches 160 μm, the etching is terminated, and the third main electrode 215 with a wide width is formed When the etching depth of the V-groove portion reaches 160 μm, the etching is terminated, and the third main electrode 215 with a wide width is formed The forming section is also automatically formed together with other V-groove sections. Next, the n-inclined channel stopper 225 is formed by diffusion, and further, for example, a selective double diffusion of phosphorus and antimony is performed to form the double buffer layer 207 (see [1] in Fig. 3). Then, a SiO2 insulating film 206 for dielectric isolation is formed over the entire surface. Its thickness may be about 4 μm. Next, the SiO2 insulating film 206 in the portion where the p+ collector 204 is to be formed is removed by selective etching, and further, a p+ single crystal layer for the p+ collector 204 is formed by epitaxial growth. For example, the thickness of the p+ epitaxial layer may be 18 μm. Then, selective etching of the p+ epitaxial layer is performed to form the p+ collector 204. Then, the p+ collector 204 in the portion where the n-short circuit layer 205 is to be formed is removed by selective etching, and further, the SiO2 dielectric isolation film 206 in the portion where the third main electrode 215 is to be formed is removed by selective etching (see [2] in Fig. 2). As a result, the single crystals in the portion where the n-short circuit layer 205 is to be formed and the portion where the third main electrode 215 is to be formed are exposed. Next, n+ epitaxial growth is performed over the entire surface until the thickness is such that all the isolation grooves are completely filled, including the portion where the third main electrode 215 is to be formed. At this time, an n single crystal grows on the portion where the n+ short circuit layer 205 is to be formed, the portion where the third main electrode 215 is to be formed, and the p+ collector 204, and an n polycrystal grows on the insulating isolation oxide film 206, and the separation region 217 has a situation where both crystals are mixed. Then, grinding and mirror polishing are performed until the p+ collector 204 is exposed to complete the element integrated substrate 201 (see [3] in Fig. 2).

[0058] After that, a novel bonded structure (SP&S-DBS) wafer is completed by bonding an n+ single crystal wafer that has only a single crystal surface bonding surface prepared separately from this wafer and serves as the element support substrate 202, and an element integrated substrate 201 that has a novel polycrystalline surface / single crystal surface mixed bonding surface (see [4] in FIG. 3). The bonded wafer of this novel bonded structure has less bending compared to the wafer of the conventional epitaxial growth substrate, and also has less bending and stronger adhesive strength compared to the wafers of the bonded structures (P&S-DBS) of the single crystal single surface and polycrystal single surface disclosed so far in Embodiment 1. The reason for the small bending is that polycrystals shrink severely during cooling after epitaxial growth compared to single crystals, causing the wafer to bend greatly, and in the new structure, the shrinkage is suppressed because single crystal regions are mixed. Also, the reason for the strong adhesive strength is that in the conventional bonded portion, there is only the bonded portion of single crystal and polycrystal, whereas in the new structure, in addition to this, there is a bonded portion of single crystal and single crystal with strong adhesive strength. However, voids tend to occur at the bonded boundary of the bonded portion of single crystal and single crystal, resulting in a decrease in the bonding strength. Therefore, efforts have been made in the bonding temperature, pressure, bonding atmosphere gas, and pretreatment material to eliminate the generation of voids. The bonded wafer thus completed with less bending and strong adhesive strength is then polished on the upper surface of the single crystal main substrate 230 until the crystal islands separated by dielectric are exposed from the upper surface side of the bonded wafer to finish the element integrated substrate 201, thereby completing a wafer for a power integrated circuit semiconductor device chip (see [5] in FIG. 3). The thickness of the completed wafer may be about 300 μm. Thereafter, 4 μm of Si in the embedded insulating film 240 formation portion is removed by selective etching, then selective ion implantation of phosphorus or aluminum is performed on the SCaDFRR221 formation portion, and then SiO2 with a thickness of 4 μm or more is formed on the entire surface by CVD, and then mirror polishing is performed to complete the formation of the embedded insulating film 240. Thereafter, although it is a known general method and the description is omitted, using a predetermined element manufacturing technique, each single crystal island is provided with an output element having a trench gate structure and a drive / control circuit element having a planar gate structure. Form elements for children, detection and protection circuits, electrodes such as the third electrode 215, and wiring are formed to complete the power integrated circuit semiconductor device of the second embodiment (see [6] in Fig. 3).

[0059] In this embodiment, by using the above-mentioned novel bonding structure (SP&S-DBS), the bending of the bonded wafers can be reduced and the bonding strength of the entire bonded wafers can be improved. As a result, the manufacturing process can be simplified in the subsequent predetermined element manufacturing process, damage during element manufacturing can be reduced, and an effect of improving the yield of good products can be obtained. Above all, the novel bonding structure (SP&S-DBS) can eliminate the conventional epitaxial growth process at a high temperature of about 1200°C for a long time, achieving a significant simplification of the manufacturing process of the power integrated circuit semiconductor device, simplifying the manufacturing equipment and maintenance, and achieving a large cost reduction, which is a great effect.

[0060] Regarding the main structural specifications other than the above, for example, the drift layer, p-body region, n+ emitter region, n-buffer layer, inclined channel stopper, and gate oxide film are the same as those in the first embodiment. On the other hand, the p+ collector region may be 1x10 19 cm -3 ·18μm, and the impurity concentration of the p+ isolation region may be 1x10 19 cm -3 . The distance from the p-body region to the SiO2 dielectric isolation film may be 170μm, the thickness of the SiO2 dielectric isolation film may be 4μm, and the p+ element support substrate may have a carrier concentration of 1x10 19 cm -3 · and a thickness of 150μm. In this case, the thickness of the element integration substrate 201, that is, the thickness of the region between the p+ element support substrate 202 and the surface of the chip body is 155μm.

[0061] Next, the characteristics of the power integrated circuit semiconductor device manufactured by the above process flow will be described. ​The power integrated circuit semiconductor element chip 200 was mounted on a package fabricated for characteristic measurement and subjected to an operation test. Naturally, the third main electrode 215 is wire-bonded to the metal terminal surface of the package to which the second main electrode 203 is die-bonded, and the two are electrically connected. The element exhibited good forward blocking characteristics, and the breakdown voltage at room temperature, i.e., the voltage at which avalanche breakdown occurs, was approximately 1.3 6 kV. Also, the leakage current before avalanche breakdown was 5×10 -6 A / cm 2 or less at room temperature and 6×10 at 50 °C, which is also good. -5 A / cm 2 or less. When a gate voltage was applied and increased in the forward state, the reverse conducting IGBT turned on, but no snap-back phenomenon was observed when it turned on. The on-voltage at room temperature when energized at a current density of 100 A / cm2 in the on state was as low as approximately 1.9 V, which is good. When energized at a current density of 100 A / cm2 in the on state, the on-voltage at room temperature was as low as approximately 1.9 V, which is good. When energized at a current density of 100 A / cm2 in the on state, the on-voltage at room temperature was as low as approximately 1.9 V, which is good. Also, the turn-off time at 50 A of conduction was approximately 0.7 μs, which is shorter than that of Si-IGBTs in the same breakdown voltage class. As a result, the turn-off time can be reduced and the speed can be increased, significantly reducing switching losses and achieving low losses. losses and achieving low losses. Furthermore, the on-voltage at room temperature when energized at a current density of 100 A / cm 2 of FWD was as low as approximately 1.5 V, which is good.

[0062] As described above, according to this embodiment, as the output element of the power integrated circuit semiconductor device chip, a vertical structure reverse conducting IGBT with a high breakdown voltage and a large current capacity can be integrated by applying SCaDFRR and an embedded insulating film, achieving high breakdown voltage, reduced chip occupation area, and low losses, and significantly increasing the capacity of the power integrated circuit semiconductor device. Also, a new polycrystalline surface · By applying the single-crystal plane mixed bonding structure (SP&S-DBS), a dielectric isolation type integrated circuit wafer with a high-quality bonding surface having strong adhesive strength, small bending, and low cost can be realized. Furthermore, the snap-back phenomenon can be eliminated and high reliability can be achieved. Also, when the inverter is refluxed, the built-in diode composed of the p-body and the n-drift layer can be utilized as a FWD diode, eliminating the need to separately provide a new diode, significantly reducing the semiconductor chip size of the power integrated circuit semiconductor device, and further reducing costs.

[0063] (Embodiment 3) Generally, SiC semiconductor devices have significantly superior performance in terms of high breakdown voltage, small size and low loss, high heat resistance, high heat dissipation, high power tolerance, etc., and are suitable for power devices. In particular, because the dielectric breakdown field strength of SiC is high, the width of the field region of the device can be reduced to about one digit of that of Si, so that the element area can be significantly reduced in the case of the same breakdown voltage. On the other hand, the dielectric isolation type power integrated circuit semiconductor device has an extremely small leakage current even at high temperatures, so it is suitable for achieving high breakdown voltage and high heat resistance, and the width of the element isolation region can be significantly narrowed, so it is suitable for a high breakdown voltage integrated circuit semiconductor device with small size and low loss. Focusing on these characteristics, the inventor of the present invention, in order to better achieve the object of the present invention, in addition to the novel polycrystalline plane / single-crystalline plane mixed bonding structure SP&S-DBS and the novel SCaDFRR structure shown in Embodiments 1 and 2, devised a novel single-crystal island crystal plane structure suitable for SiC dielectric isolation type power integrated circuit semiconductor devices, and applied these to configure this Embodiment 3. Figure 4 is a schematic cross-sectional view showing the main part of the output element of the SiC dielectric isolation type power integrated circuit semiconductor device chip 300 fabricated using the SiC semiconductor according to Embodiment 3, centered on the output element. In addition, a novel single-crystal island crystal plane structure suitable for SiC dielectric isolation type power integrated circuit semiconductor devices, and these are applied to configure this Embodiment 3. A novel single-crystal island crystal plane structure suitable for SiC dielectric isolation type power integrated circuit semiconductor devices was devised, and these were applied to configure this Embodiment 3. Figure 4 is a schematic cross-sectional view showing the main part of the SiC dielectric isolation type power integrated circuit semiconductor device chip 300 fabricated using the SiC semiconductor according to Embodiment 3, centered on the output element. It is as follows. The integrated circuit semiconductor device chip 300 is composed of an element integrated substrate 301 and an element support substrate 302 which are bonded together using the novel bonding structure SP&S-DBS according to the present invention. However, since the current SiC bulk crystal has inferior crystal quality compared to the Si bulk crystal, for example, in [1] (described in

[0057] ) of the process flow in FIG. 3 (which is the process flow of an IGBT, please note the differences from a MOSFET for reference), before forming the mask for forming the isolation grooves on the starting n single crystal main substrate 230, epitaxial growth of an n-type single crystal layer thicker than the V isolation grooves of a predetermined depth is performed on the SiC single crystal main substrate (corresponding to 230 in FIG. 3), and all the completed single crystal islands are incorporated into this epitaxial layer. As a result, since the SiC epitaxial single crystal layer has much better crystal quality than the SiC bulk crystal, each integrated circuit constituent element formed in the epitaxial single crystal island can have significantly superior characteristics compared to the case where it is formed in the SiC bulk crystal. Of course, the SiC single crystal main substrate is completely removed in the polishing process of [5] in the process flow of FIG. 3, and only the epitaxial single crystal remains in each single crystal island of the element integrated substrate. The same applies to the element integrated substrates after Embodiment 4. In addition, the above novel SiC pasting structure SP&S-DBS can be formed, for example, using the pasting method and its pretreatment described in lines 11 to 18 at the upper part of

[0036] . The SiC chips of the SiC dielectric isolation type power integrated circuit semiconductor devices in Embodiments 4, 5, and 8 hereinafter are the same.

[0064] The output element is a SiC reverse-conducting MOSFET with a designed breakdown voltage of 1.2 kV and a current capacity of about 100 A. It is integrated in the dielectric isolation islands of the element integrated substrate 301. It is a vertical reverse-conducting MOSFET with a trench gate structure and has a stripe shape. The width of the single crystal island integrating this output element is about 2.5 mm, and the length of the single crystal island is 5 mm. A large number of cells are integrated and connected in parallel in the single crystal island, but only 4 cells are schematically shown in the figure for simplicity of explanation. In a dielectric isolation type integrated circuit semiconductor device, the semiconductor chip body is configured with single crystal islands laid out through a dielectric insulating separation film 306 in the separation region 317. The side surfaces of the single crystal islands are inclined at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body. The above To realize an ideal combination of a dielectrically isolated integrated circuit semiconductor device and a SiC semiconductor, in this embodiment, a novel single crystal island crystal plane structure is used in which each surface of the single crystal island is composed of a crystal plane with a crystal orientation unique to the present invention. That is, an n-type single crystal island is formed using 4H SIC, the surface of the single crystal island is configured using the C plane, i.e., the (000-1) crystal plane, the side surface is configured using the {0-33-8} plane, and the bottom surface of the single crystal island is configured using the Si plane, i.e., the (0001) plane. As a result, the following advantages are obtained. In the production of ordinary SiC individual elements, the Si plane is excellent as a planarization technique, and extremely high flatness has been achieved at the atomic level using the Catalyst Assisted Reactive Etching (CARE) method. It has been reported that the flatness obtained by applying this method is better than that of the C plane. Therefore, by making the bottom surface of the single crystal island the Si plane, a better-quality and stronger adhesive surface between single crystal planes can be obtained in the polycrystalline plane / single crystal plane hybrid bonding structure SP&P-DBSS, which is extremely suitable for the vertical elements composed of the bonding of single crystal parts in this embodiment. The {0-33-8} plane on the side surface has an inclination angle of 54.7 degrees or (180 degrees - 54.7 degrees) with respect to the C plane on the surface, and the oxidation rate is extremely fast, making it suitable for easily forming a thick insulating isolation oxide film for high voltage resistance. Furthermore, even if there are minute defects such as micropipes that cause poor breakdown voltage in the drift region, this plane can be almost completely blocked during formation by CVD methods such as epitaxy, so it is also extremely suitable as a crystal plane for forming a high-quality inclined channel stopper for high voltage devices. Since the C plane can obtain the best MOS interface, it is suitable for fabricating MOSFETs with high channel mobility. Furthermore, the C plane has the highest oxidation rate and is extremely suitable for high voltage integrated circuit semiconductor devices that require a thick and high-quality insulating protection film under the crossover wiring. (1) In the production of ordinary SiC individual elements, the Si plane is excellent as a planarization technique, and extremely high flatness has been achieved at the atomic level using the Catalyst Assisted Reactive Etching (CARE) method. It has been reported that the flatness obtained by applying this method is better than that of the C plane. Therefore, by making the bottom surface of the single crystal island the Si plane, a better-quality and stronger adhesive surface between single crystal planes can be obtained in the polycrystalline plane / single crystal plane hybrid bonding structure SP&P-DBSS, which is extremely suitable for the vertical elements composed of the bonding of single crystal parts in this embodiment. In the production of ordinary SiC individual elements, the Si plane is excellent as a planarization technique, and extremely high flatness has been achieved at the atomic level using the Catalyst Assisted Reactive Etching (CARE) method. It has been reported that the flatness obtained by applying this method is better than that of the C plane. Therefore, by making the bottom surface of the single crystal island the Si plane, a better-quality and stronger adhesive surface between single crystal planes can be obtained in the polycrystalline plane / single crystal plane hybrid bonding structure SP&P-DBSS, which is extremely suitable for the vertical elements composed of the bonding of single crystal parts in this embodiment. In the production of ordinary SiC individual elements, the Si plane is excellent as a planarization technique, and extremely high flatness has been achieved at the atomic level using the Catalyst Assisted Reactive Etching (CARE) method. It has been reported that the flatness obtained by applying this method is better than that of the C plane. Therefore, by making the bottom surface of the single crystal island the Si plane, a better-quality and stronger adhesive surface between single crystal planes can be obtained in the polycrystalline plane / single crystal plane hybrid bonding structure SP&P-DBSS, which is extremely suitable for the vertical elements composed of the bonding of single crystal parts in this embodiment. In the production of ordinary SiC individual elements, the Si plane is excellent as a planarization technique, and extremely high flatness has been achieved at the atomic level using the Catalyst Assisted Reactive Etching (CARE) method. It has been reported that the flatness obtained by applying this method is better than that of the C plane. Therefore, by making the bottom surface of the single crystal island the Si plane, a better-quality and stronger adhesive surface between single crystal planes can be obtained in the polycrystalline plane / single crystal plane hybrid bonding structure SP&P-DBSS, which is extremely suitable for the vertical elements composed of the bonding of single crystal parts in this embodiment. In the production of ordinary SiC individual elements, the Si plane is excellent as a planarization technique, and extremely high flatness has been achieved at the atomic level using the Catalyst Assisted Reactive Etching (CARE) method. It has been reported that the flatness obtained by applying this method is better than that of the C plane. Therefore, by making the bottom surface of the single crystal island the Si plane, a better-quality and stronger adhesive surface between single crystal planes can be obtained in the polycrystalline plane / single crystal plane hybrid bonding structure SP&P-DBSS, which is extremely suitable for the vertical elements composed of the bonding of single crystal parts in this embodiment. In the production of ordinary SiC individual elements, the Si plane is excellent as a planarization technique, and extremely high flatness has been achieved at the atomic level using the Catalyst Assisted Reactive Etching (CARE) method. It has been reported that the flatness obtained by applying this method is better than that of the C plane. Therefore, by making the bottom surface of the single crystal island the Si plane, a better-quality and stronger adhesive surface between single crystal planes can be obtained in the polycrystalline plane / single crystal plane hybrid bonding structure SP&P-DBSS, which is extremely suitable for the vertical elements composed of the bonding of single crystal parts in this embodiment. (2) The {0-33-8} plane on the side surface has an inclination angle of 54.7 degrees or (180 degrees - 54.7 degrees) with respect to the C plane on the surface, and the oxidation rate is extremely fast, making it suitable for easily forming a thick insulating isolation oxide film for high voltage resistance. Furthermore, even if there are minute defects such as micropipes that cause poor breakdown voltage in the drift region, this plane can be almost completely blocked during formation by CVD methods such as epitaxy, so it is also extremely suitable as a crystal plane for forming a high-quality inclined channel stopper for high voltage devices. (3) Since the C plane can obtain the best MOS interface, it is suitable for fabricating MOSFETs with high channel mobility. Furthermore, the C plane has the highest oxidation rate and is extremely suitable for high voltage integrated circuit semiconductor devices that require a thick and high-quality insulating protection film under the crossover wiring. (3) Since the C plane can obtain the best MOS interface, it is suitable for fabricating MOSFETs with high channel mobility. Furthermore, the C plane has the highest oxidation rate and is extremely suitable for high voltage integrated circuit semiconductor devices that require a thick and high-quality insulating protection film under the crossover wiring. (3) Since the C plane can obtain the best MOS interface, it is suitable for fabricating MOSFETs with high channel mobility. Furthermore, the C plane has the highest oxidation rate and is extremely suitable for high voltage integrated circuit semiconductor devices that require a thick and high-quality insulating protection film under the crossover wiring.

[0065] Incidentally, compared with the Si semiconductor device of Embodiment 2, the SiC semiconductor device can significantly reduce the thickness of the drift region for the same breakdown voltage, so that the V-groove for forming single crystal islands can be made significantly shallower, and thus the thickness of the device integrated substrate can be significantly reduced. As a result, the following advantages can also be obtained. (1) In the epitaxial growth process of filling the V-groove during the formation of the isolation region of the device integrated substrate, the formed polycrystalline layer can be made thinner, so that the bending caused by the shrinkage of polycrystalline Si during the cooling process at the end of epitaxial growth can be reduced. As a result, processes such as polishing and bonding in the subsequent flattening process for bonding can be easily performed, and the wafer can be made larger in diameter, which is advantageous for cost reduction. (2) In order to obtain a predetermined strength with less damage in a series of manufacturing processes of forming elements on single crystal islands, the thickness of the wafer is, for example, generally about 300 to 400 μm. For example, when the thickness is 300 μm, in a 1.2 kV Si device, the drift region is about 150 μm thick, and the thickness of the device support substrate wafer needs to be reduced to about 150 μm, which is half. However, in the case of a SiC device, since the drift region can be made significantly thinner, it can be made as thick as about 250 μm. As a result, the device support substrate wafer can be made thicker and less likely to bend, and in a series of manufacturing processes of forming elements on single crystal islands, adverse effects such as bending of the wafer due to oxidation and high-temperature heat treatment and damage to the elements due to fluctuations thereof can be reduced.

[0066] Hereinafter, the configuration and characteristics of Embodiment 3 of FIG. 4 will be specifically described. In Embodiment 3, the output element is a stripe-shaped trench gate type SiC reverse conduction MOSFET 300, and most of its main functional parts are formed in the dielectric isolation island. However, since the insulating film at the bottom of this dielectric isolation island is removed, it can be connected to the n+ element support substrate 302 via the n-drain 305, and this n+ element support substrate 302 is connected to the second main electrode 303. Therefore, the element between the first main electrode 320 and the second main electrode 303 can function as a vertical reverse-conducting SiC MOSFET, and the drift resistance can be reduced compared to the case of the horizontal structure as in Embodiment 1. As a result, a significant reduction in loss can be achieved by the on-resistance reduction effect due to this and the on-resistance reduction effect due to the physical properties of SiC.

[0067] In this embodiment, similar to Embodiment 2, a significant portion of the thick insulating film 318 under the bypass wiring 316 that has been formed on the chip surface so far is embedded under the surface of the chip body to form the insulating film 340, and the SCaDFRR 321 is provided directly below it to achieve high breakdown voltage. Furthermore, the thickness of the insulating protection film 318 on the surface of the chip body is reduced to reduce the steps and the number of steps. Since the diffusion rate of impurities in SiC is extremely slow compared to Si, a high-concentration n-type inclined channel stopper has to be formed by a deposition technique such as CVD. As a result, the inclined channel stopper on the main surface of the chip under the wiring has a substantially uniform high carrier concentration (for example, 8×10 cm may be sufficient) compared to the case where it is formed by diffusion, and the difference in carrier concentration (for example, 8×10 cm may be sufficient) with the drift region 308 on the main surface of the chip is extremely large. At this portion, the extension of the channel under the wiring is abruptly stopped, and the surface electric field strength increases rapidly, causing dielectric breakdown and damage to the SiC surface portion, SiO2 film, etc. In this embodiment, in addition to the FRR, a new SCaDFRR 321 is provided to relax the surface electric field strength. This SCaDFRR 321 ion-implants a p-type dopant into the n-type inclined channel stopper on the main surface of the chip to cancel out the carrier concentration, for example, in the range of 1×10 ~5×10 cm to relax the surface electric field strength. 18 cm -3 may be sufficient), and the carrier concentration (for example, 8×10 cm 15 may be sufficient) with the drift region 308 on the main surface of the chip is extremely large. At this portion, the extension of the channel under the wiring is abruptly stopped, and the surface electric field strength increases rapidly, causing dielectric breakdown and damage to the SiC surface portion, SiO2 film, etc. In this embodiment, in addition to the FRR, a new SCaDFRR 321 is provided to relax the surface electric field strength. This SCaDFRR 321 ion-implants a p-type dopant into the n-type inclined channel stopper on the main surface of the chip to cancel out the carrier concentration, for example, in the range of 1×10 -3 to relax the surface electric field strength. ~5×10 cm 16 ~5×10 17 cm -3 to relax the surface electric field strength. In the case of a 1.2 kV SiC device, since the width of the field region is about 15 μm, which is approximately one order of magnitude smaller than that of a Si device, the high-voltage withstand effect of SCaDFRR321 formed on the surface of a tilt channel stopper with a thickness of about 5 μm becomes relatively significantly larger compared to the case of a Si device. Also, if a part of the high-voltage withstand effect by this SCaDFRR321 is used for reducing the thickness of the insulation protection film 318, a larger thickness reduction effect can be obtained compared to the case of Si. As a result, for example, a surface insulation protection oxide film of 12 μm or more is required to achieve a breakdown voltage of 1.2 kV. However, if the thickness of the buried insulation film 340 under the surface is set to about 4 μm and the insulation film thickness reduction effect accompanying the high-voltage withstand by SCaDFRR321 is added, the surface insulation protection oxide film can be made 6 μm or less, and the chip area reduction effect due to the reduction in the number of chip steps can be enjoyed. Also, by using a part of the reduction in the chip area for increasing the number of cells, the low-loss effect can be enjoyed.

[0068] Also, this device is a device that functions as a flywheel diode FWD, which is indispensable for an inverter etc. when the high-voltage main junction is reverse-biased, and corresponds to a reverse-conducting SiC MOSFET as defined in

[0007] . It is not necessary to separately introduce or form an FWD , and cost reduction can be expected due to a significant reduction in the chip area. Since the FWD requires almost the same current capacity as the MOSFET, as a result, the semiconductor chip size of the power integrated circuit semiconductor device can be reduced to approximately about half, and miniaturization and low cost of the power integrated circuit semiconductor device chip can be achieved. Incidentally, the above FWD is composed of a built-in SiC pn diode. However, in such SiC bipolar semiconductor devices, there is an on-voltage degradation phenomenon in which the on-voltage specific to SiC caused by stacking defects inherent in the device increases with time. As a result, the loss of the device during energization increases with time, the efficiency of the applied device such as an inverter deteriorates with time, and if it progresses excessively, the device may be damaged, or the current sharing balance between the devices in the module may collapse and some of the devices may be damaged, leading to damage to the applied device. As a countermeasure for eliminating or suppressing this, the present inventor has developed the MaCH-TEDREC method and disclosed it in Japanese Patent No. 5835679. This method is a method of preventing the expansion of stacking defects inherent in the device, which is the cause of degradation, by raising the device temperature to a temperature equal to or higher than the degradation suppression temperature (for example, 150°C to 200°C or higher in the case of elimination) by energizing only a large number of carriers at the start or during operation of the device. In the case of a reverse-conducting MOSFET using an internal pn diode as the FWD, since only the forward conduction current by a large number of carriers can be independently energized during forward bias, the MaCH-TEDREC method can be applied to eliminate the on-voltage degradation. Thus, this embodiment can eliminate the on-voltage degradation over time specific to SiC bipolar elements and achieve high reliability of the power integrated circuit semiconductor device.

[0069] In addition, the main structural specifications in this embodiment are shown below. For example, the drift layer 308 may have an impurity concentration of 8×10 15 cm -3 · and a thickness of 13 μm. The n+ source region 310 may have an impurity concentration and a thickness of 3×10 19 cm -3 · 0.3 μm, the p body region 309 may have an impurity concentration of 1×10 18 cm -3 · and a thickness of 0.7 μm from the main surface, the n inclined channel stopper layer may have an impurity concentration of 8×10 18 cm -3 · and a thickness of 4 μm, and the n+ drain region 304 may have an impurity concentration of 5×10 19 cm -3· It may be 13 μm thick, the distance from the p - body region to the SiO2 dielectric isolation film may be 25 μm, and the thickness of the SiO2 dielectric isolation film 306 may be 5 μm. Also, the n + element support substrate 302 is 1x10 19 cm -3 · It may be 260 μm thick. In this case, the thickness of the region between the element integration substrate 301, that is, the n + element support substrate 302 and the surface of the chip body is about 40 μm. Note that the thickness of the gate oxide film 311 may be 1000 angstroms.

[0070] Next, the characteristics of the power integrated circuit semiconductor device according to this embodiment will be described. This power integrated circuit semiconductor element chip 300 was mounted in a package fabricated for characteristic measurement and subjected to an operation test. When a forward voltage is applied between the source electrode 320 and the drain electrode 3 03 without applying a gate voltage, a leakage current flows, showing good forward blocking characteristics. The breakdown voltage at room temperature, that is, the voltage showing avalanche breakdown, is about 1.42 kV. Also, the leakage current before avalanche breakdown is 5×10 A / cm or less at room temperature and 1x10 -6 A / cm 2 or less even at a high temperature of 250℃, which is good. -6 A / cm 2 or less at room temperature and 1x10 Also, when a gate voltage is applied and increased in the forward state, the reverse - conducting MOSFET turns on. When energized at a current density of 100 A / cm 2 in the on - state, the on - voltage at room temperature is as low as 0.3 5 V, which is good, and the on - voltage at 200℃ is also as low as 0.51 V, which is good. Also, the on - resistance RonS of the characteristic is extremely small, being 3.5 mΩcm 2 at room temperature. When the gate voltage Vg is set to 20 V and energized at a current density of 300 A / cm 2 , the on - voltage is about 1.5 V, enabling a significant reduction in loss. On the other hand, when energized at a current density of 50 A / cm 2When measured under the condition of energization at a current density of, the turn-on time is 1.5 ns and the turn-off time is about 35 ns, which are short. As a result, the switching time can be reduced and the speed can be increased, and thus the switching loss can be significantly reduced and the loss can be reduced. Also, at a current density of 100 A / cm 2 Even after a 2000-hour energization test is carried out at a current density of, MaCH-TE The DREC method is effective and no on-voltage degradation phenomenon is observed.

[0071] As described above, according to this embodiment, by applying SCaDFRR and an embedded insulating film to the SiC reverse-conducting MOSFET, which is the output element of the SiC power integrated circuit semiconductor device chip, while achieving high breakdown voltage, the step and the number of steps are reduced by reducing the thickness of the insulating film on the surface of the chip body, achieving a reduction in chip area and a reduction in loss. Also, by applying the novel single-crystal island crystal plane structure and the novel polycrystal plane / single-crystal plane mixed bonding structure SP&S-DBS, a thick oxide film is easily formed under the crossover wiring, making it easy to achieve high breakdown voltage, and a dielectric isolation type integrated circuit semiconductor device with a small bend, low cost, good quality, and strong adhesive strength can be realized. Furthermore, during the reflux of the inverter, the diode composed of the p-body and n-drift layer inherent in the element can be utilized as the FWD diode, eliminating the need to separately provide a new diode, significantly reducing the semiconductor chip size of the power integrated circuit semiconductor device, and achieving lower cost. Also, high reliability can be achieved by eliminating on-voltage degradation.

[0072] (Embodiment 4) FIG. 5 is a schematic cross-sectional view showing the main part of a SiC dielectric isolation type power integrated circuit semiconductor device chip with a designed breakdown voltage of 1.2 kV and a current capacity of about 80 A, which is fabricated using the SiC semiconductor according to Embodiment 4, centering on the output element. In the event of an accident or the like, when the power conversion equipment equipped with this chip suddenly has a large current that exceeds the normal operating time An output vertical reverse-conducting M OSFET is intended to be able to handle cases where supply is necessary. Compared with Embodiment 3, the differences in the element structure are that the third main electrode 415 is provided in the adjacent isolation region 417 and externally connected to the second electrode 403 by wire bonding, the isolation region 417 is made of p-type SiC with a polarity opposite to that of the n-type element support substrate 402, and p-collectors 404 of the reverse-conducting IGBT are provided on both sides of the n-drain 405. Functionally, during normal operation, the vertical reverse-conducting MO SFET between the first main electrode 420 and the second main electrode 403 operates. During large current supply in the event of an accident or the like, the reverse-conducting IGBT between the first main electrode 420 and the second main electrode 40 3 and the third main electrode 415 also operates, and for a predetermined relatively short time until the protection device starts, the conduction current of the IGBT is increased to the conduction current of the vertical reverse-conducting MOSFET to cope with the accident. When the reverse-conducting IGBT operates, the n-drain 405 of the vertical reverse-conducting MOSFET and the element support substrate 402 function as a short-circuit part to accelerate the discharge of residual carriers during turn-off and reduce losses.

[0073] Figure 5 includes all the novel matters of the present invention described in Embodiment 2 and Embodiment 3 in Embodiment 4. That is, a novel SCaDFRR and an embedded insulating film, a novel single-crystal island crystal plane structure, a novel multi-crystal plane / single-crystal plane mixed bonding structure SP&P-DBS, a novel reverse-conducting IGBT structure provided with a third main electrode, etc. are all included, achieving equivalent effects. Also, except for the differences in the element structure within the single-crystal island and the above-mentioned ones compared with Embodiment 3, almost all the specifications, including the values, are the same.

[0074] As for the element area, the area of the single-crystal island is the same, but the part of the third main electrode has increased. Also, Since p - collectors are provided on both sides, the width of the n - drain becomes about 80%, and the rated current during operation is reduced by about 20%. However, during an accident, a reverse - conducting IGBT current can flow. For example, at an applied voltage of 7V, the element temperature rises due to self - heating, so the on - resistance of the MOSFET increases, and the conduction current does not flow in proportion to the applied voltage. However, the on - resistance of the reverse - conducting IGBT is contributed by the conductivity modulation effect and hardly changes even when the element temperature changes. As a result, during an accident, although it is for a short time limited by the thermal resistance of the package etc., an energization current of about 190A, nearly twice that of the reverse - conducting MOSFET of Embodiment 3, can be expected. Also, by eliminating the snap - back phenomenon and the on - voltage degradation of the IGBT and FWD, high reliability can be achieved. Furthermore, the FWD has a slight decrease in conduction current but is at a level where there is no practical problem, and there is no need to separately provide a new diode, so the SiC chip size can be significantly reduced and low cost can be achieved. In this embodiment, by changing the ratio of the width of the n - drain 405 to the width of the p - collector 404 according to the application, the ratio of the low - on - resistance MOSFET function to the current - carrying function can be set arbitrarily to some extent. In some cases, the third main electrode can be connected to the second main electrode, and only the MOSFET function between the first main electrode and the second main electrode can be enjoyed. As described above, according to this embodiment, although it is for a short time limited by the thermal resistance of the package etc. during an accident, a larger energization current can be expected compared to the reverse - conducting MOSFET of Embodiment 3. Also, similar to Embodiment 3, by applying SCaDFRR and the buried insulating film, high voltage resistance can be achieved, and at the same time, reduction of the insulating film thickness on the surface of the chip body can be achieved, reducing the step and the number of steps.

[0075] In this embodiment, by changing the ratio of the width of the n - drain 405 to the width of the p - collector 404 according to the application, the ratio of the low - on - resistance MOSFET function to the current - carrying function can be set arbitrarily to some extent. In some cases, the third main electrode can be connected to the second main electrode, and only the MOSFET function between the first main electrode and the second main electrode can be enjoyed.

[0076] As described above, according to this embodiment, although it is for a short time limited by the thermal resistance of the package etc. during an accident, a larger energization current can be expected compared to the reverse - conducting MOSFET of Embodiment 3. Also, similar to Embodiment 3, by applying SCaDFRR and the buried insulating film, high voltage resistance can be achieved, and at the same time, reduction of the insulating film thickness on the surface of the chip body can be achieved, reducing the step and the number of steps. ​ It is possible to achieve a reduction in chip area and low loss. Also, high reliability can be achieved by eliminating the snapback phenomenon and on-voltage degradation. Furthermore, when the inverter is refluxed, the diode composed of the p-body and the n-drift layer inherent in the element can be utilized as the FWD diode, eliminating the need to provide a separate new diode and significantly reducing the semiconductor chip size of the power integrated circuit semiconductor device, thereby reducing costs.

[0077] (Embodiment 5) FIG. 6 is a cross-sectional view schematically showing the main part of an output element of an SiC dielectric isolation type power integrated circuit semiconductor device chip with a rated breakdown voltage of 1.2 kV and a current capacity of 60 A class, which is fabricated using the SiC semiconductor according to Embodiment 5, centered on the output element. Since the SiC-IGBT has an extremely small temperature dependence of the on-resistance compared to the SiC-MOSFET, it is a vertical reverse-conducting IGBT for output intended for applications in the high-temperature region. The differences in the element structure compared to Embodiment 4 are that the separation region 517 is n-type SiC with a polarity opposite to that of the p-type element support substrate 402, an n-short circuit portion 505 of the reverse-conducting MOSFET is provided on both sides of the p-collector 504, and the element support substrate 502 is made of polycrystalline SiC. When the reverse-conducting IGBT operates, the residual carriers at turn-off can be quickly discharged through this short circuit portion 505 and the third main electrode 515 externally connected to the second main electrode 503, thereby achieving low loss. In this Embodiment 5, polycrystalline SiC is used as the element support substrate 502 in the novel polycrystalline surface / single-crystalline surface hybrid bonding structure SP&P-DBS of the present invention. However, by increasing the bonding temperature, a bonding strength comparable to that in the case of using a single-crystalline support substrate can be realized, and bending and the like are also within the allowable level, with no practical problems. The merit of significantly reducing costs compared to a single-crystalline element support substrate is extremely large.

[0078] (Embodiment 6) ​​​​FIG. 9 is a schematic cross-sectional view showing the main part of the SiC dielectric isolation type power integrated circuit semiconductor device chip 600 centered on the output element fabricated using the SiC semiconductor according to Embodiment 6. The output element is a SiC reverse-conducting MOSFET with a designed breakdown voltage of 1.2 kV and a current capacity of about 100 A. It is a vertical structure reverse-conducting MOSFET with a trench gate structure and has a stripe shape. The width of the single crystal island integrating this output element is about 2.5 mm, and the length of the single crystal island is 5 mm. Compared with Embodiment 3, Embodiment 6 is the same in all structural specifications and manufacturing process flows of the integrated circuit semiconductor device chip 600 and the SiC reverse-conducting MOSFET of the output element, and the characteristics of the manufactured output element are also almost the same, except that the side surface of the single crystal island is composed of the {11-22} crystal plane and when forming the separation region of the element integration substrate 701 without using a bonding substrate, the epitaxial growth layer is thickened to make the element integration substrate 701 also serve as an element support substrate. The side surface of the single crystal island composed of the {11-22} crystal plane in Embodiment 6 has a larger inclination angle with respect to the C plane on the surface of the single crystal island and the Si plane on the back surface than the {0-33-8} plane. Therefore, the bottom area of the single crystal island can be increased, so that the on-resistance of the output element can be reduced, and at the same time, the volume of the single crystal island can be increased, so that the heat storage capacity can be increased and the power withstand can be increased. This feature becomes more significant as the breakdown voltage of the element increases because the drift layer becomes thicker and as a result the single crystal island becomes thicker. Of course, similar effects can be obtained by using crystal planes other than {11-22}, such as the {10-12} plane and the {10-11} plane, which have a larger inclination angle with respect to the surface of the single crystal island than the {0-33-8} plane. Also, although Embodiment 6 cannot enjoy various advantages of using a bonding substrate as in the previous Embodiments 1 to 5, there is an advantage of reducing the number of manufacturing steps in that the thick element integration substrate of this embodiment can be formed by simply increasing the epitaxial time for forming the separation region of the element integration substrate.

[0079] (Embodiment 7) FIG. 7 shows a semiconductor device according to Embodiment 7, and shows the output element configuration of one phase of a Si dielectric isolation type single-phase inverter integrated circuit semiconductor device configured using a Si semiconductor element with a breakdown voltage of 1.2 kV and a current capacity of about 30 A. All the output elements are reverse-conducting Si-IGBTs with a trench gate structure. The upper arm is a reverse-conducting Si-IGBT with a vertical structure, and the lower arm is a reverse-conducting Si-IGBT with a horizontal structure. In FIG. 7, a simplified element structure is described, and the numbers and arrows of each structural factor are omitted. However, the reverse-conducting Si-IGBT with a horizontal structure has almost the same element configuration as the IGBT in Embodiment 1 of FIG. 1 except for the element size and the fact that it is formed on a p-type single crystal element support substrate. The reverse-conducting Si-IGBT with a vertical structure also has almost the same element configuration as the IGBT in Embodiment 2 of FIG. 2 except for the element size. The manufacturing process flow of the element structure in FIG. 7 is almost the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a reverse-conducting Si-IGBT with a horizontal structure larger than the reverse-conducting Si-IGBT with a vertical structure is created in the same manner as the single crystal island 260 for the small control circuit element in FIG. 3, and a wafer for manufacturing a chip for an integrated circuit semiconductor device in FIG. 3(5) is completed. Thereafter, a reverse-conducting Si-IGBT with a horizontal structure is also created in the single crystal island by a process flow almost the same as the element portion of the reverse-conducting Si-IGBT with a vertical structure formed in the single crystal island.

[0080] The upper arm of each phase of the single-phase inverter has the collectors of the reverse-conducting Si-IGBTs of each layer connected in parallel to the high-potential wiring of the power supply. Therefore, an element structure in which the collector 204 can be connected in parallel via the element support substrate to the second main electrode (collector electrode) 203 in FIG. 2 is suitable. On the other hand, the lower arm of each phase is connected in parallel to the low-high potential wiring of the power supply, but the potential of the collector changes during the operation of the inverter. Therefore, a reverse-conducting Si-IGBT with a horizontal structure in which the second main electrode (collector electrode) 203 is independent from other phases is suitable. For this reason, the structure in FIG. 7 is set as a suitable arm structure for one phase. Therefore, a reverse-conducting Si-IGBT with a horizontal structure in which the second main electrode (collector electrode) 203 is independent from other phases is suitable. For this reason, the structure in FIG. 7 is set as a suitable arm structure for one phase. Therefore, a reverse-conducting Si-IGBT with a horizontal structure in which the second main electrode (collector electrode) 203 is independent from other phases is suitable. For this reason, the structure in FIG. 7 is set as a suitable arm structure for one phase. Therefore, a reverse-conducting Si-IGBT with a horizontal structure in which the second main electrode (collector electrode) 203 is independent from other phases is suitable. For this reason, the structure in FIG. 7 is set as a suitable arm structure for one phase. Therefore, a reverse-conducting Si-IGBT with a horizontal structure in which the second main electrode (collector electrode) 203 is independent from other phases is suitable. For this reason, the structure in FIG. 7 is set as a suitable arm structure for one phase. Compared with the vertical structure reverse-conducting Si-IGBT, the horizontal structure reverse-conducting Si-IGBT has a larger drift resistance. Therefore, to make the current capacities of the 1.2 kV elements of the upper and lower arms approximately the same, it is necessary to increase the element area by about three times so that the on-resistances can be made approximately equal. According to the preliminary calculation results, it is expected that a single-chip single-phase inverter of 600 V, 5 kW, and a PWM frequency of about 20 kHz can be realized with a chip size of 20 mm x 20 mm. As a result, it is expected to make a great contribution to the miniaturization, weight reduction, and low loss of various motor-equipped devices such as home appliances, office equipment, vehicles, and industrial equipment.

[0081] (Embodiment 8) The semiconductor device according to Embodiment 8 of FIG. 8 is a SiC dielectric isolation type three-phase inverter integrated circuit semiconductor device configured using a SiC semiconductor element with a breakdown voltage of 1.2 kV and a current capacity of about 80 A. The output element configuration of one phase is shown. All the output elements have a trench gate structure. The upper arm is a vertical structure reverse-conducting SiC-MOSFET, and the lower arm is a horizontal structure reverse-conducting SiC-MOS FET. Although a simplified structure is shown in FIG. 8, the vertical structure reverse-conducting SiC-M OSFET has substantially the same element configuration as the SiC-MOSFET of Embodiment 3 in FIG. 4 except for the element size. Also, the horizontal structure reverse-conducting SiC-IGBT is composed of SiC semiconductors instead of Si, and the values of each configuration factor become the values corresponding to the SiC element, and the element configuration within the single crystal island is substantially the same as that of the IGBT of Embodiment 1 in FIG. 1 except for the element size. OSFET has substantially the same element configuration as the SiC-MOSFET of Embodiment 3 in FIG. 4 except for the element size. Also, the horizontal structure reverse-conducting SiC-IGBT is composed of SiC semiconductors instead of Si, and the values of each configuration factor become the values corresponding to the SiC element, and the element configuration within the single crystal island is substantially the same as that of the IGBT of Embodiment 1 in FIG. 1 except for the element size. OSFET has substantially the same element configuration as the SiC-MOSFET of Embodiment 3 in FIG. 4 except for the element size. Also, the horizontal structure reverse-conducting SiC-IGBT is composed of SiC semiconductors instead of Si, and the values of each configuration factor become the values corresponding to the SiC element, and the element configuration within the single crystal island is substantially the same as that of the IGBT of Embodiment 1 in FIG. 1 except for the element size. The manufacturing process flow of the element structure in FIG. 8 is substantially the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a horizontal structure reverse-conducting SiC-MOSFET larger than the vertical structure reverse-conducting SiC-MOSFET is created in the same way as the single crystal island 260 for small control circuit elements, and the wafer for the integrated circuit semiconductor device chip in FIG. 3(5) is completed. Then, a single The manufacturing process flow of the element structure in FIG. 8 is substantially the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a horizontal structure reverse-conducting SiC-MOSFET larger than the vertical structure reverse-conducting SiC-MOSFET is created in the same way as the single crystal island 260 for small control circuit elements, and the wafer for the integrated circuit semiconductor device chip in FIG. 3(5) is completed. Then, a single The manufacturing process flow of the element structure in FIG. 8 is substantially the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a horizontal structure reverse-conducting SiC-MOSFET larger than the vertical structure reverse-conducting SiC-MOSFET is created in the same way as the single crystal island 260 for small control circuit elements, and the wafer for the integrated circuit semiconductor device chip in FIG. 3(5) is completed. Then, a single The manufacturing process flow of the element structure in FIG. 8 is substantially the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a horizontal structure reverse-conducting SiC-MOSFET larger than the vertical structure reverse-conducting SiC-MOSFET is created in the same way as the single crystal island 260 for small control circuit elements, and the wafer for the integrated circuit semiconductor device chip in FIG. 3(5) is completed. Then, a single The manufacturing process flow of the element structure in FIG. 8 is substantially the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a horizontal structure reverse-conducting SiC-MOSFET larger than the vertical structure reverse-conducting SiC-MOSFET is created in the same way as the single crystal island 260 for small control circuit elements, and the wafer for the integrated circuit semiconductor device chip in FIG. 3(5) is completed. Then, a single The manufacturing process flow of the element structure in FIG. 8 is substantially the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a horizontal structure reverse-conducting SiC-MOSFET larger than the vertical structure reverse-conducting SiC-MOSFET is created in the same way as the single crystal island 260 for small control circuit elements, and the wafer for the integrated circuit semiconductor device chip in FIG. 3(5) is completed. Then, a single The manufacturing process flow of the element structure in FIG. 8 is substantially the same as the process flow in FIG. 3. That is, although not shown, a single crystal island for a horizontal structure reverse-conducting SiC-MOSFET larger than the vertical structure reverse-conducting SiC-MOSFET is created in the same way as the single crystal island 260 for small control circuit elements, and the wafer for the integrated circuit semiconductor device chip in FIG. 3(5) is completed. Then, a single The process is almost the same as that for the element part of the vertical structure reverse conducting SiC-MOSFET formed in the crystal island. Lateral reverse conducting SiC MOSFETs are also fabricated within the single crystal island by flow.

[0082] The upper arm of each phase of the three-phase inverter is connected to the high-potential wiring of the power supply, and the reverse-conducting SiC-MOSF Since the collectors of the ETs are connected in parallel, the element is connected to the second main electrode (drain electrode) 203 in FIG. A device structure in which the drains 204 can be connected in parallel via a supporting substrate is preferable. The lower arm of the collector is connected in parallel to the low and high potential wiring of the power supply, but Since the potential of the second main electrode (drain electrode) 203 is independent of the other phases, Therefore, the most suitable structure is the reverse conducting SiC-MOSFET shown in FIG. This sets out the structure of 8. Compared to vertical reverse conducting SiC MOSFETs, lateral reverse conducting SiC MOSFETs have a Therefore, in order to make the current capacity of the 1.2 kV elements of the upper and lower arms almost the same, The size of the single crystal island of the lateral reverse conducting SiC-MOSFET is approximately It is necessary to increase the power supply by about 1.9 times. The estimated power supply voltage is 600V, 30kW, and PWM frequency is 1.9 times. The 20kHz class one-chip three-phase inverter is a 20mm x 20mm device despite being a three-phase configuration. It is expected that this can be achieved at chip size. As a result, various motor-equipped devices for home appliances, offices, vehicles, industrial use, etc. can be made smaller, lighter, and have lower loss. - It can make a significant contribution to high reliability.

[0083] (Embodiment 9) The semiconductor device according to the ninth embodiment is a SiC dielectrically isolated three-phase inverter integrated circuit semiconductor device configured using SiC semiconductor elements having a withstand voltage of 1.2 kV and a current capacity of 60 A, although not shown. All the output elements constituting the single-phase section are reverse-conducting SiC-IGBTs with a trench gate structure. Among them, the upper arm is a vertical-structure reverse-conducting SiC-IGBT, and the lower arm is a horizontal-structure reverse-conducting Si C-IGBT. The element support substrate is composed of a p+ polycrystalline substrate. The vertical-structure reverse-conducting Si C-IGBT has almost the same element configuration as the IGBT in Embodiment 5 of FIG. 6. The horizontal-structure reverse-conducting SiC-IGBT is the same as that in Embodiment 1 of FIG. 1 in terms of element size and the structure factor with corresponding values for the SiC semiconductor, except that it is formed on a p-type single-crystalline element support substrate. In addition, since there are few differences from the above Embodiment 6, the description is omitted. However, despite the large current capacity of 60A and the three-phase configuration, the on-resistance reduction effect due to the conductivity modulation of the IGBT contributes significantly, and it is expected that a 600V, 20kW, PWM frequency 20 kHz-class one-chip three-phase inverter suitable for high-temperature applications can be realized with a chip size of 20mm x 20mm. As a result, it can greatly contribute to the miniaturization, weight reduction, low loss, and high reliability of various motor-mounted devices for home appliances, office equipment, vehicles, and industries. As described above, the present invention has been described based on the first to ninth embodiments. However, it is obvious to those skilled in the art that the present invention is not limited to these and various modifications and applications can be easily made. For example,

[0084] by changing the numerical values of the structural specifications or modifying the cell structure, it can be naturally applied to a power integrated circuit semiconductor device using a reverse-conducting semiconductor element with a breakdown voltage higher than 2kV or, conversely, a low breakdown voltage lower than 1k V as an output element. Although the n-type reverse-conducting SiC-IGBT has been mentioned, it is also obvious that the same can be developed for a p-type reverse-conducting SiC-IGBT with different polarities. The cell shape has also been mentioned as a It goes without saying that it can be deformed and applied to various mesh shapes including honeycomb shapes other than the trib shape. In addition, it goes without saying that it can also be applied to semiconductor devices with various gates such as planar gates other than the trench gate type IGBT and MOSFET mentioned above. Furthermore, although reverse conduction SiC-IGBT and reverse conduction SiC-MOSFET have been mentioned as reverse conduction semiconductor devices, other transistors such as static induction transistors and junction gate transistors can be developed, and it can also be developed for reverse conduction semiconductor devices using other wide bandgap semiconductors such as GaN and diamond. Moreover, although the dielectric isolation type integrated circuit semiconductor device called EPIC has been mentioned, the crystal plane structure of the single crystal island is not limited to the structure mentioned in the present invention, and it can be easily deduced by those skilled in the art that the side surface can be constituted by a crystal plane having a specific constant crystal plane angle with respect to the front and back surfaces of the single crystal island. Also, although 4H-SiC has been mentioned, it can be easily deduced that it can also be applied and developed to other polytype SiC crystals. Furthermore, it is easy for those skilled in the art to apply it to SOI other than EPIC and other dielectric isolation type integrated circuit semiconductor devices, and it can also be deformed and applied to pn junction isolation type integrated circuit semiconductor devices. In addition, although the dielectric isolation type integrated circuit semiconductor device called EPIC has been mentioned, the crystal plane structure of the single crystal island is not limited to the structure mentioned in the present invention, and it can be easily deduced by those skilled in the art that the side surface can be constituted by a crystal plane having a specific constant crystal plane angle with respect to the front and back surfaces of the single crystal island. Also, although 4H-SiC has been mentioned, it can be easily deduced that it can also be applied and developed to other polytype SiC crystals. Furthermore, it is easy for those skilled in the art to apply it to SOI other than EPIC and other dielectric isolation type integrated circuit semiconductor devices, and it can also be deformed and applied to pn junction isolation type integrated circuit semiconductor devices. In addition, although the dielectric isolation type integrated circuit semiconductor device called EPIC has been mentioned, the crystal plane structure of the single crystal island is not limited to the structure mentioned in the present invention, and it can be easily deduced by those skilled in the art that the side surface can be constituted by a crystal plane having a specific constant crystal plane angle with respect to the front and back surfaces of the single crystal island. Also, although 4H-SiC has been mentioned, it can be easily deduced that it can also be applied and developed to other polytype SiC crystals. Furthermore, it is easy for those skilled in the art to apply it to SOI other than EPIC and other dielectric isolation type integrated circuit semiconductor devices, and it can also be deformed and applied to pn junction isolation type integrated circuit semiconductor devices. In addition, although the dielectric isolation type integrated circuit semiconductor device called EPIC has been mentioned, the crystal plane structure of the single crystal island is not limited to the structure mentioned in the present invention, and it can be easily deduced by those skilled in the art that the side surface can be constituted by a crystal plane having a specific constant crystal plane angle with respect to the front and back surfaces of the single crystal island. Also, although 4H-SiC has been mentioned, it can be easily deduced that it can also be applied and developed to other polytype SiC crystals. Furthermore, it is easy for those skilled in the art to apply it to SOI other than EPIC and other dielectric isolation type integrated circuit semiconductor devices, and it can also be deformed and applied to pn junction isolation type integrated circuit semiconductor devices.

Industrial Applicability

[0085] The present invention can be used in various inverters such as those for EVs, HEVs, and electric railway vehicles, and by significantly reducing the size and weight and loss, efficiency can be improved and the driving range can be extended. Also, efficiency can be improved by reducing the size and weight of power conditioners for solar power generation and wind power generation. Furthermore efficiency can be improved by reducing the size and weight of power conditioners for solar power generation and wind power generation. Furthermore it can be applied to the power supplies and inverters of home appliances and office equipment to reduce the size and weight and loss. As such, the industrial applicability is extremely large.

Explanation of Signs

[0086] [1]. 101, 201, 301, 401, 501, 601: Elementary subset integrated substrate. [2]. 102, 202, 302, 402, 502, 602: Element support substrate. [3]. 103, 203, 303, 403, 503, 603: First main electrode. [4]. 104, 204, 304, 404, 504, 604: p+ collector layer. [5]. 105, 205, 305, 405, 505, 605: n+ short circuit part or n+ drain. [6]. 106, 206, 306, 406, 506, 606: Insulating isolation oxide film. [7]. 107, 207, 307, 407, 507, 607: n buffer layer. [8]. 108, 208, 308, 408, 508, 608: n drift layer. [9]. 109, 209, 309, 409, 509, 609: p body region.

[10] . 110, 210, 310, 410, 510, 610: n+ emitter region.

[11] . 111, 211, 311, 411, 511, 611: Gate oxide film.

[12] . 112, 212, 312, 412, 512, 612: Polycrystalline Si electrode.

[13] . 113, 213, 313, 413, 513, 613: Gate electrode.

[14] . 114, 214, 314, 414, 514, 614: Interlayer insulating film.

[15] . 115, 215, 315, 415, 515, 615: Third main electrode.

[16] . 116, 216, 316, 416, 516, 616: Crossing wiring.

[17] . 117, 217, 317, 417, 517, 617: Separation region.

[18] . 118, 218, 318, 418, 518, 618: Insulating film under crossing wiring.

[19] . 119, 219, 319, 419, 519, 619: Internal wiring.

[20] .120, 220, 320, 420, 520, 620: First main electrode.

[21] .121, 221, 321, 421, 521, 621: Surface carrier concentration reduction electric field relaxation region (SCaDFRR).

[22] .122, 222, 322, 422, 522, 622: Electrode of the element for control circuit.

[23] .123, 223, 323, 423, 523, 623: Field plate.

[24] .124, 224, 324, 424, 524, 624: Surface electric field relaxation layer (abbreviation: FRR).

[25] .125, 225, 325, 425, 525, 625: Inclined channel stopper

[26] .140, 240, 340, 440, 540, 640: Buried insulating film.

[27] .230: Single crystal main substrate.

Claims

1. A dielectric isolation type integrated circuit semiconductor device, wherein a semiconductor chip body is configured by laying single crystal islands via a dielectric isolation film in a separation region, the side surfaces of the single crystal islands have an inclination at a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components in the single crystal islands are connected by wirings provided on a surface insulating protection film on the surface of the semiconductor chip body and the integrated circuit components in other single crystal islands. In the integrated circuit semiconductor device, In the wiring among the above wirings that are connected via a junction (such as a pn junction or a Schottky junction) that causes a rectifying action with the single crystal island, when defining a wiring portion that crosses over the separation region of the semiconductor chip body, the dielectric isolation film, and the channel stopper in the single crystal island as a crossover wiring, A power integrated circuit semiconductor device, characterized by including an integrated circuit component provided with a surface carrier concentration reduction electric field relaxation region (SCaDFRR) having the same polarity as the channel stopper layer and a lower impurity concentration on the surface of the channel stopper layer under the crossover wiring.

2. According to

1. , an embedded insulating protection film is provided between the surface carrier concentration reduction electric field relaxation region (SCaDFRR) on the surface of the channel stopper of the integrated circuit component and the surface of the semiconductor chip body, and this embedded insulating protection film is in contact with the surface insulating protection film on the surface of the semiconductor chip body. A power integrated circuit semiconductor device characterized by this.

3. According to

1. or

2. , The semiconductor chip body of the dielectric isolation type integrated circuit semiconductor device is configured by laminating and bonding an element integrated substrate in which the single crystal islands including the integrated circuit components are laid in the separation region, and an element support substrate having both the support function and the conductive path function of the element integrated substrate. The integrated circuit component includes a lateral IGBT in a specific single crystal island of the element integrated substrate, a buffer layer is provided in contact with the collector at least on the bottom surface of the lateral IGBT, and a part of the buffer layer is exposed on the semiconductor chip surface and connected to the electrode of the collector of the lateral IGBT to be short-circuited with the collector. A power integrated circuit semiconductor device characterized by this.

4. According to

1. or

2. , The semiconductor chip body of the dielectric isolation type integrated circuit semiconductor device is configured by laminating and bonding an element integrated substrate in which single crystal islands including the integrated circuit constituent elements are spread over the separation region, and an element support substrate having both a support function and a conductive path function of the element integrated substrate. The element integrated substrate is provided with a predetermined single crystal island obtained by removing the dielectric isolation film at the bottom of the single crystal island in order to integrate vertical semiconductor elements. The main functional part of the vertical semiconductor element connected to the first main electrode and the control electrode on the surface of the predetermined single crystal island is formed between the island surface of the predetermined single crystal island and the buffer at the bottom of the island. The drain or collector of the vertical semiconductor element is connected to the buffer and exposed on the bonding surface of the element integrated substrate and bonded to the element support substrate. A second main electrode provided on the back surface of the element support substrate opposite to the bonding surface is connected to the drain or collector of the element integrated substrate via the element support substrate, and a vertical semiconductor element is formed between the first main electrode and the second main electrode. A power integrated circuit semiconductor device characterized by this.

5. In

4. , the vertical semiconductor element is a bipolar element, the first main electrode is formed on the surface of the predetermined single crystal island where the main functional part of the element integrated substrate is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body. A third main electrode is formed on the surface of the channel stopper of the predetermined single crystal island where the main functional part is formed or on the surface of the separation region adjacent to the predetermined single crystal island through the dielectric isolation film, and a part of the separation region is connected to the buffer at the bottom of the island of the predetermined single crystal island and the collector. The drift layer of the main functional part and the separation region of the element integrated substrate have the same polarity, but the element support substrate has the opposite polarity. When the second main electrode and the third main electrode are electrically connected, the element between the first main electrode, the second main electrode, and the third main electrode constitutes a vertical reverse conduction semiconductor element. A power integrated circuit semiconductor device characterized by this.

6. In claim 4, the vertical semiconductor device is a unipolar device, the first main electrode is formed on the surface of the predetermined single crystal island where the main functional part of the device integrated substrate is formed, and the second main electrode is formed on the back surface of the element support substrate of the semiconductor chip body. A third main electrode is formed on the surface of the channel stopper of the predetermined single crystal island where the main functional part is formed or on the surface of the adjacent isolation region via the dielectric isolation film, and a part of the isolation region is connected to the buffer at the bottom of the island of the predetermined single crystal island and the drain. The drift layer of the main functional part and the element support substrate have the same polarity, but the isolation region of the device integrated substrate has the opposite polarity. By electrically connecting the second main electrode and the third main electrode, the device between the first main electrode, the second main electrode, and the third main electrode constitutes a vertical reverse conduction semiconductor device. A power integrated circuit semiconductor device characterized by this.

7. The power integrated circuit semiconductor device according to claim 5 or claim 6, characterized in that the vertical reverse conduction semiconductor device has a single buffer layer or a multi-buffer layer composed of two or more layers.

8. The power integrated circuit semiconductor device according to any one of claims 3 to 7, characterized in that the semiconductor chip body has a structure (SP&S-DBS) in which the device integrated substrate having a mixed attachment surface of a polycrystalline surface and a single crystal surface and the element support substrate having a single crystal surface attachment surface are bonded, or a structure (SP&P-DBS) in which the device integrated substrate having a mixed attachment surface of a polycrystalline surface and a single crystal surface and the element support substrate having a polycrystalline surface attachment surface are bonded.

9. The power integrated circuit semiconductor device according to any one of claims 1 to 8, characterized in that the semiconductor chip body is composed of a SiC semiconductor.

10. In claim 9, the single crystal island has a single crystal island crystal plane structure in which the surface is composed of a C plane, that is, a crystal plane of (000-1) plane, the side surface is composed of {0-33-8} plane, and the bottom surface of the single crystal island is composed of a Si plane, that is, (0001) plane. A power integrated circuit semiconductor device characterized by this.

11. A dielectric isolation type integrated circuit semiconductor device, wherein the semiconductor chip body is formed by laying single crystal islands via a dielectric isolation film in a separation region, the side surfaces of the single crystal islands have a predetermined angle determined by the crystal orientation with respect to the surface of the semiconductor chip body, and the integrated circuit components in the single crystal islands are connected to the integrated circuit components in other single crystal islands and the wiring provided on the surface insulation protection film on the surface of the semiconductor chip body. A power integrated circuit semiconductor device, characterized in that the semiconductor chip body is composed of a SiC semiconductor, the chip surface is formed using a crystal plane of the C plane, i.e., the (000-1) plane, the side surface is formed by the {0-33-8} plane, and the bottom surface of the single crystal island has a single crystal island crystal plane structure formed by the Si plane, i.e., the (0001) plane.

12. A power integrated circuit semiconductor device incorporating an inverter circuit, wherein each phase arm configuration of the inverter circuit includes an upper arm configured to include the vertical semiconductor element or the vertical reverse conduction semiconductor element according to any one of

4. to

10. , and a lower arm configured to include the lateral reverse conduction semiconductor element according to

3. .

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