Semiconductor device, method for manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device capable of reducing a switching loss.SOLUTION: A semiconductor device comprises: a silicon carbide layer that has a first surface and a second surface opposed to the first surface; a gate electrode; and a gate insulating layer. The silicon carbide layer includes: a first trench that has a first region extending in a first direction, a second region connected to the first region, and a third region connected to the second region and extending in the first direction, and in which a second width in a second direction of the second region is larger than a first width in the second direction of the first region and a third width in the second direction of the third region; an n-type first silicon carbide region; a p-type second silicon carbide region between the first silicon carbide region and the first surface; an n-type third silicon carbide region between the second silicon carbide region and the first surface; a p-type fourth silicon carbide region between the first trench and the first silicon carbide region; and a fifth silicon carbide region located in the second direction in the second region to electrically connect between the second and fourth silicon carbide regions.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator.

Background Art

[0002] Silicon carbide (SiC) is expected as a material for next-generation semiconductor devices. Silicon carbide has excellent physical properties such as a bandgap about three times that of silicon, a breakdown electric field strength about ten times that of silicon, and a thermal conductivity about three times that of silicon. By utilizing these physical properties, a semiconductor device capable of low-loss and high-temperature operation can be realized.

[0003] In a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a trench gate structure in which a gate electrode is provided in a trench is applied to realize a low on-resistance. By applying the trench gate structure, the channel area per unit area increases and the on-resistance is reduced.

[0004] Also, in a vertical MOSFET, reduction of switching loss is desired for low loss.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing switching loss.

Means for Solving the Problems

[0007] The semiconductor device according to the embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface facing the first surface. The silicon carbide layer has a first region located on the side of the first surface and extending in the first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction. A first trench has a second width in the second direction of the second region that is larger than a first width in the second direction of the first region and a third width in the second direction of the third region. The semiconductor device also includes an n-type first silicon carbide region, a p-type second silicon carbide region located between the first silicon carbide region and the first surface and having a distance from the second surface to the first trench that is larger than the distance from the second surface, an n-type third silicon carbide region located between the second silicon carbide region and the first surface, a p-type fourth silicon carbide region located between the first trench and the first silicon carbide region, and a fifth silicon carbide region located in the second direction of the second region and electrically connecting the second silicon carbide region and the fourth silicon carbide region. The semiconductor device further includes a gate electrode located in the first trench, a gate insulating layer located between the gate electrode and the silicon carbide layer, a first electrode located on the side of the first surface of the silicon carbide layer and in contact with the third silicon carbide region, and a second electrode located on the side of the second surface of the silicon carbide layer. Well, the second silicon carbide region has a first part and a second part. The first part is located between the first trench and the second part. The p-type impurity concentration of the second part is higher than that of the first part, and the fifth silicon carbide region is in contact with the second part. 。

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] Also, in the following description, n ++ n + n, n - and p ++ p + p, p - When the notations of, p, p are used, these notations represent the relative levels of the impurity concentrations in each conductivity type. That is, n ++ has a relatively higher n-type impurity concentration than n + , n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p ++ has a relatively higher p-type impurity concentration than p + , p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that the n + type and the n - type may be simply referred to as the n-type, and the p + type and the p - type may be simply referred to as the p-type.

[0011] The impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative level of the impurity concentration can be determined, for example, from the level of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Also, the distance such as the width and depth of the impurity region can be obtained, for example, by SIMS. Also, the distance such as the width and depth of the impurity region can be obtained, for example, from the SCM image.

[0012] The depth of the trench, the thickness of the insulating layer, etc. can be measured, for example, on the images of SIMS or a Transmission Electron Microscope (TEM).

[0013] In addition, in this specification, the "p-type impurity concentration" of the p-type silicon carbide region means the net p-type impurity concentration obtained by subtracting the n-type impurity concentration of the region from the p-type impurity concentration of the region. Also, the "n-type impurity concentration" of the n-type silicon carbide region means the net n-type impurity concentration obtained by subtracting the p-type impurity concentration of the region from the n-type impurity concentration of the region.

[0014] (First Embodiment) The semiconductor device of the first embodiment is a silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface facing the first surface, the silicon carbide layer having a first region located on the side of the first surface and extending in the first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction, the second width of the second region in the second direction being larger than the first width of the first region in the second direction and the third width of the third region in the second direction, a first trench, an n-type first silicon carbide region, a p-type second silicon carbide region located between the first silicon carbide region and the first surface and having a distance from the second surface larger than the distance from the second surface to the first trench, an n-type third silicon carbide region located between the second silicon carbide region and the first surface, a p-type fourth silicon carbide region located between the first trench and the first silicon carbide region, and a fifth silicon carbide region located in the second direction of the second region and electrically connecting the second silicon carbide region and the fourth silicon carbide region, a gate electrode located in the first trench, a gate insulating layer located between the gate electrode and the silicon carbide layer, a first electrode located on the side of the first surface of the silicon carbide layer and in contact with the third silicon carbide region, and a second electrode located on the side of the second surface of the silicon carbide layer.

[0015] The semiconductor device of the first embodiment is a vertical MOSFET 100 using silicon carbide. The MOSFET 100 is a MOSFET having a trench gate structure in which a gate electrode is provided in a trench. Further, the MOSFET 100 is an n-channel type MOSFET using electrons as carriers.

[0016] FIG. 1 is a schematic plan view of the semiconductor device of the first embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 4 is a schematic cross-sectional view of the semiconductor device of the first embodiment. FIG. 5 is a schematic cross-sectional view of the semiconductor device of the first embodiment.

[0017] FIG. 1 is a diagram showing a pattern of a first trench on a first surface P1 of a silicon carbide layer. FIG. 2 is a cross-sectional view taken along line AA' of FIG. 1. FIG. 3 is a cross-sectional view taken along line BB' of FIG. 1. FIG. 4 is a cross-sectional view taken along line CC' of FIG. 1. FIG. 5 is a cross-sectional view taken along line SS' of FIGS. 2, 3, and 4. FIG. 5 is a diagram showing the pattern of the first trench and the pattern of the fifth silicon carbide region.

[0018] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0019] The silicon carbide layer 10 includes a gate trench 21 (first trench), an n + -type drain region 24, an n - -type drift region 26 (first silicon carbide region), a p-type body region 28 (second silicon carbide region), an n + -type source region 30 (third silicon carbide region), a p ++ -type gate trench bottom region 32 (fourth silicon carbide region), a p + -type connection region 34 (fifth silicon carbide region), and a p ++ -type contact region 36.

[0020] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The p-type body region 28 (the second silicon carbide region) has a first low-concentration portion 28a (the first portion), a high-concentration portion 28b (the second portion), and a second low-concentration portion 28c.

[0021] The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode. The gate trench 21 is an example of a first trench. The drift region 26 is an example of a first silicon carbide region. The body region 28 is an example of a second silicon carbide region. The source region 30 is an example of a third silicon carbide region. The gate trench bottom region 32 is an example of a fourth silicon carbide region. The connection region 34 is an example of a fifth silicon carbide region. The first low-concentration portion 28a is an example of a first portion. The high-concentration portion 28b is an example of a second portion.

[0022] The silicon carbide layer 10 is located between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 has a first surface (denoted as “P1” in FIG. 2) and a second surface (denoted as “P2” in FIG. 2). Hereinafter, the first surface P1 is also referred to as the front surface, and the second surface P2 is also referred to as the back surface. The second surface P2 faces the first surface P1.

[0023] The first direction and the second direction are directions parallel to the first surface P1. Also, the second direction is a direction perpendicular to the first direction. Also, the third direction is a direction perpendicular to the first surface. The third direction is a direction perpendicular to the first direction and the second direction.

[0024] Hereinafter, “depth” means the depth with reference to the first surface P1.

[0025] The silicon carbide layer 10 is single-crystalline SiC. The silicon carbide layer 10 is, for example, 4H-SiC. The thickness of the silicon carbide layer 10 is, for example, 5 μm or more and 500 μm or less.

[0026] The first surface P1 is, for example, a surface inclined 0 degrees or more and 8 degrees or less with respect to the (0001) surface. That is, it is a surface whose normal is inclined 0 degrees or more and 8 degrees or less with respect to the c-axis in the

[0001] direction. In other words, the off-angle with respect to the (0001) surface is 0 degrees or more and 8 degrees or less. Further, the second surface P2 is, for example, a surface inclined 0 degrees or more and 8 degrees or less with respect to the (000-1) surface.

[0027] (0001) surface is referred to as a silicon surface. (000-1) surface is referred to as a carbon surface. The inclination directions of the first surface P1 and the second surface P2 are, for example, in the [11-20] direction. The [11-20] direction is the a-axis direction. In FIG. 2, for example, the second direction shown in the figure is the a-axis direction.

[0028] The gate trench 21 exists in the silicon carbide layer 10. The gate trench 21 is located on the side of the first surface P1 of the silicon carbide layer 10. The gate trench 21 is a groove formed in the silicon carbide layer 10.

[0029] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region. The fourth region 21d is continuous with the third region 21c.

[0030] The first region 21a and the third region 21c extend in the first direction. The second region 21b and the fourth region 21d extend, for example, in the second direction.

[0031] The first region 21a faces the third region 21c in the second direction. The first region 21a is repeatedly arranged in the second direction. The third region 21c is repeatedly arranged in the second direction. The third region 21c is sandwiched between two first regions 21a.

[0032] The second region 21b is repeatedly arranged in the first direction. Two adjacent second regions 21b face each other in the first direction.

[0033] The fourth region 21d is repeatedly arranged in the first direction. Two adjacent fourth regions 21d face each other in the first direction.

[0034] The width of the first region 21a in the second direction is the first width w1. The width of the second region 21b in the second direction is the second width w2. The width of the third region 21c in the second direction is the third width w3. The width of the fourth region 21d in the second direction is the fourth width w4.

[0035] The second width w2 is larger than the first width w1. For example, the second width w2 is at least twice the first width w1.

[0036] The second width w2 is larger than the third width w3. For example, the second width w2 is at least twice the third width w3.

[0037] The fourth width w4 is larger than the first width w1. For example, the fourth width w4 is at least twice the first width w1.

[0038] The fourth width w4 is larger than the third width w3. For example, the fourth width w4 is at least twice the third width w3.

[0039] The depth of the gate trench 21 is, for example, 1 μm or more and 2 μm or less. The first width w1 of the first region 21a of the gate trench 21 is, for example, 0.5 μm or more and 1 μm or less.

[0040] The gate trench 21 penetrates the source region 30 and the body region 28.

[0041] The gate electrode 16 is located in the gate trench 21. The gate electrode 16 is provided between the source electrode 12 and the drain electrode 14.

[0042] The gate electrode 16 is a conductive layer. The gate electrode 16 is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0043] The gate insulating layer 18 is located between the gate electrode 16 and the silicon carbide layer 10. The gate insulating layer 18 is provided between the source region 30, the body region 28, the drift region 26, and the connection region 34 and the gate electrode 16.

[0044] The gate insulating layer 18 is, for example, a silicon oxide film. For the gate insulating layer 18, a High-k insulating film (a high dielectric constant insulating film such as HfSiON, ZrSiON, AlON, etc.) can be applied, for example. Also, for the gate insulating layer 18, a laminated film of a silicon oxide film (SiO2) and a High-k insulating film can be applied, for example.

[0045] The interlayer insulating layer 20 is provided on the gate electrode 16. The interlayer insulating layer 20 is provided between the gate electrode 16 and the source electrode 12.

[0046] The thickness of the interlayer insulating layer 20 is, for example, thicker than the thickness of the gate insulating layer 18. The interlayer insulating layer 20 is, for example, a silicon oxide film. The interlayer insulating layer 20 electrically separates the gate electrode 16 and the source electrode 12.

[0047] The interface between the source electrode 12 and the interlayer insulating layer 20 is, for example, on the side of the second surface P2 from the first surface P1. The interface between the source electrode 12 and the interlayer insulating layer 20 is, for example, located in the gate trench 21.

[0048] As shown in FIGS. 2, 3, and 4, on the first surface P1, the upper surface of the gate trench 21 is covered with the source electrode 12.

[0049] The source electrode 12 is located on the side of the first surface P1 of the silicon carbide layer 10. The source electrode 12 is provided on the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the source region 30 and the contact region 36.

[0050] The source electrode 12 is in contact with the source region 30 at the first surface P1 of the silicon carbide layer 10.

[0051] The source electrode 12 contains metal. The metal forming the source electrode 12 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The source electrode 12 may include, for example, metal silicide or metal carbide in contact with the silicon carbide layer 10.

[0052] The drain electrode 14 is located on the second surface P2 side of the silicon carbide layer 10. The drain electrode 14 is provided on the second surface P2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 24.

[0053] The drain electrode 14 is, for example, a metal or a metal semiconductor compound. The drain electrode 14 includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0054] n + The n-type drain region 24 is provided on the second surface P2 side of the silicon carbide layer 10. The drain region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 24 is, for example, 1×10 18 cm -3 or more and 1×10 21 cm -3 or less.

[0055] n - The n-type drift region 26 is provided on the drain region 24. The drift region 26 is located between the first surface P1 and the drain region 24.

[0056] The drift region 26 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 26 is lower than the n-type impurity concentration of the drain region 24. The n-type impurity concentration of the drift region 26 is, for example, 4×10 14 cm -3 or more and 1×10 18 cm -3 or less.

[0057] The p-type body region 28 is located between the drift region 26 and the first surface P1.

[0058] The body region 28 has a first low-concentration portion 28a (first portion), a high-concentration portion 28b (second portion), and a second low-concentration portion 28c. The first low-concentration portion 28a is located between the gate trench 21 and the high-concentration portion 28b. The high-concentration portion 28b is located between the first low-concentration portion 28a and the second low-concentration portion 28c.

[0059] The first low-concentration portion 28a functions as a channel formation region of the MOSFET 100. For example, when the MOSFET 100 is in the on state, a channel through which electrons flow is formed in the first low-concentration portion 28a.

[0060] The high-concentration portion 28b has a function of suppressing the short-channel effect of the MOSFET 100. By providing the high-concentration portion 28b in the body region 28, a decrease in the threshold voltage of the MOSFET 100 when the channel length becomes short is suppressed.

[0061] The body region 28 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the high-concentration portion 28b is higher than the p-type impurity concentration of the first low-concentration portion 28a. The p-type impurity concentration of the high-concentration portion 28b is higher than the p-type impurity concentration of the second low-concentration portion 28c.

[0062] The p-type impurity concentration of the high-concentration portion 28b is, for example, 2 times or more and 10 times or less the p-type impurity concentration of the first low-concentration portion 28a. The p-type impurity concentration of the high-concentration portion 28b is, for example, 2 times or more and 10 times or less the p-type impurity concentration of the second low-concentration portion 28c.

[0063] The p-type impurity concentrations of the first low-concentration portion 28a and the second low-concentration portion 28c are, for example, 5×10 16 cm -3 or more and 5×10 17 cm -3 or less. The p-type impurity concentration of the high-concentration portion 28b is, for example, 1×10 17 cm -3 or more and 5×10 18 cm -3 or less.

[0064] The depth of the body region 28 is shallower than the depth of the gate trench 21. The depth of the body region 28 is, for example, not less than 0.4 μm and not more than 1.0 μm.

[0065] The distance from the second surface P2 to the body region 28 (d1 in FIG. 2) is greater than the distance from the second surface P2 to the gate trench 21 (d2 in FIG. 2).

[0066] n + The n-type source region 30 is located between the body region 28 and the first surface P1. The source region 30 is in contact with the source electrode 12. The source region 30 is in contact with the gate insulating layer 18.

[0067] The source region 30 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 30 is higher than the n-type impurity concentration of the drift region 26. The n-type impurity concentration of the source region 30 is, for example, 1×10 19 cm -3 or more and 1×10 21 cm -3 or less.

[0068] The depth of the source region 30 is shallower than the depth of the body region 28. The depth of the source region 30 is, for example, not less than 0.3 μm and not more than 0.6 μm.

[0069] p ++ The p-type gate trench bottom region 32 is located between the gate trench 21 and the drift region 26. The gate trench bottom region 32 is in contact with the bottom surface of the gate trench 21. The gate trench bottom region 32 is in contact with the gate insulating layer 18.

[0070] The gate trench bottom region 32 has a function of relaxing the electric field applied to the gate insulating layer 18 during the off operation of the MOSFET 100.

[0071] The gate trench bottom region 32 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the gate trench bottom region 32 is higher than, for example, the p-type impurity concentration in the body region 28. The p-type impurity concentration in the gate trench bottom region 32 is, for example, 10 times or more the p-type impurity concentration in the body region 28.

[0072] The p-type impurity concentration in the gate trench bottom region 32 is, for example, 5×10 17 cm -3 or more and 5×10 19 cm -3 or less.

[0073] The p-type impurity concentration in the gate trench bottom region 32 between the second region 21b of the gate trench 21 and the drift region 26 is higher than the p-type impurity concentration in the gate trench bottom region 32 between the first region 21a of the gate trench 21 and the drift region 26.

[0074] p + type connection region 34 is located in the second direction of the second region 21b of the gate trench 21. The connection region 34 electrically connects the body region 28 and the gate trench bottom region 32.

[0075] The connection region 34 is in contact with the body region 28. The connection region 34 is in contact with, for example, the high-concentration portion 28b of the body region 28. The connection region 34 is in contact with the gate trench bottom region 32.

[0076] For example, a part 26a of the drift region 26 is located between the gate trench 21 and the connection region 34. A part 26a of the drift region 26 exists between the gate trench 21 and the connection region 34 in the second direction of the gate trench 21. The connection region 34 is spaced apart from the gate trench 21 in the second direction.

[0077] The connection region 34 is also located, for example, in the first direction of the second region 21b of the gate trench 21. The connection region 34 in the first direction of the second region 21b is in contact with the gate trench 21, for example. The connection region 34 is in contact with the gate trench 21 in the first direction, for example.

[0078] The connection region 34 is not provided in the second direction of the first region 21a of the gate trench 21. The connection region 34 is not provided in the second direction of the third region 21c of the gate trench 21. The length of the connection region 34 in the first direction (d3 in FIG. 5) is, for example, 1.5 times or less the length of the second region 21b of the gate trench 21 in the first direction (d4 in FIG. 5).

[0079] The connection region 34 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the connection region 34 is lower than that of the p-type impurity concentration of the gate trench bottom region 32, for example. The p-type impurity concentration of the connection region 34 is higher than that of the first low-concentration portion 28a of the body region 28, for example. The p-type impurity concentration of the connection region 34 is higher than that of the second low-concentration portion 28c of the body region 28, for example. The p-type impurity concentration of the connection region 34 is substantially the same as that of the high-concentration portion 28b of the body region 28, for example. The p-type impurity concentration of the connection region 34 is lower than that of the high-concentration portion 28b of the body region 28, for example.

[0080] The p-type impurity concentration of the connection region 34 is, for example, 1×10 17 cm -3 or more and 5×10 18 cm -3 or less.

[0081] The p ++ -type contact region 36 is located between the body region 28 and the first surface P1. The contact region 36 is in contact with the source electrode 12. The contact region 36 is in contact with the gate insulating layer 18, for example.

[0082] The contact region 36 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the contact region 36 is higher than the p-type impurity concentration in the body region 28. The p-type impurity concentration in the contact region 36 is, for example, 10 times or more the p-type impurity concentration in the body region 28. The p-type impurity concentration in the contact region 36 is, for example, 5×10 17 cm -3 or more and 5×10 20 cm -3 or less.

[0083] Next, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described.

[0084] The method for manufacturing a semiconductor device according to the first embodiment includes a first surface parallel to a first direction and a second direction orthogonal to the first direction, a second surface facing the first surface, an n-type first silicon carbide region located between the second surface and the first surface, a p-type second silicon carbide region located between the first silicon carbide region and the first surface, and an n-type third silicon carbide region located between the second silicon carbide region and the first surface. On the side of the first surface of the silicon carbide layer, a first region extending in the first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction are provided. A first trench is formed in which a second width in the second direction of the second region is larger than a first width in the second direction of the first region and a third width in the second direction of the third region. P-type impurities are implanted into the bottom surface of the first trench to perform a first ion implantation for forming a first p-type region. A second ion implantation is performed in which p-type impurities are implanted in a direction inclined with respect to the normal of the first surface on one side surface of the first region, one side surface of the second region, and one side surface of the third region to form a second p-type region. A third ion implantation is performed in which p-type impurities are implanted in a direction inclined with respect to the normal of the first surface on the other side surface of the first region, the other side surface of the second region, and the other side surface of the third region to form a third p-type region. A gate insulating layer is formed in the first trench, and a gate electrode is formed on the gate insulating layer in the first trench.

[0085] Figures 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 6, 8, 10, 12, 14, and 16 show cross-sections corresponding to the cross-section of FIG. 2, that is, AA' of FIG. 1. Figures 7, 9, 11, 13, 15, and 17 show cross-sections corresponding to the cross-section of FIG. 3, that is, BB' of FIG. 1.

[0086] First, a silicon carbide layer 10 having a first surface P1 parallel to a first direction and a second direction orthogonal to the first direction, and a second surface P2 facing the first surface is prepared (FIGS. 6 and 7). Hereinafter, the first surface P1 is also referred to as the front surface, and the second surface P2 is also referred to as the back surface.

[0087] The silicon carbide layer 10 has an n + -type drain region 24, an n - -type drift region 26 (first silicon carbide region), a p-type body region 28 (second silicon carbide region), an n + -type source region 30 (third silicon carbide region), and a p ++ -type contact region 36. The drain region 24, the drift region 26, the body region 28, the source region 30, and the contact region 36 are formed, for example, by ion implantation into an n - -type epitaxial layer formed by epitaxial growth.

[0088] Next, a mask material 50 is formed on the surface of the silicon carbide layer 10. The mask material 50 is formed, for example, by depositing a film by Chemical Vapoer Deposition (CVD) method, lithography method, and patterning the film using a reactive ion etching (RIE) method. The mask material 50 is, for example, a silicon oxide film.

[0089] Next, a gate trench 21 (first trench) is formed using the mask material 50 as a mask (FIGS. 8 and 9). The gate trench 21 is formed using the RIE method. The gate trench 21 is formed so as to penetrate the source region 30 and the body region 28.

[0090] The gate trench 21 has a first region 21a, a second region 21b, and a third region 21c. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region 21b.

[0091] The first region 21a and the third region 21c extend in a first direction. The second region 21b extends in a second direction.

[0092] The width of the first region 21a in the second direction is a first width w1. The width of the second region 21b in the second direction is a second width w2. The width of the third region 21c in the second direction is a third width w3.

[0093] The second width w2 is larger than the first width w1. The second width w2 is larger than the third width w3.

[0094] Next, a first ion implantation is performed (FIGS. 10 and 11). In the first ion implantation, p-type impurities are implanted into the bottom surface of the gate trench 21 to form a p ++ -type gate trench bottom region 32. The gate trench bottom region 32 is an example of a first p-type region.

[0095] The p-type impurities are, for example, aluminum ions. In the first ion implantation, for example, aluminum ions are implanted in a direction perpendicular to the normal of the first surface P1. The gate trench bottom region 32 is formed in the drift region 26 near the bottom of the gate trench 21.

[0096] Next, a second ion implantation is performed (FIGS. 12 and 13). In the second ion implantation, p-type impurities are implanted into one side surface of the gate trench 21 to form a part of the p + -type high-concentration portion 28b of the body region 28 and a part of the p + -type connection region 34. A part of the high-concentration portion 28b and a part of the connection region 34 are examples of a second p-type region.

[0097] The second ion implantation injects p-type impurities into one side surface of the first region 21a, one side surface of the second region 21b, and one side surface of the third region 21c.

[0098] The p-type impurities are, for example, aluminum ions. In the second ion implantation, for example, aluminum ions are implanted in a direction inclined with respect to the normal line of the first surface P1 (the dotted line in FIGS. 12 and 13). The aluminum ions are implanted, for example, in a direction along the second direction. In the second ion implantation, an oblique ion implantation method is used.

[0099] As shown in FIG. 12, high-concentration portions 28b are formed on one side surface of the first region 21a and one side surface of the third region 21c in the second direction. Since the deep portions and the bottom surfaces of the side surfaces of the first region 21a and the deep portions and the bottom surfaces of the side surfaces of the third region 21c are shielded from ion implantation by the mask material 50, aluminum ions are not implanted. Also, aluminum ions are not implanted on the other side surface of the first region 21a and the other side surface of the third region 21c in the second direction.

[0100] Also, as shown in FIG. 13, a high-concentration portion 28b and a connection region 34 are formed on one side surface of the second region 21b in the second direction. The portions of the body region 28 other than the high-concentration portion 28b become the first low-concentration portion 28a or the second low-concentration portion 28c. Aluminum ions are not implanted on the other side surface of the second region 21b in the second direction.

[0101] Next, a third ion implantation is performed (FIGS. 14 and 15). In the third ion implantation, p-type impurities are implanted on the other side surface of the gate trench 21, and another part of the p + type high-concentration portion 28b of the body region 28, and another part of the p + type connection region 34 are formed. A part of the high-concentration portion 28b and another part of the connection region 34 are examples of the third p-type region.

[0102] The third ion implantation injects p-type impurities into the other side surfaces of the first region 21a, the other side surfaces of the second region 21b, and the other side surfaces of the third region 21c.

[0103] The p-type impurities are, for example, aluminum ions. In the third ion implantation, for example, aluminum ions are implanted in a direction inclined with respect to the normal line of the first surface P1 (the dotted line in FIGS. 14 and 15). In the third ion implantation, for example, aluminum ions are implanted in a direction inclined in the opposite direction to the first ion implantation with respect to the normal line of the first surface P1.

[0104] The aluminum ions are implanted, for example, in a direction along the second direction. The aluminum ions are implanted from the opposite direction to the second ion implantation. In the third ion implantation, an oblique ion implantation method is used.

[0105] As shown in FIG. 14, high-concentration portions 28b are formed on the other side surfaces of the first region 21a and the third region 21c in the second direction. Since the deep portions and the bottom surfaces of the side surfaces of the first region 21a and the deep portions and the bottom surfaces of the side surfaces of the third region 21c are shielded from ion implantation by the mask material 50, aluminum ions are not implanted.

[0106] Also, as shown in FIG. 15, a high-concentration portion 28b and a connection region 34 are formed on the other side surface of the second region 21b in the second direction. The portions of the body region 28 other than the high-concentration portion 28b become the first low-concentration portion 28a or the second low-concentration portion 28c.

[0107] As shown in FIG. 14, by the second ion implantation and the third ion implantation, high-concentration portions 28b are formed on both side surfaces of the first region 21a in the second direction and on both side surfaces of the third region 21c in the second direction. Also, as shown in FIG. 14, by the second ion implantation and the third ion implantation, a high-concentration portion 28b and a connection region 34 are formed on both side surfaces of the second region 21b in the second direction.

[0108] In addition, by the second ion implantation and the third ion implantation, aluminum ions are implanted, for example, also into the side surface of the second region 21b in the first direction. Therefore, a high-concentration portion 28b and a connection region 34 are formed on the side surface of the second region 21b in the first direction. For example, since the side surface of the gate trench 21 has a tapered shape, aluminum ions are also implanted into the side surface of the second region 21b in the first direction.

[0109] In the second ion implantation and the third ion implantation, aluminum ions are not implanted into the bottom surface of the first region 21a and the bottom surface of the third region 21c. On the other hand, in the second ion implantation and the third ion implantation, aluminum ions are implanted into the bottom surface of the second region 21b. Therefore, the p-type impurity concentration of the gate trench bottom region 32 directly below the second region 21b becomes higher than the p-type impurity concentration of the gate trench bottom region 32 directly below the first region 21a and the third region 21c.

[0110] Next, the mask material 50 is removed. Next, using a known process technology, a gate insulating layer 18 and a gate electrode 16 are formed in the gate trench 21. Also, an interlayer insulating layer 20 is formed on the gate electrode 16 (FIGS. 16 and 17).

[0111] Thereafter, using a known process technology, a source electrode 12 is formed on the surface of the silicon carbide layer 10. Also, a drain electrode 14 is formed on the back surface of the silicon carbide layer 10. By the above manufacturing method, the MOSFET 100 shown in FIGS. 1 to 5 is manufactured.

[0112] Next, the operation and effects of the semiconductor device and the manufacturing method of the semiconductor device according to the first embodiment will be described.

[0113] The MOSFET 100 applies a trench gate structure in which a gate electrode 16 is provided in a gate trench 21. By applying the trench gate structure, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is reduced.

[0114] The MOSFET 100 has a high-concentration portion 28b in the body region 28. By having the high-concentration portion 28b, the short-channel effect of the MOSFET 100 is suppressed. Therefore, it becomes possible to shorten the channel length of the MOSFET 100. Specifically, for example, it becomes possible to shorten the length in the depth direction (the third direction) of the first low-concentration portion 28a along the side surface of the gate trench 21. Thus, the on-resistance of the MOSFET 100 is further reduced.

[0115] Also, the MOSFET 100 has a gate-trench bottom region 32 at the bottom of the gate trench 21. By having the gate-trench bottom region 32, when the MOSFET 100 is in the off state, the electric field applied to the gate insulating layer 18 at the bottom of the gate trench 21 is relaxed. Thus, the reliability of the gate insulating layer 18 is improved.

[0116] For example, if the potential of the gate-trench bottom region 32 is in a floating state, the switching loss of the MOSFET increases. For example, if the potential of the gate-trench bottom region 32 is in a floating state, during the turn-off operation of the MOSFET, it takes time to discharge holes from the gate-trench bottom region 32, resulting in an increase in switching loss.

[0117] The MOSFET 100 has a connection region 34 that electrically connects the gate-trench bottom region 32 and the body region 28. By having the connection region 34, the potential of the gate-trench bottom region 32 is fixed to the potential of the source electrode 12. Therefore, for example, during the turn-off operation of the MOSFET, the discharge of holes from the gate-trench bottom region 32 is promoted. Thus, the switching loss of the MOSFET 100 can be reduced.

[0118] Further, in the MOSFET 100, the gate trench 21 has a first region 21a, a second region 21b, and a third region 21c. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region. The first region 21a and the third region 21c extend in a first direction. The second region 21b extends in a second direction. The width of the first region 21a in the second direction is a first width w1. The width of the second region 21b in the second direction is a second width w2. The width of the third region 21c in the second direction is a third width w3. The second width w2 is greater than the first width w1. The second width w2 is greater than the third width w3.

[0119] Since the gate trench 21 of the MOSFET 100 has the above pattern, a high-concentration portion 28b that suppresses the short-channel effect of the MOSFET 100 and a connection region 34 that reduces the switching loss of the MOSFET 100 can be formed by the same ion implantation process. Specifically, the high-concentration portion 28b and the connection region 34 can be formed simultaneously by the second ion implantation and the third ion implantation described in the above manufacturing method. Therefore, an increase in the manufacturing process can be suppressed, and the manufacturing cost of the MOSFET 100 can be reduced.

[0120] Preferably, the second width w2 of the gate trench 21 is at least twice the first width w1, and more preferably at least three times the first width w1. As the second width w2 becomes wider, the formation of the connection region 34 becomes easier. For the same reason, preferably, the second width w2 is at least twice the third width w3, and more preferably at least three times the third width w3.

[0121] Preferably, the second width w2 of the gate trench 21 is at most ten times the first width w1, and more preferably at most eight times the first width w1. As the second width w2 becomes narrower, the ratio of the channel formation region occupying the side surface of the gate trench 21 increases. Therefore, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is reduced. For the same reason, preferably, the second width w2 is at most ten times the third width w3, and more preferably at most eight times the third width w3.

[0122] The length of the connection region 34 in the first direction (d3 in FIG. 5) is preferably 1.5 times or less the length of the second region 21b of the gate trench 21 in the first direction (d4 in FIG. 5). By shortening the length of the connection region 34 in the first direction, the ratio of the channel formation region occupying the side surface of the gate trench 21 increases. Therefore, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is reduced.

[0123] It is preferable that a part 26a of the drift region 26 is located between the gate trench 21 and the connection region 34. By having a part 26a of the drift region 26 between the gate trench 21 and the connection region 34, the first low-concentration portion 28a directly above the gate trench 21 facing the connection region 34 functions as a channel formation region. Therefore, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is further reduced.

[0124] The connection region 34 is preferably also located in the first direction of the second region 21b of the gate trench 21. By having the connection region 34 also in the first direction of the second region 21b, for example, during the turn-off operation of the MOSFET, the discharge of holes from the gate trench bottom region 32 is further promoted. Thus, the switching loss of the MOSFET 100 can be further reduced.

[0125] As described above, according to the MOSFET of the first embodiment, it is possible to simultaneously achieve reduction of on-resistance, improvement of the reliability of the gate insulating layer, and reduction of switching loss. Also, according to the MOSFET and the manufacturing method of the MOSFET of the first embodiment, it is possible to reduce the manufacturing cost.

[0126] (Second Embodiment) The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that the first trench has a fourth region that faces the second region in the first direction and is continuous with the first region and the third region. Hereinafter, for the content overlapping with the first embodiment, some descriptions may be omitted.

[0127] The semiconductor device of the second embodiment is a vertical MOSFET 200 using silicon carbide. The MOSFET 200 is a MOSFET having a trench gate structure in which a gate electrode is provided in a trench. Further, the MOSFET 200 is an n-channel type MOSFET using electrons as carriers.

[0128] The shape of the gate trench of the MOSFET 200 of the second embodiment is different from that of the MOSFET 100 of the first embodiment.

[0129] FIG. 18 is a schematic plan view of the semiconductor device of the second embodiment. FIG. 19 is a schematic cross-sectional view of the semiconductor device of the second embodiment. FIG. 20 is a schematic cross-sectional view of the semiconductor device of the second embodiment. FIG. 21 is a schematic cross-sectional view of the semiconductor device of the second embodiment. FIG. 22 is a schematic cross-sectional view of the semiconductor device of the second embodiment. FIG. 23 is a schematic cross-sectional view of the semiconductor device of the second embodiment.

[0130] FIG. 18 is a diagram showing a pattern of a first trench on a first surface P1 of a silicon carbide layer. FIG. 19 is a cross-sectional view taken along the line AA' of FIG. 18. FIG. 20 is a cross-sectional view taken along the line BB' of FIG. 18. FIG. 21 is a cross-sectional view taken along the line CC' of FIG. 18. FIG. 22 is a cross-sectional view taken along the line DD' of FIG. 18. FIG. 23 is a cross-sectional view taken along the line SS' of FIGS. 19, 20, 21, and 22. FIG. 23 is a diagram showing a pattern of the first trench and a pattern of a fifth silicon carbide region.

[0131] The MOSFET 200 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0132] The silicon carbide layer 10 includes a gate trench 21 (first trench), an n + -type drain region 24, an n - -type drift region 26 (first silicon carbide region), a p-type body region 28 (second silicon carbide region), an n + -type source region 30 (third silicon carbide region), a p ++The gate trench bottom region 32 (the fourth silicon carbide region), p + type connection region 34 (the fifth silicon carbide region), p ++ has a type contact region 36.

[0133] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The p-type body region 28 (the second silicon carbide region) has a first low-concentration portion 28a (the first portion), a high-concentration portion 28b (the second portion), and a second low-concentration portion 28c.

[0134] The gate electrode 16 includes a crosslinked portion 16a.

[0135] The source electrode 12 is an example of the first electrode. The drain electrode 14 is an example of the second electrode. The gate trench 21 is an example of the first trench. The drift region 26 is an example of the first silicon carbide region. The body region 28 is an example of the second silicon carbide region. The source region 30 is an example of the third silicon carbide region. The gate trench bottom region 32 is an example of the fourth silicon carbide region. The connection region 34 is an example of the fifth silicon carbide region. The first low-concentration portion 28a is an example of the first portion. The high-concentration portion 28b is an example of the second portion.

[0136] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region. The fourth region 21d is continuous with the third region 21c and the first region 21a. The gate trench 21 is annular.

[0137] The first region 21a and the third region 21c extend in a first direction. The second region 21b and the fourth region 21d extend in a second direction.

[0138] The first region 21a faces the third region 21c in the second direction. The first region 21a is repeatedly arranged in the second direction. The third region 21c is repeatedly arranged in the second direction. The third region 21c is sandwiched between two first regions 21a.

[0139] The second region 21b is repeatedly arranged in the first direction. The second region 21b faces the fourth region 21d in the first direction.

[0140] The silicon carbide layer 10 of the MOSFET 200 includes a plurality of annular gate trenches 21 that are separated from each other.

[0141] As shown in FIGS. 20 and 21, the gate electrode 16 includes a cross-bridge portion 16a. The cross-bridge portion 16a has a function of electrically connecting the gate electrodes 16 in two separated gate trenches 21 adjacent to each other in the second direction.

[0142] The MOSFET of the second embodiment can be manufactured by changing the pattern when forming the gate trench 21 and the pattern when processing the gate electrode 16 from the manufacturing method of the MOSFET of the first embodiment.

[0143] As described above, according to the MOSFET of the second embodiment, it is possible to simultaneously achieve reduction of on-resistance, improvement of the reliability of the gate insulating layer, and reduction of switching loss. Further, according to the MOSFET of the second embodiment and the manufacturing method of the MOSFET, it is possible to reduce the manufacturing cost.

[0144] (Third Embodiment) The semiconductor device of the third embodiment is different from the semiconductor device of the first embodiment in that the pattern of the first trench is different. Hereinafter, some descriptions may be omitted for the content overlapping with the first embodiment.

[0145] The semiconductor device of the third embodiment is a vertical MOSFET 300 using silicon carbide. MOSFET 300 is a MOSFET having a trench gate structure in which a gate electrode is provided in a trench. Also, MOSFET 300 is an n-channel MOSFET using electrons as carriers.

[0146] In MOSFET 300 of the third embodiment, the shape of the gate trench is different from that of MOSFET 100 of the first embodiment.

[0147] FIG. 24 is a schematic cross-sectional view of the semiconductor device of the third embodiment. FIG. 24 is a diagram showing the pattern of the first trench and the pattern of the fifth silicon carbide region. FIG. 24 corresponds to FIG. 5 of the first embodiment.

[0148] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region. The fourth region 21d is continuous with the third region 21c and the first region 21a.

[0149] The first region 21a and the third region 21c extend in the first direction. The second region 21b and the fourth region 21d extend in the second direction.

[0150] The first region 21a is repeatedly arranged in the second direction. The third region 21c is repeatedly arranged in the second direction.

[0151] FIG. 25 is a schematic cross-sectional view of the first modification of the semiconductor device of the third embodiment. FIG. 25 is a diagram showing the pattern of the first trench and the pattern of the fifth silicon carbide region. FIG. 25 corresponds to FIG. 24 of the third embodiment.

[0152] In MOSFET 301 of the first modification of the third embodiment, the shape of the gate trench is different from that of MOSFET 300 of the third embodiment.

[0153] FIG. 26 is a schematic cross-sectional view of a second modification of the semiconductor device according to the third embodiment. FIG. 26 is a diagram showing the pattern of the first trench and the pattern of the fifth silicon carbide region. FIG. 26 corresponds to FIG. 24 of the third embodiment.

[0154] In the MOSFET 302 of the second modification of the third embodiment, the shape of the gate trench is different from that of the MOSFET 300 of the third embodiment.

[0155] The MOSFETs of the third embodiment and the modifications can be manufactured by changing the pattern in forming the gate trench 21 from the manufacturing method of the MOSFET of the first embodiment.

[0156] As described above, according to the MOSFETs of the third embodiment and the modifications, it is possible to simultaneously achieve reduction of on-resistance, improvement of the reliability of the gate insulating layer, and reduction of switching loss. Also, according to the manufacturing method of the MOSFETs of the third embodiment and the modifications, it is possible to reduce the manufacturing cost.

[0157] (Fourth Embodiment) The semiconductor device according to the fourth embodiment is different from the semiconductor device according to the first embodiment in that the silicon carbide layer further includes a second trench that is adjacent to the first region in the second direction, is located on the side of the first surface, extends in the first direction, and a part of the first electrode is located inside. Hereinafter, for the content overlapping with the first embodiment, some descriptions may be omitted.

[0158] The semiconductor device according to the fourth embodiment is a vertical MOSFET 400 using silicon carbide. The MOSFET 400 is a MOSFET having a trench gate structure in which a gate electrode is provided in a trench. Also, the MOSFET 400 is a so-called double trench structure MOSFET in which a source electrode is provided in a trench. Also, the MOSFET 400 is an n-channel type MOSFET using electrons as carriers.

[0159] FIG. 27 is a schematic plan view of a semiconductor device according to the fourth embodiment. FIG. 28 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. FIG. 29 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. FIG. 30 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. FIG. 31 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0160] FIG. 27 is a diagram showing patterns of a first trench and a second trench on a first surface P1 of a silicon carbide layer. FIG. 28 is a cross-sectional view taken along line AA' of FIG. 27. FIG. 29 is a cross-sectional view taken along line BB' of FIG. 27. FIG. 30 is a cross-sectional view taken along line CC' of FIG. 28. FIG. 31 is a cross-sectional view taken along line SS' of FIGS. 28, 29, and 30. FIG. 31 is a diagram showing patterns of the first trench and the second trench and a pattern of a fifth silicon carbide region.

[0161] The MOSFET 400 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0162] The silicon carbide layer 10 has a gate trench 21 (first trench), a contact trench 22 (second trench), an auxiliary trench 23, an n + -type drain region 24, an n - -type drift region 26 (first silicon carbide region), a p-type body region 28 (second silicon carbide region), an n + -type source region 30 (third silicon carbide region), a p ++ -type gate trench bottom region 32 (fourth silicon carbide region), a p + -type connection region 34 (fifth silicon carbide region), and a p ++ -type electric field relaxation region 38.

[0163] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The p-type body region 28 (second silicon carbide region) has a first low-concentration portion 28a (first portion), a high-concentration portion 28b (second portion), and a second low-concentration portion 28c.

[0164] The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode. The gate trench 21 is an example of a first trench. The drift region 26 is an example of a first silicon carbide region. The body region 28 is an example of a second silicon carbide region. The source region 30 is an example of a third silicon carbide region. The gate trench bottom region 32 is an example of a fourth silicon carbide region. The connection region 34 is an example of a fifth silicon carbide region. The first low-concentration portion 28a is an example of a first portion. The high-concentration portion 28b is an example of a second portion.

[0165] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region. The fourth region 21d is continuous with the third region 21c.

[0166] The contact trench 22 exists in the silicon carbide layer 10. The contact trench 22 is located on the side of the first surface P1 of the silicon carbide layer 10. The contact trench 22 is a groove formed in the silicon carbide layer 10.

[0167] The contact trench 22 is adjacent to the first region 21a of the gate trench 21 in a second direction. The contact trench 22 extends in a first direction. A part 12a of the source electrode 12 is located inside the contact trench 22.

[0168] The auxiliary trench 23 exists in the silicon carbide layer 10. The auxiliary trench 23 is located on the side of the first surface P1 of the silicon carbide layer 10. The auxiliary trench 23 is a groove formed in the silicon carbide layer 10.

[0169] The auxiliary trench 23 is adjacent to the second region 21b of the gate trench 21 in a first direction. The auxiliary trench 23 extends in a second direction. A part 12a of the source electrode 12 is located inside the auxiliary trench 23.

[0170] p ++The electric field relaxation region 38 of the [type] is located between the contact trench 22 and the drift region 26. The electric field relaxation region 38 is in contact with the bottom surface and the side surface of the contact trench 22. The electric field relaxation region 38 is in contact with a part 12a of the source electrode 12 in the contact trench 22.

[0171] p ++ The p-type electric field relaxation region 38 is located between the auxiliary trench 23 and the drift region 26. The electric field relaxation region 38 is in contact with the bottom surface and the side surface of the auxiliary trench 23. The electric field relaxation region 38 is in contact with a part 12a of the source electrode 12 in the auxiliary trench 23.

[0172] The electric field relaxation region 38 has a function of relaxing the electric field applied to the gate insulating layer 18 during the OFF operation of the MOSFET 400. The electric field relaxation region 38 is fixed, for example, at the same potential as the potential of the source electrode 12.

[0173] The electric field relaxation region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field relaxation region 38 is higher than the p-type impurity concentration of the body region 28. The p-type impurity concentration of the electric field relaxation region 38 is, for example, 5×10 17 cm -3 or more and 5×10 20 cm -3 or less.

[0174] The MOSFET of the fourth embodiment can be manufactured by adding the step of forming the contact trench 22 and the auxiliary trench 23 and the step of forming the electric field relaxation region 38 to the manufacturing method of the MOSFET of the first embodiment.

[0175] Note that the contact trench 22 and the auxiliary trench 23 may be connected in the second direction.

[0176] FIG. 32 is a schematic cross-sectional view of a modification of the semiconductor device of the fourth embodiment. FIG. 32 is a diagram showing the patterns of the first trench and the second trench and the pattern of the fifth silicon carbide region. FIG. 32 corresponds to FIG. 31 of the fourth embodiment.

[0177] The MOSFET 401 of the modification of the fourth embodiment is different from the MOSFET 400 of the fourth embodiment in that the silicon carbide layer 10 does not include the auxiliary trench 23.

[0178] According to the MOSFET 401 of the modification, the channel area per unit area increases as compared with the MOSFET 400. Therefore, the on-resistance of the MOSFET 401 is further reduced.

[0179] As described above, according to the MOSFETs of the fourth embodiment and the modification, it is possible to simultaneously achieve reduction of on-resistance, improvement of the reliability of the gate insulating layer, and reduction of switching loss. Further, according to the MOSFETs of the fourth embodiment and the modification and the manufacturing method of the MOSFET, it is possible to reduce the manufacturing cost.

[0180] (Fifth Embodiment) The semiconductor device of the fifth embodiment is different from the semiconductor device of the second embodiment in that the silicon carbide layer further includes a second trench that is adjacent to the first region in the second direction, is located on the side of the first surface, extends in the first direction, and a part of the first electrode is located inside. Hereinafter, for the content overlapping with the second embodiment, some descriptions may be omitted.

[0181] The semiconductor device of the fifth embodiment is a vertical MOSFET 500 using silicon carbide. The MOSFET 500 is a MOSFET having a trench gate structure in which a gate electrode is provided in a trench. Further, the MOSFET 500 is a MOSFET having a so-called double trench structure in which a source electrode is provided in a trench. Further, the MOSFET 500 is an n-channel type MOSFET that uses electrons as carriers.

[0182] FIG. 33 is a schematic plan view of the semiconductor device according to the fifth embodiment. FIG. 34 is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. FIG. 35 is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. FIG. 36 is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. FIG. 37 is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. FIG. 38 is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.

[0183] FIG. 33 is a view showing a first trench and a second pattern on a first surface P1 of a silicon carbide layer. FIG. 34 is a cross-sectional view taken along line AA' of FIG. 33. FIG. 35 is a cross-sectional view taken along line BB' of FIG. 33. FIG. 36 is a cross-sectional view taken along line CC' of FIG. 33. FIG. 37 is a cross-sectional view taken along line DD' of FIG. 33. FIG. 38 is a cross-sectional view taken along line SS' of FIGS. 34, 35, 36, and 37. FIG. 38 is a view showing a pattern of a first trench and a second trench and a pattern of a fifth silicon carbide region.

[0184] The MOSFET 500 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0185] The silicon carbide layer 10 has a gate trench 21 (first trench), a contact trench 22 (second trench), an auxiliary trench 23, an n + -type drain region 24, an n - -type drift region 26 (first silicon carbide region), a p-type body region 28 (second silicon carbide region), an n + -type source region 30 (third silicon carbide region), a p ++ -type gate trench bottom region 32 (fourth silicon carbide region), a p + -type connection region 34 (fifth silicon carbide region), and a p ++ -type electric field relaxation region 38.

[0186] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The p-type body region 28 (the second silicon carbide region) has a first low-concentration portion 28a (the first portion), a high-concentration portion 28b (the second portion), and a second low-concentration portion 28c.

[0187] The gate electrode 16 includes a crosslinked portion 16a.

[0188] The source electrode 12 is an example of the first electrode. The drain electrode 14 is an example of the second electrode. The gate trench 21 is an example of the first trench. The drift region 26 is an example of the first silicon carbide region. The body region 28 is an example of the second silicon carbide region. The source region 30 is an example of the third silicon carbide region. The gate trench bottom region 32 is an example of the fourth silicon carbide region. The connection region 34 is an example of the fifth silicon carbide region. The first low-concentration portion 28a is an example of the first portion. The high-concentration portion 28b is an example of the second portion.

[0189] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region. The fourth region 21d is continuous with the third region 21c and the first region 21a. The gate trench 21 is annular.

[0190] The contact trench 22 is present in the silicon carbide layer 10. The contact trench 22 is located on the side of the first surface P1 of the silicon carbide layer 10. The contact trench 22 is a groove formed in the silicon carbide layer 10.

[0191] The contact trench 22 is adjacent to the first region 21a of the gate trench 21 in the second direction. The contact trench 22 extends in the first direction. A part 12a of the source electrode 12 is located inside the contact trench 22.

[0192] The auxiliary trench 23 exists in the silicon carbide layer 10. The auxiliary trench 23 is located on the side of the first surface P1 of the silicon carbide layer 10. The auxiliary trench 23 is a groove formed in the silicon carbide layer 10.

[0193] The auxiliary trench 23 is adjacent to the second region 21b of the gate trench 21 in the first direction. The auxiliary trench 23 extends in the second direction. A part 12a of the source electrode 12 is located inside the auxiliary trench 23.

[0194] p ++ The p-type electric field relaxation region 38 is located between the contact trench 22 and the drift region 26. The electric field relaxation region 38 is in contact with the bottom surface and the side surface of the contact trench 22. The electric field relaxation region 38 is in contact with a part 12a of the source electrode 12 in the contact trench 22.

[0195] p ++ The p-type electric field relaxation region 38 is located between the auxiliary trench 23 and the drift region 26. The electric field relaxation region 38 is in contact with the bottom surface and the side surface of the auxiliary trench 23. The electric field relaxation region 38 is in contact with a part 12a of the source electrode 12 in the auxiliary trench 23.

[0196] The electric field relaxation region 38 has a function of relaxing the electric field applied to the gate insulating layer 18 during the off operation of the MOSFET 500. The electric field relaxation region 38 is fixed to the same potential as the potential of the source electrode 12, for example.

[0197] The electric field relaxation region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field relaxation region 38 is higher than the p-type impurity concentration of the body region 28. The p-type impurity concentration of the electric field relaxation region 38 is, for example, 5×10 17 cm -3 or more and 5×10 20 cm -3 or less.

[0198] The MOSFET 500 of the fifth embodiment can be manufactured by adding a process of forming the contact trench 22 and the auxiliary trench 23 and a process of forming the electric field relaxation region 38 to the manufacturing method of the MOSFET of the second embodiment.

[0199] Note that the contact trench 22 and the auxiliary trench 23 may be connected in the second direction.

[0200] FIG. 39 is a schematic cross-sectional view of a modified example of the semiconductor device of the fifth embodiment. FIG. 39 is a diagram showing the patterns of the first trench and the second trench and the pattern of the fifth silicon carbide region. FIG. 39 corresponds to FIG. 38 of the fifth embodiment.

[0201] The MOSFET 501 of the modified example of the fifth embodiment is different from the MOSFET 500 of the fifth embodiment in that the silicon carbide layer 10 does not include the auxiliary trench 23.

[0202] According to the MOSFET 501 of the modified example, the channel area per unit area increases as compared with the MOSFET 500. Therefore, the on-resistance of the MOSFET 501 is further reduced.

[0203] As described above, according to the MOSFETs of the fifth embodiment and the modified example, it is possible to simultaneously achieve reduction of on-resistance, improvement of the reliability of the gate insulating layer, and reduction of switching loss. Further, according to the MOSFETs and the manufacturing method of the MOSFETs of the fifth embodiment and the modified example, it is possible to reduce the manufacturing cost.

[0204] (Sixth Embodiment) The semiconductor device of the sixth embodiment is different from the semiconductor device of the third embodiment in that the silicon carbide layer further includes a second trench that is adjacent to the first region in the second direction, is located on the side of the first surface, extends in the first direction, and a part of the first electrode is located inside. Hereinafter, for the content overlapping with the third embodiment, some descriptions may be omitted.

[0205] The semiconductor device of the sixth embodiment is a vertical MOSFET 600 using silicon carbide. The MOSFET 600 is a MOSFET having a trench gate structure in which a gate electrode is provided in a trench. Further, the MOSFET 600 is a MOSFET having a so-called double trench structure in which a source electrode is provided in a trench. Further, the MOSFET 600 is an n-channel type MOSFET using electrons as carriers.

[0206] FIG. 40 is a schematic plan view of the semiconductor device of the sixth embodiment. FIG. 41 is a schematic cross-sectional view of the semiconductor device of the sixth embodiment.

[0207] FIG. 40 is a diagram showing a first trench and a second pattern on a first surface P1 of a silicon carbide layer. FIG. 41 is a diagram showing the patterns of the first trench and the second trench and the pattern of the fifth silicon carbide region. FIG. 41 is a diagram showing the patterns of the gate trench 21 and the contact trench 22 and the pattern of the connection region 34.

[0208] The silicon carbide layer 10 includes a gate trench 21 (first trench) and a contact trench 22 (second trench). The silicon carbide layer 10 has a p ++ -type electric field relaxation region 38. The structure of the contact trench 22 and the p ++ -type electric field relaxation region 38 is the same as, for example, that of the MOSFET 400 of the fourth embodiment or the MOSFET 500 of the fifth embodiment.

[0209] The gate trench 21 has a first region 21a, a second region 21b, a third region 21c, and a fourth region 21d. The second region 21b is continuous with the first region 21a. The third region 21c is continuous with the second region. The fourth region 21d is continuous with the third region 21c and the first region 21a.

[0210] The first region 21a and the third region 21c extend in a first direction. The second region 21b and the fourth region 21d extend in a second direction.

[0211] The first region 21a is repeatedly arranged in the second direction. The third region 21c is repeatedly arranged in the second direction.

[0212] The contact trench 22 exists in the silicon carbide layer 10. The contact trench 22 is located on the side of the first surface P1 of the silicon carbide layer 10. The contact trench 22 is a groove formed in the silicon carbide layer 10.

[0213] The contact trench 22 is adjacent to the first region 21a of the gate trench 21 in the second direction. The contact trench 22 extends in the first direction. A part 12a of the source electrode 12 is located inside the contact trench 22.

[0214] The MOSFET of the sixth embodiment can be manufactured by adding a step of forming the contact trench 22 and a step of forming the electric field relaxation region 38 to the manufacturing method of the MOSFET of the third embodiment.

[0215] As described above, according to the MOSFET of the sixth embodiment, it is possible to simultaneously achieve reduction of on-resistance, improvement of the reliability of the gate insulating layer, and reduction of switching loss. Further, according to the MOSFET and the manufacturing method of the MOSFET of the sixth embodiment, it is possible to reduce the manufacturing cost.

[0216] (Seventh Embodiment) The inverter circuit and the drive device of the seventh embodiment are drive devices including the semiconductor device of the first embodiment.

[0217] FIG. 42 is a schematic diagram of the drive device of the seventh embodiment. The drive device 1000 includes a motor 140 and an inverter circuit 150.

[0218] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three output terminals U, V, and W for alternating voltage is realized. The motor 140 is driven by the alternating voltage output from the inverter circuit 150.

[0219] According to the seventh embodiment, by providing the MOSFET 100 with improved characteristics, the characteristics of the inverter circuit 150 and the drive device 1000 are improved.

[0220] (Eighth Embodiment) The vehicle of the eighth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0221] FIG. 43 is a schematic diagram of the vehicle of the eighth embodiment. The vehicle 1100 of the eighth embodiment is a railway vehicle. The vehicle 1100 includes a motor 140 and an inverter circuit 150.

[0222] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three output terminals U, V, and W for alternating voltage is realized. The motor 140 is driven by the alternating voltage output from the inverter circuit 150. The wheels 90 of the vehicle 1100 are rotated by the motor 140.

[0223] According to the eighth embodiment, by providing the MOSFET 100 with improved characteristics, the characteristics of the vehicle 1100 are improved.

[0224] (Ninth Embodiment) The vehicle of the ninth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0225] FIG. 44 is a schematic diagram of a vehicle according to the ninth embodiment. The vehicle 1200 according to the ninth embodiment is an automobile. The vehicle 1200 includes a motor 140 and an inverter circuit 150.

[0226] The inverter circuit 150 is composed of three semiconductor modules each having the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three output terminals U, V, and W for alternating voltage is realized.

[0227] The motor 140 is driven by the alternating voltage output from the inverter circuit 150. The wheels 90 of the vehicle 1200 are rotated by the motor 140.

[0228] According to the ninth embodiment, by providing the MOSFET 100 with improved characteristics, the characteristics of the vehicle 1200 are improved.

[0229] (Tenth Embodiment) The elevator according to the tenth embodiment is an elevator including the semiconductor device of the first embodiment.

[0230] FIG. 45 is a schematic diagram of an elevator according to the tenth embodiment. The elevator 1300 according to the tenth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0231] The inverter circuit 150 is composed of three semiconductor modules each having the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three output terminals U, V, and W for alternating voltage is realized.

[0232] The motor 140 is driven by the alternating voltage output from the inverter circuit 150. The hoist 616 is rotated by the motor 140, and the car 610 moves up and down.

[0233] According to the tenth embodiment, by providing the MOSFET 100 with improved characteristics, the characteristics of the elevator 1300 are improved.

[0234] As described above, in the first to sixth embodiments, the case of 4H-SiC as the crystal structure of silicon carbide has been described as an example. However, the present invention can also be applied to silicon carbide with other crystal structures such as 6H-SiC and 3C-SiC.

[0235] In addition, in the first to sixth embodiments, the MOSFET has been described as an example of the semiconductor device. However, for example, the present invention can also be applied to an Insulated Gate Bipolar Toramsistor (IGBT).

[0236] In addition, in the seventh to tenth embodiments, the case of providing the semiconductor device of the first embodiment has been described as an example. However, it is also possible to apply the semiconductor devices of the second to sixth embodiments.

[0237] In addition, in the seventh to tenth embodiments, the case of applying the semiconductor device of the present invention to a vehicle or an elevator has been described as an example. However, the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0238] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. For example, the components of one embodiment may be replaced or changed with the components of another embodiment. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0239] 10 Silicon carbide layer 12 Source electrode (first electrode) Part of the 12a source electrode (part of the first electrode) 14 Drain electrode (second electrode) 16 Gate electrode 18 Gate insulating layer 21 Gate trench (first trench) 21a First region 21b Second region 21c Third region 21d Fourth region 22 Contact trench (second trench) 26 Drift region (first silicon carbide region) 26a Part of the drift region (part of the first silicon carbide region) 28 Body region (second silicon carbide region) 28a First low-concentration part (first part) 28b High-concentration part (second part) 30 Source region (third silicon carbide region) 32 Gate trench bottom region (fourth silicon carbide region) 34 Connection region (fifth silicon carbide region) 100 MOSFET (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device) 500 MOSFET (semiconductor device) 600 MOSFET (semiconductor device) 1000 Driving device 1100 Vehicle 1200 Vehicle 1300 Elevator P1 First surface P2 Second surface w1 First width w2 Second width w3 Third width

Claims

1. A silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface facing the first surface, a first trench located on the side of the first surface, having a first region extending in the first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction, wherein a second width of the second region in the second direction is greater than a first width of the first region in the second direction and a third width of the third region in the second direction; a first n-type silicon carbide region; a second p-type silicon carbide region located between the first silicon carbide region and the first surface, having a distance from the second surface to the first trench smaller than a distance from the second surface; a third n-type silicon carbide region located between the second silicon carbide region and the first surface; a fourth p-type silicon carbide region located between the first trench and the first silicon carbide region; a fifth silicon carbide region located in the second direction of the second region and electrically connecting the second silicon carbide region and the fourth silicon carbide region; a silicon carbide layer including the above; a gate electrode located in the first trench; a gate insulating layer located between the gate electrode and the silicon carbide layer; a first electrode located on the side of the first surface of the silicon carbide layer and in contact with the third silicon carbide region; a second electrode located on the side of the second surface of the silicon carbide layer; comprising; the second silicon carbide region has a first portion and a second portion, the first portion is located between the first trench and the second portion, and a p-type impurity concentration of the second portion is higher than that of the first portion; the fifth silicon carbide region is in contact with the second portion. A semiconductor device.

2. A silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface facing the first surface, a first trench located on the side of the first surface, having a first region extending in the first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction, wherein a second width of the second region in the second direction is greater than a first width of the first region in the second direction and a third width of the third region in the second direction; a first n-type silicon carbide region; A p-type second silicon carbide region that is located between the first silicon carbide region and the first surface and has a distance from the second surface that is greater than the distance from the second surface to the first trench; An n-type third silicon carbide region that is located between the second silicon carbide region and the first surface; A p-type fourth silicon carbide region that is located between the first trench and the first silicon carbide region; A fifth silicon carbide region that is located in the second direction of the second region and electrically connects the second silicon carbide region and the fourth silicon carbide region; A silicon carbide layer including the above; A gate electrode located in the first trench; A gate insulating layer located between the gate electrode and the silicon carbide layer; A first electrode located on the side of the first surface of the silicon carbide layer and in contact with the third silicon carbide region; A second electrode located on the side of the second surface of the silicon carbide layer; Comprising; A semiconductor device in which a part of the first silicon carbide region is located between the first trench and the fifth silicon carbide region.

3. The semiconductor device according to claim 1 or claim 2, wherein the fifth silicon carbide region is in contact with the second silicon carbide region, and the fifth silicon carbide region is in contact with the fourth silicon carbide region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second region extends in the second direction.

5. The semiconductor device according to any one of claims 1 to 4, wherein the second width is at least twice the first width.

6. The p-type impurity concentration of the fourth silicon carbide region between the second region and the first silicon carbide region is Higher than the p-type impurity concentration of the fourth silicon carbide region between the first region and the first silicon carbide region. The semiconductor device according to any one of claims 1 to 5.

7. The length of the fifth silicon carbide region in the first direction is at most 1.5 times the length of the second region in the first direction. The semiconductor device according to any one of claims 1 to 6.

8. The p-type impurity concentration of the fifth silicon carbide region is lower than the p-type impurity concentration of the fourth silicon carbide region. The semiconductor device according to any one of claims 1 to 7.

9. The first region and the third region face each other in the second direction. The semiconductor device according to any one of claims 1 to 8.

10. The semiconductor device according to claim 9, wherein the first trench further has a fourth region that faces the second region in the first direction and is continuous with the first region and the third region.

11. The semiconductor device according to any one of claims 1 to 10, wherein the silicon carbide layer further includes a second trench that is adjacent to the first region in the second direction, is located on the side of the first surface, extends in the first direction, and has a part of the first electrode located therein.

12. The semiconductor device according to any one of claims 1 to 11, wherein a fifth silicon carbide region that is in contact with the first trench is located in the first direction of the second region.

13. An inverter circuit including the semiconductor device according to any one of claims 1 to 12.

14. A drive device including the semiconductor device according to any one of claims 1 to 12.

15. A vehicle including the semiconductor device according to any one of claims 1 to 12.

16. An elevator including the semiconductor device according to any one of claims 1 to 12.

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