Semiconductor Transistor Having a Precise Geometric Shape and Related Manufacturing Method

Abstract

To provide a semiconductor transistor with precise geometries.SOLUTION: A semiconductor transistor includes a semiconductor substrate with an original surface, an active region, a shallow trench isolation region, a shallow trench isolation region, a first conductive region and a second conductive region located within the active region, and a spacer. The active region is formed based on the semiconductor substrate and the active region has a fin structure. The shallow trench isolation region surrounds the active region and a gate structure of the semiconductor transistor crosses over the fin structure. The spacer contacts to a sidewall of the gate structure and on the fin structure. A width of the fin structure under the spacer is wider than that of the fin structure under the gate structure, the fin structure has a lateral profile along a direction substantially parallel to the original surface, and the lateral profile of the fin structure includes a rounded corner under the spacer.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 63 / 427,845, filed Nov. 24, 2022. The content of this application is incorporated herein by reference.

[0002] The present invention relates to a semiconductor transistor and a method of manufacturing the same, and in particular, to a semiconductor transistor having precise and well - controlled geometric shapes (e.g., fin structure, fin width, source / drain regions, and / or the shape or dimensions of metal plugs connecting to the source / drain regions), and thus reducing the area of the semiconductor transistor and preventing the collapse of the fin structure.

Background Art

[0003] The most widely used semiconductor MOSFET (Metal - Oxide - Semiconductor Field - Effect Transistor) structure at various process nodes from 20 nm to 5 nm is the so - called "FinFET (Fin Field - Effect Transistor) or Tri - Gate FET". This type of 3D (three - dimensional) FET enables effective miniaturization of its planar area and can enhance its performance, but these miniaturization and performance are required to satisfy Moore's Law. However, Table 1 shows the state - of - the - art transistor density (unit: million transistors / mm 2 , MTr / mm 2 ) by the technologies of different manufacturers, and our calculated values based on the semiconductor transistor density (28.88 MTr / mm 2 ) of the 16 - nm node of Manufacturer A when following Moore's Law. However, while the process node is scaled from 16 nm to 3 nm, it is clear that the number of transistors increasing per unit area fails to meet the requirements of Moore's Law regardless of whether it is Manufacturer A or Manufacturer B. For example, in Table 1, the ideal target numbers of transistors for the 7 - nm and 5 - nm process nodes are 150.88 MTr / mm 2 and 295.73 MTr / mm 2However, in most of the state-of-the-art manufacturing capabilities, the realistic number of transistors per 1mm 2 is found to be much less than what it should be. Table 1 is as follows.

[0004]

Table 1

[0005] One reason that limits the effectiveness of scaling the planar region of FinFETs is due to the scaling of the pitch of the fin body (fin width + fin pitch). For example, the cross-sectional dimensions of a 14nm FinFET, which is a state-of-the-art technology node, are shown in Figure 1. The fin body has a narrow upper region (about 2 - 3nm), a wider central body width (about 5 - 8nm), an even wider width at the bottom of the fin body at the same height as the bottom of the gate (about 9 - 13nm), and a very wide distance between two adjacent FinFETs at the bottom of the STI (usually shallow trench isolation of oxide material), with a strange and sharp shape. The vertical profile of the fin structure has a stepwise transition from the small upper region to the very wide distance at the bottom of the STI. Therefore, the pitch can be about 48nm depending on the capabilities of individual manufacturers / factories, that is, about 3.5F when the minimum feature size or process node declared by individual manufacturers is F. Some weaknesses are revealed here.

[0006] (1) The most important parameter that affects the performance and quality of FinFETs is surely the width of the fin body. However, as shown in state-of-the-art FinFET technology, its variation is large and it is difficult to control precisely.

[0007] (2) This "mountain" shape of the fin is very difficult to maintain its consistency and minimize its variation.

[0008] (3) Optimizing both the width and depth of the STI for this "mountain" is difficult.

[0009] (4) The pitch occupies at least 3F to 5F, which hinders the scaling of the planar area of the semiconductor transistor.

[0010] (5) The main parameters of performance and leakage are affected by the shape and size of this sharp-shaped fin, and it is difficult to minimize their variations.

[0011] (6) As the dimensions of the fin body narrow due to scaling, it may easily bend or fall off. Also, since more FinFETs have to be manufactured on a larger and more complex die, the number of this type of "mountain" fin has increased significantly.

Summary of the Invention

Problems to be Solved by the Invention

[0012] However, in the prior art, there is no excellent technology to solve the above problems. Therefore, in order to meet the requirements of Moore's Law to increase the number of transistors per unit area and reduce the cost per transistor, how to solve the above problems is an issue.

Means for Solving the Problems

[0013] Embodiments of the present invention provide a semiconductor transistor. The semiconductor transistor includes a semiconductor substrate, an active region, a shallow trench isolation region, a first conductive region, a second conductive region, and a spacer. The semiconductor substrate has an original surface. The active region is formed based on the semiconductor substrate, and the active region has a fin structure. The shallow trench isolation region surrounds the active region, and a gate structure of the semiconductor transistor straddles the fin structure. The first conductive region and the second conductive region of the semiconductor transistor are located within the active region. The spacer contacts a sidewall of the gate structure and is on the fin structure. A width of the fin structure under the spacer is wider than a width of the fin structure under the gate structure, the fin structure has a horizontal profile along a direction substantially parallel to the original surface, and the horizontal profile of the fin structure includes a rounded corner under the spacer.

[0014] According to one aspect of the present invention, the first conductive region is restricted by the shallow trench isolation region, and a width of the first conductive region is wider than a width of the fin structure under the gate structure.

[0015] According to one aspect of the present invention, the fin structure includes a fin body and a fin base, the fin structure has a vertical profile along a direction substantially perpendicular to the original surface, and the vertical profile includes a stepped transition or a non-stepped transition between the fin body and the fin base.

[0016] According to one aspect of the present invention, the horizontal profile of the fin structure further provides another stepped transition or a non-stepped transition between the fin structure under the gate structure and the rounded corner.

[0017] According to one aspect of the present invention, the first conductive region contacts a first end of the fin structure, the second conductive region contacts a second end of the fin structure, and the first conductive region and the second conductive region are independent of the fin structure.

[0018] According to one aspect of the present invention, the bottom of the gate structure above the shallow trench isolation region is lower than the bottom of the first conductive region and / or the second conductive region.

[0019] According to one aspect of the present invention, at least two side surfaces of the first conductive region or the second conductive region are in contact with the metal-containing region.

[0020] Another embodiment of the present invention provides a semiconductor transistor. The semiconductor transistor includes a semiconductor substrate, an active region, a shallow trench isolation region, a gate structure, a first conductive region, a second conductive region, a trench, and an internal spacer. The semiconductor substrate has an original surface. The active region is formed based on the semiconductor substrate, and the active region has a fin structure. The shallow trench isolation region surrounds the active region. The gate structure of the semiconductor transistor straddles the fin structure and covers a first portion of the shallow trench isolation region. The first conductive region and the second conductive region of the semiconductor transistor are located within the active region. The trench extends along the longitudinal direction of the gate structure. The internal spacer is filled in the contact portion with the side wall of the gate structure, and the width of the internal spacer is limited by the trench. The fin structure includes a fin body and a fin base, the fin body is covered by the gate structure, and the spacer covers at least the side wall of the fin body.

[0021] According to one aspect of the present invention, the spacer further covers a portion of the side wall of the fin base.

[0022] According to one aspect of the present invention, the spacer is a composite spacer including an oxide sub-spacer and a SiCOH sub-spacer surrounding the side wall and the upper surface of the oxide sub-spacer.

[0023] According to one aspect of the present invention, at least two side surfaces of the first conductive region or the second conductive region are in contact with the metal-containing region.

[0024] According to one aspect of the present invention, the upper surface of the first portion of the shallow trench isolation region covered by the gate structure is lower than the upper surface of the other portion of the shallow trench isolation region not covered by the gate structure.

[0025] According to one aspect of the present invention, the fin structure has a vertical profile along a direction substantially perpendicular to the original surface, and the vertical profile of the fin structure provides a first stepped transition or a non-stepped transition.

[0026] According to one aspect of the present invention, the first stepped transition or non-stepped transition is between the fin body and the fin base.

[0027] According to one aspect of the present invention, the fin structure has a horizontal profile along a direction substantially along the original surface, and the horizontal profile of the fin structure provides a second stepped transition or a non-stepped transition.

[0028] According to one aspect of the present invention, the second stepped transition or non-stepped transition is between the gate structure and the first conductive region.

[0029] According to one aspect of the present invention, the horizontal profile of the fin structure further provides a third stepped transition or non-stepped transition between the gate structure and the second conductive region.

[0030] According to one aspect of the present invention, the first conductive region and / or the second conductive region is restricted by the shallow trench isolation region.

[0031] According to one aspect of the present invention, the bottom of the gate structure on the first portion of the shallow trench isolation region is lower than the bottom of the first conductive region and / or the second conductive region.

[0032] According to one aspect of the present invention, the first conductive region and the second conductive region are independent of the fin structure and are not on the shallow trench isolation region.

[0033] Another embodiment of the present invention provides a semiconductor transistor. The semiconductor transistor includes a semiconductor substrate, an active region, a shallow trench isolation region, a gate structure, a first conductive region, a second conductive region, and an internal spacer. The semiconductor substrate has an original surface. The active region is formed based on the semiconductor substrate, and the active region has a fin structure. The shallow trench isolation region surrounds the active region. The gate structure of the semiconductor transistor straddles the fin structure and covers a first portion of the shallow trench isolation region. The first conductive region and the second conductive region of the semiconductor transistor are located within the active region. The internal spacer contacts the sidewall of the gate structure. The fin structure includes a fin body and a fin base, the fin body is covered by the gate structure, and the spacer covers at least the sidewall of the fin body. The fin structure has a vertical profile along a direction substantially perpendicular to the original surface, and the vertical profile of the fin structure provides a first stepped transition or a non-stepped transition.

[0034] According to one aspect of the present invention, the spacer further covers a portion of the sidewall of the fin base.

[0035] According to one aspect of the present invention, the spacer is a composite spacer including an oxide sub-spacer and a SiCOH sub-spacer surrounding the sidewall and the upper surface of the oxide sub-spacer.

[0036] According to one aspect of the present invention, at least two side surfaces of the first conductive region or the second conductive region contact a metal-containing region.

[0037] According to one aspect of the present invention, the upper surface of the first portion of the shallow trench isolation region covered by the gate structure is lower than the upper surface of the other portion of the shallow trench isolation region not covered by the gate structure.

[0038] According to one aspect of the present invention, the first stepped transition or the non-stepped transition is between the fin body and the fin base.

[0039] According to one aspect of the present invention, the fin structure has a horizontal profile along a direction substantially along the original surface, and the horizontal profile of the fin structure is provided with a second stepped transition portion or a non-stepped transition portion.

[0040] According to one aspect of the present invention, the first conductive region and / or the second conductive region is limited by a shallow trench isolation region.

[0041] According to one aspect of the present invention, the bottom of the gate structure on the first portion of the shallow trench isolation region is lower than the bottom of the first conductive region and / or the second conductive region.

[0042] According to one aspect of the present invention, the first conductive region and the second conductive region are independent of the fin structure and are not on the shallow trench isolation region.

[0043] Another embodiment of the present invention provides a manufacturing method. The manufacturing method includes forming a fin structure including a fin body and a fin base on a semiconductor substrate, forming a gate structure on the fin structure, forming a gate spacer on the fin structure, and controlling the width of the fin body in the gate structure such that the width of the fin body inside the gate structure and outside the gate spacer is narrower than the width of the fin body under the gate spacer. The fin structure has a horizontal profile along a direction substantially parallel to the original surface, and the horizontal profile of the fin structure includes a rounded corner under the gate spacer.

[0044] According to one aspect of the present invention, the step of forming the fin structure includes defining the fin structure by a pad cover layer, etching a semiconductor substrate using a first etching process based on the pad cover layer to form a fin body, forming a side spacer layer to cover the sidewalls of the fin body, and further etching the semiconductor substrate using a second etching process based on the pad cover layer and the spacer layer to form a fin base.

[0045] According to one aspect of the present invention, the step of forming the gate structure includes forming a STI region so as to surround the fin structure, wherein the upper surface of the STI region is higher than the original surface of the semiconductor substrate, defining the gate structure by a patterned photoresist, and etching downward the portion of the STI region and the portion of the pad cover layer within the gate structure.

[0046] According to one aspect of the present invention, the step of forming a gate spacer on the fin structure includes forming a polysilicon spacer to cover the sidewalls of the gate structure, forming a TiN layer and a tungsten material to fill the remaining portion of the gate structure, removing the polysilicon spacer to form a groove within the gate structure, etching downward the STI region within the groove, forming a gate spacer to fill the groove, and removing the TiN layer and the tungsten material.

[0047] According to one aspect of the present invention, the step of controlling the width of the fin body within the gate structure includes etching downward the STI region within the gate structure, removing the side spacer layer within the gate structure to expose the sidewalls of the fin body, and etching the fin body in the horizontal direction such that the width of the fin body within the gate structure and outside the gate spacer is narrower than the width of the fin body under the gate spacer.

[0048] According to one aspect of the present invention, the manufacturing method further includes removing a pad cover layer in a gate structure to expose the upper surface of a fin body, forming an EOT (equivalent oxide thickness) spacer on both the upper surface and the sidewall of the fin body, and forming a gate structure so as to cover the upper surface and the sidewall of the fin body and the sidewall of the fin base in the gate structure. The gate structure includes a gate dielectric layer and a gate conductive layer that cover the fin body, the fin base, and the STI region within the defined gate structure.

[0049] According to one aspect of the present invention, the manufacturing method includes removing a pad cover layer outside a defined gate structure to expose a first portion of the original surface of a semiconductor substrate, etching the semiconductor substrate based on the first portion of the original surface to form a first trench, and forming a first conductive structure of a semiconductor transistor based on the first trench.

[0050] According to one aspect of the present invention, the step of forming the first conductive structure includes forming a coating oxide layer based on the surface of the first trench, etching a portion of the coating oxide layer to form an exposed sidewall of the semiconductor substrate, and forming a doped semiconductor structure based on the exposed sidewall of the semiconductor substrate, wherein the doped semiconductor structure is restricted by the STI region, and filling the first trench and forming a metal structure in contact with the doped semiconductor structure.

[0051] According to one aspect of the present invention, the doped semiconductor structure includes a semiconductor region doped at a low concentration and a semiconductor region doped at a high concentration.

[0052] These and other objects of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments shown in the various figures and drawings.

Brief Description of the Drawings

[0053]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Embodiments for Carrying Out the Invention

[0054] The present invention achieves a new 3D FET structure that can improve or eliminate the above problems and has a smaller fin pitch with a more precise fin width. Therefore, it discloses a new manufacturing method and its inventive principle for approaching the requirements of Moore's Law by reducing the plane of the semiconductor transistor, increasing the number of transistors per unit area, and reducing the cost per transistor. The new FinFET or trigate FET is called an RB-FinFET or RB-trigate FET (RB: rectangular body), which can be achieved by the manufacturing method described in FIG. 2A. The detailed steps are as follows.

[0055] Step 10: Start.

[0056] Step 20: Based on a semiconductor substrate, form a fin structure having a fin body and a fin base.

[0057] Step 30: Define a gate region on the fin structure.

[0058] Step 40: Thin the fin structure within the gate region.

[0059] Step 50: Form a gate structure within the gate region.

[0060] Step 60: Form the source region and the drain region.

[0061] Step 70: End.

[0062] See FIGS. 2B, 3, and 4. Step 20 may include the following.

[0063] Step 102: Define the active region by a cover layer (such as a composite layer having a pad oxide layer 204 and a pad nitride layer 206 shown in FIG. 3).

[0064] Step 104: Etch the semiconductor substrate using a first etching process based on the cover layer to form the fin body of the fin structure (FIG. 3).

[0065] Step 106: Form a spacer layer (such as a composite layer of an oxide spacer - 1 208 and a nitride spacer - 1 210) to cover the sidewalls of the fin body (FIG. 3).

[0066] Step 108: Further etch the semiconductor substrate by a second etching process based on the cover layer and the spacer layer to form the fin base of the fin structure (FIG. 4).

[0067] Next, see FIGS. 2C, 5, 6, 7, 8, 9, and 10. Step 30 may include the following.

[0068] Step 110: Form a shallow trench isolation (STI) region 212 to surround the fin structure (FIG. 5).

[0069] Step 112: Define a gate region over the active region and the STI region 212 by a patterned photoresist including an oxide-2 layer 602 and a photoresist layer 604 (FIG. 6).

[0070] Step 114: Remove the photoresist layer 604 within the gate region, form spacers 702, and deposit a TiN layer 704 and a thick tungsten layer 706 (FIG. 7).

[0071] Step 116: Remove the spacers 702 to form trenches 802, etch the STI region 212 within the trenches 802 downward, and remove the oxide-2 layer 602 (FIG. 8).

[0072] Step 118: Remove the thin pad nitride layer within the trenches 802, deposit a thin SiCOH layer 902, deposit a thin oxide layer 904, and then polish the SiCOH layer 902, the oxide layer 904, the STI region 212, and the TiN layer 704 / W layer 706 using CMP technology (FIG. 9).

[0073] Step 120: Etch the upper portion of the oxide layer 904 (or a composite deep sidewall spacer), deposit a SiCOH layer 1202, polish the SiCOH layer 1202 using CMP technology, and then remove the TiN layer 704 / W layer 706 (FIG. 10).

[0074] See FIGS. 2D, 11, and 12. Step 40 may include the following.

[0075] Step 122: Etch the surrounding STI oxide region within the gate region downward, etch and remove the oxide spacer-1 208 / nitride spacer-1 210 within the gate region to expose the sidewalls of the fin body, and horizontally etch the fin body to a target width (FIG. 11).

[0076] Step 124: Isotropically etch a portion of the SiCOH layer 902 of the internal stress deep spacer, and remove the thin pad nitride layer and the pad oxide layer 204 within the gate region (FIG. 12).

[0077] Refer to FIGS. 2E and 13. Step 50 may include the following.

[0078] Step 126: Form a gate dielectric layer 1302 on the thin fin body within the gate region (FIG. 13).

[0079] Step 128: Form a gate conductive layer 1304 on the gate dielectric layer 1302 (FIG. 13).

[0080] Step 130: Form a gate cap layer 1306 on the gate conductive layer 1304 (FIG. 13).

[0081] Refer to FIGS. 2F, 14, 15, 16 and 17. Step 60 may include the following.

[0082] Step 132: Remove the cover layer outside the gate structure (FIG. 14).

[0083] Step 134: Based on the exposed portion of the OSS, etch the semiconductor substrate to form two trenches 1502 (FIG. 15).

[0084] Step 136: Thermally grow an oxide-3 layer 1504 (FIG. 15).

[0085] Step 138: Form a nitride layer 1602 (FIG. 16).

[0086] Step 140: Etch and remove a portion of the oxide-3 layer 1504 (FIG. 16).

[0087] Step 142: Within the shallow trench 1502, form an n-type lightly doped drain (LDD) 1702, an n + doped source region 1704 and an n + doped drain region 1706, and form a metal contact portion including a TiN layer 1708 and a tungsten plug 1710 (FIG. 17).

[0088] Well-designed, starting with a doped p-type well 202, which is disposed within a p-type substrate 200 (in another embodiment of the present invention, instead of starting with the p-type well 202, it is also possible to start with the p-type substrate 200), and in one example, the p-type substrate 200 has a concentration close to 5×10 15 dopants / cm 3 and can supply a p-type substrate voltage (usually grounded, i.e., 0V) across most of the body of the FinFET.

[0089] In step 102, as shown in FIG. 3(a), a pad oxide layer 204 is thermally grown on the OSS (original silicon surface), and a pad nitride layer 206 is deposited on the pad oxide layer 204. Next, using photolithography techniques, the active regions to which the fin bodies of the FinFETs are assigned are defined.

[0090] In step 104, as shown in FIG. 3(a), based on the pad nitride layer 206, the first etching process removes the pad nitride layer 206 and the pad oxide layer 204 from the active regions using anisotropic etching techniques, and then uses a first dig etching (reactive ion etching, RIE, etc.) to dig into the silicon to create trenches formed within the silicon at a depth of approximately 50 nm in the p-type well 202. In one embodiment of the present invention, the width of the pad nitride layer 206 on the active region along the Y direction shown in FIG. 3(b) is 9 nm at a process node of F = 5 nm, the space between two active regions is 9 nm, and as a result, the pitch is 18 nm = 3.6F. In other embodiments of the present invention, the width of the pad nitride layer 206 on the active region along the Y direction can be 12 nm at a process node of F = 12 nm, the space between two active regions is 12 nm, and as a result, the pitch is 24 nm = 2F. The foregoing numbers are listed for illustrative purposes and the present invention is not limited to those dimensions.

[0091] Next, in step 106, as shown in FIG. 3(a), a thermal oxidation treatment is performed along the exposed silicon sidewalls to vertically form a thin oxide spacer 1 208 outside the fin body, and a nitride spacer 1 210 is vertically formed outside the oxide spacer 1 208. The oxide spacer -1 208 and the nitride spacer -1 210 can protect the fin body structure. It should be noted that in one example, the oxide spacer -1 208 is very thin and has little effect on the fin width. Also, FIG. 3(b) is a top view corresponding to FIG. 3(a), FIG. 3(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 3(b), and FIG. 3(c) is a cross-sectional view along the cutting line in the Y direction shown in FIG. 3(b).

[0092] Next, in step 108, as shown in FIG. 4(a), using the anisotropic etching technique (i.e., the second dig etching) with the pad nitride layer 206 and the nitride spacer 1 210 as masks, the silicon of the p-type well 202 (such as a silicon depth of 100 nm) is removed to form a deep trench, and the depth from the top of the OSS of the deep trench is made about 150 - 200 nm. Also, FIG. 4(b) is a top view corresponding to FIG. 4(a), FIG. 4(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 4(b), and FIG. 4(c) is a cross-sectional view along the cutting line in the Y direction shown in FIG. 4(b). As shown in FIG. 4(c), due to the presence of the oxide spacer -1 208 and the nitride spacer -1 210, the vertical profile of the fin structure (along the direction (Z-axis) substantially perpendicular to the OSS) has a stepped transition between the part of the fin structure formed by the first dig etching and the part of the fin structure formed by the second dig etching. This can also be a non-stepped transition formed by different etching processes.

[0093] Next, in step 110, as shown in FIG. 5(a), an oxide layer having a thickness sufficient to fill the deep trenches is deposited. Next, using CMP (Chemical Mechanical Polishing) technology, the oxide deposited in excess on top of the pad nitride layer 206 is removed to form a shallow trench isolation (STI) 212 (or STI region - 1 or simply referred to as STI - 1), and the upper surface of the STI region 212 is, for example, at the height up to the top of the pad nitride layer 206 and higher than the OSS. Also, FIG. 5(b) is a top view corresponding to FIG. 5(a), FIG. 5(a) is a cross - sectional view along the cutting line in the X direction shown in FIG. 5(b), and FIG. 5(c) is a cross - sectional view along the cutting line in the Y direction shown in FIG. 5(b).

[0094] Via the oxide spacer - 1 208, nitride spacer - 1 210, and STI region 212, the fin structure formed by the first dry etching and the second dry etching (see FIG. 4(c)) is well protected. In a conventional FinFET, the fin structure is formed by only one etching, and the fin body appears trapezoidal (see FIG. 1), so it is difficult to control the width of the fin body, and the fin body is easily crushed. By the multiple silicon dry etchings (i.e., the first dry etching and the second dry etching) and the protection process according to the present invention, the crushing of the fin structure during the etching process can be prevented, and the shape of the fin structure is rectangular, especially in the portion of the fin structure formed by the first dry etching.

[0095] The following describes a method for forming an RB structure having a narrow fin body. In step 112, as shown in FIG. 6(a), an oxide-2 layer 602 is deposited, and then a photolithography technique is used to define a gate region not protected by a photoresist layer 604. Next, using the photoresist layer 604 as a protective mask, the oxide-2 layer 602 within the gate region is etched away, and then the pad nitride layer 206 within the gate region is thinned (referred to as a thin pad nitride layer). The STI region 212 within the gate region is also etched and removed to the depth of the bottom of the etched STI region up to the top of the thin pad nitride layer (the etched STI region is called thin STI-1). Also, FIG. 6(b) is a top view corresponding to FIG. 6(a), FIG. 6(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 6(b), and FIG. 6(c) is a cross-sectional view along the cutting line in the Y direction shown in FIG. 6(b).

[0096] Next, in step 114, as shown in FIG. 7(a), the photoresist layer 604 is removed. Due to the height difference from the original height of the pad nitride layer 206 / STI region 212 to both the thin pad nitride layer and the thin STI-1, spacers 702 (for example, intrinsic amorphous silicon (or polysilicon) spacers with a thickness of 7 - 8 nm) are formed on both sides of the pad nitride layer 206 (that is, a thin layer of intrinsic amorphous silicon is deposited inside the gate region, and then the intrinsic amorphous silicon is etched using an anisotropic etching technique to form the spacers 702). Next, a sufficiently thick TiN layer 704 and a tungsten (W) layer 706 are deposited on the upper surface of the thin pad nitride layer, and then a CMP technique is used to polish the TiN layer 704 and the tungsten layer 706 until the spacers 702 are exposed. Also, FIG. 7(b) is a top view corresponding to FIG. 7(a), and FIG. 7(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 7(b).

[0097] Next, in step 116, as shown in FIG. 8(a), by removing the spacer 702 using an anisotropic etching technique, a groove 802 is formed between the TiN layer 704 and the pad nitride layer 206. The bottom of the groove 802 is located on each of the thin pad nitride layer above the thin STI-1 in the gate region and the silicon portion in the active region along the longitudinal direction of the gate (refer to the direction of the cutting line in the Y direction shown in FIG. 6(b)). Thereafter, using an anisotropic etching technique, the STI region 212 within the groove 802 (but outside the active region) is removed to a depth deeper than the depth of the fin body (for example, a depth of about 60 nm). The oxide-2 layer 602 can also be removed in step 116. Further, FIG. 8(b) is a top view corresponding to FIG. 8(a), FIG. 8(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 8(b), and FIG. 8(c) is a cross-sectional view along the cutting line in the X1 direction shown in FIG. 8(b).

[0098] Next, in step 118, as shown in FIG. 9(a), the thin pad nitride layer within the groove 802 is removed until the pad oxide layer 204 is exposed. The pad oxide layer 204 is on top of the OSS. Next, a SiCOH layer 902 that enters the two edges within the groove 802 but is not thick enough to cover the groove 802 is deposited (for example, since it is about 2 nm thick, an empty groove remains with a width of about 4 nm).

[0099] Next, as shown in FIG. 9(a), an oxide layer 904 is deposited to completely fill the empty trench. Thereafter, using CMP technology, the SiCOH layer 902 / oxide layer 904 over the pad nitride layer 206, STI region 212, and TiN layer 704 / W layer 706 is polished. The SiCOH layer 902 and oxide layer 904 (e.g., 2 nm SiCOH layer + 4 nm central oxide layer + 2 nm SiCOH layer) surround the depth of the fin body and are located above the pad oxide layer 204 over both the OSS in the trench 802 and the deep fin shape, forming a composite deep sidewall spacer below the OSS. Such a composite deep sidewall spacer can introduce stress and can be referred to as an internal stress deep spacer. Also, FIG. 9(b) is a top view corresponding to FIG. 9(a), FIG. 9(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 9(b), and FIG. 9(c) is a cross-sectional view along the cutting line in the X1 direction shown in FIG. 9(b).

[0100] Thereafter, in step 120, as shown in FIG. 10(a), using anisotropic etching technology, the upper portion (e.g., about 5 nm thick) of the oxide layer 904 (or the composite deep sidewall spacer) is etched downward to leave a trench over the composite deep sidewall spacer. Next, a SiCOH layer 1202 (e.g., 2 nm thick) is deposited to completely fill the upper trench over the composite deep sidewall spacer. Next, using CMP technology, the upper portion of the SiCOH layer 1202 is removed until the upper portions of the TiN layer 704 / W layer 706, the SiCOH layer 1202, and the pad nitride layer 206 become a flat surface.

[0101] Next, the TiN layer 704 / W layer 706 is removed so that the exposed region from the top view (shown in FIG. 10(b)) shows an internal stress deep spacer having a thin pad nitride layer within the gate region, a surrounding low oxide region within the gate region (i.e., the STI region 212), and a SiCOH cap (i.e., the SiCOH layer 1202). Also, FIG. 10(b) is a top view corresponding to FIG. 10(a), and FIG. 10(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 10(b).

[0102] Option 1: With fin thinning Next, in step 122, as shown in FIG. 11(a), the surrounding STI oxide region (i.e., STI region 212) within the gate region is etched downward until its upper surface is below the OSS of about 60 nm, exposing the fin body covered by the oxide spacer-1 208 / nitride spacer-1 210, and making the fin base the same way.

[0103] Next, as shown in FIG. 11(c), the oxide spacer 1 208 / nitride spacer 1 210 within the gate region is etched away to expose the sidewalls of the fin body. A horizontal etching technique for removing the exposed silicon of the fin body / fin base between the two internal stress deep spacers is performed to thin the fin body to the target width (e.g., the remaining horizontal width of the fin body within the gate region is narrowed to about 6 nm, and silicon is removed horizontally by about 3 nm on each side. However, the width of the fin body under the pad nitride layer 206 / pad oxide layer 204 in the other active regions (outside the gate region) remains about 12 nm). Therefore, even if the fin body within the gate region is thinned, the remaining fin bodies extending horizontally at the two ends of the active region are still protected by the oxide spacer-1 208, nitride spacer-1 210, and STI region-1, and the same applies to the fin base. For this reason, it is possible to effectively prevent the collapse of the thinned fin body. Also, FIG. 11(b) is a top view corresponding to FIG. 11(a), FIG. 11(a) is a cross-sectional view along the cutting line in the X1 direction shown in FIG. 11(b), and FIG. 11(c) is a cross-sectional view along the cutting line in the Y direction shown in FIG. 11(b). Also, the cross-sectional view along the cutting line in the X direction shown in FIG. 11(b) can refer to FIG. 10(a).

[0104] Next, in step 124, as shown in Fig. 12(a), the SiCOH layer 902 of the internal stress deep spacer is isotropically etched by about 1 to 2 nm to expose the silicon region thereunder. The silicon under and around the SiCOH layer 902 of the internal stress deep spacer may be removed, and finally, as marked by circle A in Fig. 12(b), it should be noted that it becomes a rounded corner with a thickness of about the SiCOH layer 902 (e.g., due to the thinning effect of the fin, about 2 nm = 66% of 3 nm). Further, as marked by circle B in Fig. 12(b), the horizontal profile (along the X direction) of the fin structure further provides a stepped transition portion or a non-stepped transition portion after the rounded corner. Next, the thin pad nitride layer and the pad oxide layer 204 on top of the narrow fin structure are removed (e.g., about 6 nm width of the fin structure of the semiconductor transistor body). Fig. 12(b) is a top view corresponding to Fig. 12(a), Fig. 12(a) is a cross-sectional view along the cutting line in the X direction shown in Fig. 12(b), Fig. 12(c) is a cross-sectional view along the cutting line in the Y1 direction shown in Fig. 12(b), Fig. 12(d) is a cross-sectional view along the cutting line in the Y2 direction shown in Fig. 12(b), Fig. 12(c) corresponds to the gate region, and Fig. 12(d) corresponds to the source region / drain region.

[0105] Thereafter, an EOT (equivalent oxide thickness) of about 1.2 nm, such as an HK material, is formed on both the upper part and the sidewalls of the fin structure. The EOT is formed at a depth such that the thin fin body is exposed and also in the region of the aforementioned rounded corner. Thus, the channel region is on both sides of the narrow fin structure and has a small rounded extension up to the wide fin region under the composite deep sidewall spacer. From the upper surface on the EOT towards the channel region and the body region of the narrow fin structure, the entire silicon body is a p-substrate until an LDD (lightly doped drain) n-type doping is formed. Thus, there is no thin EOT, and there is also no extra gate-drain / source capacitance formed between the gate region and the drain / source region. By an appropriate design of forming the edge of the LDD region in the gate region, concerns about either underlap or overlap between the gate and the drain / source region are reduced.

[0106] Next, in step 126, as shown in FIG. 13(a), a gate dielectric layer 1302 (e.g., a Hi-k / oxide gate dielectric material) is formed within the gate region. Thereafter, in step 128, as shown in FIG. 13(a), a gate conductive material (e.g., N + polysilicon) 1304 is deposited, and then CMP / etch-back is performed on the gate conductive material 1304. Thereafter, in step 130, as shown in FIG. 13(a), a nitride layer 13062 and a hard mask oxide (HM_oxide) layer 13064 of the gate cap layer 1306 are deposited, and then CMP is performed on the HM_oxide layer 13064 and the nitride layer 13062 so that the upper portion of the HM_oxide layer 13064 aligns with the pad nitride layer 206. However, the gate dielectric layer 1302, the gate conductive material 1304, and the gate cap layer 1306 function as a gate structure. Also, FIG. 13(b) is a top view corresponding to FIG. 13(a), FIG. 13(a) is a cross-sectional view taken along the cutting line in the X direction shown in FIG. 13(b), and FIG. 13(c) is a cross-sectional view taken along the cutting line in the Y direction shown in FIG. 13(b).

[0107] Hereinafter, an example of forming the source / drain regions will be described. In step 132, as shown in FIG. 14(a), the cover layer (pad nitride layer 206 and pad oxide layer 204) outside the gate structure is removed to expose the silicon surface, although a part of the STI region 212 and the HM_oxide layer 13064 may also be removed. Note that the upper portion of the STI region 212 (along the X direction shown in FIG. 14(b)) is higher than the OSS, and such a high STI region 212 can help limit the formation of the source / drain regions by selective growth described later. Also, FIG. 14(b) is a top view corresponding to FIG. 14(a), and FIG. 14(a) is a cross-sectional view taken along the cutting line in the X direction shown in FIG. 14(b).

[0108] Next, in step 134, as shown in FIG. 15(a), some of the exposed silicon is etched away to form a shallow trench 1502 (e.g., about 80 nm deep) for the source / drain regions.

[0109] Next, in step 136, as shown in FIG. 15(a), using a thermal oxidation process called the oxidation-3 process, an oxide-3 layer 1504 (including both an oxide-3V layer 15042 (assuming a sharp crystal orientation <110>) that penetrates the vertical sidewalls of the semiconductor transistor body and an oxide-3B layer 15044 on top of the bottom of the shallow trench 1502 corresponding to the source / drain region) is grown. However, the oxidation-3 process hardly grows oxide (i.e., oxide-3 layer 1504) on these walls so that the width of the source / drain region is not much affected by the oxidation-3 process. As shown in FIG. 15(a), the thicknesses of the oxide-3V layer 15042, the oxide-3B layer 15044, and subsequent figures are shown only for illustrative purposes, and their geometric shapes are not proportional to the dimensions of the STI region 212 shown in these figures. For example, the thicknesses of the oxide-3V layer 15042 and the oxide-3B layer 15044 are about 10 - 20 nm, but the vertical height of the STI region 212 can be about 150 - 200 nm. However, it is very important to design the oxidation-3 process so that the thickness of the oxide-3V layer 15042 can be very accurately controlled at precisely controlled thermal oxidation temperature, timing, and growth rate. By thermal oxidation on a well-defined silicon surface, 40% of the thickness of the oxide-3V layer 15042 is removed from the thickness of the exposed <110> silicon surface within the vertical walls of the semiconductor transistor body, and the remaining 60% of the thickness of the oxide-3V layer 15042 should be counted as an additional outside the vertical walls of the semiconductor transistor body. Also, FIG. 15(b) is a top view corresponding to FIG. 15(a), and FIG. 15(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 15(b).

[0110] Next, in step 138, as shown in FIG. 16(a), using CVD nitride deposition and then performing etch-back to form a nitride layer 1602 on the oxide-3B layer 15044. (In another embodiment of the present invention, optionally, tungsten is further deposited and etch-back is performed to form a tungsten layer on the nitride layer 1602. Next, TiN is deposited and etch-back is performed to form a TiN layer on the tungsten layer, such that the upper part of the TiN layer is about 20 - 40 nm lower than the OSS).

[0111] Next, in step 140, as shown in FIG. 16(a), an etching process is performed to etch the oxide-3 layer 1504, particularly the oxide-3V layer 15042, to expose the <110> crystal orientation of the silicon region. However, the width of the exposed <110> crystal orientation silicon can be about 9 nm, which is larger than the width of the fin body under the gate (about 6 nm). FIG. 16(b) is a top view corresponding to FIG. 16(a), and FIG. 16(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 16(b).

[0112] Thereafter, in step 142, as shown in FIG. 17(a), using a selective growth technique (such as selective epitaxial growth (SEG) technique), an n-type LDD 1702, an n + doped source region 1704, and an n + doped drain region 1706 are respectively formed from the exposed <110> crystal orientation of the silicon region. The grown n-type LDD 1702 and / or n + doped source region 1704 and n + doped drain region 1706 can be annealed such that the interface between the n-type LDD 1702 and the p-type substrate material of the p-type well 202 is close to the narrow channel region. It should be noted that ion implantation is not required to form all the channel, drain, and source regions, and high-temperature and long-time thermal annealing are not required to remove the damage caused by the heavy impact for forming these regions. Further, since the upper surface of the STI region 212 is higher than the OSS, the n-type LDD 1702, n + doped source region 1704, and n +The doped drain region 1706 is restricted by the high STI region 212 without growing on the STI region and has a well-grown <110> crystalline silicon structure.

[0113] Finally, a TiN layer 1708 and then a tungsten plug 1710 are deposited to fill the shallow trench 1502 corresponding to the source / drain region and form a metal contact. Therefore, the metal contact is self-aligned with respect to the doped drain region 1706 without using an additional photolithography process for forming a contact hole. At this point, + the doped drain region 1706. + the doped source region 1704 and + the height of the doped drain region 1706 is about 40 - 50 nm, + the doped source region 1704 and + the doped drain region 1706 is surrounded by the TiN layer 1708 and the tungsten plug 1710 at least on two sides (the upper surface and the outermost sidewall), so the contact resistance is dramatically reduced. Further, since the STI region 212 corresponding to the gate region is etched about 60 - 80 nm below the upper part of the OSS, the bottom of the gate structure (refer to FIG. 11(b)) (above the STI region 212) can be made about 10 - 20 nm lower than the bottom of the doped source region 1704 and + the doped drain region 1706, and the Ioff can also be reduced. Also, FIG. 17(b) is a top view corresponding to FIG. 17(a), FIG. 17(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 17(b), FIG. 17(c) is a cross-sectional view along the cutting line in the Y1 direction shown in FIG. 17(b), FIG. 17(d) is a cross-sectional view along the cutting line in the Y2 direction shown in FIG. 17(b), FIG. 17(c) corresponds to the gate region, and FIG. 17(d) corresponds to + the doped drain region 1706. Further, the width of the fin body in the gate region is narrower (for example, 6 nm as shown in FIG. 17(c)), + the doped source region 1704 ( + the doped source region 1704 ( +It is clear that the width of the doped drain region 1706) is wider (for example, 12 nm as shown in FIG. 17(d)). n + The doped source region 1704 (n + Since the width of the doped drain region 1706) is wider than the width of the fin body in the gate region, n + The doped source region 1704 (n + the resistance of the doped drain region 1706) can be controlled within an acceptable range, n + The doped source region 1704 (n + the wide width of the doped drain region 1706) is also useful for metal contact.

[0114] In the above-described embodiment, n + the doped source region 1704 / n + Although the gate structure is first formed before the formation of the doped source region 1704 / doped drain region 1706, it is well known that the "gate-last" process can be carried out without difficulty in the present invention and does not need to be described in detail here.

[0115] Option 2: Without fin thinning The above-described process, particularly the internal stress deep spacer, can be applied to a fin structure without thinning. Following the above FIG. 10, the surrounding low oxide region in the gate region is etched downward until its upper surface is under the OSS of about 60 nm (as shown in FIG. 18(a)) so that the fin body covered by the oxide spacer-1 208 / nitride spacer-1 210 is exposed and becomes part of the fin base. Next, the oxide spacer-1 208 / nitride spacer-1 210 is etched away to expose the sidewalls of the fin body (as shown in FIG. 18(c)). Also, FIG. 18(b) is a top view corresponding to FIG. 18(a), FIG. 18(a) is a cross-sectional view along the cutting line in the X1 direction shown in FIG. 18(b), and FIG. 18(c) is a cross-sectional view along the cutting line in the Y direction shown in FIG. 18(b). Furthermore, as shown in FIG. 18(b), since the cross-sectional view along the cutting line in the X direction can refer to FIG. 10(a), further description is omitted for simplicity.

[0116] Next, as shown in FIG. 19(b), remove the thin pad nitride layer and the pad oxide layer 204 on top of the narrow fin structure (e.g., about 6 nm width of the fin of the semiconductor transistor body). Also, FIG. 19(b) is a top view corresponding to FIG. 19(a), FIG. 19(a) is a cross-sectional view along the cutting line in the Y direction shown in FIG. 19(b), and FIG. 19(c) is a cross-sectional view along the cutting line in the Y2 direction shown in FIG. 19(b). Further, as shown in FIG. 19(b), since the cross-sectional view along the cutting line in the X direction can refer to FIG. 12(a), further description is omitted for simplicity.

[0117] Thereafter, as shown in FIG. 20(a), a gate dielectric layer 2002 (e.g., Hi-k / oxide gate dielectric material) is formed in the defined gate region, a gate conductive material (e.g., N + polysilicon) 2004 is deposited, and then CMP / etch-back is performed on the gate conductive material 2004. Thereafter, a nitride layer 20062 and a hard mask oxide (HM_oxide) layer 20064 of the gate cap layer 2006 are deposited, and then CMP is performed on the nitride layer 20062 and the hard mask oxide layer 20064 so that the top of the HM_oxide layer 20064 aligns with the pad nitride layer 206. Also, FIG. 20(b) is a top view corresponding to FIG. 20(a), FIG. 20(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 20(b), and FIG. 20(c) is a cross-sectional view along the cutting line in the Y direction shown in FIG. 20(b). Since the processes after forming the source / drain regions are the same as the processes described in FIGS. 14, 15, 16, and 17, the illustration is omitted.

[0118] In summary, a 3D transistor structure with a precise fin body width and a robust base is disclosed. Even when the dimensions are reduced by scaling, the fin body can be robust and not easily bent. Furthermore, in the new 3D FET structure, since the source / drain regions are well restricted during formation, the fin pitch can be reduced, thus approaching a state where it can meet the requirements from Moore's law of reducing the area of semiconductor transistors, increasing the number of transistors per unit area, and lowering the cost per transistor. Since the doped source and drain are surrounded by tungsten layers on at least three sides, the contact resistance between the source / drain region and the metal plug is also reduced. Additionally, the vertical profile (Z-direction) of the fin structure has a stepped transition, and the fin body region is rectangular. The width of the fin body in the channel region or gate region is well controlled by the aforementioned thinning oxidation of the fin. Thus, in the channel region, there is a narrow body width (the fin body as the channel, e.g., 6 nm) and the other wider body width reserved for the source / drain region (the fin body as S / D, e.g., 9 nm). Therefore, the horizontal profile (X-direction) of the fin body of the present invention also has a stepped transition.

[0119] Compared with the conventional FinFET structure, the proposed FinFET structure according to the present invention has the following advantages.

[0120] (1) An internal stress deep spacer is formed or filled in the groove, and the width of the internal stress deep spacer is restricted by the width of the groove.

[0121] (2) In the conventional FinFET structure, it was difficult to control the shape and dimensions of the fin body. However, in the gate structure according to the present invention, the dimensions and shape of the fin body are well controlled. The width of the fin body in the gate structure is well controlled by a horizontal etching process (for example, the width of the fin body can be easily controlled within 3 to 6 nm while the technology node exceeds 10 nm). Furthermore, the depth of the fin body in the gate structure is also easily controlled by the first dig etching described in FIG. 4(c). Therefore, the fin body of the present invention in the gate structure can be rectangular in the Y-direction profile, and in the X-direction profile, there are rounded corners between the thinned fin body and the source / drain regions.

[0122] (3) The fin structure in the conventional FinFET structure is easily crushed, especially when the technology node drops to 10 nm or less. Nevertheless, in the present invention, the fin body and the fin base are formed or defined by separate etching steps. Therefore, even if the fin body in the gate region is thinned, the remaining fin bodies extending horizontally at the two ends of the active region are still protected by the oxide spacer-1, nitride spacer-1, and STI region and hardly collapse. Furthermore, the fin base under the fin body is completely surrounded by the STI region, and the fin base is a robust base.

[0123] (4) It is difficult to control the crystal structure of the conventional FinFET and the dimensions of the source / drain regions (regardless of whether they are by ion implantation or selective growth). On the other hand, in the present invention, the n-type LDD and the n + doped source and drain regions only grow selectively based on the <110> crystal structure. Furthermore, since the upper part of the STI region is higher than the OSS, the selectively grown n-type LDD and the n + doped source and drain regions are restricted by the high STI region without growing on the STI region.

[0124] (5) In the present invention, since the width of the source / drain region is wider than the width of the fin body in the gate region, the resistance of the source / drain region can be controlled within an allowable range, and the wide width of the source / drain region is also useful for metal contact.

[0125] (6) There is no extra gate-D / S capacitance formed between the gate region and the drain / source region. By an appropriate design in which the edge of the n-type LDD region is formed in the gate region, concerns about either underlap or overlap between the gate and the drain / source region are reduced.

[0126] The present invention has been illustrated and described with reference to embodiments, but it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent configurations included within the spirit and scope of the appended claims.

Claims

1. A semiconductor transistor, comprising: a semiconductor substrate having an original surface; an active region formed based on the semiconductor substrate, the active region having a fin structure; a shallow trench isolation region surrounding the active region; a gate structure of the semiconductor transistor straddling the fin structure; a first conductive region and a second conductive region of the semiconductor transistor located on two opposing side surfaces of the gate structure, wherein a bottom of the gate structure above the shallow trench isolation region is lower than bottoms of the first conductive region and the second conductive region; a spacer in contact with a sidewall of the gate structure and on the fin structure, wherein a bottom of the spacer outside the active region is lower than an upper surface of the fin structure; a width of the fin structure under the spacer is wider than a width of the fin structure under the gate structure, the fin structure has a horizontal profile along a direction parallel to the original surface, and the horizontal profile of the fin structure includes a rounded corner under the spacer.

2. The semiconductor transistor according to claim 1, wherein the first conductive region is limited by the shallow trench isolation region, and a width of the first conductive region is wider than a width of the fin structure under the gate structure.

3. The semiconductor transistor according to claim 1, wherein the fin structure includes a fin body and a fin base, the fin structure has a vertical profile along a direction perpendicular to the original surface, and the vertical profile includes a stepped transition or a non-stepped transition between the fin body and the fin base.

4. The semiconductor transistor according to claim 3, wherein the horizontal profile of the fin structure further includes another stepped transition or a non-stepped transition between the fin structure under the gate structure and the rounded corner.

5. The semiconductor transistor according to claim 1, wherein the first conductive region contacts a first end of the fin structure, the second conductive region contacts a second end of the fin structure, and the first conductive region and the second conductive region are independent of the fin structure.

6. The semiconductor transistor according to claim 1, wherein an upper surface of the shallow trench isolation region adjacent to the first conductive region and / or the second conductive region is higher than an upper surface of the first conductive region and / or the second conductive region.

7. The semiconductor transistor according to claim 1, wherein at least two side surfaces of the first conductive region or the second conductive region are in contact with a metal-containing region.

8. A semiconductor transistor, comprising: a semiconductor substrate having an original surface; an active region formed based on the semiconductor substrate, the active region having a fin structure; a shallow trench isolation region surrounding the active region; a gate structure of the semiconductor transistor that straddles the fin structure and covers a first portion of the shallow trench isolation region; a first conductive region and a second conductive region of the semiconductor transistor located within the active region; a groove along a longitudinal direction of the gate structure, wherein a bottom of the groove outside the active region is lower than an upper surface of the fin structure; an internal spacer buried in contact with a sidewall of the gate structure, the width of the internal spacer being limited by the groove; and the fin structure includes a fin body and a fin base, the fin body is covered by the gate structure, and the internal spacer covers at least a sidewall of the fin body.

9. The semiconductor transistor according to claim 8, wherein the internal spacer further covers a portion of a sidewall of the fin base.

10. The semiconductor transistor according to claim 8, wherein the internal spacer is a composite spacer including an oxide sub-spacer and a SiCOH sub-spacer surrounding sidewalls and an upper surface of the oxide sub-spacer.

11. The semiconductor transistor according to claim 8, wherein at least two side surfaces of the first conductive region or the second conductive region are in contact with a metal-containing region.

12. The semiconductor transistor according to claim 8, wherein an upper surface of the first portion of the shallow trench isolation region covered by the gate structure is lower than an upper surface of another portion of the shallow trench isolation region not covered by the gate structure.

13. The fin structure has a vertical profile along a direction perpendicular to the original surface, and the vertical profile of the fin structure is provided with a first stepped transition portion or a non-stepped transition portion. The semiconductor transistor according to claim 8.

14. The semiconductor transistor according to claim 13, wherein the first stepped transition portion or the non-stepped transition portion is between the fin body and the fin base.

15. The fin structure has a horizontal profile along a direction parallel to the original surface, and the horizontal profile of the fin structure is provided with a second stepped transition portion or a non-stepped transition portion. The semiconductor transistor according to claim 13.

16. The semiconductor transistor according to claim 15, wherein the second stepped transition portion or the non-stepped transition portion is between the gate structure and the first conductive region.

17. The semiconductor transistor according to claim 16, wherein the horizontal profile of the fin structure further includes a third stepped transition portion or a non-stepped transition portion between the gate structure and the second conductive region.

18. The semiconductor transistor according to claim 8, wherein the first conductive region and / or the second conductive region is restricted by the shallow trench isolation region.

19. The semiconductor transistor according to claim 8, wherein the bottom of the gate structure above the first portion of the shallow trench isolation region is lower than the bottom of the first conductive region and / or the second conductive region.

20. The first conductive region and the second conductive region are independent of the fin structure, not on the shallow trench isolation region, and the upper surface of the shallow trench isolation region adjacent to the first conductive region and / or the second conductive region is higher than the upper surface of the first conductive region and / or the second conductive region. The semiconductor transistor according to claim 8.

21. A semiconductor transistor, comprising: A semiconductor substrate having an original surface; An active region formed based on the semiconductor substrate, the active region having a fin structure; A shallow trench isolation region surrounding the active region; A gate structure of the semiconductor transistor that straddles the fin structure and covers a first portion of the shallow trench isolation region. The first and second conductive regions of the semiconductor transistor located within the active region, wherein the upper surface of the shallow trench isolation region is higher than the upper surface of the fin structure, the first and second conductive regions An internal spacer that contacts the sidewall of the gate structure, wherein the bottom of the internal spacer outside the active region is lower than the upper surface of the fin structure, and the internal spacer The fin structure includes a fin body and a fin base, the fin body is covered by the gate structure, and the internal spacer covers at least the sidewall of the fin body The fin structure has a vertical profile along a direction perpendicular to the original surface, and the vertical profile of the fin structure provides a first stepped transition portion or a non-stepped transition portion, a semiconductor transistor

22. The semiconductor transistor according to claim 21, wherein the internal spacer further covers a portion of the sidewall of the fin base

23. The semiconductor transistor according to claim 21, wherein the internal spacer is a composite spacer including an oxide sub-spacer and a SiCOH sub-spacer surrounding the sidewall and upper surface of the oxide sub-spacer

24. The semiconductor transistor according to claim 21, wherein at least two side surfaces of the first conductive region or the second conductive region are in contact with a metal-containing region

25. The upper surface of the first portion of the shallow trench isolation region covered by the gate structure is lower than the upper surface of the other portion of the shallow trench isolation region not covered by the gate structure, the semiconductor transistor according to claim 21

26. The semiconductor transistor according to claim 21, wherein the first stepped transition portion or the non-stepped transition portion is between the fin body and the fin base

27. The fin structure has a horizontal profile along a direction along the original surface, and the horizontal profile of the fin structure provides a second stepped transition portion or a non-stepped transition portion, the semiconductor transistor according to claim 21

28. The semiconductor transistor according to claim 21, wherein the first conductive region and / or the second conductive region is restricted by the shallow trench isolation region

29. The semiconductor transistor according to claim 21, wherein a bottom portion of the gate structure above the first portion of the shallow trench isolation region is lower than a bottom portion of the first conductive region and / or the second conductive region.

30. The semiconductor transistor according to claim 21, wherein the first conductive region and the second conductive region are independent of the fin structure, are not on the shallow trench isolation region, and an upper surface of the shallow trench isolation region adjacent to the first conductive region and / or the second conductive region is higher than an upper surface of the first conductive region and / or the second conductive region.

31. A method of manufacturing a semiconductor transistor, comprising: forming a fin structure on an active region of a semiconductor substrate based on the semiconductor substrate, the fin structure including a fin body and a fin base; forming a dummy gate structure spanning the fin structure; forming a gate spacer adjacent to the dummy gate structure on the fin structure, wherein a bottom of the gate spacer outside the active region is lower than an upper surface of the fin structure; removing the dummy gate structure to expose a gate trench; etching the fin body in the gate trench to control a width of the fin body, wherein the fin structure has a horizontal profile along a direction parallel to an original surface, and the horizontal profile of the fin structure includes a rounded corner under the gate spacer; forming a true gate structure spanning the fin structure, wherein a width of the fin body outside the gate spacer that is spanned by the true gate structure is narrower than a width of the fin body under the gate spacer.

32. The step of forming the fin structure includes: defining the fin structure by a pad cover layer; etching the semiconductor substrate using a first etching process based on the pad cover layer to form the fin body; forming a side spacer layer to cover sidewalls of the fin body; The manufacturing method according to claim 31, further comprising etching the semiconductor substrate using a second etching process based on the pad cover layer and the side spacer layer to form the fin base portion.

33. The step of forming the dummy gate structure includes forming a STI region so as to surround the fin structure, wherein an upper surface of the STI region is higher than the original surface of the semiconductor substrate; defining a gate region in order to form the dummy gate structure by a patterned photoresist; etching downward a portion of the STI region and a portion of the pad cover layer within the gate region. The manufacturing method according to claim 32.

34. The step of forming the gate spacer adjacent to the dummy gate structure on the fin structure includes forming a polysilicon spacer covering sidewalls of the gate region; forming a TiN layer and a tungsten material to fill the remaining portion of the gate region to form a dummy gate structure; removing the polysilicon spacer to form a groove within the gate region; etching downward the STI region within the groove; forming the gate spacer to fill the groove; removing the dummy gate structure to expose the gate trench within the gate region. The manufacturing method according to claim 33.

35. The step of etching the fin body within the gate trench to control the width of the fin body includes etching downward the STI region within the gate trench; removing the side spacer layer within the gate trench to expose sidewalls of the fin body; horizontally etching the fin body such that the width of the fin body that straddles the true gate structure and is outside the gate spacer is narrower than the width of the fin body under the gate spacer. The manufacturing method according to claim 34.

36. removing the pad cover layer within the gate trench to expose an upper surface of the fin body; forming a gate dielectric spacer of the true gate structure on both the upper surface and the sidewalls of the fin body. Further including forming a gate conductive layer of the true gate structure in the gate trench so as to cover the upper surface and the side walls of the fin body and the side walls of the fin base in the gate trench. The manufacturing method according to claim 35, wherein the true gate structure includes a gate dielectric spacer covering the fin body, the fin base, and the STI region and the gate conductive layer in the gate trench.

37. Removing the pad cover layer outside the true gate structure to expose a first portion of the original surface of the semiconductor substrate. Etching the semiconductor substrate based on the first portion of the original surface to form a first trench. The manufacturing method according to claim 36, further including forming a first conductive structure of the semiconductor transistor based on the first trench.

38. The step of forming the first conductive structure includes: Forming a coating oxide layer based on the surface of the first trench. Etching a portion of the coating oxide layer to form an exposed side wall of the semiconductor substrate. Forming a doped semiconductor structure based on the exposed side wall of the semiconductor substrate, wherein the doped semiconductor structure is limited by the STI region. The manufacturing method according to claim 37, including filling the first trench and forming a metal structure in contact with the doped semiconductor structure.

39. The manufacturing method according to claim 38, wherein the doped semiconductor structure includes a low-concentration doped semiconductor region and a high-concentration doped semiconductor region.

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