Printed Wiring Board and Method of Manufacturing the Same

Abstract

To provide a printed wiring board with less load.SOLUTION: A printed wiring board has: an insulating substrate having a through hole from a first surface to a second surface; a cylindrical through hole conductor formed on the inner surface of the through hole, a filler filling the majority of a space surrounded by the through hole conductor; a first land covering the first surface and the filler around the through hole; a second land covering the second surface and the filler around the through hole; a first resin insulating layer having a first via hole exposing the first land; a second resin insulating layer having a second via hole exposing the second land; a first uppermost conductor layer; a second uppermost conductor layer; a first via hole conductor; and a second via hole conductor. The filler includes a first recess recessed from the first surface, and a second recess recessed from the second surface, a second distance between the second surface and the bottom of the second recess is larger than a first distance between the first surface and the bottom of the first recess, the first recess is filled with the first land, and the second recess is filled with the second land.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed by this specification relates to a printed wiring board and a method for manufacturing a printed wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a multilayer printed wiring board. A plated-through hole is formed in a substrate. A resin paste for forming a filling layer is filled in the internal space of the plated-through hole. More resin paste than the volume of the internal space is filled so that the internal space of the plated-through hole is completely filled with the resin paste. The resin paste filled in the internal space is semi-cured. The surplus resin paste protruding from the plated-through hole is removed by polishing. The filling layer is formed by completely curing the resin paste. Since the resin paste shrinks during curing, the formed filling layer has a recess near the opening surface of the plated-through hole. Then, a connection land for closing the recess is formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] [Problems of Patent Document 1] In the technology of Patent Document 1, in order to form a filling layer, an excessive amount of resin paste is filled in the internal space of the plated-through hole, and the surplus resin paste is removed after semi-curing. It is considered that the man-hours required to form the filling layer and the amount of resin paste used are large, and the manufacturing load is high.

Means for Solving the Problems

[0005] The printed wiring board of the present invention includes an insulating substrate having a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; a cylindrical through hole conductor formed on the inner surface of the through hole; a filler filling most of the space surrounded by the through hole conductor; a first land connected to the through hole conductor and covering the first surface around the through hole and the filler; a second land connected to the through hole conductor and covering the second surface around the through hole and the filler; a first resin insulating layer formed on the first surface and the first land and having a first via hole exposing the first land; a second resin insulating layer formed on the second surface and the second land and having a second via hole exposing the second land; a first top conductor layer formed on the first resin insulating layer; a second top conductor layer formed on the second resin insulating layer; a first via hole conductor formed on the inner surface of the first via hole and connected to the first top conductor layer; and a second via hole conductor formed on the inner surface of the second via hole and connected to the second top conductor layer. The filler includes a first recess recessed from the first surface and a second recess recessed from the second surface. A second distance between the second surface and the bottom of the second recess is greater than a first distance between the first surface and the bottom of the first recess. The first land fills the first recess, and the second land fills the second recess.

[0006] In the printed wiring board of the embodiment, the filler has a first recess and a second recess. A second distance between the second surface and the bottom of the second recess is greater than a first distance between the first surface and the bottom of the first recess. Since the filler has the above characteristics, when the printed wiring board of the embodiment is formed, the amount of resin paste used for forming the filler is less than that in the conventional case. Since the process of removing the surplus resin paste can be omitted, the man-hours required for forming the filler are also less than those in the conventional case. The manufacturing load is less than that in the conventional case.

[0007] The method for manufacturing a printed wiring board according to the present invention includes preparing a copper-clad laminate including an insulating substrate having a first surface and a second surface opposite to the first surface, a first copper foil laminated on the first surface of the insulating substrate, and a second copper foil laminated on the second surface; forming a through hole penetrating the copper-clad laminate in the copper-clad laminate; forming a cylindrical through-hole conductor on the inner surface of the through hole; filling a resin paste into the space surrounded by the through-hole conductor from the first surface side so that the exposed surface of the first copper foil and the surface of the resin paste facing the exposed surface of the first copper foil are located on substantially the same plane and the surface of the resin paste facing the exposed surface of the second copper foil is recessed from the exposed surface of the second copper foil, thereby forming the resin paste in the space; curing the resin paste to form a filler having a first recess recessed from the first surface and a second recess recessed from the second surface from the resin paste; forming a first land connected to the through-hole conductor and covering the first surface around the through hole and the filler; and forming a second land connected to the through-hole conductor and covering the second surface around the through hole and the filler. A second distance between the second surface and the bottom of the second recess is larger than a first distance between the first surface and the bottom of the first recess, the first land fills the first recess, and the second land fills the second recess.

[0008] According to the method for manufacturing a printed wiring board of the embodiment, when filling the resin paste into the space, the resin paste is not filled in the entire area of the space. The amount of the resin paste used for forming the filler is less than that in the prior art. Further, since the step of removing the excess resin paste protruding from the space can be omitted, the man-hours required for forming the filler are also less than those in the prior art. The manufacturing load of the printed wiring board is less than that in the prior art.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 2I

Figure 2J

Figure 2K

Figure 3

Mode for Carrying Out the Invention

[0010] [Embodiment] FIG. 1 is a cross-sectional view showing a part of a printed wiring board 2 according to an embodiment. As shown in FIG. 1, the printed wiring board 2 includes an insulating substrate 10, a first conductor layer 30F, a second conductor layer 30B, a first resin insulating layer 40F, a second resin insulating layer 40B, a first top conductor layer 50F, and a second top conductor layer 50B.

[0011] The insulating substrate 10 is a core substrate. The insulating substrate 10 is formed using a thermosetting resin having insulating properties. The insulating substrate 10 may contain inorganic particles such as silica. The insulating substrate 10 may contain a reinforcing material such as glass cloth. The insulating substrate 10 may be formed using a photocurable resin having insulating properties.

[0012] The insulating substrate 10 has a first surface 10F (the upper surface in FIG. 1) and a second surface 10B on the side opposite to the first surface 10F. The insulating substrate 10 has a through-hole 12, a through-hole conductor 16, and a filler 20. The through-hole 12 extends from the first surface 10F to the second surface 10B. In the example of FIG. 1, two through-holes 12 are shown. In a modified example, the number of through-holes 12 is not limited to two. The through-hole conductor 16 is formed on the inner surface of the through-hole 12. The through-hole conductor 16 is cylindrical. The through-hole conductor 16 covers the inner surface of the through-hole 12.

[0013] The filler 20 fills most of the space surrounded by the through-hole conductor 16. The filler 20 is formed using a thermosetting resin having insulating properties. The filler 20 may contain inorganic particles such as silica. The filler 20 may contain a reinforcing material such as glass cloth. The filler 20 has a first recess 22F and a second recess 22B. The first recess 22F is a recess formed on the first surface 10F side of the filler 20. The first recess 22F is recessed from the first surface 10F. The second recess 22B is a recess formed on the second surface 10B side of the filler 20. The second recess 22B is recessed from the second surface 10B. A second distance D2 between the second surface 10B and the bottom of the second recess 22B is larger than a first distance D1 between the first surface 10F and the bottom of the first recess 22F.

[0014] The first conductor layer 30F is formed on the first surface 10F. The first conductor layer 30F is formed of copper. The first conductor layer 30F includes two first lands 36F and three signal wirings 38F. The signal wiring 38F is formed by a seed layer 32F and an electrolytic plating film 34F on the seed layer 32F. The first land 36F is formed by an electrolytic plating film 26F in the first recess 22F, a seed layer 32F on the electrolytic plating film 26F, and an electrolytic plating film 34F on the seed layer 32F. The first land 36F is connected to the through-hole conductor 16. The first land 36F covers the first surface 10F and the filler 20 around the through-hole 12. The first land 36F fills the first recess 22F. The upper surface of the first land 36F is flat.

[0015] The second conductor layer 30B is formed on the second surface 10B. The second conductor layer 30B is formed of copper. The second conductor layer 30B includes two second lands 36B and three signal wirings 38B. The signal wirings 38B are formed of a seed layer 32B and an electrolytic plating film 34B on the seed layer 32B. The second land 36B is formed of the electrolytic plating film 26B in the second recess 22B, the seed layer 32B on the electrolytic plating film 26B, and the electrolytic plating film 34B on the seed layer 32B. The second land 36B is connected to the through-hole conductor 16. The second land 36B covers the second surface 10B and the filler 20 around the through-hole 12. The second land 36B fills the second recess 22B. The upper surface of the second land 36B is flat.

[0016] The first resin insulating layer 40F is formed on the first surface 10F and the first conductor layer 30F. The first resin insulating layer 40F is formed with a first via hole 44F that exposes the first land 36F. The first resin insulating layer 40F is formed using a thermosetting resin having insulating properties. The first resin insulating layer 40F may contain inorganic particles such as silica. The first resin insulating layer 40F may contain a reinforcing material such as glass cloth. The first resin insulating layer 40F may be formed using a photocurable resin having insulating properties.

[0017] The first top conductor layer 50F is formed on the first resin insulating layer 40F. The first top conductor layer 50F is formed of copper. The first top conductor layer 50F includes two first pads 56F and three signal wirings 58F. The first pads 56F and the signal wirings 58F are formed of a seed layer 52F and an electrolytic plating film 54F on the seed layer 52F.

[0018] A first via hole conductor 42F is formed on the inner surface of the first via hole 44F. The first via hole conductor 42F is formed of copper. The first via hole conductor 42F is connected to the first top conductor layer 50F. The first via hole conductor 42F is connected to the first land 36F. The first via hole conductor 42F is formed of a seed layer 52F and an electrolytic plating film 54F on the seed layer 52F.

[0019] The second resin insulating layer 40B is formed on the second surface 10B and the second conductor layer 30B. The second resin insulating layer 40B is formed with a second via hole 44B that exposes the second land 36B. The second resin insulating layer 40B is formed using a thermosetting resin having insulating properties. The second resin insulating layer 40B may contain inorganic particles such as silica. The second resin insulating layer 40B may contain a reinforcing material such as glass cloth. The second resin insulating layer 40B may be formed using a photocurable resin having insulating properties.

[0020] The second top conductor layer 50B is formed on the second resin insulating layer 40B. The second top conductor layer 50B is formed of copper. The second top conductor layer 50B includes two second pads 56B and three signal wirings 58B. The second pads 56B and the signal wirings 58B are formed by a seed layer 52B and an electrolytic plating film 54B on the seed layer 52B.

[0021] A second via hole conductor 42B is formed on the inner surface of the second via hole 44B. The second via hole conductor 42B is formed of copper. The second via hole conductor 42B is connected to the second top conductor layer 50B. The second via hole conductor 42B is connected to the second land 36B. The second via hole conductor 42B is formed by a seed layer 52B and an electrolytic plating film 54B on the seed layer 52B.

[0022] [Method for manufacturing the printed wiring board 2 of the embodiment] Figs. 2A to 2K show a method for manufacturing the printed wiring board 2 of the embodiment. Figs. 2a to 2k are cross-sectional views. Fig. 2a shows a copper-clad laminate 11. The copper-clad laminate 11 has an insulating substrate 10, a first copper foil 14F laminated on the first surface 10F, and a second copper foil 14B laminated on the second surface 10B. The copper-clad laminate 11 is formed with a through hole 12 extending from the first surface 10F to the second surface 10B.

[0023] As shown in FIG. 2B, a cylindrical through-hole conductor 16 is formed on the inner surface of the through-hole 12. The through-hole conductor 16 is formed by electroless plating. The first copper foil 14F and the second copper foil 14B may be thickened by electroless plating.

[0024] As shown in FIG. 2C, the resin paste 24 is filled from the first surface 10F side into the space surrounded by the through-hole conductor 16. The resin paste 24 does not fill the entire space. The exposed surface of the first copper foil 14F and the surface of the resin paste 24 facing the exposed surface of the first copper foil 14F are located in substantially the same plane. On the other hand, the surface of the resin paste 24 facing the exposed surface of the second copper foil 14B is recessed from the exposed surface of the second copper foil 14B. The resin paste 24 is formed of a thermosetting resin having insulating properties. The resin paste 24 is not cured at this point.

[0025] The resin paste 24 is thermally cured. Thereby, as shown in FIG. 2D, the filler 20 is formed from the resin paste 24. The filler 20 fills most of the space surrounded by the through-hole conductor 16. The filler 20 has a first recess 22F and a second recess 22B. The first recess 22F is a recess formed on the first surface 10F side of the filler 20 and is recessed from the first surface 10F. The second recess 22B is a recess formed on the second surface 10B side of the filler 20 and is recessed from the second surface 10B. The second distance D2 between the second surface 10B and the bottom of the second recess 22B is larger than the first distance D1 between the first surface 10F and the bottom of the first recess 22F.

[0026] As shown in FIG. 2E, an electrolytic plating film 26F is formed on the first copper foil 14F. An electrolytic plating film 26B is formed on the second copper foil 14B. The electrolytic plating film 26F fills the inside of the first recess 22F. The electrolytic plating film 26B fills the inside of the second recess 22B.

[0027] The electrolytic plating film 26F and the first copper foil 14F are thinned. In the embodiment, the upper surface of the electrolytic plating film 26F and the upper surface of the first copper foil 14F are polished, whereby the electrolytic plating film 26F and the first copper foil 14F are thinned. In the embodiment, as shown in FIG. 2F, the electrolytic plating film 26F and the first copper foil 14F are removed leaving the electrolytic plating film 26F that fills the first recess 22F. As a result, the first surface 10F is exposed. The upper surface of the first surface 10F and the electrolytic plating film 26F that fills the first recess 22F are located in substantially the same plane. Similarly, the electrolytic plating film 26B and the second copper foil 14B are thinned. As shown in FIG. 2F, the electrolytic plating film 26B and the second copper foil 14B are removed leaving the electrolytic plating film 26B that is filled in the second recess 22B. As a result, the second surface 10B is exposed. The upper surface of the second surface 10B and the electrolytic plating film 26B that fills the second recess 22B are located in substantially the same plane.

[0028] As shown in FIG. 2G, a seed layer 32F is formed on the electrolytic plating film 26F that fills the first surface 10F and the first recess 22F. A seed layer 32B is formed on the electrolytic plating film 26B that fills the second surface 10B and the second recess 22B. The seed layers 32F and 32B are formed by electroless plating.

[0029] As shown in FIG. 2H, a plating resist 100F is formed on the seed layer 32F. The plating resist 100F has an opening 102F that exposes the seed layer 32F. Similarly, a plating resist 100B is formed on the seed layer 32B. The plating resist 100B has an opening 102B that exposes the seed layer 32B.

[0030] As shown in FIG. 2I, an electrolytic plating film 34F is formed on the seed layer 32F exposed from the plating resist 100F. The electrolytic plating film 34F fills the opening 102F. Similarly, an electrolytic plating film 34B is formed on the seed layer 32B exposed from the plating resist 100B. The electrolytic plating film 34B fills the opening 102B.

[0031] The plating resists 100F and 100B are removed. Thereafter, the seed layers 32F and 32B exposed from the electrolytic plating films 34F and 34B are removed. As shown in FIG. 2J, a first land 36F is formed by the electrolytic plating film 26F filling the first recess 22F, the seed layer 32F, and the electrolytic plating film 34F. The upper surface of the first land 36F is flat. A signal wiring 38F is formed by the seed layer 32F and the electrolytic plating film 34F. A first conductor layer 30F including the first land 36F and the signal wiring 38F is formed. A second land 36B is formed by the electrolytic plating film 26B filling the second recess 22B, the seed layer 32B, and the electrolytic plating film 34B. The upper surface of the second land 36B is flat. A signal wiring 38B is formed by the seed layer 32B and the electrolytic plating film 34B. A second conductor layer 30B including the second land 36B and the signal wiring 38B is formed.

[0032] As shown in FIG. 2K, a first resin insulating layer 40F is formed on the first surface 10F and the first conductor layer 30F. A second resin insulating layer 40B is formed on the second surface 10B and the second conductor layer 30B.

[0033] Thereafter, a first via hole 44F exposing the first land 36F is formed in the first resin insulating layer 40F (see FIG. 1). A second via hole 44B exposing the second land 36B is formed in the second resin insulating layer 40B (see FIG. 1). Thereafter, by the semi-additive method, a first top conductor layer 50F is formed on the first resin insulating layer 40F, and a first via hole conductor 42F connected to the first top conductor layer 50F is formed on the inner surface of the first via hole 44F. Similarly, a second top conductor layer 50B is formed on the second resin insulating layer 40B, and a second via hole conductor 42B connected to the second top conductor layer 50B is formed on the inner surface of the second via hole 44B. The printed wiring board 2 (FIG. 1) of the embodiment is obtained.

[0034] According to the manufacturing method of the embodiment, when the resin paste 24 is filled from the first surface 10F side into the space surrounded by the through-hole conductor 16, the resin paste 24 is not filled over the entire area of the space (FIG. 2C). The filler 20 formed from the resin paste 24 has a first recess 22F and a second recess 22B (FIG. 2D). A second distance D2 between the second surface 10B and the bottom of the second recess 22B is larger than a first distance D1 between the first surface 10F and the bottom of the first recess 22F. According to the manufacturing method of the embodiment, the amount of the resin paste 24 used for forming the filler 20 is less than that in the prior art. Also, the step of removing the excess resin paste 24 protruding from the space can be omitted. Therefore, the man-hours required for forming the filler 20 are also less than those in the prior art. According to the manufacturing method of the embodiment, the manufacturing load of the printed wiring board 2 is less than that in the prior art.

[0035] In the embodiment, the upper surfaces of the first land 36F and the second land 36B are flat. Resin remaining on the upper surfaces of the first land 36F and the second land 36B is suppressed. The first land 36F and the first via-hole conductor 42F are surely connected. The second land 36B and the second via-hole conductor 42B are surely connected. A printed wiring board 2 with stable performance is obtained.

[0036] [Another example of the embodiment] In another example of the embodiment, after the resin paste 24 is thermally cured to form the filler 20 (see FIG. 2D), the upper surface of the first copper foil 14F is further polished. Thereby, excess resin adhering to the first copper foil 14F around the through-hole 12 is removed. Resin remaining in the first land 36F formed later is suppressed. A printed wiring board 2 with stable performance is obtained.

[0037] [First modification example of the embodiment] In the first modification example, the configuration of the obtained printed wiring board 2 is the same as that of the embodiment. In the first modification example, a part of the manufacturing method of the printed wiring board 2 is different from that of the embodiment. In the first modification example, the first conductor layer 30F and the second conductor layer 30B are formed by the M-SAP method. Also in the first embodiment, as shown in FIG. 2E, an electrolytic plating film 26F is formed on the first copper foil 14F, and an electrolytic plating film 26B is formed on the second copper foil 14B. The electrolytic plating film 26F fills the first recess 22F. The electrolytic plating film 26B fills the second recess 22B.

[0038] Subsequently, the electrolytic plating film 26F and the first copper foil 14F are thinned. In the first modification example, the upper surface of the electrolytic plating film 26F and the upper surface of the first copper foil 14F are polished so that the electrolytic plating film 26F and the first copper foil 14F are thinned. At this time, as shown in FIG. 3, the upper surface of the electrolytic plating film 26F and the upper surface of the first copper foil 14F are polished so that a part of the first copper foil 14F remains. The first surface 10F is not exposed. The thinned first copper foil 14F remains on the first surface 10F. Similarly, the electrolytic plating film 26B and the second copper foil 14B are thinned. As shown in FIG. 3, the upper surface of the electrolytic plating film 26B and the upper surface of the second copper foil 14B are polished so that a part of the second copper foil 14B remains. The second surface 10B is not exposed. The thinned second copper foil 14B remains on the second surface 10B.

[0039] In the first modification example, since the first copper foil 14F remains on the first surface 10F and the second copper foil 14B remains on the second surface 10B, the formation of the seed layers (32F, 32B in FIG. 2G) is omitted. In the first modification example, a plating resist 100F (see FIG. 2H) is formed on the first copper foil 14F remaining on the first surface 10F, and a plating resist 100B (see FIG. 2H) is formed on the second copper foil 14B remaining on the second surface 10B.

[0040] Thereafter, an electrolytic plating film 34F is formed on the first copper foil 14F exposed from the plating resist 100F (see FIG. 2I). An electrolytic plating film 34B is formed on the second copper foil 14B exposed from the plating resist 100B. The plating resists 100F and 100B are removed. Thereafter, the first copper foil 14F and the second copper foil 14B exposed from the electrolytic plating films 34F and 34B are removed (see FIG. 2J). A first conductor layer 30F is formed including an electrolytic plating film 26F filling the first recess 22F, a first land 36F formed by the first copper foil 14F and the electrolytic plating film 34F, and a signal wiring 38F formed by the first copper foil 14F and the electrolytic plating film 34F. A second conductor layer 30B is formed including an electrolytic plating film 26B filling the second recess 22B, a second land 36B formed by the second copper foil 14B and the electrolytic plating film 34B, and a signal wiring 38B formed by the second copper foil 14B and the electrolytic plating film 34B.

[0041] According to the manufacturing method of the first modification example, the first conductor layer 30F and the second conductor layer 30B are formed by the M-SAP method. The first copper foil 14F remaining on the first surface 10F and the second copper foil 14B remaining on the second surface 10B serve the same role as the seed layers (32F and 32B in FIG. 2G). In the first modification example, since the M-SAP method is used, the first conductor layer 30F and the second conductor layer 30B including fine wirings can be formed. A high-performance printed wiring board 2 can be obtained.

Description of Reference Numerals

[0042] 2: Printed Wiring Board 10: Insulating Substrate 10F: First Surface 10B: Second Surface 12: Through-Hole 14F: First Copper Foil 14B: Second Copper Foil 16: Through-Hole Conductor 20: Filling Material 22F: First Recess 22B: Second Recess 36F: First Land 36B: Second Land 40F: First Resin Insulation Layer 40B: Second Resin Insulation Layer 42F: First via hole conductor 42B: Second via hole conductor 44F: First via hole 44B: Second via hole 50F: First top conductor layer 50B: Second top conductor layer

Claims

1. An insulating substrate having a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; A cylindrical through-hole conductor formed on the inner surface of the through hole; A filler filling most of the space surrounded by the through-hole conductor; A first land connected to the through-hole conductor and covering the first surface around the through hole and the filler; A second land connected to the through-hole conductor and covering the second surface around the through hole and the filler; A first resin insulating layer formed on the first surface and the first land and having a first via hole exposing the first land; A second resin insulating layer formed on the second surface and the second land and having a second via hole exposing the second land; A first top conductor layer formed on the first resin insulating layer; A second top conductor layer formed on the second resin insulating layer; A first via hole conductor formed on the inner surface of the first via hole and connected to the first top conductor layer; A second via hole conductor formed on the inner surface of the second via hole and connected to the second top conductor layer, wherein the filler includes a first recess recessed from the first surface and a second recess recessed from the second surface, a second distance between the second surface and the bottom of the second recess is larger than a first distance between the first surface and the bottom of the first recess, the first land fills the first recess, and the second land fills the second recess.

2. The printed wiring board according to claim 1, wherein an upper surface of the first land is flat and an upper surface of the second land is flat.

3. Preparing a copper-clad laminate including an insulating substrate having a first surface and a second surface opposite to the first surface, a first copper foil laminated on the first surface of the insulating substrate, and a second copper foil laminated on the second surface; Forming a through hole penetrating the copper-clad laminate in the copper-clad laminate; Forming a cylindrical through-hole conductor on the inner surface of the through hole; Filling a resin paste into the space surrounded by the through-hole conductor from the first surface side so that a surface of the resin paste facing the exposed surface of the first copper foil and the exposed surface of the first copper foil are located in substantially the same plane and a surface of the resin paste facing the exposed surface of the second copper foil is recessed from the exposed surface of the second copper foil, thereby forming the resin paste in the space. By curing the resin paste, a filler having a first recess recessed from the first surface and a second recess recessed from the second surface is formed from the resin paste. Forming a first land that is connected to the through-hole conductor and covers the first surface around the through-hole and the filler. A method of manufacturing a printed wiring board, including forming a second land that is connected to the through-hole conductor and covers the second surface around the through-hole and the filler, wherein a second distance between the second surface and the bottom of the second recess is greater than a first distance between the first surface and the bottom of the first recess, the first land fills the first recess, and the second land fills the second recess.

4. The method of manufacturing a printed wiring board according to claim 3, further including removing excess resin paste adhering to the first surface around the through-hole by polishing the upper surface of the first surface after curing the resin paste.

5. The method of manufacturing a printed wiring board according to claim 3, wherein an upper surface of the first land is flat and an upper surface of the second land is flat.

6. The method of manufacturing a printed wiring board according to claim 3, further including forming a first resin insulating layer on the first surface and the first land after forming the first land; forming a first via hole exposing the first land in the first resin insulating layer; forming a first top conductor layer on the first resin insulating layer; forming a first via hole conductor connected to the first top conductor layer on an inner surface of the first via hole; forming a second resin insulating layer on the second surface and the second land after forming the second land; forming a second via hole exposing the second land in the second resin insulating layer; forming a second top conductor layer on the second resin insulating layer; and forming a second via hole conductor connected to the second top conductor layer on an inner surface of the second via hole.

Images