Capacitance network and method for improving high-voltage operation of high electron mobility transistors

Abstract

To provide a method and HEMT semiconductor device for improving high voltage operation of a high electron mobility transistor.SOLUTION: In a capacitance network (HEMT), an integrated and / or external capacitance network comprises a fixed number of capacitively coupled field plates to distribute an electric field in a drift region. The capacitively coupled field plates are advantageously fabricated on the same metal layer to lower the cost; and the capacitance network is provided to control field plate potentials. The potentials on each field plate are pre-determined through the capacitance network, resulting in a uniform and / or substantially uniform electric field distribution along the drift region.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of U.S. Provisional Patent Application No. 62 / 873,307, filed Jul. 12, 2019, which is hereby incorporated by reference in its entirety.

[0002] The present invention relates to a capacitance network for improving the high - voltage operation of a high electron mobility transistor (HEMT), and more specifically, to a lateral gallium nitride (GaN) HEMT including a field plate coupled through a capacitance network.

Background Art

[0003] Gallium nitride (GaN) and other wide - bandgap group - III nitride - based direct - bandgap semiconductor materials exhibit a high breakdown electric field and are useful for high current density. In this regard, GaN - based semiconductor devices are actively being studied as alternatives to silicon - based semiconductor devices in power and high - frequency applications. For example, a GaN HEMT can provide a lower on - resistance with a higher breakdown voltage compared to a silicon power field - effect transistor of the same area.

[0004] A field - effect transistor (FET) can be either enhancement - mode or depletion - mode. An enhancement - mode device can represent a transistor (e.g., a field - effect transistor) that blocks current (i.e., is off) when no gate bias is applied (i.e., when the gate - to - source bias is zero). In contrast, a depletion - mode device can represent a transistor that conducts current (i.e., is on) when the gate - to - source bias is zero.

Summary of the Invention

[0005] Non-limiting and non-exhaustive embodiments of a capacitance network for improving the high-voltage operation of a high electron mobility transistor (HEMT) are described with reference to the following figures, and like reference numerals in different figures indicate like parts unless otherwise specified.

Brief Description of the Drawings

[0006]

Figure 1A

Figure 1B

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Figure 4A

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Figure 10A

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Throughout the several views of the drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are drawn to be concise and clear, and are not necessarily drawn to scale. For example, the dimensions of some of the elements and layers in the figures may be exaggerated relative to other elements to make the various embodiments of the teachings herein more readily understandable. Additionally, common but well-understood elements, layers, and / or process steps that are useful or necessary in a commercially suitable embodiment are often not depicted so as not to obscure the figures of these various embodiments of the capacitance network for improving the high voltage operation of a high electron mobility transistor.

[0008] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the capacitance network for improving the high voltage operation of a high electron mobility transistor. However, it will be apparent to those skilled in the art that specific details are not necessarily used to practice the teachings herein. In other instances, well-known materials or methods are not described in detail so as not to obscure the present disclosure.

[0009] References herein to "one embodiment," "an embodiment," "one example," or "an example" mean that a particular feature, structure, method, process, and / or characteristic described in connection with the embodiment or example is included in at least one embodiment of the capacitance network for improving the high voltage operation of a high electron mobility transistor. Accordingly, the use of the phrases "in one embodiment," "in an embodiment," "one example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Further, the particular features, structures, methods, steps, and / or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Additionally, it is understood that the figures provided with this specification are for the purpose of explanation to those skilled in the art and are not necessarily drawn to scale.

[0010] In the context of the present application, when a transistor is in an "off state" or "off", the transistor blocks current and / or substantially does not conduct current. Conversely, when a transistor is in an "on state" or "on", the transistor can conduct current substantially. By way of example, in one embodiment, a high-voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) that supports a high voltage between a drain, which is a first terminal, and a source, which is a second terminal. In some embodiments, an integrated control device circuit can be used to drive a power switch when adjusting the energy provided to a load. Further, for the purposes of the present disclosure, "ground" or "ground potential" represents a reference voltage or reference potential with respect to which all other voltages or potentials in an electronic circuit or integrated circuit (IC) are defined or measured.

[0011] As described above, a HEMT and / or a GaN HEMT can provide a lower on-resistivity with a higher breakdown voltage compared to a silicon power field-effect transistor of the same area. However, it has been found that the breakdown voltage of a HEMT and / or a GaN HEMT can be limited by a non-uniform electric field in the drift region. Therefore, it may be desirable to find a method of distributing the electric field in the drift region so that it is uniform and / or substantially uniform.

[0012] Conventional approaches for distributing an electric field include using a field plate. However, conventional field plate designs for high-voltage HEMTs (e.g., lateral high-voltage HEMTs) can be limited to providing a quadratic electric field distribution along the drift region. Further, conventional field plate designs may require a thick dielectric to support a high breakdown voltage. This can, in turn, increase process cost and complexity. Thus, it may also be desirable to find a method for distributing an electric field without increasing process cost and complexity.

[0013] A capacitance network (HEMT) for improving the high-voltage operation of a high electron mobility transistor is presented herein. The integrated and / or external capacitance network can comprise a fixed number of capacitively coupled field plates for distributing an electric field in the drift region. The capacitively coupled field plates can be beneficially fabricated in the same metal layer to reduce cost, and the capacitance network can be provided to control the field plate potential. The potential at each field plate can be predefined through the capacitance network, resulting in a uniform and / or substantially uniform electric field distribution along the drift region.

[0014] Figure 1A shows a simplified schematic diagram 100a of a device cross-section including a capacitance network 140 according to an embodiment. The simplified schematic diagram 100a shows a semiconductor layer 102 that may include aluminum gallium nitride (AlGaN), gallium nitride (GaN), and / or a combination of both AlGaN and GaN. The simplified schematic diagram 100a further shows interconnects to a source, a gate, and a drain. In one embodiment, the interconnect layer may be identified as ohmic contacts 104-105, a source field plate (SFP) 106, a drain field plate (DFP) 107, vias 108-109, a first metal layer 110 (i.e., to the source), a first metal layer 111 (i.e., to the drain), vias 112-113, a second metal layer 114 (i.e., to the source), and a second metal 115 (i.e., to the drain). Further, the gate interconnect may include a gate field plate 120, a via 122, and a first metal layer 124 (i.e., to the gate).

[0015] The drift region may be present along and / or near the surface (i.e., the upper part) of the semiconductor layer 102 between the gate (GATE) and the drain (DRAIN). Field plates 131-134 may be fabricated using the first metal layer along the drift region such that the field plates 131-134 are positioned above the drift region of the semiconductor layer 102. To reduce process steps and / or cost, the field plates 131-134 may be beneficially formed in the same metal layer (i.e., metal 1) as the first metal layers 110-111, 124.

[0016] The capacitance network 140 can be electrically connected to the field plates 131 - 134, to the ground (GND), and / or in one or more layers (e.g., in via 113) to the drain. The embodiment of FIG. 1A shows four field plates 131 - 134, but there can be more or fewer than four field plates 131 - 134. For example, only one field plate 131 may exist.

[0017] The capacitance network 140 can be an external network and / or an internal (i.e., integrated) network provided to adjust the field plate potential (i.e., the field plate voltage). By adjusting the field plate potential to a known (i.e., selected) value, the electric field within the drift region of the semiconductor layer 102 can be adjusted (i.e., distributed) in a controlled manner. By this method, the electric field can be distributed substantially uniformly.

[0018] FIG. 1B shows a schematic view 100b of a device cross-section including the capacitance network 140 according to an embodiment. The schematic view 100b shows parasitic field plate capacitances C1 - C4 and C11 - C15. The parasitic field plate capacitances C1 - C4 and C11 - C15 can provide a coupling such that the field plates 131 - 134 are capacitively coupled. The capacitance network 140 can provide capacitors C21 - C24 adjusted to control and / or select the field plate potential (i.e., the field plate voltage). The capacitors C21 - C24 can be at least partially determined by simulation and / or by experiment to select the field plate potential.

[0019] FIG. 1C shows a schematic diagram 100c of a device cross-section including a capacitance network 140 according to an embodiment. The capacitance network 140 includes additional impedances R1 - R6 electrically coupled between ground (GND) and the drain (i.e., to via 113). The impedances R1 - R6 can be resistors, passive elements, and / or non-linear components (e.g., active field effect transistors) tuned to connect to field plates 131 - 134. In some embodiments, the impedances R1 - R6 can beneficially provide discharge characteristics that allow the charge on field plates 131 - 134 to be removed and / or controlled.

[0020] FIG. 2A shows a schematic diagram 200a of a device including a capacitance network 206 according to an embodiment. The schematic diagram 200a includes a transistor 202 including a gate G, a source S, and a drain D, and as schematically shown, the field plate 204 can be electrically coupled between the gate G and the drain D. The schematic diagram 200a further shows additional information related to the system voltage. For example, the capacitance network 206 can be coupled to ground (GND) and to the field plate 204 to provide field plate potentials VFP1 - VFP4. Additionally, a drain-to-source voltage VDS can be applied to the drain D. Further, a gate-to-source voltage VGS can be applied to the gate G, and the source S can be connected to ground (GND).

[0021] FIG. 2B shows a schematic diagram 200b of a device including a capacitance network 206 according to an embodiment. The field plate 204 includes field plates 231-234 coupled to parasitic capacitances C30-C34. The capacitance network includes capacitors C35-C38 connected to field plates 231-234 respectively. The values of capacitors C35-C38 can be selected to control (i.e., select) the field plate potentials VFP1-VFP4, and by selecting the field plate potentials VFP1-VFP4, the electric field along the drift region of transistor 202 can be controlled. The drift region of transistor 202 can be between gate G and drain D, and there may be more or less than four field plates 231-234. Accordingly, there may be more or less than four further capacitors C35-C38.

[0022] FIG. 2C shows a schematic diagram 200c of a device including a capacitance network 206 according to an embodiment. The schematic diagram 200c shows an embodiment including a discharge network 207. The discharge network 207 can also be coupled to the field plate 204.

[0023] FIG. 2D shows a schematic diagram of a device 200d including a capacitance network 206 according to an embodiment. As shown, the discharge network 207 can include impedances Z1-Z5 electrically coupled between drain D and gate G. The impedances are further electrically coupled to the field plates 231-234 to provide discharge characteristics. In some embodiments, the impedances Z1-Z5 may be implemented by active devices (e.g., field effect transistors). In other embodiments, the impedances Z1-Z5 may be implemented by resistors and / or passive components.

[0024] Figure 3A shows a device cross-section 300a including an equipotential diagram according to an embodiment. The device cross-section 300a can be that of a HEMT device including a source (S) 302, a gate (G) 304, and a drain (D) 306. The device cross-section 300a further shows field plates 312-314 located between the gate 304 and the drain 306 along the "X" axis. The equipotential diagram can be derived from a simulation of the device cross-section 300a.

[0025] Figure 3B shows a device cross-section 300b including an equipotential diagram according to an embodiment. The equipotential diagram is shown by lines and can be further derived using a device simulator.

[0026] Figure 3C shows a device cross-section 300c including an equipotential diagram according to an embodiment. The device cross-section 300c shows further details related to the device material and the drift region. For example, the device cross-section 300c shows a high-voltage region 320 corresponding to where the field plates 312-314 are formed above the drift region (i.e., the high-voltage region). The field plates 312-314 can be further labeled as field plates f1-f3.

[0027] The device cross-section 300c further represents a GaN buffer layer 352 and an aluminum oxide (Al2O3) layer 354. In the device cross-section 300c, the simulated values of the electrostatic potential (V) can be shown according to a color-coded key (e.g., having values ranging from 1.0560 volts to 1,202.9 volts).

[0028] Figure 3C can correspond to an equipotential diagram by simulation for a 1200V device including three capacitively coupled field plates 312-314 (f1-f3). By assigning an adjustable external capacitance to each field plate as a means of emulating an electrostatic capacitance network, the device of Figure 3C can be shown to support 1200V with a uniform 2DEG field in a wider HV region (see, for example, Figure 4C).

[0029] FIG. 4A shows plots 402, 404 of potential and electric field as a function of distance along the drift region according to an embodiment. The embodiment may correspond to simulation results of device cross-sections 300a-c. Further, plot 402 may correspond to potential and plot 404 may correspond to electric field. As shown, between about 17 micrometers and 35 micrometers, plot 404 is substantially uniform so as to improve plot 402 as a function of distance. By this technique, the maximum value of the potential (i.e., plot 402) reaches about 1200 volts (V).

[0030] FIG. 4B shows plots 402, 404 of potential and electric field as a function of distance along the drift region according to an embodiment. FIG. 4B further shows the position of high voltage region 420 corresponding to high voltage region 320. As shown in plot 404, the electric field is substantially uniform within high voltage region 420 (e.g., within the drift region).

[0031] FIG. 4C shows plots 402, 404 of potential and electric field as a function of distance along the drift region according to an embodiment. FIG. 4C may be similar to FIG. 4B except that it includes additional labels indicating the positions of field plates 312-314 (f1-f3). For example, plot 404 corresponding to potential shows plateaus 431-433 corresponding to the positions of field plates 312-314 (f1-f3).

[0032] As described above, the device may support 1200 volts with a uniform 2DEG electric field in a wider high voltage (HV) region 420. A uniform electric field in the two-dimensional electron gas (2DEG) region may beneficially provide a stable dynamic on-resistance (Rdson) in GaN devices.

[0033] FIG. 5 shows plots corresponding to field plate potentials 502 - 504 as a function of drain voltage according to an embodiment. The embodiment may further correspond to simulation results of device cross-sections 300a - c. The field plate potentials 502 - 504 are provided as a function of drain voltage Vdrain, and may show how the coupling ratio of each field plate 312 - 314 (e.g., field plates f1 - f3) can be calculated by the ratio of the field plate potential to the drain voltage.

[0034] FIG. 6 shows an upper layout diagram 600 of a device according to an embodiment. The upper layout diagram 600 shows an active region 610 including stripes oriented parallel to the YP direction. As can be understood by those skilled in the art, a transistor and / or semiconductor device can be manufactured to include an active region in which current, voltage, and / or power can be actively controlled, and further, an interconnect layer including a pad layer adjacent to the active region may exist. In this regard, the upper layout diagram 600 further shows where the interconnects (e.g., metallization and / or pad layer) can be located to connect to the drain D and source S. For example, pads 601 - 603 can be drain pads 601 - 603 that enable connection (i.e., electrical connection) to the drain stripe and / or segment within the active region 610, and pad 608 can be a source pad 608 that enables connection (i.e., electrical connection) to the source stripe and / or segment within the active region 610. Further, pad 607 can be a gate pad 607 that enables connection (i.e., electrical connection) to the gate region within the active region 610.

[0035] In one embodiment, a capacitance network (e.g., capacitance network 140 and / or capacitance network 206) can be located outside the active region 610. For example, as shown in FIG. 6, the capacitance network 606 can be located outside the active region 610 near the drain pad 602. Further, a field plate (e.g., field plates 131-134, field plate 204, and / or field plates 312-314) can be located inside the active region 610. For example, field plates, such as field plates 312-314, can be located parallel to the direction YP and within (i.e., inside) the active region 610. FIG. 6 shows the capacitance network 606 located near the drain pad 602, but other arrangements are possible. For example, the capacitance network 606 can be located near or within the source pad 608. Alternatively, the device can use a layout that includes multiple capacitance networks and / or integrated capacitance networks as described below in connection with FIGS. 10A and 11A.

[0036] FIG. 7 shows a conceptual flowchart 700 for distributing an electric field in a drift region (e.g., high voltage regions 320 and / or 420) according to an embodiment. Step 702 can correspond to forming at least one field plate (e.g., any one of field plates 131-134, 231-234, 312-314, and / or f1-f3) above the drift region. Step 704 can correspond to coupling a capacitance network (e.g., capacitance network 140, 206) to at least one field plate to establish (realize) a selected potential (e.g., any one of field plate potentials VFP1-VFP4) at the at least one field plate. Step 706 can correspond to providing the selected potential such that the electric field (e.g., see plot 404 of the electric field) is substantially uniform (e.g., see plot 404 within the high voltage region 420).

[0037] FIG. 8 shows a conventional field plate design for a high voltage lateral gallium nitride device, and FIG. 9 shows a cross-section and electrical schematic of a lateral gallium nitride device according to the teachings herein. FIG. 9 may further show parasitic capacitances, resistor electrostatic discharge network elements, and capacitance networks for establishing coupling ratios. The capacitance network may be realized by a metal-insulator-metal (MIM) structure, which may be inherently included in the GaN process. The MIM structure may be realized through vertical metal plates and / or adjacent metal comb plates.

[0038] FIG. 10A shows an upper layout diagram 1000 of a device according to an embodiment. Similar to the upper layout diagram 600, the upper layout diagram 1000 shows an active region 1020 including stripes oriented parallel to the direction YP. Further, the upper layout diagram 1000 further shows locations where interconnects (e.g., metallizations and / or pad layers) may be positioned to connect to the drain D and source S. For example, pads 1004-1006 may be drain pads 1004-1006 that enable connection (i.e., electrical connection) to drain stripes and / or segments within the active region 1020, and pad 1024 may be a source pad 1024 that enables connection (i.e., electrical connection) to source stripes and / or segments within the active region 1020. Further, pad 1023 may be a gate pad 1023 that enables connection (i.e., electrical connection) to the gate region within the active region 1020.

[0039] In an embodiment of the upper layout diagram 1000, the capacitance network (e.g., capacitance network 140 and / or capacitance network 206) may include capacitors 1021 and 1022 located outside the active region 1020. Field plates, such as field plates 312-314, may be positioned parallel to the direction YP and within (i.e., inside) the active region 1020.

[0040] For example, FIG. 10B shows an upper layout diagram of the stripe region 1025 according to the embodiment of FIG. 10A, showing a field plate pattern 1050 and a field plate pattern 1051. The field plate pattern 1050 can be electrically coupled to the capacitor 1021 (or capacitor 1022), and the field plate pattern 1051 can be electrically coupled to the capacitor 1022 (or capacitor 1021). In one embodiment, the capacitors 1021 and 1022 can have a capacitance value in the range of 1 picofarad to 10 picofarads (pF). For example, the capacitor 1021 can have a value of 5.4 pF, and the capacitor 1022 can have a value of 7.6 pF.

[0041] FIG. 11A shows an upper layout diagram 1100 of a device according to an embodiment. Similar to the upper layout diagrams 600 and 1000, the upper layout diagram 1100 shows an active region 1120 including stripes oriented parallel to the direction YP. However, different from the embodiments shown in the upper layout diagrams 600 and 1000, the device of the upper layout diagram 1100 realizes a capacitor network (such as a capacitance network 140 and / or a capacitance network 206) using embedded capacitors distributed within the active region 1120.

[0042] For example, FIG. 11B shows an upper layout diagram, and FIG. 11C shows a cross-sectional view of the stripe region 1125 according to the embodiment of FIG. 11A. FIG. 11B shows that the field plate pattern 1134 is electrically coupled to the embedded capacitor pattern 1136 by the interconnect link 1135.

[0043] The cut line 1137 shown between point A (source S) and point B (drain D) in the upper layout diagram may correspond to the cross-sectional view of FIG. 11C. Point A may be aligned with (and electrically coupled to) the source interconnect 1140, and point B may be aligned with (and electrically coupled to) the drain interconnect 1142. The embedded capacitor pattern 1136 may be electrically coupled to the embedded capacitor 1146, and the field plate pattern 1134 may be electrically coupled to the field plate 1144.

[0044] The problems solved by the capacitance network (HEMT) for improving the high-voltage operation of high electron mobility transistors may include enabling the high-voltage operation of lateral gallium nitride (GaN) devices without increasing the complexity and cost of the process.

[0045] An ideal (i.e., conventional) field plate design for a lateral HV device may involve an approximately quadratic electric field distribution along the drift region. This can be achieved by increasing the height of the field plate while increasing the thickness of the dielectric as the breakdown voltage increases (see, for example, FIG. 8), but this increases the process cost and complexity. The teachings herein may be applicable to lateral GaN devices including multiple capacitively coupled field plates, and the field plates may preferably be constructed in the same metal layer to reduce cost, in which case the potential at each field plate may be predefined through the capacitance network, resulting in a uniform electric field distribution along the drift region at the maximum operating voltage.

[0046] Furthermore, the function of the capacitance network may be to establish the desired potential at each of the capacitively coupled field plates by a predefined capacitance combined with parasitic capacitance to provide the correct (e.g., ideal or substantially ideal) coupling ratio.

[0047] The foregoing description of the illustrated examples of the disclosure, including the matters set forth in the abstract, is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Specific embodiments of the capacitance network for improving the high-voltage operation of a high electron mobility transistor are described herein for purposes of illustration, but various equivalent modifications can be made without departing from the broader spirit and scope of the disclosure. Indeed, it is understood that specific exemplary device cross-sections are presented for purposes of explanation and that other embodiments can be used in accordance with the teachings herein.

[0048] The invention is defined in the claims, but it must be understood that the invention could alternatively be defined by the following examples.

[0049] Example 1. A high electron mobility transistor (HEMT) comprising a drift region, at least one field plate located above the drift region, the drift region being configured to support an electric field, at least one field plate, and a capacitance network electrically coupled to the at least one field plate, the capacitance network being configured to distribute the electric field.

[0050] Example 2. The HEMT according to Example 1, wherein the HEMT is a lateral gallium nitride (GaN) semiconductor device.

[0051] Example 3. The HEMT according to any one of the foregoing examples, wherein the capacitance network is configured to uniformly distribute the electric field.

[0052] Example 4. The HEMT according to any one of the foregoing examples, wherein the capacitance network is configured to establish a selected potential at at least one field plate.

[0053] Example 5. The HEMT according to any one of the foregoing examples, wherein the selected potential is selected to uniformly distribute the electric field.

[0054] Example 6. The HEMT according to any one of the foregoing examples, wherein the capacitance network includes at least one impedance configured to discharge at least one field plate.

[0055] Example 7. A semiconductor device comprising: a drift region formed laterally between a gate and a drain, the drift region being configured to support an electric field; a plurality of field plates located above the drift region, the plurality of field plates including a first field plate configured to support a first potential and a second field plate configured to support a second potential; and a capacitance network electrically coupled to the plurality of field plates, the capacitance network being configured to establish the first potential and the second potential to distribute the electric field.

[0056] Example 8. The semiconductor device according to Example 7, wherein the capacitance network is configured to establish a first potential and a second potential.

[0057] Example 9. The semiconductor device according to any one of Examples 7 to 8, wherein the capacitance network includes a first capacitor electrically coupled to the first field plate and a second capacitor electrically coupled to the second field plate.

[0058] Example 10. The semiconductor device according to any one of Examples 7 to 9, wherein the capacitance network is an external capacitance network.

[0059] Example 11. The semiconductor device according to any one of Examples 7 to 10, wherein the capacitance network includes an embedded capacitor.

[0060] Example 12. The semiconductor device according to any one of Examples 7 to 11, wherein the first capacitor is configured to establish a first potential and the second capacitor is configured to establish a second potential.

[0061] Example 13. The semiconductor device according to any one of Examples 7 to 12, wherein the first capacitor is electrically coupled between a direct current (DC) potential and a first field plate, and the second capacitor is electrically coupled between the DC potential and a second field plate.

[0062] Example 14. The semiconductor device according to any one of Examples 7 to 13, further comprising a first impedance electrically coupled between a DC potential and a first field plate, and a second impedance electrically coupled between a drain and a second field plate.

[0063] Example 15. The semiconductor device according to any one of Examples 7 to 14, wherein the DC potential is ground.

[0064] Example 16. The semiconductor device according to any one of Examples 7 to 15, comprising a third field plate configured to support a third potential, a third capacitor electrically coupled between a DC potential and the third field plate, a third impedance electrically coupled between the first field plate and the third field plate, and a fourth impedance electrically coupled between the third field plate and the second field plate.

[0065] Example 17. The semiconductor device according to any one of Examples 7 to 16, wherein the capacitance network is configured to establish a first potential, a second potential, and a third potential to distribute an electric field.

[0066] Example 18. The semiconductor device according to any one of Examples 7 to 17, wherein the electric field is substantially uniform.

[0067] Example 19. A semiconductor device according to any one of Examples 7 to 18, wherein the electric field withstands a voltage of at least 1200 volts.

[0068] Example 20. A method of distributing an electric field in a drift region of a high-voltage semiconductor device, comprising forming at least one field plate above the drift region, coupling a capacitance network to the at least one field plate to establish a selected potential in the at least one field plate, and providing the selected potential such that the electric field is substantially uniform.

[0069] Example 21. The method according to Example 20, wherein coupling the capacitance network to the at least one field plate includes coupling a first capacitor to the at least one field plate.

[0070] Example 22. The method according to any one of Examples 20 to 21, wherein coupling the capacitance network to the at least one field plate includes coupling a static discharge impedance to the at least one field plate.

[0071] Example 23. The method according to any one of Examples 20 to 22, wherein forming at least one field plate above the drift region includes forming at least one field plate inside the active region.

[0072] Example 24. The method according to any one of Examples 20 to 23, wherein coupling the capacitance network to the at least one field plate includes forming the capacitance network outside the active region.

[0073] (Additional Note 1) A high electron mobility transistor (HEMT) semiconductor device (100), wherein the HEMT semiconductor device comprises a drift region formed horizontally between a gate and a drain, the drift region being configured to support an electric field, said drift region; and a plurality of field plates located above the drift region, the plurality of field plates comprising a first field plate configured to support a first potential and a second field plate configured to support a second potential, said plurality of field plates; and a capacitance network electrically coupled to the plurality of field plates, the capacitance network being configured to establish the first potential in the first field plate and the second potential in the second field plate in order to distribute the electric field supported by the drift region, said capacitance network; and comprising the capacitance network a first capacitor electrically coupled to the first field plate and coupled between the first field plate and a DC potential; a second capacitor electrically coupled to the second field plate and coupled between the second field plate and the DC potential; a first impedance electrically coupled between the DC potential and the first field plate; a second impedance electrically coupled between the drain and the second field plate; comprising the first impedance and the second impedance being field effect transistors HEMT semiconductor device. (Additional Note 2) the capacitance network being an external capacitance network The HEMT semiconductor device according to claim 1. (Additional Note 3) the capacitance network comprising an embedded capacitor (1146) The HEMT semiconductor device according to claim 1. (Additional Note 4) the DC potential being ground The HEMT semiconductor device according to supplementary note item 1. (Supplementary note item 5) The plurality of field plates includes third field plates (132, 133) configured to support a third potential. The capacitance network a third capacitor electrically coupled between the DC potential and the third field plate; a third impedance electrically coupled between the first field plate and the third field plate; a fourth impedance electrically coupled between the third field plate and the second field plate; and includes The HEMT semiconductor device according to supplementary note item 1. (Supplementary note item 6) The capacitance network is configured to establish the first potential, the second potential, and the third potential to distribute the electric field. The HEMT semiconductor device according to supplementary note item 5. (Supplementary note item 7) The electric field is substantially uniform. The HEMT semiconductor device according to supplementary note item 6. (Supplementary note item 8) The electric field withstands a voltage of at least 1200 volts. The HEMT semiconductor device according to supplementary note item 7.

Claims

1. A high electron mobility transistor (HEMT), wherein the HEMT comprises a drift region, a plurality of field plates located above the drift region, a capacitance network comprising a plurality of external or embedded capacitors electrically coupled to respective ones of the plurality of field plates, the capacitance network being configured to distribute an electric field in the drift region when the high electron mobility transistor is in an off state, the capacitance network further comprising an impedance coupled to discharge the field plates, the impedance including an active device, the capacitance network, and a HEMT comprising.

2. The HEMT is a lateral gallium nitride (GaN) semiconductor device, The HEMT according to claim 1.

3. The capacitance network is configured to establish a selected potential at at least one of the field plates, The HEMT according to claim 1.

4. The impedance is a field effect transistor, The HEMT according to any one of claims 1 to 3.

5. The capacitance network a first capacitor electrically coupled between a first field plate of the field plates and a DC potential, a second capacitor electrically coupled between a second field plate of the field plates and a DC potential, comprising, The HEMT according to any one of claims 1 to 4.

6. The first capacitor is electrically coupled between the first field plate and the DC potential, The second capacitor is electrically coupled between the second field plate and the DC potential, The HEMT according to claim 5.

7. A first impedance of the impedance is electrically coupled between the DC potential and the first field plate, A second impedance of the impedance is electrically coupled between a drain and the second field plate, The HEMT according to claim 6.

8. The DC potential is ground, The HEMT according to claim 6 or claim 7.

9. A first impedance of the impedances is electrically coupled between the gate of the HEMT and the first field plate; A second impedance of the impedances is electrically coupled between the drain and the second field plate. The HEMT according to claim 6. **Claim 10** A high electron mobility transistor (HEMT) semiconductor device (100), the HEMT semiconductor device comprising: A drift region formed laterally between a gate and a drain, the drift region configured to support an electric field; A plurality of field plates positioned above the drift region, the plurality of field plates comprising a first field plate configured to support a first potential and a second field plate configured to support a second potential; A capacitance network electrically coupled to the plurality of field plates, the capacitance network configured to establish the first potential at the first field plate and the second potential at the second field plate to distribute the electric field supported by the drift region; Comprising: The capacitance network comprising: A first capacitor electrically coupled to the first field plate, the first capacitor between the first field plate and a DC potential; A second capacitor electrically coupled to the second field plate, the second capacitor between the second field plate and the DC potential; A first impedance electrically coupled between the gate and the first field plate; A second impedance electrically coupled between the drain and the second field plate; Comprising: The first impedance and the second impedance are field effect transistors. HEMT semiconductor device. **Claim 11** The capacitance network is an external capacitance network. The HEMT semiconductor device according to claim 10. **Claim 12** The capacitance network comprises an embedded capacitor. The HEMT semiconductor device according to claim 10.

13. The first capacitor is configured to establish the first potential, The second capacitor is configured to establish the second potential, The semiconductor device according to claim 10.

14. The DC potential is ground, The HEMT semiconductor device according to claim 10.

15. The plurality of field plates includes a third field plate configured to support a third potential, The capacitance network, A third capacitor electrically coupled between the DC potential and the third field plate, A third impedance electrically coupled between the first field plate and the third field plate, A fourth impedance electrically coupled between the third field plate and the second field plate, Comprising, The HEMT semiconductor device according to claim 10.

16. The capacitance network is configured to establish the first potential, the second potential, and the third potential to distribute the electric field, The HEMT semiconductor device according to claim 15.

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