Semiconductor device

Abstract

To provide a semiconductor device in which a gate insulating film of an off-transistor is less likely to be damaged by electrostatic discharge.SOLUTION: Disclosed is a semiconductor device 100 having an off-transistor 10 in which a gate electrode and a source region of a MOS transistor are connected to a first power terminal 100a or a second power terminal 100c, and a drain region 15 is connected to an external signal terminal 100b. In the semiconductor device 100, the gate electrode 13 of the off-transistor 10 comprises: an electrode part 13a formed above a channel region C; and a capacitance generating part 13b which extends so as to generate capacitance together with wiring 18 electrically connected to the drain region 15.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In semiconductor devices, an ESD protection element may be provided to protect internal elements from various surges and noises typified by Electro-Static Discharge (ESD).

[0003] Examples of ESD protection elements include diode elements, bipolar elements, thyristor elements, etc. that are formed independently or parasitically. Among these, a so-called "off transistor" that connects the drain of an N-type Metal-Oxide-Semiconductor (MOS) transistor to an external terminal and grounds the gate and source for use in an off state is well known. This off transistor has a function of preventing an electrostatic surge from propagating to internal elements and discharging the surge to a substrate or the like.

[0004] Regarding such off transistors, various proposals have been made. For example, an off transistor to which an RC timer in which a resistance element and a capacitance element are connected in series is connected has been proposed for the purpose of improving ESD protection characteristics (see, for example, Patent Document 1).

[0005] Also, as models of electrostatic discharge related to the destruction of semiconductor devices, a Human Body Model (HBM) and a Charged Device Model (CDM), which are classified from viewpoints such as the waveform, energy, and time of a surge, are well known.

[0006] The HBM is a model in which a charged human discharges to a semiconductor device, and discharges a relatively large amount of energy to the semiconductor device in several 10 nsec to several 100 nsec. On the one hand, CDM has attracted more attention than HBM in recent years because the automation of manufacturing processes has reduced the operations where humans touch semiconductor devices. This CDM is a model in which charge is discharged by contacting a metal part such as a device or a jig from a terminal of a charged semiconductor device, and although the amount of energy is relatively small, it discharges from the semiconductor device in an extremely short time of several tens of picoseconds to several hundreds of picoseconds.

[0007] Therefore, severe transient phenomena occur in CDM, and in an off-transistor, if a large potential difference occurs between the gate electrode and the drain region, there is a possibility of breakdown.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] Therefore, one aspect of the present invention aims to provide a semiconductor device in which the gate insulating film of an off-transistor is less likely to be electrostatically broken down.

Means for Solving the Problems

[0010] A semiconductor device according to an embodiment of the present invention is in a semiconductor device having an off-transistor in which a gate electrode and a source region of a MOS transistor are connected to a first power supply terminal or a second power supply terminal, and a drain region is connected to an external signal terminal, the gate electrode of the off-transistor includes an electrode portion formed over a channel region, and a capacitance forming portion that extends to form a capacitance with a wiring electrically connected to the drain region.

Effects of the Invention

[0011] According to one aspect of the present invention, it is possible to provide a semiconductor device in which the gate insulating film of an off-transistor is less likely to be electrostatically broken down.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals are given to the same components, and redundant explanations may be omitted. Also, in the drawings, the X direction, the Y direction, and the Z direction are orthogonal to each other. The direction including the X direction and the direction opposite to the X direction (-X direction) is referred to as the "X-axis direction", the direction including the Y direction and the direction opposite to the Y direction (-Y direction) is referred to as the "Y-axis direction", and the direction including the Z direction and the direction opposite to the Z direction (-Z direction) is referred to as the "Z-axis direction" (height direction, thickness direction). In this regard, in the following embodiments, the surface on the Z-direction side of each film may be referred to as the "surface". The drawings are schematic, and the ratios of width, length, and depth are not as shown in the drawings.

[0014] (First Embodiment) FIG. 1 is a circuit diagram showing an off-transistor included in a semiconductor device according to a first embodiment. As shown in FIG. 1, the semiconductor device 100 includes a first power supply terminal 100a at a power supply potential, an external signal terminal 100b to which a control signal for turning the semiconductor device 100 on and off is input, a second power supply terminal 100c at a ground potential, and an off transistor 10. Note that the semiconductor device is not particularly limited and can be appropriately selected according to the purpose. For example, semiconductor devices having functions such as regulators, sensors, memories, and battery controls can be mentioned.

[0015] In this embodiment, the off transistor 10 is an NMOS transistor. The drain terminal D is connected to the external signal terminal 100b, and the gate terminal G and the source terminal S are connected to the second power supply terminal 100c at a ground potential.

[0016] FIG. 2 is a schematic plan view showing an off transistor according to the first embodiment. FIG. 3 is a schematic cross-sectional view taken along line III-III shown in FIG. 2. As shown in FIGS. 2 and 3, the off transistor 10 is formed by structurally combining a well region 11, an isolation oxide film 12, a gate electrode 13, a gate insulating film 14, a drain region 15, a source region 16, an interlayer insulating film 17, a wiring 18, and a protective film 19 on the surface of a silicon semiconductor substrate B.

[0017] The well region 11 is a region in which P-type impurities are implanted into the silicon semiconductor substrate B by an ion implantation method or the like.

[0018] The isolation oxide film 12 is formed around the off transistor 10 in order to electrically isolate the off transistor 10 from other semiconductor elements. In this embodiment, the isolation oxide film 12 is LOCOS (Local Oxidation of Silicon). Note that for element isolation, in this embodiment, the isolation oxide film 12 is LOCOS, but it is not limited to this. For example, it may be shallow trench isolation (STI).

[0019] The gate electrode 13 includes an electrode portion 13a formed over the channel region C for forming an NMOS transistor, and a capacitance forming portion 13b for increasing the gate-drain capacitance to increase the electrostatic breakdown voltage of the off-transistor.

[0020] The electrode portion 13a is formed by forming a polysilicon film over a gate insulating film 14 formed over the well region 11, and implanting N-type impurities into the polysilicon film.

[0021] The capacitance forming portion 13b is formed by forming a polysilicon film over the isolation oxide film 12, implanting N-type impurities into the polysilicon film, and is electrically connected to the electrode portion 13a. This capacitance forming portion 13b is disposed below a wiring 18 electrically connected to the drain region 15, and extends through an interlayer insulating film 17 to form a capacitance with the wiring 18. That is, the capacitance forming portion 13b extends from the electrode portion 13a to increase the gate-drain capacitance and increase the electrostatic breakdown voltage of the off-transistor.

[0022] The drain region 15 and the source region 16 are regions where N-type impurities are implanted at a high concentration by an ion implantation method or the like on the surface of the well region 11. Since the implanted impurities diffuse also directly under the gate electrode 13 by a heat treatment in the manufacturing process, a region where the gate electrode 13 overlaps with the drain region 15 and the source region 16 is formed in a plan view. The overlapping region forms the gate-drain capacitance and the gate-source capacitance, but the area of the overlapping region is small. Therefore, the gate-drain capacitance is the sum of a small capacitance formed between the electrode portion 13a of the gate electrode 13 and the drain region 15 and a large capacitance formed between the capacitance forming portion 13b and the wiring 18. Therefore, the gate-drain capacitance becomes larger than the gate-source capacitance, i.e., the capacitance generated between the gate electrode 13 and the ground potential, and the potential of the gate electrode 13 easily follows the potential of the drain region 15. For this reason, in the off transistor 10, a potential difference hardly occurs between the gate electrode 13 and the drain region 15, and breakdown of the gate insulating film 14 can be suppressed.

[0023] The drain region 15 is electrically connected to the wiring 18 through the contact hole H. The wiring 18 connected to the drain region 15 is connected to the drain terminal D shown in FIG. 1 by wire bonding or the like from the opening P of the protective film 19, and is connected to the external signal terminal 100b through the drain terminal D.

[0024] The source region 16 is connected to the second power supply terminal 100c through the source terminal S shown in FIG. 1 and is at the ground potential. Also, the well region 11 is at the ground potential.

[0025] The interlayer insulating film 17 is formed so as to cover the well region 11, the isolation oxide film 12, the gate electrode 13, the drain region 15, and the source region 16. In this embodiment, the interlayer insulating film 17 is a silicon oxide film doped with phosphorus and boron (sometimes referred to as a "BPSG (Boro-Phospho Silicate Glass) film"). The film thickness of the interlayer insulating film 17 can be, for example, 500 nm or more.

[0026] The wiring 18 is formed on the interlayer insulating film 17 and is connected to the drain region 15 through the contact hole H as described above. This wiring 18 is formed of an aluminum alloy. Examples of the aluminum alloy include Al - Si - Cu, as well as Al - Nd, Al - Cu, and Al - Si.

[0027] The protective film 19 protects the entire semiconductor device including the off transistor 10. In this embodiment, the protective film 19 is a silicon nitride film. In this embodiment, the protective film 19 has a single-layer structure of a silicon nitride film. However, the present invention is not limited to this, and for example, a two-layer structure of a silicon oxide film and a silicon nitride film may be used.

[0028] As described above, in the OFF transistor 10, since the capacitance forming portion 13b is formed in the gate electrode 13, even if a high-speed potential change occurs between the gate and the drain due to electrostatic discharge in CDM, the potential of the gate electrode 13 easily follows the potential of the drain region 15. Therefore, in the OFF transistor 10, a potential difference is less likely to occur between the gate electrode 13 and the drain region 15, and breakdown of the gate insulating film 14 can be suppressed.

[0029] (Second Embodiment) FIG. 4 is a schematic cross-sectional view showing an OFF transistor included in a semiconductor device according to the second embodiment. As shown in FIG. 4, the second embodiment is the same as the first embodiment except that the structure of the wiring 18 in the first embodiment is changed and a capacitance forming layer A electrically connected to the drain region 15 is formed in the vicinity above the capacitance forming portion 13b. Therefore, the same components as those in the first embodiment described with reference to FIGS. 1 to 3 are denoted by the same reference numerals and will not be described again.

[0030] The capacitance forming layer A is formed by forming a polysilicon film on the interlayer insulating film 17 formed on the capacitance forming portion 13b and implanting N-type impurities into the polysilicon film. The capacitance forming layer A is electrically connected to the drain region 15 by wiring (not shown) using the polysilicon film.

[0031] As for the dimensions of the capacitance forming layer A, in terms of increasing the capacitance formed between the capacitance forming portion 13b and the capacitance forming layer A, dimensions equivalent to those of the capacitance forming portion 13b are preferable. The interlayer insulating film 17 between the capacitance forming portion 13b and the capacitance forming layer A is preferably a silicon nitride film having a high dielectric constant in terms of increasing the capacitance formed between the capacitance forming portion 13b and the capacitance forming layer A. The film thickness of the interlayer insulating film 17 between the capacitance forming portion 13b and the capacitance forming layer A is preferably made thin in terms of increasing the capacitance formed between the capacitance forming portion 13b and the capacitance forming layer A, and for example, it is preferably about 10 nm.

[0032] Thus, in the second embodiment, by forming the capacitance forming layer A, which is electrically connected to the drain region 15, in the vicinity of the capacitance forming portion 13b of the gate electrode 13, a capacitance larger than the capacitance formed between the capacitance forming portion 13b and the wiring 18 can be obtained as compared with the first embodiment. As a result, the potential of the gate electrode 13 more easily follows the potential of the drain region 15 than in the first embodiment, so that a potential difference is less likely to occur between the gate electrode 13 and the drain region 15, and breakdown of the gate insulating film 14 can be further suppressed.

[0033] In the second embodiment, the capacitance forming layer A is formed in the interlayer insulating film 17 between the capacitance forming portion 13b and the wiring 28, but the positions of the capacitance forming portion 13b and the capacitance forming layer A may be interchanged as shown in FIG. 5.

[0034] As described above, the semiconductor device according to an embodiment of the present invention has an off-transistor in which the gate and source of the NMOS transistor are grounded, and the off-transistor has a gate electrode including an electrode portion formed over the channel region, a wiring electrically connected to the drain region, and a capacitance forming portion extending so as to form a capacitance. As a result, even if a high-speed potential change occurs between the gate and the drain due to electrostatic discharge in CDM in this off-transistor, the potential of the gate electrode easily follows the potential of the drain region, so that a potential difference is less likely to occur between the gate electrode and the drain region, and breakdown of the gate insulating film can be suppressed.

[0035] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and designs and the like within the scope not departing from the gist of the present invention are also included. For example, in the first and second embodiments, the off-transistor is N-type and the well region is P-type. However, the present invention is not limited to this, and the off-transistor may be P-type and the well region may be N-type. In this case, for the off-transistor, the gate electrode and the source region of the PMOS transistor are connected to the first power supply terminal. In addition, the external signal terminal is defined as the terminal to which an external signal is input. However, the present invention is not limited to this, and any terminal to which static electricity can be applied may be used. For example, it may be a power supply terminal to which a power supply voltage such as the first power supply or the second power supply is input.

Explanation of Reference Numerals

[0036] 10 Off-transistor 11 Well region 12 Isolation oxide film 13 Gate electrode 13a Electrode portion 13b Capacitance forming portion 14 Gate insulating film 15 Drain region 16 Source region 17 Interlayer insulating film 18, 28 Wiring 19 Protective film 100 Semiconductor device 100a First power supply terminal 100b External signal terminal 100c Second power supply terminal A Capacitance forming layer B Silicon semiconductor substrate C Channel region H Contact hole P Opening

Claims

1. In a semiconductor device having an off-transistor in which a gate electrode and a source region of a MOS transistor are connected to a first power supply terminal or a second power supply terminal, and a drain region is connected to an external signal terminal, the off-transistor includes: the gate electrode includes an electrode portion formed over a channel region, a wiring electrically connected to the drain region, and a capacitance forming portion extending to form a capacitance; near a lower portion of the capacitance forming portion of the gate electrode, a capacitance forming layer is provided at a position sandwiching the capacitance forming portion between the wiring, and is electrically connected to the drain region; the semiconductor device, wherein the capacitance forming layer is formed on a surface of an isolation oxide film for electrically isolating the MOS transistor.

2. The semiconductor device according to claim 1, wherein an interlayer insulating film between the capacitance forming portion and the capacitance forming layer is a silicon nitride film.

3. The semiconductor device according to claim 1 or 2, wherein a capacitance formed between the gate electrode and the drain region is larger than a capacitance generated between the gate electrode and a ground potential.

Images