Electronic component, circuit board, and method for manufacturing an electronic component

Abstract

To provide an electronic component in which an amount of protruding solder from a mount surface is suppressed and wetting and climbing of the solder up to a surface on the opposite side of the mount surface is prevented.SOLUTION: A multilayer ceramic capacitor 1A, which is an electronic component, includes: an element assembly 2 in which a dielectric 2A and internal electrode layers 3A and 3B are provided; and external electrodes 6A and 6B including a base layer 7 formed on a plurality of surfaces of the element assembly, connected to internal electrodes, and containing metal, a plating layer 9 formed on the base layer on a mount surface side of the element assembly and on a side surface side where the internal electrodes are connected to the base layer, and a covering layer 8 formed on the base layer on the surface on the opposite side of the mount surface and having lower solder wettability than the plating layer. The covering layer exists up to an edge where an upper surface M3 and a side surface M2 on the opposite side of a mount surface M1 are in contact, and at this edge, an end part of the covering layer is formed to be uneven.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an electronic component, a circuit board, and a method for manufacturing an electronic component.

Background Art

[0002] In order to reduce the mounting area of electronic components as electronic devices are miniaturized, an external electrode may be formed on a base body provided with internal electrodes. At this time, the electronic component is mounted on the circuit board by connecting the external electrode and the circuit board via solder.

[0003] Here, the external electrode may be formed not only on the mounting surface of the base body but also on the side surface and the upper surface of the base body. In this case, the solder may spread from the side surface to the upper surface of the external electrode, which may cause an increase in the height of the circuit board.

[0004] In order to prevent the solder from spreading on the side surface and the upper surface of the terminal electrode, Patent Document 1 discloses a configuration in which the side surface portions of the first and second terminal electrodes, which are portions formed on the side surface of the electronic component, are covered with an oxide film.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the configuration in which the surface of the side surface portion of the terminal electrode is covered with an oxide film, when an excessive amount of solder is supplied, the amount of solder overflowing from the mounting surface in an unexpected direction may increase, which may hinder the high-density mounting of the electronic component. In addition, in a general configuration in which the entire surface of the external electrode is wetted with solder, the solder may spread from the side surface to the upper surface of the external electrode, and the circuit board on which the component is mounted may become higher than the original design. Therefore, an object of the present invention is to provide an electronic component, a circuit board, and a method for manufacturing an electronic component that can prevent solder from wetting up to the surface opposite to the mounting surface while suppressing the amount of solder protruding from the mounting surface.

Means for Solving the Problems

[0007] To solve the above problems, an electronic component according to an aspect of the present invention includes a dielectric and a body provided with internal electrodes, an underlayer formed on a plurality of surfaces of the body and connected to the internal electrodes and containing a metal, a plating layer formed on the underlayer on the mounting surface side of the body and on the side surface side where the internal electrodes are connected to the underlayer, and a coating layer formed on the underlayer on the surface opposite to the mounting surface and having a lower solder wettability than the plating layer. The external electrode includes the coating layer, and the coating layer exists up to the edge where the surface opposite to the mounting surface and the side surface are in contact. At this edge, irregularities are formed at the end of the coating layer.

[0008] Preferably, the height difference of the irregularities is in the range of 0.1 μm to 10 μm. The underlayer extends from the side surface of the body to the front and rear surfaces and the upper and lower surfaces. The mounting surface is provided on the lower surface side of the body, the coating layer is provided on the upper surface side of the body, and the plating layer may be further formed on the underlayer on the front surface side and the rear surface side of the body.

[0009] The coating layer may contain an oxide film of the metal.

[0010] The underlayer contains a co-material mixed with the metal, and the coating layer may include the co-material.

[0011] The co-material contained in the underlayer and the co-material contained in the coating layer may have the same composition.

[0012] The co-material may be an oxide ceramic containing the dielectric.

[0013] The coating layer may be a resist film containing resin.

[0014] The underlying layer contains a glass component, The coating layer may include a glass phase having the same composition as the glass component contained in the underlying layer.

[0015] The metal in the underlying layer may be a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, and Ni.

[0016] The plating layer may include a Ni plating layer and a Sn plating layer formed on the Ni plating layer.

[0017] The coating layer may be arranged in a continuous strip shape along the edges in contact with the side surface and the front and rear surfaces, respectively, on the surface opposite to the mounting surface of the external electrode.

[0018] The underlying layer includes a chamfered surface where the ridge portion of the underlying layer is chamfered, and at least a part of the end portion of the coating layer may be located along the chamfered surface of the underlying layer.

[0019] The angle formed by the tangent line of the chamfered surface at the position where the end portion of the coating layer contacts the side surface of the underlying layer and the surface opposite to the mounting surface of the external electrode may be greater than 45°.

[0020] The element includes a laminate in which a first internal electrode layer and a second internal electrode layer are alternately laminated via the dielectric, the external electrode includes a first external electrode and a second external electrode provided on opposite side surfaces of the laminate, the first internal electrode layer may be connected to the first external electrode, and the second internal electrode layer may be connected to the second external electrode.

[0021] Further, according to the circuit board according to one aspect of the present invention, it is a circuit board on which any of the above electronic components is mounted, and the electronic component is connected to the circuit board via a solder layer attached to the plating layer on the mounting surface side in a state where the solder layer wets the side surface of the external electrode.

[0022] Further, a method for manufacturing an electronic component according to an aspect of the present invention includes a step of forming a body provided with a dielectric and internal electrodes, a step of applying an electrode material containing a metal to the side surface and the periphery of the body, a step of firing the electrode material to form an underlayer containing the metal on the side surface and the periphery of the body, a step of forming a coating layer covering the surface of the underlayer, and a step of removing the coating layer on the mounting surface side and the side surface of the body while leaving the coating layer on the surface opposite to the mounting surface side of the body. A step of forming a plating layer on the underlayer on the mounting surface side and the side surface of the body, the coating layer has a lower solder wettability than the plating layer, and the step of removing the coating layer includes forming irregularities at the end of the coating layer at an edge where the surface opposite to the mounting surface side and the side surface are in contact.

[0023] Preferably, the height difference of the unevenness is in the range of 0.1 μm to 10 μm. The step of forming a coating layer covering the surface of the underlayer may include a step of oxidizing the metal and forming an oxide film of the metal on the surface of the underlayer.

[0024] The electrode material contains a glass component, The step of forming a coating layer covering the surface of the underlayer may include a step of causing a glass phase composed of the glass component to rise to the surface of the underlayer during firing of the electrode material.

[0025] The step of removing the coating layer on the mounting surface side and the side surface of the external electrode may include a step of blast-polishing the coating layer from the mounting surface side of the underlayer.

Advantages of the Invention

[0026] According to the present invention, it is possible to prevent solder from wetting up to the surface opposite to the mounting surface while suppressing the amount of solder protruding from the mounting surface.

Brief Description of the Drawings

[0027]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 4H

Figure 4I

Figure 4J

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 7A

Figure 7B

Figure 7C

Figure 8

Figure 9

Figure 10

Figure 11

Mode for Carrying Out the Invention

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the present invention, and not all combinations of features described in the embodiments are essential to the configuration of the present invention. The configuration of the embodiments can be appropriately modified or changed according to the specifications of the apparatus to which the present invention is applied and various conditions (usage conditions, usage environment, etc.). The technical scope of the present invention is determined by the scope of claims and is not limited by the following individual embodiments. In addition, the drawings used in the following description may differ in actual structure, scale, shape, etc. in order to make each configuration easier to understand.

[0029] (First Embodiment) FIG. 1 is a perspective view showing the configuration of a multilayer ceramic capacitor according to the first embodiment, and FIG. 2 is a cross-sectional view obtained by cutting the multilayer ceramic capacitor of FIG. 1 in the length direction. In FIGS. 1 and 2, the multilayer ceramic capacitor 1A includes a body 2 and external electrodes 6A and 6B. The body 2 includes a laminate 2A, a lower cover layer 5A, and an upper cover layer 5B. The laminate 2A includes internal electrode layers 3A and 3B and a dielectric layer 4.

[0030] The lower cover layer 5A is provided below the laminate 2A, and the upper cover layer 5B is provided above the laminate 2A. The internal electrode layers 3A and 3B are alternately laminated via the dielectric layer 4. At this time, the shapes of the body 2 and the laminate 2A can be substantially rectangular parallelepiped shapes. The body 2 may be chamfered along the ridge lines of the body 2. In the following description, the direction in which the side surfaces of the body 2 face each other may be referred to as the length direction DL, the direction in which the front and rear surfaces of the body 2 face each other may be referred to as the width direction DW, and the direction in which the upper and lower surfaces of the body 2 face each other may be referred to as the lamination direction DS.

[0031] The external electrodes 6A and 6B are located on the side surfaces of the body 2 that face each other in a separated state. Each of the external electrodes 6A and 6B extends from each side surface of the body 2 to the front and rear surfaces and the upper and lower surfaces.

[0032] In the length direction DL, the internal electrode layers 3A and 3B are alternately arranged at different positions within the laminate 2A. At this time, the internal electrode layer 3A can be arranged on one side surface side of the body 2 with respect to the internal electrode layer 3B, and the internal electrode layer 3B can be arranged on the other side surface side of the body 2 with respect to the internal electrode layer 3A. Then, the end of the internal electrode layer 3A is drawn out to the end of the dielectric layer 4 on one side surface side in the length direction DL of the body 2 and connected to the external electrode 6A. The end of the internal electrode layer 3B is drawn out to the end of the dielectric layer 4 on the other side surface side in the length direction DL of the body 2 and connected to the external electrode 6B. On the other hand, in the direction (width direction DW) orthogonal to the direction (length direction DL) in which the side surfaces of the body 2 face each other, the ends of the internal electrode layers 3A and 3B are covered with the dielectric layer 4. In the width direction DW, the positions of the ends of the internal electrode layers 3A and 3B may be aligned.

[0033] Incidentally, the outer dimensions of the multilayer ceramic capacitor 1A may be, for example, length > width > height, or length > width = height. For example, the length can be 1.0 mm, the width can be 0.5 mm, and the height can be 0.15 mm, or the length can be 1.0 mm, the width can be 0.5 mm, and the height can be 0.5 mm. Further, the thicknesses of the internal electrode layers 3A and 3B and the dielectric layer 4 in the stacking direction DS can each be in the range of 0.05 μm to 5 μm, for example, 0.3 μm.

[0034] The materials of the internal electrode layers 3A and 3B can be selected from, for example, metals such as Cu (copper), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), or may be alloys containing these metals.

[0035] The material of the dielectric layer 4 can be mainly composed of, for example, a ceramic material having a perovskite structure. Note that the main component only needs to be contained at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 can be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanium zirconate, and titanium oxide.

[0036] The materials of the lower cover layer 5A and the upper cover layer 5B can be mainly composed of, for example, a ceramic material. At this time, the main component of the ceramic material of the lower cover layer 5A and the upper cover layer 5B may be the same as the main component of the ceramic material of the dielectric layer 4.

[0037] Each of the external electrodes 6A and 6B includes an underlayer 7 formed on the body 2 and a plating layer 9 formed on the underlayer 7. Each of the external electrodes 6A and 6B has a mounting surface M1, a side surface M2, and an upper surface M3. The mounting surface M1 is a surface that faces the circuit board on which the multilayer ceramic capacitor 1A is mounted. The mounting surface M1 is provided on the lower surface side of the body 2. The upper surface M3 is a surface opposite to the mounting surface M1.

[0038] Surfaces other than the mounting surface M1 and the side surface M2 of each of the external electrodes 6A and 6B (the upper surface M3) are covered with a coating layer 8. A plating layer 9 is formed on the base layer 7 on the mounting surface M1 and the side surface M2 sides of each of the external electrodes 6A and 6B. Note that the plating layer 9 can be provided not only on the mounting surface M1 side and the pair of side surface M2 sides of the element body 2 but also on the base layer 7 on the front side and the rear side (M4 side) of the element body 2. The thickness of each of the external electrodes 6A and 6B on the mounting surface M1, the side surface M2 side, and the front and rear surface M4 sides is, for example, 10 to 40 μm.

[0039] The conductive material of the base layer 7 can be mainly composed of, for example, a metal or an alloy containing at least one selected from Cu, Fe (iron), Zn (zinc), Al (aluminum), Ni, Pt, Pd, Ag, Au, and Sn (tin). The base layer 7 may contain a particulate co-material. The co-material can reduce the difference in the coefficient of thermal expansion between the element body 2 and the base layer 7 by being mixed in an island shape in the base layer 7, and can relieve the stress applied to the base layer 7. The co-material is, for example, a ceramic component that is the main component of the dielectric layer 4. The base layer 7 may contain a glass component. The glass component is used for densifying the base layer 7 by being mixed with the base layer 7. This glass component is, for example, an oxide such as Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron).

[0040] On the upper surfaces M3 of the respective external electrodes 6A and 6B, a coating layer 8 is formed on the base layer 7. The coating layer 8 includes an oxide film formed by oxidation of the metal of the base layer 7 and a surface layer in which the co-material of the base layer 7 is exposed on the surface. On the surface of the coating layer 8, the oxide film of the base layer 7 and the co-material of the base layer 7 are mixed. Thus, the material of the coating layer 8 includes the oxide film of the metal used as the conductive material of the base layer 7. Further, the material of the coating layer 8 may include the co-material of the base layer 7. The thickness of the oxide film is, for example, 0.05 to 3 μm. The component of the oxide film is, for example, nickel oxide or copper oxide. The co-material of the base layer 7 is, for example, an oxide ceramic which is the main component of the dielectric layer 4, and its main component is barium titanate. Since the surface of the coating layer 8 has a mixture of the metal oxide film and the co-material, solder is difficult to wet.

[0041] The base layer 7 and the coating layer 8 may contain the metal components included in the element body 2. This metal component is, for example, Mg (Ni, Cr, Sr, Al, Na, Fe may be contained in trace amounts). At this time, the base layer 7 and the coating layer 8 can include, as a compound of the metal used as the conductive material of the base layer 7, the metal contained in the element body 2, and oxygen, for example, a compound containing Mg, Ni, and O.

[0042] The material of the plating layer 9 is mainly composed of a metal such as Cu, Ni, Al, Zn, Sn, or an alloy of two or more of these. The plating layer 9 may be a plating layer of a single metal component or a plurality of plating layers of different metal components. The plating layer 9 can have, for example, a three-layer structure including a Cu plating layer 9A formed on the underlying layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B, as shown in FIG. 2. The Cu plating layer 9A can improve the adhesion of the plating layer 9 to the underlying layer 7. The Ni plating layer 9B can improve the heat resistance of each of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C can improve the wettability of the solder of the plating layer 9. The plating layer 9 is formed on a part of the underlying layer 7 and conducts with the internal electrode layer. Also, the plating layer 9 conducts with the terminals of the circuit board through solder. When the metal component of the underlying layer 7 is Cu, the Cu plating layer 9A may not be formed, and at this time, the plating layer 9 may have a two-layer structure including the Ni plating layer 9B and the Sn plating layer 9C formed on the Ni plating layer 9B.

[0043] As described above, according to the first embodiment described above, the upper surfaces M3 of the external electrodes 6A and 6B are covered with the coating layer 8, and the plating layer 9 is formed on the mounting surfaces M1 and the side surfaces M2 of the external electrodes 6A and 6B. Thereby, while preventing the solder from wetting on the upper surfaces M3 of the external electrodes 6A and 6B, the solder can be made to wet on the side surfaces M2 of the external electrodes 6A and 6B. For this reason, even when an excessive amount of solder is supplied, it is possible to suppress the solder from protruding from the mounting area of the multilayer ceramic capacitor 1A while preventing an increase in the height during mounting of the multilayer ceramic capacitor 1A. For this reason, it is possible to achieve high-density mounting of electronic components mounted on the circuit board while preventing the circuit board on which the electronic components are mounted from becoming higher than the design. Also, the coating layer on the upper surface of the element body 2 can buffer mechanical stress applied from above and prevent cracks, breaks, and chips from occurring in the element body.

[0044] (Second Embodiment) FIG. 3 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to the second embodiment, and FIGS. 4A to 4J are cross-sectional views showing the method for manufacturing a multilayer ceramic capacitor according to the second embodiment. In FIGS. 4C to 4J, a case is shown in which the internal electrode layers 3A and 3B are alternately laminated by two layers through the dielectric layer 4.

[0045] In S1 of FIG. 3, a dispersant and an organic binder and an organic solvent as a molding aid are added to the dielectric material powder, and pulverized and mixed to produce a paste-like slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may contain additives. The additives are, for example, oxides or glasses of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si. The organic binder is, for example, a polyvinyl butyral resin or a polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0046] Next, as shown in S2 of FIG. 3 and FIG. 4A, a slurry containing ceramic powder is applied in a sheet shape on a carrier film and dried to produce a green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. For applying the slurry, a doctor blade method, a die coater method, a gravure coater method, or the like can be used.

[0047] Next, as shown in S3 of FIG. 3 and FIG. 4B, a conductive paste for internal electrodes is applied to the green sheet 24 of the layer that forms the internal electrode layers 3A and 3B in FIG. 1 among the plurality of green sheets so as to form a predetermined pattern, thereby forming the internal electrode pattern 23. At this time, a plurality of internal electrode patterns 23 separated in the longitudinal direction of the green sheet 24 can be formed on one green sheet 24. The conductive paste for internal electrodes contains a metal powder used as the material of the internal electrode layers 3A and 3B. For example, when the metal used as the material of the internal electrode layers 3A and 3B is Ni, the conductive paste for internal electrodes contains Ni powder. Further, the conductive paste for internal electrodes contains a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for internal electrodes may contain, as a co-material, a ceramic material that is the main component of the dielectric layer 4. For the application of the conductive paste for internal electrodes, a screen printing method, an inkjet printing method, a gravure printing method, or the like can be used.

[0048] Next, as shown in S4 of FIG. 3 and FIG. 4C, a laminated block is produced by stacking a plurality of green sheets 24 with internal electrode patterns 23 formed thereon and outer-layer green sheets without internal electrode patterns formed thereon in a predetermined order. At this time, the internal electrode patterns 23A and 23B of the green sheets 24 adjacent in the stacking direction are stacked so as to be alternately shifted in the longitudinal direction of the green sheet 24. Also, a portion where only the internal electrode pattern 23A is stacked in the stacking direction, a portion where the internal electrode patterns 23A and 23B are alternately stacked in the stacking direction, and a portion where only the internal electrode pattern 23B is stacked in the stacking direction are formed.

[0049] Next, as shown in S5 of FIG. 3 and FIG. 4D, the laminated block obtained in the molding step of S4 in FIG. 3 is pressed to crimp the green sheet 24. As a method for pressing the laminated block, for example, a method of sandwiching the laminated block with a resin film and performing hydrostatic pressing can be used.

[0050] Next, as shown in S6 of FIG. 3 and FIG. 4E, the pressed laminated block is cut and separated into individual rectangular parallelepiped-shaped elements. The cutting of the laminated block is performed at the portion where only the internal electrode pattern 23A is stacked in the stacking direction and the portion where only the internal electrode pattern 23B is stacked in the stacking direction. For cutting the laminated block, methods such as blade dicing can be used, for example.

[0051] At this time, as shown in FIG. 4F, internal electrode layers 3A and 3B alternately laminated via the dielectric layer 4 are formed in the individuated element 2. The internal electrode layer 3A is drawn out from the surface of the dielectric layer 4 on one side surface of the element 2, and the internal electrode layer 3B is drawn out from the surface of the dielectric layer 4 on the other side surface of the element 2.

[0052] Next, as shown in S7 of FIG. 3, the binder contained in the element 2 individuated in S6 of FIG. 3 is removed. For removing the binder, for example, the element is heated in an N2 atmosphere at about 350°C.

[0053] Next, as shown in S8 of FIG. 3, conductive paste for the underlayer is applied to both side surfaces of the element 2 from which the binder has been removed in S7 of FIG. 3 and to four surfaces of the peripheral surface of each side surface and dried. The conductive paste for the underlayer contains metal powder or filler used as the conductive material of the underlayer 7. For example, when the metal used as the conductive material of the underlayer 7 is Ni, the conductive paste for the underlayer contains Ni powder or filler. Further, the conductive paste for the underlayer contains, as a co-material, for example, a ceramic component which is the main component of the dielectric layer 4. For example, particles of an oxide ceramic having barium titanate as the main component (D50 particle size: 0.8 μm to 4 μm) are mixed into the conductive paste for the underlayer as a co-material. The conductive paste for the underlayer also contains a binder and a solvent.

[0054] Next, as shown in S9 of FIG. 3 and FIG. 4G, the green body 2 coated with the conductive paste for the base layer in S8 of FIG. 3 is fired to integrate the internal electrode layers 3A and 3B and the dielectric layer 4, and to form the base layer 7 integrated with the green body 2. The firing of the green body 2 is performed, for example, in a firing furnace at 1000 to 1350 ° C. for 10 minutes to 2 hours. When base metals such as Ni or Cu are used for the internal electrode layers 3A and 3B, in order to prevent oxidation of the internal electrode layers 3A and 3B, firing can be performed in a reducing atmosphere in the firing furnace.

[0055] Next, as shown in S10 of FIG. 3 and FIG. 4H, by oxidizing the metal exposed on the surface of the base layer 7, a coating layer 8 including an oxide film of the metal is formed on the surface of the base layer 7. The coating layer 8 may contain a co-material of the base layer 7. For the oxidation of the metal exposed on the surface of the base layer 7, for example, a re-oxidation treatment can be performed at 600 ° C. to 1000 ° C. in an N2 gas atmosphere. In addition, oxygen may be added to the atmosphere gas of the re-oxidation treatment so that an oxide film of the metal exposed on the surface of the base layer 7 is formed to a sufficient thickness.

[0056] Next, as shown in S11 of FIG. 3 and FIG. 4I, as a pre-plating treatment, by blast polishing, the oxide film on the base layer 7 on the mounting surface M1 side, the pair of side surface M2 sides, and the front and rear surface sides is removed, and the metal contained in the base layer 7 is exposed on the mounting surface M1 side, the pair of side surface M2 sides, and the front and rear surface sides. In blast polishing, as shown in FIG. 5A, the green body 2 is placed on the substrate 31 in the blast processing apparatus so that the mounting surface M1 side faces upward and the upper surface M3 side is in contact, and blast media is projected from directly above the green body 2. At this time, the blast media projected from directly above wraps around the pair of side surfaces and the front and rear surface sides of the green body 2 but does not wrap around the upper surface M3 side. Therefore, the oxide film on the base layer 7 can be removed on the mounting surface M1 side, the pair of side surface M2 sides, and the front and rear surface sides while leaving the oxide film on the base layer 7 on the upper surface M3 side.

[0057] Next, as shown in S12 of FIG. 3 and FIG. 4J, a plating layer 9 is formed on the base layer 7 on the mounting surface M1 side and the side surface M2 side. In forming the plating layer 9, for example, Cu plating, Ni plating, and Sn plating can be sequentially performed. At this time, the element 2 with the oxide film removed on the base layer 7 on the mounting surface M1 side and the side surface M2 side is accommodated in a barrel together with the plating solution, and the plating layer 9 can be formed by rotating the barrel and applying electricity. At this time, since there is an oxide film on the base layer 7 on the upper surface M3 side, no plating layer is formed.

[0058] FIG. 5A is a plan view showing an example of the process of FIG. 4I, and FIG. 5B is a cross-sectional view obtained by cutting the process of FIG. 5A in the length direction. In FIGS. 5A and 5B, the element 2 with the oxide film formed on the surface of the base layer 7 is disposed on the substrate 31. At this time, the upper surface M3 side of the element 2 is attached to the substrate 31 via the fixing tape 32 so that the mounting surface M1 side of the element 2 faces upward. Then, the blasting medium 34 is projected from the nozzle 33 installed directly above the element 2 onto the element 2. The blasting medium 34 is, for example, particles made of zircon or alumina.

[0059] The projection conditions can mainly set the projection speed, the projection amount, and the projection area. The projection speed is adjusted by the pressure and path of the blasting medium 34. The projection amount is adjusted by the medium circulation and the projection time. The projection area is adjusted by the nozzle shape and the distance between the element 2 and the nozzle 33.

[0060] At this time, the blasting medium 34 projected from the nozzle 33 wraps around the pair of side surfaces, the front surface, and the rear surface of the element 2. Therefore, while leaving the oxide film on the base layer 7 on the upper surface M3 side, the oxide film on the base layer 7 is removed on the mounting surface M1 side, the pair of side surfaces M2 side, and the front and rear surfaces. Note that the polishing amount of the oxide film on the base layer 7 on the mounting surface M1 side, the pair of side surfaces M2 side, and the front and rear surface sides can be set within a range in which the plating layer 9 can be formed on the base layer 7 on the mounting surface M1 side, the side surface M2 side, and the front and rear surfaces.

[0061] As described above, according to the second embodiment described above, by removing the oxide film on the mounting surface M1, side surfaces M2, and front and rear surfaces of the base layer 7 of each of the external electrodes 6A and 6B by blast polishing, while the upper surface M3 of each of the external electrodes 6A and 6B remains covered with the coating layer 8, the plating layer 9 can be selectively and efficiently formed on the mounting surface M1, side surfaces M2, and front and rear surfaces of each of the external electrodes 6A and 6B. Therefore, while suppressing an increase in the number of steps, it is possible to prevent the circuit board on which the electronic component is mounted from becoming higher than designed, and it is possible to achieve high-density mounting of the electronic components mounted on the circuit board.

[0062] In addition, in the above-described embodiment, the method using blast polishing has been described for removing the coating layer 8 on the mounting surface M1, side surfaces M2, and front and rear surfaces of each of the external electrodes 6A and 6B. However, isotropic dry etching such as plasma etching may be used, or chemical polishing such as wet etching may be used.

[0063] (Third Embodiment) FIG. 6A is a cross-sectional view showing a configuration example of an end portion of a coating layer of a multilayer ceramic capacitor according to the third embodiment. In FIG. 6A, the base layer 7 includes a chamfered surface 7A where the ridge portion of the base layer 7 is chamfered. The chamfered surface 7A of the base layer 7 may have a shape in which the ridge portion of the base layer 7 is cut off, or may have a curved shape. For example, the radius of curvature of the chamfered surface 7A of the base layer 7 can be within the range of 1 μm to 50 μm.

[0064] At least a part of the end portion of the coating layer 8 is located along the chamfered surface 7A of the base layer 7. Thereby, while sufficiently securing the area where the solder wets from the side surface M2 of the base layer 7 to the end portion of the coating layer 8, it is possible to suppress the solder from overflowing onto the upper surface M3 of the base layer 7.

[0065] The angle θ formed by the tangent line of the chamfered surface 7A at the position where the end of the coating layer 8 contacts the side surface M2 of the base layer 7 and the upper surface M3 of the external electrode 6A can be made greater than 45°. Thereby, the overflow of solder from the side surface M2 to the upper surface M3 can be effectively suppressed. Note that the angle θ can be controlled by the projection conditions during the blast polishing in FIGS. 5A and 5B.

[0066] FIG. 6B is a cross-sectional view showing a configuration example of the interface between the end of the coating layer and the base layer of the multilayer ceramic capacitor according to the third embodiment. In FIG. 6B, irregularities 8A are provided at the end of the coating layer 8 on the chamfered surface 7A of the base layer 7. These irregularities 8A are caused by variations in the wrap-around of the blast media 34 of the element 2 to the side surface in FIG. 5B. The range of the height difference TH of the irregularities 8A at the end of the coating layer 8 can be, for example, within the range of 0.1 μm to 10 μm by controlling the variations by changing the position of the nozzle 33 of the blast polishing during processing. Thereby, even when the solder wets up to the end of the coating layer 8, the crack can be made less likely to extend linearly.

[0067] As described above, according to the third embodiment described above, by arranging the end of the coating layer 8 along the chamfered surface 7A of the base layer 7, a sufficient area for the solder to wet can be ensured, and the overflow of the solder from the mounting area of the multilayer ceramic capacitor 1A can be reduced.

[0068] (Fourth Embodiment) FIG. 7A is a cross-sectional view showing the configuration of a circuit board on which the multilayer ceramic capacitor according to the fourth embodiment is mounted. In FIG. 7A, land electrodes 42A and 42B are formed on a circuit board 41. The multilayer ceramic capacitor 1A is connected to the land electrodes 42A and 42B via solder layers 43A and 43B attached to the Sn plating layers 9C of the external electrodes 6A and 6B. Here, the upper surfaces M3 of the external electrodes 6A and 6B are covered with a coating layer 8, and plating layers 9A to 9C are formed on the mounting surface M1 and the side surfaces M2 of the external electrodes 6A and 6B. Thereby, when mounting the multilayer ceramic capacitor 1A on the circuit board 41, while preventing the solder from wetting and rising on the upper surfaces M3 of the external electrodes 6A and 6B, the solder can be wet and absorbed on the side surfaces M2 and the front and rear surfaces of the external electrodes 6A and 6B. For this reason, even when an excessive amount of solder is supplied onto the land electrodes 42A and 42B, it is possible to suppress the solder from overflowing from the land electrodes 42A and 42B while preventing the circuit board 41 on which the multilayer ceramic capacitor 1A is mounted from becoming higher than the design. For this reason, it is possible to narrow the interval between the electronic components mounted on the circuit board 41 while suppressing a short circuit between the electronic components mounted on the circuit board 41, and high-density mounting of electronic components can be achieved.

[0069] At this time, the solder can be wet and risen until the Sn plating layer 9C disappears, and the solder absorption area can be increased as compared with the case where the coating layer 8 is on the side surfaces M2 of the external electrodes 6A and 6B.

[0070] Further, by wetting and rising the solder on the side surfaces M2 of the external electrodes 6A and 6B, the multilayer ceramic capacitor 1A can be supported on the circuit board 41 at the mounting surface M1 and the side surfaces M2 of the external electrodes 6A and 6B. For this reason, the mounting strength of the multilayer ceramic capacitor 1A can be improved as compared with the case where the multilayer ceramic capacitor 1A is supported on the circuit board 41 only by the mounting surface M1 of the external electrodes 6A and 6B, and even when the circuit board 41 is used for in-vehicle applications, it is possible to suppress the multilayer ceramic capacitor 1A from falling off the circuit board 41 due to vibration or the like.

[0071] Furthermore, the stress from the base body 2 can be absorbed by the base layer 7 and the coating layer 8 on the upper surfaces M3 of the external electrodes 6A and 6B, making it difficult for cracks to enter the base body 2.

[0072] As described above, according to the fourth embodiment described above, while enabling solder wetting on the mounting surfaces M1 and side surfaces M2 of each of the external electrodes 6A and 6B, by providing the coating layer 8 on the upper surface M3 of each of the external electrodes 6A and 6B, the reliability of the multilayer ceramic capacitor 1A mounted on the circuit board 41 can be improved, and the mounting density of electronic components on the circuit board 41 can be improved.

[0073] (First Comparative Example) FIG. 7B is a cross-sectional view showing the configuration of a circuit board on which a multilayer ceramic capacitor according to the first comparative example is mounted. In FIG. 7B, the multilayer ceramic capacitor 1A' includes external electrodes 6A' and 6B' instead of the external electrodes 6A and 6B in FIG. 7A. Each of the external electrodes 6A' and 6B' includes a coating layer 8', a Cu plating layer 9A', a Ni plating layer 9B', and a Sn plating layer 9C' instead of the coating layer 8, the Cu plating layer 9A, the Ni plating layer 9B, and the Sn plating layer 9C in FIG. 7A.

[0074] Surfaces other than the mounting surface M1 of the external electrodes 6A' and 6B' (side surface M2 and upper surface M3) are covered with the coating layer 8'. A Cu plating layer 9A', a Ni plating layer 9B', and a Sn plating layer 9C' are formed on the base layer 7 on the mounting surface M1 and the side surface M2 side of each of the external electrodes 6A' and 6B'.

[0075] On one side, land electrodes 42A' and 42B' are formed on the circuit board 41. The multilayer ceramic capacitor 1A' is connected to the land electrodes 42A' and 42B' via solder layers 43A' and 43B' attached to the Sn plating layers 9C' of the external electrodes 6A' and 6B, respectively. At this time, since the side surfaces M2 of the external electrodes 6A' and 6B are covered with the coating layer 8', solder does not wet the side surfaces M2 of the external electrodes 6A' and 6B. Therefore, when an excessive amount of solder is supplied, the solder layers 43A' and 43B' may protrude from the mounting surface M1 onto the circuit board 41, which may hinder the high-density mounting of electronic components.

[0076] (Second Comparative Example) FIG. 7C is a cross-sectional view showing the configuration of a circuit board on which a multilayer ceramic capacitor according to the second comparative example is mounted. In FIG. 7C, the multilayer ceramic capacitor 1A'' includes external electrodes 6A'' and 6B'' instead of the external electrodes 6A and 6B in FIG. 7A. The external electrodes 6A'' and 6B'' include a Cu plating layer 9A'', a Ni plating layer 9B'', and a Sn plating layer 9C'' instead of the coating layer 8, the Cu plating layer 9A, the Ni plating layer 9B, and the Sn plating layer 9C in FIG. 7A.

[0077] A Cu plating layer 9A'', a Ni plating layer 9B'', and a Sn plating layer 9C'' are formed on the mounting surface M1, the side surface M2, and the underlying layer 7 on the upper surface M3 side of the external electrodes 6A'' and 6B''.

[0078] The multilayer ceramic capacitor 1A'' is connected to the land electrodes 42A and 42B via solder layers 43A'' and 43B'' attached to the Sn plating layers 9C'' of the external electrodes 6A'' and 6B'', respectively. At this time, solder wets up to the upper surface M3 through the side surfaces M2 of the external electrodes 6A'' and 6B'', and solder layers 43A'' and 43B'' bulging on the upper surfaces M3 of the external electrodes 6A'' and 6B'' are formed. Therefore, the circuit board 41 on which the multilayer ceramic capacitor 1A'' is mounted may become higher than the original design.

[0079] (Fifth Embodiment) FIG. 8 is a plan view seen from the coating layer side showing the configuration of the multilayer ceramic capacitor according to the fifth embodiment. In FIG. 8, the multilayer ceramic capacitor 1B includes coating layers 8A and 8B instead of the coating layer 8 in FIG. 1. The multilayer ceramic capacitor 1B can be configured in the same manner as the multilayer ceramic capacitor 1A in FIG. 1 except that the coating layers 8A and 8B are provided instead of the coating layer 8 in FIG. 1. Each of the coating layers 8A and 8B is located in a part including a boundary region where the ends of the coating layers 8A and 8B are in contact with the side surfaces M2 of the underlying layers 7A and 7B on the upper surfaces M3 of the external electrodes 6A and 6B. For example, each of the coating layers 8A and 8B can be arranged in a continuous strip shape along the outer edges in three directions of the upper surfaces M3 of the external electrodes 6A and 6B so as to cover the ends of the upper surfaces M3 of the external electrodes 6A and 6B. The outer edges of the upper surfaces M3 of the external electrodes 6A and 6B are the edges in contact with the side surfaces M2 and the edges in contact with the front and rear surfaces M4. At this time, the planar shape of each of the coating layers 8A and 8B can be a shape with one side of a quadrangle open.

[0080] When forming the coating layers 8B and 8C on the upper surfaces M3 of the external electrodes 6A and 6B, for example, after covering the inner regions of the coating layers 8B and 8C on the upper surfaces M3 of the external electrodes 6A and 6B with a resist film, the upper surfaces M3 of the external electrodes 6A and 6B can be polished by blasting in the methods of FIGS. 5A and 5B.

[0081] As described above, according to the fifth embodiment described above, the coating layers 8A and 8B are formed on the upper surfaces M3 of the external electrodes 6A and 6B, and the plating layer 9 is formed on the mounting surface M1 and the side surface M2 of the external electrodes 6A and 6B. Thereby, while suppressing the overflow of solder from the mounting area of the multilayer ceramic capacitor 1B, it is possible to prevent an increase in the height during mounting of the multilayer ceramic capacitor 1B, prevent the circuit board on which the electronic component is mounted from becoming higher than the design, and achieve high-density mounting of the electronic components mounted on the circuit board.

[0082] In the above-described embodiment, an example in which the coating layer 8 is formed including a metal oxide film used as the conductive material of the base layer 7 has been shown. The coating layer 8 may be configured to include a glass phase having the same composition as the glass component contained in the base layer 7.

[0083] (Sixth Embodiment) FIG. 9 is a flowchart showing a method for manufacturing a multilayer ceramic capacitor according to the sixth embodiment. Note that FIG. 3 shows a case where the coating layer 8 is formed including a metal oxide film used as the conductive material of the base layer 7, and FIG. 9 shows a case where the coating layer 8 is formed including a glass phase having the same composition as the glass component contained in the base layer 7.

[0084] In S21 to S27 of FIG. 9, a green body 2 from which the binder has been removed is produced by the same steps as S1 to S7 of FIG. 3.

[0085] Next, as shown in S28 of FIG. 9, the green body 2 from which the binder has been removed in S27 of FIG. 9 is fired to integrate the internal electrode layers 3A and 3B and the dielectric layer 4. The firing of the green body 2 is performed, for example, in a firing furnace at 1000 to 1350°C for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A and 3B, firing can be performed in a reducing atmosphere in the firing furnace in order to prevent oxidation of the internal electrode layers 3A and 3B.

[0086] Next, as shown in S29 of FIG. 9, a conductive paste for the base layer is applied to both side surfaces of the green body 2 fired in S28 of FIG. 9 and to four surfaces of the peripheral surface of each side surface, and then dried. The conductive paste for the base layer contains a metal powder or filler used as the conductive material of the base layer 7. For example, when the metal used as the conductive material of the base layer 7 is Cu, the conductive paste for the base layer contains a Cu powder or filler. Further, the conductive paste for the base layer contains a glass sintering aid (for example, SiO2, etc.). The content of the glass sintering aid can be, for example, in the range of 11 wt% to 13 wt%.

[0087] Next, the green body 2 coated with the conductive paste for the underlayer is fired to form an underlayer 7 integrated with the green body 2. The firing of the green body 2 is performed, for example, in a firing furnace at 850°C for 15 minutes or more. On the surface of the underlayer 7 sintered under such conditions, a glass phase having the same composition as the glass component contained in the underlayer 7 rises to form a coating layer 8. No plating adheres to the surface of the underlayer 7 where the glass phase has risen, and no solder adheres during mounting. Note that the higher the firing temperature, the longer the firing time, and the larger the content of the glass sintering aid, the easier it is for the glass phase to rise to the surface of the underlayer 7. Therefore, based on the firing temperature, the firing time, and the content of the glass sintering aid, the thickness of the glass phase can be controlled.

[0088] Next, as shown in S30 and S31 of FIG. 9, plating pretreatment and plating are performed by the same steps as S11 and S12 of FIG. 3.

[0089] As described above, according to the sixth embodiment described above, the coating layer 8 is configured to include a glass phase having the same composition as the glass component contained in the underlayer 7, and the other configurations are the same as those of the first to fifth embodiments. Also in such a coating layer 8, it is possible to prevent the solder from wetting on the surfaces of the external electrodes 6A and 6B on which the coating layer 8 is formed.

[0090] (Seventh Embodiment) FIG. 10 is a perspective view showing the configuration of an electronic component according to the seventh embodiment. In FIG. 10, a chip inductor is taken as an example of the electronic component. In FIG. 10, the chip inductor 61 includes a green body 62 and external electrodes 66A and 66B. The green body 62 includes a coil pattern 63, internal electrode layers 63A and 63B, and a magnetic material 64. The shape of the green body 62 can be a substantially rectangular parallelepiped shape. The external electrodes 66A and 66B are located on the opposing side surfaces of the green body 62 in a separated state from each other. Each of the external electrodes 66A and 66B extends from each side surface of the green body 62 to the front and rear surfaces and the upper and lower surfaces.

[0091] The coil pattern 63 and the internal electrode layers 63A and 63B are covered with a magnetic material 64. However, the end of the internal electrode layer 63A is drawn out from the magnetic material 64 on one side surface of the base body 62 and connected to the external electrode 66A. The end of the internal electrode layer 63B is drawn out from the magnetic material 64 on the other side surface of the base body 62 and connected to the external electrode 66B.

[0092] The materials of the coil pattern 63 and the internal electrode layers 63A and 63B can be selected from metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, and may also be alloys containing these metals. The magnetic material 64 is, for example, ferrite.

[0093] Each of the external electrodes 66A and 66B includes an underlayer 67 and a plating layer 69. Each of the external electrodes 66A and 66B has a mounting surface M1, a side surface M2, an upper surface M3, and front and rear surfaces M4. The mounting surface M1 is the surface facing the circuit board on which the chip inductor 61 is mounted. The upper surface M3 is the surface opposite to the mounting surface M1.

[0094] The conductive material of the underlayer 67 can be mainly composed of a metal or an alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The underlayer 67 contains a co-material. The co-material is, for example, a ceramic component that is the main component of the magnetic material 64. The underlayer 67 may contain a glass component. This glass component is, for example, an oxide such as Ba, Sr, Ca, Zn, Al, Si, or B.

[0095] The surfaces (upper surface M3) other than the mounting surface M1, the side surface M2, and the front and rear surfaces M4 of each of the external electrodes 66A and 66B are covered with a coating layer 68. The coating layer 68 may be configured to include an oxide film of the metal used as the conductive material of the underlayer 67, or may be configured to include a glass phase having the same composition as the glass component contained in the underlayer 67. A plating layer 69 is formed on the underlayer 67 on the mounting surface M1 side, the side surface M2 side, and the front and rear surfaces M4 of each of the external electrodes 66A and 66B.

[0096] As described above, according to the seventh embodiment described above, by providing the coating layer 68 on the upper surfaces M3 of the external electrodes 66A and 66B of the chip inductor 61, it is possible to suppress the overflow of solder from the mounting area of the chip inductor 61 and prevent an increase in the height during mounting of the chip inductor 61.

[0097] (Eighth Embodiment) FIG. 11 is a perspective view showing the configuration of an electronic component according to the eighth embodiment. In FIG. 11, a chip resistor is taken as an example of the electronic component. In FIG. 11, the chip resistor 71 includes a body 72, external electrodes 76A and 76B, and a protective film 75. The body 72 includes a resistor 73, an internal electrode layer 73B, and a substrate 74. The shape of the body 72 can be a substantially rectangular parallelepiped shape. The external electrodes 76A and 76B are located on the opposing side surfaces of the body 72 in a separated state from each other. Each of the external electrodes 76A and 76B extends from each side surface of the body 72 to the upper and lower surfaces.

[0098] The resistor 73 and the internal electrode layer 73B are disposed on the substrate 74 and covered with the protective film 75. One end of the resistor 73 is connected to the internal electrode layer 73B on the substrate 74. Also, the internal electrode layer 73B extends to one side surface side of the body 72 and is connected to the external electrode 76B. An internal electrode layer (not shown) connected to the other end of the resistor 73 extends to the other side surface side of the body 72 and is connected to the external electrode 76A.

[0099] The material of the resistor 73 can be selected from metals such as Ag and Pd, for example, and may be an alloy containing these metals. The material of the resistor 73 may be a metal oxide such as ruthenium oxide. The material of the internal electrode layer 73B can be selected from metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, for example, and may be an alloy containing these metals. The material of the substrate 74 is, for example, an oxide ceramic such as alumina. The material of the protective film 75 is, for example, glass or resin.

[0100] Each of the external electrodes 76A and 76B includes an underlying layer 77 and a plating layer 79. Each of the external electrodes 76A and 76B has a mounting surface M1, a side surface M2, and an upper surface M3. The mounting surface M1 is the surface facing the circuit board on which the chip resistor 71 is mounted. The upper surface M3 is the surface on the opposite side of the mounting surface M1.

[0101] The conductive material of the underlying layer 77 can be mainly composed of a metal or an alloy containing at least one selected from, for example, Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The underlying layer 77 contains a co-material. The co-material is, for example, a ceramic component that is the main component of the substrate 74. The underlying layer 77 may contain a glass component. This glass component is, for example, an oxide such as Ba, Sr, Ca, Zn, Al, Si, or B.

[0102] Surfaces other than the mounting surface M1 and the side surface M2 of each of the external electrodes 76A and 76B (upper surface M3) are covered with a coating layer 78. The coating layer 78 may be configured to include an oxide film of the metal used as the conductive material of the underlying layer 77, or may be configured to include a glass phase having the same composition as the glass component contained in the underlying layer 77. A plating layer 79 is formed on the underlying layer 77 on the mounting surface M1 and the side surface M2 sides of each of the external electrodes 76A and 76B.

[0103] As described above, according to the eighth embodiment described above, by providing the coating layer 78 on the upper surface M3 of the external electrodes 76A and 76B of the chip resistor 71, it is possible to suppress the overflow of solder from the mounting area of the chip resistor 71 and prevent an increase in the height during mounting of the chip resistor 71.

[0104] In the above-described embodiment, the case where a coating layer is provided on the upper surface of the external electrode has been taken as an example to prevent the solder from spreading on the upper surface of the external electrode. However, a coating layer having a lower wettability of solder than the plating layer of the external electrode may be provided on the upper surface of the external electrode. The wettability of the solder can be measured by, for example, the contact angle. At this time, the contact angle of the solder on the coating layer is higher than the contact angle of the solder on the plating layer. Here, the contact angle can be confirmed, for example, by dipping the product in a molten solder bath and then pulling it out, checking the cross-section in the vertical direction of the target surface, and measuring the angle at which the solder contacts the surface.

[0105] In the above-described embodiment, a two-terminal component has been taken as an example of the electronic component. However, an electronic component having three or more terminals, such as a transistor or a transformer, may also be used.

[0106] Also, instead of the material of the above-described embodiment, the coating layer 8 may be a resist film containing resin. By using a resist film as the coating layer 8, it can be formed to a desired thickness.

Explanation of Reference Numerals

[0107] 1 Multilayer ceramic capacitor 2 Body 2A Laminate 3A, 3B Internal electrode layer 4 Dielectric layer 5A, 5B Cover layer 6A, 6B External electrode 7 Underlayer 8 Coating layer 9 Plating layer

Claims

1. A dielectric body, a base body provided with internal electrodes, a base layer formed on a plurality of surfaces of the base body and connected to the internal electrodes and containing a metal, a plating layer formed on the base layer on the mounting surface side of the base body and on the side surface where the internal electrodes are connected to the base layer, and a coating layer formed on the base layer on the surface opposite to the mounting surface and having lower solder wettability than the plating layer. The external electrode includes and comprises the coating layer exists up to the edge where the surface opposite to the mounting surface and the side surface are in contact, and does not exceed the edge, An electronic component, characterized in that at the edge, unevenness is formed at the end of the coating layer.

2. The electronic component according to claim 1, characterized in that the height difference of the unevenness is in the range of 0.1 μm to 10 μm.

3. The base layer extends from the side surface of the base body to the front and rear surfaces and the upper and lower surfaces, the mounting surface is provided on the lower surface side of the base body, the coating layer is provided on the upper surface side of the base body, The electronic component according to claim 1 or 2, characterized in that the plating layer is further formed on the base layer on the front surface side and the rear surface side of the base body.

4. The electronic component according to any one of claims 1 to 3, characterized in that the coating layer contains an oxide film of the metal.

5. The base layer contains a co-material mixed with the metal, The electronic component according to any one of claims 1 to 4, characterized in that the coating layer includes the co-material.

6. The electronic component according to claim 5, characterized in that the co-material contained in the base layer and the co-material contained in the coating layer have the same composition.

7. The electronic component according to claim 5 or 6, characterized in that the co-material is an oxide ceramic containing the dielectric.

8. The electronic component according to any one of claims 1 to 7, characterized in that the coating layer is a resist film containing resin.

9. The base layer contains a glass component, The electronic component according to any one of claims 1 to 3, characterized in that the coating layer has a glass phase having the same composition as the glass component contained in the base layer.

10. The electronic component according to any one of claims 1 to 9, characterized in that the metal of the base layer is a metal or alloy containing at least one selected from Cu, Fe, Zn, Al and Ni.

11. The plating layer is a Ni plating layer, The electronic component according to any one of claims 1 to 10, comprising a Sn plating layer formed on the Ni plating layer.

12. The electronic component according to any one of claims 1 to 11, wherein the coating layer is arranged in a continuous strip shape along the edges in contact with the side surface and the front and rear surfaces, respectively, on the surface opposite to the mounting surface of the external electrode.

13. The base layer includes a chamfered surface where the ridge portion of the base layer is chamfered, The electronic component according to any one of claims 1 to 12, wherein at least a part of the end portion of the coating layer is located along the chamfered surface of the base layer.

14. The electronic component according to claim 13, wherein the angle formed by the tangent line of the chamfered surface at the position where the end portion of the coating layer contacts the side surface of the base layer and the surface opposite to the mounting surface of the external electrode is greater than 45°.

15. The element includes a laminate in which a first internal electrode layer and a second internal electrode layer are alternately laminated via the dielectric, The external electrode includes a first external electrode and a second external electrode provided on the side surfaces of the laminate facing each other, The first internal electrode layer is connected to the first external electrode, The electronic component according to any one of claims 1 to 14, wherein the second internal electrode layer is connected to the second external electrode.

16. A circuit board on which the electronic component according to any one of claims 1 to 15 is mounted, The circuit board is characterized in that the electronic component is connected to the circuit board through a solder layer attached to the plating layer on the mounting surface side in a state where the solder layer has spread to the side surface of the external electrode.

17. A step of forming an element provided with a dielectric and an internal electrode; A step of applying an electrode material containing a metal to the side surface and the periphery of the element; A step of firing the electrode material to form a base layer containing the metal on the side surface and the periphery of the element; A step of forming a coating layer covering the surface of the base layer; A step of removing the coating layer on the mounting surface side and the side surface of the element while leaving the coating layer on the surface opposite to the mounting surface side of the element; A step of forming a plating layer on the mounting surface side and the side surface of the element on the base layer; The coating layer has a lower wettability of solder than the plating layer. The step of removing the coating layer includes forming irregularities at the end of the coating layer at the edge where the surface opposite to the mounting surface side and the side surface are in contact, in the manufacturing method of an electronic component.

18. The manufacturing method of the electronic component according to claim 17, wherein the height difference of the irregularities is in the range of 0.1 μm to 10 μm.

19. The step of forming a coating layer covering the surface of the base layer The manufacturing method of the electronic component according to claim 17 or 18, characterized by comprising a step of oxidizing the metal and forming an oxide film of the metal on the surface of the base layer.

20. The electrode material contains a glass component, The step of forming a coating layer covering the surface of the base layer The manufacturing method of the electronic component according to claim 17 or 18, characterized by comprising a step of causing a glass phase composed of the glass component to float on the surface of the base layer during firing of the electrode material.

21. The step of removing the coating layers on the mounting surface side and the side surface side of the element body includes a step of blast-polishing the coating layer from the mounting surface side of the base layer, in the manufacturing method of the electronic component according to any one of claims 17 to 20.

Images