Method and apparatus (assembly of chips onto a substrate)

Abstract

To provide techniques for assembling a chip and a substrate.SOLUTION: An exemplary method includes: at a bonding temperature, bonding a semiconductor chip to an organic laminate substrate using solder; at an underfill dispense temperature without cooldown from the bonding temperature to room temperature, dispensing an underfill between the semiconductor chip and the organic laminate substrate; and curing the underfill within a range of temperatures above the underfill dispense temperature. Another exemplary method includes: depositing a first solder on pads of an organic laminate substrate; bringing a second solder on pillars of a semiconductor chip into contact with the first solder on the pads of the organic laminate substrate; and soldering the semiconductor chip to the organic laminate substrate.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to electrical, electronic, and computer technologies, and more particularly to the assembly of integrated circuit (IC) chip packages.

Background Art

[0002] It is well known that the miniaturization of IC technology has been progressing rapidly. The recently achieved technology node is the 5nm (nanometer) transistor scale, enabling a transistor density of 134 million per square millimeter within the chip. However, the interconnection between a chip having a high-density bump wiring and an organic multilayer substrate is difficult. The connector pitch (the center-to-center distance between adjacent connectors) limits the speed at which data can be transferred between the chips, thereby setting an upper limit on the achievable performance not only in multi-chip packages but also in a practical single-chip package operating with an off-chip memory module. The current goal for chip stack interconnection is a pitch of less than 55μm (micrometer).

Summary of the Invention

Problems to be Solved by the Invention

[0003] Similar to the problem of quantum tunneling for increasing transistor density, the nearest-neighbor short circuit during soldering is a problem for narrowing the connector pitch of the chip. One approach to reducing the risk of short circuits is to reduce the amount of solder provided for each controlled collapse chip connector (C4) bump on the chip.

[0004] Another issue when reducing the pitch of a chip connector is the possible deformation of the chip and substrate that occurs during the thermal excursion of common processing steps. The thermal stress caused by the difference in the coefficient of thermal expansion (CTE) between the semiconductor chip and the organic laminate substrate is an element that must always be considered when aligning the chip connector with the substrate pads. At pitches narrower than about 55 μm, misalignment and misconnection are more likely to occur due to thermal stress.

Means for Solving the Problem

[0005] The principle of the present invention provides a technique for assembling a chip onto a substrate. In one aspect, an exemplary method includes joining a semiconductor chip to an organic laminate substrate using solder at a joining temperature, discharging an underfill between the semiconductor chip and the organic laminate substrate at the discharging temperature of the underfill without cooling from the joining temperature to room temperature, and curing the underfill within a temperature range higher than the discharging temperature of the underfill. Before bonding, discharging at least two spots of a volatile adhesive between the semiconductor chip and the organic multilayer substrate, and the bonding being performed in a formic acid atmosphere including.

[0006] According to another aspect, an exemplary method includes depositing a first solder on the pads of an organic laminate substrate, bringing a second solder on the pillars of a semiconductor chip into contact with the first solder on the pads of the organic laminate substrate, and soldering the semiconductor chip to the organic laminate substrate. further, the first solder having a lower melting point than the second solder including.

[0007] According to another aspect, an exemplary apparatus includes a semiconductor chip 401 having pillars 402 protruding from the lower surface thereof with a pitch of 55 μm (micrometers) or less, and a cap 406 of a first solder attached to the lower end of the pillars; an organic laminate substrate 403 having pads 404 protruding from the upper surface thereof with the same pitch as the semiconductor chip, and a cap 408 of a second solder attached to the upper surface of the pads; and two or more dots of a volatile adhesive 1208 that attaches the upper surface of the organic laminate substrate to the lower surface of the semiconductor chip. It is found that the second solder further has a lower melting point than the first solder. According to another aspect, an exemplary device includes a semiconductor chip 401 having pillars 402 protruding from the lower surface of the semiconductor chip 401 at a pitch of 55 μm (micrometers) or less, an organic multilayer substrate 403 having pads 404 protruding from the upper surface of the organic multilayer substrate 403 at the same pitch as the semiconductor chip, and a joint composed of a ternary composition that bonds each pillar to the corresponding pad, the joint not melting at 150°C.

[0008] In view of the foregoing, the technology of the present invention can provide substantially beneficial technical effects. For example, one or more embodiments provide one or more of the following.

[0009] Underfill reduces thermal stress and protects the chip connector from shear stress during cooling from the solder joint temperature to room temperature.

[0010] Improved reliability of solder connections from chips to organic substrates at C4 pitches of less than 55 μm.

[0011] Generally, underfill before cooling is an advantageous technique. It is most effective for joining large chips with fine pitch bumps to warped substrates, but can be used regardless of the chip size or the size of the micro bumps, and can also be applied to bridge chip assemblies. This technique can be used not only for a single chip, but also for joining multiple chips to the same substrate.

[0012] These and other features and advantages of the present invention will become apparent from the following detailed description of its exemplary embodiments, which should be read in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0013]

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DETAILED DESCRIPTION OF THE INVENTION

[0014] Referring to FIG. 1, a prior art process 100 for bonding a semiconductor chip 102 to an organic laminate substrate 104 includes several steps. At 106, the chip 102 is immersed in a flux bath 108. At 110, the flux-treated chip 102 is thermocompression bonded to the substrate 104. At 112, the flux residue is washed away from between the chip 102 and the substrate 104. At 114, an underfill 116 is dispensed and cured between the chip 102 and the substrate 104.

[0015] The flux dipping in step 106 is performed at room temperature. The fluidization of the flux solid is performed at a higher temperature (typically, 90°C (Celsius) to 150°C). The thermocompression bonding in step 110 is performed at an even higher temperature (typically, 235°C to 245°C, generally at least 20°C to 30°C higher than the solidus temperature of the solder). However, the flux cleaning in step 112 is performed at room temperature or near it (typically, about 70°C to 90°C). The underfill dispensing in step 114 is achieved at a slightly warm temperature (typically, about 80°C to 120°C), and then the underfill curing is achieved at another high temperature (typically, about 120°C to 160°C).

[0016] It has been found that it is not successful to attempt to connect a large silicon chip having 40-μm pitch I / Os to an organic substrate using a conventional belt furnace reflow as commonly used to bond silicon chips to organic substrates. One reason for this is the warpage of the laminate at both room temperature and near the melting point of the solder, where the amount of warpage becomes larger than the height of the solder of the micro-bumps. In a normal chip stacking implementation, it is common to use C4 solder having a diameter of 80 μm or more instead of micro-bumps, as the solder of this diameter can function well because it can follow the laminate to some extent even if the laminate is warped. However, it is very difficult to directly connect a large silicon chip having narrow-pitch micro-bumps to an organic substrate.

[0017] The cooling thermal excursion between step 110 (thermocompression bonding) and step 112 (flux cleaning) subjects the solder joint between the chip 102 and the substrate 104 to thermomechanical stress due to the mismatch in the coefficient of thermal expansion (CTE) between these two components. Generally, the organic laminate substrate 104 has a CTE that is 3 to 10 times larger than that of the chip. Thus, as shown in FIG. 2, the surface 120 of the substrate 104 facing the chip 102 is closer to the chip at a lower temperature (e.g., room temperature) than at a higher temperature (e.g., the bonding temperature).

[0018] When the thermal cycle of the substrate 104 is repeated during or before chip assembly, warpage is induced as shown in FIG. 2. A typical warpage causes the substrate to curve at room temperature, and the amount (in a non-limiting example) is such that the difference in the vertical distance between the edge and the center of the chip between room temperature and a typical solder joint temperature reaches about 12 - 22 μm (micrometers) for a 30 mm (millimeter) chip and substrate. The exemplary values herein are only for the amount of warpage of this particular laminate, and the amount of warpage varies greatly depending on the thickness, size, material, and structure of the laminate. For example, when the core material of the laminate is thin, the amount of warpage may exceed 100 micrometers. Even if a laminate with a thicker core is used to keep the warpage low as in this case, when the chip is large and the bump pitch is fine, bonding becomes extremely difficult. A typical warpage of the substrate 104 results in undesirable consequences such as, for a large chip (about 30 mm), the solder can only wet the substrate pads around the edge of the chip during reflow or other bonding processes.

[0019] Furthermore, in the case of the Au surface finish of the pads, there is a problem that the solder from the semiconductor chip wets the side surfaces of the pads of the organic laminate substrate rather than filling the joint between the pillars of the semiconductor chip and the substrate pads. This occurs because Au is a very wettable material during solder reflow.

[0020] For example, FIG. 3 shows a chip assembly 300. The chip assembly 300 includes a semiconductor chip 301 having Cu pillars 302 with a pitch of less than 55 μm, and an organic multilayer substrate 303 having substrate connector pads 304. In the conventional example, solder caps / micro bumps 306 are present on the pillars 302. In fine pitch bonding, pillars and micro bumps are used instead of C4 balls. The pillars are made of a high melting point material such as Cu (or even Ni) and a solder cap of a low melting point material. The composition of the pillar is a layered Cu / Ni / Cu / SnAg. The first Cu is used to increase the height, Ni is used as a barrier layer, and the second Cu is used to react with SnAg when it melts. The height Hp of the pillar is 5 to 30 μm. The composition of the pad is a layered Cu / Ni / Pd / Au having a gold coating layer. For example, the layers are 5 to 20 μm of Cu, 0.5 to 5 μm of Ni, 0.02 to 0.2 μm of Pd, and 0.01 to 0.2 μm of Au. The pillars 302 and the pads 304 have a relatively high melting point according to their composition, while the solder caps 306 have a lower melting point according to their composition. The diameter D of the pillar 302 (about 10 to 30 μm) and the surface tension of the liquid solder limit the height Hs and the volume of the solder cap 306 to a substantially hemispherical shape with a radius of 5 to 15 μm. This amount of solder is not sufficient to wet both the side and the top of the pad 304. As a result, during reflow, the solder wets the side of the pad 304 and little solder remains on the top. Within the range of the desired connector pitch specification, it is impossible to make the pillar 302 thicker. Therefore, it is not possible to apply more solder on the pillar.

[0021] According to one aspect of the present disclosure, the inventors considered that it might be possible to modify the conventional chip assembly process such that solder is also present on the pad 304 during reflow / bonding. Thus, FIG. 4 shows a detailed view of a chip assembly 400 including C4 pillars 402 protruding downward from a chip 401 and substrate pads 404 protruding upward from a substrate 403. According to an exemplary embodiment, there is one solder cap / micro-bump 406 on the pillar 402 and another solder cap / micro-bump 408 on the pad 404. The combined height and volume of the two solder caps 406, 408 absorb the gap induced by the warp between the chip 401 and the substrate 403 and provide sufficient solder at the bonding interface even if it wets and spreads over the side surface of the pad 404.

[0022] One or more embodiments advantageously achieve a structure shown in FIG. 4 that is different from conventional chip assembly. Aspects of the present disclosure provide several techniques for generating a solder cap 408 on the substrate pad 404 prior to reflow / bonding of the chip.

[0023] FIG. 5 schematically shows a process 500 for bonding a chip 401 to a substrate 403 according to an exemplary embodiment. At 502, a low melting point solder, such as SnBi (tin-bismuth), as a specific example Sn 42 Bi 58Prepare a transfer die 503 having bumps 504 such as these. Such solder has a eutectic melting point of 139°C. At 506, by reflowing the solder at a relatively low temperature, i.e., 139°C to 150°C, the solder bumps 504 are transferred from the transfer die 503 to the pads 404 of the substrate 403. At 508, the transfer die 503 is pulled, leaving the low-melting-point solder as bumps 408 on the pads 404. At 510, prepare a chip 401 having solder bumps 406 of SnAg (tin-silver) or similar solder on the pillars 402. The SnAg solder has a melting point of about 221°C. At 512, the chip 401 is bonded to the substrate 403 by heating the assembly to a bonding temperature, e.g., 139°C to 150°C. Since low-temperature SnBi solder is used, it is advantageous that the bonding temperature is lower than the conventional range of 235°C to 245°C for reflow of SnAg solder and the like. By lowering the temperature, thermal excursion and the accompanying thermo-mechanical stress are reduced, thereby reducing the warping of the substrate 403. Also, by lowering the temperature, only local melting is possible instead of complete melting of the conventional C4 solder. By locally melting, the nearest-neighbor short circuit is reduced, thereby making it possible to narrow the pitch (make it finer). Since the SnAg solder of the bumps 406 dominates the joint after reflow (in one or more embodiments, the bumps 406 are larger than the bumps 408 and the Bi from the bumps 408 only becomes part of the ternary composition with SnAg), the joint does not melt at the designed operating temperature of 150°C.

[0024] FIG. 6 schematically shows a process 600 for bonding chip 401 to substrate 403 according to another exemplary embodiment. At 602, a die 603 of only solder having solder bumps 604, such as SnAg solder, is provided. At 606, a part of each solder bump 604 is transferred to pad 404 of substrate 403 to form bump 408 on pad 404. At 608, the die 603 of only solder is retracted. At 610, a chip 401 with pillars 402 having solder bumps 406 is provided. At 612, the chip 401 is bonded to the substrate 403 by heating in a temperature range of 235°C to 245°C, thereby reflowing the solder bumps 406, 408.

[0025] FIG. 7 schematically shows a process 700 for bonding chip 401 to substrate 403 according to yet another exemplary embodiment. At 702, a chip 401 having solder bumps 703 on pillars 402 is provided. At 706, the solder bumps 703 are transferred from the pillars 402 to the pads 404 of the substrate 403 by reflow, thereby forming bumps 408 on the pads. At 708, the chip 401 is retracted to obtain additional solder. At 710, (additional) solder bumps 406 are provided to the chip 401 on the pillars 402. At 712, the chip 401 is bonded to the substrate 403 by thermocompression bonding of the solder bumps 406, 408 in a temperature range of 235°C to 245°C.

[0026] Considering that the chip bonding processes 500, 600, 700 incorporate a novel structure that overcomes to some extent the long-known problem that warping of the substrate inhibits proper wetting of the solder, other aspects of the present disclosure relate to further improvements enabled by having solder caps on both the pillars and the pads.

[0027] For example, FIG. 8 schematically shows a process 800 for bonding a semiconductor chip 401 to an organic substrate 403 according to an exemplary embodiment.

[0028] At 802, a volatile tackifier (VTA) 410 is dispensed onto a substrate 403. The VTA 410 is disposed at least at the corners of the chip 401 footprint. The VTA generally vaporizes at a temperature exceeding 180°C, for example, 190°C to 250°C, so that after reflow, no volatile tackifier remains. Suitable VTAs include, for example, alcohols such as C-9-11-iso-C-1-rich having a viscosity exceeding 30 kcP (kilo centipoise) at room temperature and a boiling point of about 180 to 250°C. The VTA can be applied on the chip side rather than the substrate side.

[0029] At 812, the chip 401 is bonded to the substrate 403. The bonding can be performed, for example, at a temperature of 235°C to 245°C in a belt furnace reflow that can create a formic acid atmosphere, in a chamber-type formic acid oven, or in a thermocompression bonder (TCB) where chip bonding is performed in a formic acid atmosphere. Alternatively, when using a method different from the formic acid atmosphere (e.g., HCl etching) to reduce the oxide film on the solder and components, the bonding can be achieved by reflow in a belt furnace or a chamber oven at a temperature of 235°C to 245°C under an atmosphere of less than 100 ppm of oxygen. At 812, the solder bumps of the chip pillars fuse with the solder caps of the substrate pads. However, as far as this method is concerned, it is not an absolute requirement that the pads on the laminate side have solder. This method can be applied to chips and substrates of any structure.

[0030] By using the VTA to attach the chip 401 to the substrate 403 immediately before bonding and using a formic acid atmosphere instead of a solder flux, it is more advantageously possible to proceed from bonding (step 812) to underfill (step 814) without an intermediate cooling step to wash away the flux from under the chip. In other embodiments, HCl etching can be used instead of the formic acid atmosphere.

[0031] In one or more embodiments, a no-clean flux can be used prior to bonding. Instead of a formic acid atmosphere, by using a no-clean flux in a belt furnace or the like, it becomes possible to perform underfill without cooling for flux cleaning. Those skilled in the art are familiar with "no-clean" fluxes. A no-clean flux may also be called a flux that does not require cleaning, but it does not mean that the components are completely removed from the laminate surface before and during the bonding process. Depending on the combination with underfill, underfill voids may occur, which can affect reliability tests, and for this reason, those combinations may not be used.

[0032] In 814, the underfill 815 is discharged at about 100°C (without pre-cooling to room temperature after bonding), and the underfill is cured while maintaining the temperature between the bonding temperature and room temperature, for example, 90°C to 150°C.

[0033] FIG. 9 schematically shows a comparison of the processes 100 and 800 of FIGS. 1 and 8. Those skilled in the art will understand that after bonding the chip 401 to the substrate 403, the two processes diverge. In process 100, the package follows from step 110 (bonding) to step 112 (flux cleaning with hot water at 60°C to 80°C) before step 114 (discharge and curing of underfill), while in process 800, the package proceeds directly from step 812 (bonding) to step 814 (underfill) without an intermediate lower-temperature excursion.

[0034] FIG. 10 shows a cross-sectional image of the semiconductor chip 1001 and the substrate 1003 after cooling from step 110 (bonding) of the process 100 shown in FIG. 1. Due to different coefficients of thermal expansion, at room temperature, there is a significant thermal strain between the chip 1001 and the substrate 1003. As a result, the pillar 1002 of the chip 1001 is not aligned with the pad 1004 of the substrate 1003. A person skilled in the art will notice that the rightmost pillar 1006 is aligned between the rightmost pad 1007 and the central pad 1008, which is a typical example of a nearest-neighbor short circuit. When this structure is underfilled, the misalignment is fixed.

[0035] On the other hand, FIG. 11 shows a cross-sectional image of the semiconductor chip 1101 and the substrate 1103 after step 814 (underfill) by the process 800 shown in FIG. 8. A person skilled in the art will notice that since there was only a slight thermal excursion from step 812 (bonding) to step 814 (underfill), the appropriate alignment of the pillar 1102 with respect to the pad 1104 was fixed by the steps of underfill dispensing and curing.

[0036] FIG. 12 schematically shows another process 1200 for bonding a semiconductor chip 401 to an organic substrate 403 according to an exemplary embodiment. At 1201, a template die 503 having solder bumps 504 is immersed in a flux bath 1202 at room temperature. At 1203, the solder is transferred to the substrate 403 by thermocompression bonding. At 1204, the transfer die is pulled from the substrate. At 1205, the solder is reflowed at a temperature higher than the solder solidus temperature. At 1206, the remaining flux is rinsed away at a temperature slightly higher than room temperature (e.g., 80° C. to 100° C.). At 1207, an adhesive material 1208 that can decompose and vaporize immediately below the solder reflow temperature is applied to the substrate at room temperature. At 1209, the chip 401 is bonded to the substrate 403 using a belt furnace in a formic acid atmosphere. At 1210, without intermediate cooling to room temperature, it proceeds directly to the dispensing and curing of underfill 1211 at a temperature suitable for the underfill material, e.g., 80° C. to 120° C. Note in FIG. 12 that in steps 1209 and 1210, micro-bumps are present between elements 401 and 403, and their details are omitted to avoid confusion. Exemplary figures of the micro-bumps and underfill are shown in other drawings.

[0037] FIG. 13 shows another method 1300 for bonding a chip 401 to a substrate 403. Steps 1201, 1203, 1204, 1205, 1206 are the same as the method 1200 described with reference to FIG. 12. However, according to method 1300, after step 1206 (flux rinsing), it proceeds to thermocompression bonding in a formic acid atmosphere at 1309. Then, at 1210, without intermediate cooling to room temperature, it proceeds directly to the dispensing and curing of underfill 1211 at a temperature suitable for the underfill material, e.g., 80° C. to 120° C.

[0038] Figure 14 shows another method 1400 for bonding chip 401 to substrate 403. At 1403, transfer die 503 is thermocompression bonded to substrate 403. At 1204, the transfer die is pulled. At 1405, the solder is reflowed in a formic acid atmosphere. At 1309, chip 401 is thermocompression bonded to substrate 403. Step 1210 is the same as in methods 1200 and 1300, resulting in underfill 1211 between chip 401 and substrate 403.

[0039] Figure 15 shows another method 1500 for bonding chip 401 to substrate 403. Step 1403 (solder transfer by thermocompression bonding) is the same as in method 1400. Step 1204 (chip pulling) is the same as in method 1200. Step 1405 (solder reflow in a formic acid atmosphere) is the same as in method 1400. Steps 1207 (depositing adhesive material 1208), 1209 (belt furnace bonding chip 401 to substrate 403 in a formic acid atmosphere), and 1210 (discharging and curing underfill without intermediate cooling to room temperature) are the same as in method 1200. Note the underfill 1211. In Figure 15, in steps 1209 and 1210, there are micro - bumps between elements 401 and 403, and it should be noted that the details of these are omitted to avoid confusion. Exemplary figures of micro - bumps and underfill are shown in other drawings.

[0040] Based on the foregoing discussion, generally, an exemplary method according to one aspect of the present invention includes bonding a semiconductor chip to an organic laminate substrate using solder at a bonding temperature, discharging an underfill between the semiconductor chip and the organic laminate substrate at an underfill discharge temperature without cooling from the bonding temperature to room temperature, and curing the underfill within a temperature range higher than the underfill discharge temperature.

[0041] In one or more embodiments, the bonding is performed in a belt furnace. One or more embodiments of the method also include discharging at least two spots of a volatile adhesive between the semiconductor chip and the organic laminate substrate prior to bonding. In one or more embodiments, the bonding is performed in a formic acid atmosphere. In one or more embodiments, the vaporization temperature of the volatile adhesive coincides with (is equal to) or is slightly lower (by about 5 to 10 °C) than the solidus temperature of the solder used to bond the semiconductor chip to the organic laminate substrate (i.e., the vaporization temperature of the volatile adhesive is selected to be within a range of 10 °C or less from the temperature that coincides with (is equal to) the solidus temperature of the solder used to bond the semiconductor chip to the organic laminate substrate).

[0042] In one or more embodiments, prior to bonding, the semiconductor chip is subjected to HCl etching, and during bonding, an atmosphere having an oxygen concentration of 100 ppm or less is maintained.

[0043] In one or more embodiments, the bonding is performed using a thermocompression bonding tool. In one or more embodiments, the bonding is performed in a formic acid atmosphere.

[0044] In one or more embodiments, the bonding is performed at 235 °C to 245 °C, the underfill discharge is performed at 80 °C to 120 °C, and the underfill curing is performed at 120 °C to 160 °C.

[0045] According to another aspect, an exemplary method includes depositing a first solder on a pad of an organic laminate substrate, bringing a second solder on a pillar of a semiconductor chip into contact with the first solder on the pad of the organic laminate substrate, and soldering the semiconductor chip to the organic laminate substrate.

[0046] In one or more embodiments, the first solder has a lower melting point than the second solder. In one or more embodiments, the first solder has a melting point of 135 °C (Celsius) to 145 °C.

[0047] In one or more embodiments, the first solder has the same melting point as the second solder.

[0048] In one or more embodiments, an exemplary method includes plating a first solder on a pillar, and depositing the first solder on a pad includes reflowing the first solder from the pillar to the pad.

[0049] In one or more embodiments, an exemplary method includes plating a first solder on a template die, and depositing the first solder on a pad includes reflowing the first solder from the template die to the pad.

[0050] According to another aspect, an exemplary apparatus includes a semiconductor chip 401 having pillars 402 protruding from a lower surface of the semiconductor chip at a pitch of 55 μm (micrometers) or less, with a cap 406 of a first solder attached to a lower end of the pillar; an organic multilayer substrate 403 having pads 404 protruding from an upper surface of the organic multilayer substrate at the same pitch as the semiconductor chip, with a cap 408 of a second solder attached to an upper surface of the pad; and two or more dots of a volatile adhesive 1208 that attaches the upper surface of the organic multilayer substrate to the lower surface of the semiconductor chip.

[0051] In one or more embodiments, the second solder has a lower melting point than the first solder. In one or more embodiments, the second solder has a melting point of 135°C (degrees Celsius) to 145°C.

[0052] In one or more embodiments, the second solder has the same melting point as the first solder. In one or more embodiments, the first and second solders have a solidus temperature of 215°C to 230°C.

[0053] In one or more embodiments, the vaporization temperature of the volatile adhesive is a temperature such that no volatile adhesive remains after soldering the semiconductor chip to the organic multilayer substrate.

[0054] While specific embodiments have been described with respect to bonding a single chip to a substrate, embodiments of the present invention are equally applicable to bonding a chip package to a substrate, and whenever the term "semiconductor chip" is found in the claims, that term is equally applicable to a multi-chip package.

[0055] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments of the present invention. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application to or technical improvement over the technologies found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein.

Description of Reference Numerals

[0056] 100 Process 102 Semiconductor Chip 104 Substrate 108 Flux Bath 116 Underfill 120 Surface 300 Chip Assembly 301 Semiconductor Chip 302 Pillar 303 Organic Substrate 304 Pad 306 Solder Cap 400 Chip Assembly 401 Chip 402 Pillar 403 Substrate 404 Pad 406 Solder Cap 408 Bump 500 Process 503 Die 504 Bump 600 Process 603 Die 604 bump 700 process 703 solder bump 800 process 815 underfill 1001 chip 1002 pillar 1003 substrate 1004 pad 1006 pillar 1007 pad 1008 pad 1101 semiconductor chip 1102 pillar 1103 substrate 1104 pad 1200 process 1202 flux bath 1208 volatile adhesive 1211 underfill Hp height Hs height

Claims

1. A method comprising: at a bonding temperature, bonding a semiconductor chip to an organic multilayer substrate using solder; without cooling from the bonding temperature to room temperature, discharging an underfill between the semiconductor chip and the organic multilayer substrate at a discharging temperature of the underfill; curing the underfill within a temperature range higher than the discharging temperature of the underfill; and further comprising, prior to the bonding, discharging at least two spots of a volatile adhesive between the semiconductor chip and the organic multilayer substrate; wherein the bonding is performed in a formic acid atmosphere.

2. The method according to claim 1, wherein the bonding is performed in a belt furnace.

3. The method according to claim 1, further comprising selecting the vaporization temperature of the volatile adhesive to be within a range of 10 °C or less from a temperature that coincides with the solidus temperature of the solder used for bonding the semiconductor chip to the organic multilayer substrate.

4. The method according to claim 2, further comprising, prior to the bonding, subjecting the semiconductor chip to HCl etching and, during the bonding, maintaining an atmosphere with an oxygen concentration of 100 ppm or less.

5. The method according to claim 1, wherein the bonding is performed using a thermocompression bonding tool.

6. The method according to claim 1, wherein the bonding is performed at 235 °C to 245 °C, the discharging of the underfill is performed at 80 °C to 120 °C, and the curing of the underfill is performed at 120 °C to 160 °C.

7. A method comprising: depositing a first solder on pads of an organic multilayer substrate; bringing a second solder on pillars of a semiconductor chip into contact with the first solder on the pads of the organic multilayer substrate; after bringing the second solder into contact with the first solder, solder-bonding the semiconductor chip to the organic multilayer substrate; and wherein the first solder has a lower melting point than the second solder.

8. The method according to claim 7, wherein the first solder has a melting point of 135 °C to 145 °C.

9. The method according to claim 7, further comprising plating the first solder on the pillars, and depositing the first solder on the pads includes reflowing the first solder from the pillars to the pads.

10. The method according to claim 7, further comprising plating the first solder on a template die, wherein depositing the first solder on the pad includes reflowing the first solder from the template die to the pad.

11. An apparatus comprising a semiconductor chip having pillars protruding from a lower surface of the semiconductor chip at a pitch of 55 μm (micrometers) or less, with caps of a first solder attached to lower ends of the pillars; an organic laminate substrate having pads protruding from an upper surface of the organic laminate substrate at the same pitch as the semiconductor chip, with caps of a second solder attached to upper surfaces of the pads; two or more dots of a volatile adhesive for attaching the upper surface of the organic laminate substrate to the lower surface of the semiconductor chip; and the apparatus, wherein the second solder has a lower melting point than the first solder.

12. The apparatus according to claim 11, wherein the second solder has a melting point of 135°C (degrees Celsius) to 145°C.

13. The apparatus according to claim 11, wherein a vaporization temperature of the volatile adhesive is a temperature at which no residue of the volatile adhesive remains after soldering the semiconductor chip to the organic laminate substrate.

14. An apparatus comprising a semiconductor chip having pillars protruding from a lower surface of the semiconductor chip at a pitch of 55 μm (micrometers) or less; an organic laminate substrate having pads protruding from an upper surface of the organic laminate substrate at the same pitch as the semiconductor chip; a joint comprising a ternary composition that joins each pillar to a corresponding pad, the joint not melting at 150°C; and the apparatus.

15. The apparatus according to claim 14, wherein the ternary composition comprises silver, tin, and bismuth.

16. The apparatus according to claim 15, comprising underfill between the semiconductor chip and the organic laminate substrate.

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