Singulating individual chips from a wafer having small chips and small separation channels

Abstract

An embodiment of the present invention includes a method for singulating IC chips from a wafer. The method can include receiving a wafer having a substrate formed below an active layer. The wafer includes a first IC chip including a first portion of the active layer and a first portion of the substrate. An isolation trench is formed by removing a first segment of the active layer and a first segment of the substrate, both of which underlie a first isolation channel in the wafer, using an etching operation. The isolation trench separates the first portion of the active layer from the remaining portion of the active layer and the first portion of the substrate from the remaining portion of the substrate. The first IC chip is separated from the wafer by removing a first section of the remaining portion of the substrate, both of which underlie the first portion of the substrate.

Description

[Technical field]

[0001] The present invention relates generally to the fabrication and packaging of integrated circuits (ICs) formed on a portion of a semiconductor wafer. More specifically, the present invention relates to a manufacturing system and method for singulating (i.e., removing) individual IC chips (i.e., semiconductor dies) from a wafer, where the IC chips are separated from one another on the semiconductor wafer by relatively small chip separation channel widths (e.g., less than about 20 μm). [Background technology]

[0002] A semiconductor wafer is manufactured in a series of stages, such as a front-end-of-line (FEOL) stage, a middle-of-line (MOL) stage, and a back-end-of-line (BEOL) stage. The process flow for manufacturing modern semiconductor wafers is often identified based on which of the FEOL stage, the MOL stage, or the BEOL stage it corresponds to. Generally, in the FEOL stage, device elements (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate / wafer. The processes of the FEOL stage include wafer preparation, isolation, gate patterning, and the formation of wells, source / drain (S / D) regions, extension junctions, silicide regions, and liners. The processes of the FEOL stage also include forming a plurality of IC chips or semiconductor dies on the surface of the semiconductor wafer. Each IC chip comprises a circuit formed by electrically connecting active components and passive components. The MOL stage typically includes a process flow for forming an interconnect structure (e.g., lines, wires, metal-filled vias, contacts, etc.) that communicatively couples to the active regions (e.g., gates, sources, and drains) of the device elements. During the BEOL stage, layers of interconnect structures are formed on top of these logic and functional layers to complete the semiconductor wafer. Most semiconductor wafers require more than one layer of interconnects to form all the necessary connections, and five to twelve layers of interconnects are added in the BEOL process.

[0003] The BEOL process can include singulating (or removing) each IC chip from a completed semiconductor wafer and packaging one or more of the IC chips to provide structural support and environmental isolation. With the proliferation of small or miniaturized mobile computing systems, the size of each IC chip has been continuously decreasing. However, known methods for singulating IC chips from a completed semiconductor wafer have drawbacks when applied to semiconductor wafers having relatively small IC chips and relatively small chip separation channels. For example, the singulation process known as dicing uses a water-cooled rotating disk to cut open the chip separation channels to singulate each IC chip of the semiconductor wafer. Since dicing involves a rotating disk (e.g., metal, polymer, diamond, etc.), the chip separation channels need to be relatively wide, typically greater than about 50 μm, more typically greater than about 100 μm. Since a significant portion of the semiconductor floorplan has to be allocated to the chip separation channels, the number of IC chips that can be formed on a given semiconductor wafer is reduced. In addition, the rotating disk used in the dicing process results in an increase in the roughness (e.g., generally greater than 10 μm Ra) around the singulated IC chips. Assembly tools that align the singulated IC chips with their host motherboards during packaging use the peripheral edges of the IC chips as reference points for properly aligning the solder posts of the IC chips with the bonding pads of the motherboard. When the peripheral edges of the IC chips are rough, assembly tools that use such peripheral edges of the IC chips as references have difficulty properly aligning such IC chips with their host motherboards.

[0004] Laser ablation singulation processes use a laser to remove material within a chip separation trench, thereby singulating individual IC chips from a semiconductor wafer. Laser ablation provides better width and outer edge roughness of the chip separation trench compared to dicing. However, the laser ablation singulation process has a problem in that molten debris or slag deposits on the surface of the semiconductor wafer, thereby damaging the IC chips to be singulated. In addition, it is very difficult to protect the semiconductor wafer during the laser ablation singulation process because the molten material (e.g., metal, dielectric, etc.) destroys any protective film disposed on the semiconductor wafer.

[0005] A singulation process known as "stealth dicing" uses a laser to create defects in a silicon substrate by scanning a laser beam along an intended cut line. Next, an underlying carrier membrane is expanded to induce fracture and effectively pull the IC chips away from the substrate. A drawback of known stealth dicing techniques is that for IC chip dimensions less than 0.5 mm, a phenomenon known as meanderance occurs, resulting in singulated IC chips having sufficient peripheral edge roughness to interfere with the alignment process of assembly tools. In addition, known stealth dicing techniques lack the reliability and consistency of required performance because the substrate is not reliably and consistently separated, thereby resulting in the IC chips remaining connected to each other and, as a result, further requiring additional processing to achieve singulation. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0006] Embodiments of the present invention are directed to a method of singulating integrated circuit (IC) chips from a host semiconductor wafer. In a non-limiting embodiment of the present invention, the method includes receiving the host semiconductor wafer having a substrate and an active layer formed on the substrate. The host semiconductor wafer further includes a first IC chip including a first portion of the active layer and a first portion of the substrate. A first isolation trench is formed by using an etching operation to remove a first segment of the active layer and a first segment of the substrate that are together under a first isolation channel of the host semiconductor wafer. The first isolation trench separates the first portion of the active layer from the remaining portion of the active layer, and also separates the first portion of the substrate from the remaining portion of the substrate. The first IC chip is singulated from the host semiconductor wafer by using a substrate removal operation to remove a first section of the remaining portion of the substrate that is together under the first portion of the substrate.

[0007] The technical effects and advantages of the above-described embodiments of the present invention include the use of an etching operation for forming the first isolation trench, whereby the first isolation trench is enabled to have a feature resolution range that matches the feature resolution range (i.e., the feature dimension range) of the etching operation. From the perspective of the present invention, the etching operation enables the formation of an isolation trench having a width dimension of less than about 20 microns. In some embodiments of the present invention, the etching operation enables the formation of an isolation trench having a width dimension of from about 10 microns to about 20 microns.

[0008] The above-described embodiment of the present invention can further include a first isolation trench having a first segment and a second segment. The first segment of the first isolation trench separates a first portion of the active layer from the remaining portion of the active layer. The second segment of the first isolation trench separates a first portion of the substrate from the remaining portion of the substrate. The etching operation can include a first etching operation configured to form the first segment of the first isolation trench and a second etching operation configured to form the second segment of the first isolation trench. The active layer can include a front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) layer. The first etching operation can include a sputter etch operation, and the second etching operation can include a directional reactive ion etch (RIE) operation. The substrate removal operation can include polishing a first section of the remaining portion of the substrate that is co-located under the first portion of the substrate.

[0009] Additional technical effects and advantages of the above-described embodiments of the present invention include forming the first segment of the isolation trench using sputter etch operations. The sputter etch operations are configured to remove multiple different types of materials (e.g., metals, dielectrics, doped semiconductors, etc.) in the FEOL layer and the BEOL layer where the active layer can then be formed. The sputter etch operations are also configured to form smooth edges during the removal of multiple different types of materials (e.g., metals, dielectrics, doped semiconductors, etc.) in the FEOL layer and the BEOL layer where the active layer can then be formed. The directional RIE operation is configured to directionally remove semiconductor materials (e.g., silicon) where the substrate can then be formed. The directional RIE operation is also configured to form smooth edges during the removal of semiconductor materials (e.g., silicon) where the substrate can then be formed. The polishing operation used to remove the first section of the remaining portion of the substrate that is together under the first portion of the substrate is configured to form smooth edges during the polishing operation. The smooth peripheral edges formed during the etching operation and the polishing operation improve the functionality of packaging tools that rely on the automatic detection of the peripheral edges of the IC chip to accurately align the IC chip to its support substrate (e.g., motherboard) during packaging. In an embodiment of the present invention, the sputter etch operation, the directional reactive ion etching operation, and the polishing operation result in a singulated IC chip having a very smooth peripheral edge with a roughness level of less than about 4 μm Ra.

[0010] The above-described embodiment of the present invention may further include the host semiconductor wafer further comprising a second IC chip including a second portion of the active layer and a second portion of the substrate. A second isolation trench may be formed by removing the second segment of the active layer and the second segment of the substrate, both of which underlie a second isolation channel in the host semiconductor wafer, in parallel with the above-described removal of the first segment of the active layer and the first segment of the substrate. The second isolation trench separates the second portion of the active layer from the remaining portion of the active layer and the second portion of the substrate from the remaining portion of the substrate. The second IC chip is singulated from the host semiconductor wafer by substrate removal, which removes the second section of the remaining portion of the substrate, both of which underlie the second section of the substrate, in parallel with the above-described removal of the first section of the remaining portion of the substrate, both of which underlie the first portion of the substrate.

[0011] Additional technical effects and advantages of the above-described embodiments of the present invention include the sputter etching operation being applied in parallel to all of the IC chips on the host semiconductor wafer, the directional RIE operation being applied in parallel to all of the IC chips on the host semiconductor wafer, and the substrate polishing operation being applied across all of the IC chips on the host semiconductor wafer. Applying etching and polishing operations in parallel to all of the IC chips on the host semiconductor wafer improves efficiency and reduces costs compared to known singulation operations that are applied in series to each IC chip on the host semiconductor wafer.

[0012] The above-described embodiments of the present invention may further include forming a photoresist layer on the host semiconductor wafer, wherein the photoresist layer defines the first and second separation channels of the host semiconductor wafer. In some embodiments of the present invention, the photoresist layer may have a predetermined thickness. In some embodiments of the present invention, a curing process may be applied to the photoresist layer.

[0013] The additional technical effects and advantages of the above-described embodiments of the present invention are to improve the resistance of the photoresist layer to damage caused by the etching operations (e.g., sputter etching and directional RIE) used to remove the first segment of the active layer where the curing process and the predetermined thickness are below the first isolation channel of the host semiconductor wafer.

[0014] Embodiments of the present invention are also directed to a manufacturing system configured to implement the above-described manufacturing method and to provide the above-described technical effects and advantages.

[0015] Additional features and advantages are realized through the technology described herein. Other embodiments and aspects are described in detail herein. For a better understanding, refer to this specification and the drawings.

[0016] The subject matter regarded as the present invention is particularly pointed out and distinctly claimed in the claims appended hereto. The foregoing and other features and advantages will be apparent from the following detailed description of the invention taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3A-1

Figure 3A-2

Figure 3B-1

Figure 3B-2

Figure 4A-1

Figure 4A-2

Figure 4B-1

Figure 4B-2

Figure 5-1

Figure 5-2

Figure 6

Figure 7

Figure 8

Figure 9

[0018] In the accompanying drawings and the following detailed description of the disclosed embodiments, various elements shown in the drawings are assigned three- or four-digit reference numbers.

DETAILED DESCRIPTION OF THE INVENTION

[0019] For the sake of brevity, conventional techniques related to the manufacture and use of aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing the various technical features described herein are well known. Accordingly, for the sake of brevity, many details of conventional implementations will only be briefly mentioned herein or will be completely omitted without providing details of well-known systems or processes or combinations thereof.

[0020] The terms "separation channel", "chip separation channel", "chip separation channel pattern", "dicing channel", and their equivalents are used herein to define a two-dimensional (2D) area on the surface of a semiconductor wafer that defines a top-down two-dimensional (2D) area of a three-dimensional (3D) "separation channel", "chip separation channel", or "chip separation channel pattern", or a combination thereof, formed in the semiconductor wafer to separate IC chips formed on the semiconductor wafer from each other.

[0021] The terms "separation trench", "chip separation trench", "chip separation trench pattern", and their equivalents are used herein to define a three-dimensional trench formed in a semiconductor wafer to separate IC chips formed on the semiconductor wafer from each other.

[0022] The terms "lithography", "photolithography", and their equivalents are used herein to identify a process of transferring a pattern of the geometry of a mask onto a layer of photosensitive material (referred to as a resist or photoresist) covering the surface of a semiconductor wafer. Radiation is transmitted through the transparent portions of the mask and renders the exposed photoresist soluble or insoluble in a developer, thereby enabling the direct transfer of the mask pattern onto the wafer. After the pattern is defined, an etching process is used to selectively remove the masked portions of the underlying layer.

[0023] The terms "resolution", "mask resolution", "pattern resolution", "feature resolution", and their equivalents are used herein to identify one or more minimum feature dimensions that can be transferred with high fidelity onto a photoresist film on a semiconductor wafer in the form of a photoresist film pattern (or opening).

[0024] Turning now to an overview of aspects of the invention, embodiments of the invention provide manufacturing systems and methods for singulating (i.e., removing) individual IC chips (or semiconductor dies) from their host semiconductor wafer, where the host semiconductor wafer comprises various BEOL and FEOL layers on a wafer substrate (e.g., silicon). In some embodiments of the invention, the BEOL layers can include far-BEOL layers, and the FEOL layers can include MOL layers. The IC chips are separated from one another on the host semiconductor wafer by chip separation channels. The separation channels define the footprints of isolation trenches to be formed, having relatively small width dimensions (e.g., less than about 20 μm). Instead of relying on known dicing, stealth dicing, or laser ablation singulation techniques, or a combination thereof, embodiments of the invention utilize a novel arrangement of etching and polishing operations to singulate the IC chips from their host semiconductor wafer. In accordance with an aspect of the present invention, the IC chips are isolated from one another by defining chip isolation channels on the surface of a host semiconductor wafer and then etching through the isolation channels and various Far-BEOL, BEOL, MOL, or FEOL layers, or combinations thereof, on the semiconductor wafer to form initial isolation trenches that stop on the host semiconductor wafer substrate.

[0025] At this stage of the novel singulation process, the initial separation trenches separate each IC chip from each other at the Far-BEOL level, BEOL level, MOL level, or FEOL level or a combination thereof, while the Far-BEOL level, BEOL level, MOL level, or FEOL level or a combination thereof of each IC chip still adheres at separate locations on the underlying substrate of the host semiconductor wafer. According to an aspect of the present invention, the bottom surface of each initial separation trench is an exposed portion of the underlying substrate. The initial separation trench is extended a predetermined distance into the substrate by applying directional etching to the exposed portion of the underlying substrate within the initial separation trench, thereby forming extension separation trenches. The extension separation trenches define each chip substrate of each IC chip, where each chip substrate has one end connected to one of the Far-BEOL level, BEOL level, MOL level, or FEOL level or a combination thereof of the IC chip, and the other end connected to the bottom section of the underlying semiconductor wafer substrate remaining after the extension separation trenches are formed. To release each IC chip (including the IC chip substrate) from the remaining bottom section of the semiconductor wafer substrate, the remaining bottom section of the wafer substrate is removed to open the bottom end of the extension separation trench, thereby releasing each IC chip (including the IC chip substrate) from the remaining bottom section of the wafer substrate. In an embodiment of the present invention, at least a later stage of the process used to remove the remaining bottom section of the wafer substrate is a fine polishing process.

[0026] In embodiments of the present invention, the initial etching operation used to form the initial isolation trench is configured and arranged to etch through various materials (e.g., metals, dielectrics, doped semiconductor materials, etc.) where the Far-BEOL layer, BEOL layer, MOL layer, or FEOL layer or combinations thereof are formed. In some embodiments of the present invention, the initial etching operation is a sputter etching operation. In some embodiments of the present invention, the sputter etching operation uses argon as the bombardment ions. In some embodiments of the present invention, the directional etching operation used to form the extended isolation trench is a directional reactive ion etching (RIE). In some embodiments of the present invention, the directional RIE operation used to form the extended isolation trench is a so-called "Bosch" directional RIE operation. In embodiments of the present invention, the Bosch directional RIE process is a high aspect ratio plasma etching process that uses rapid gas switching between cycles of isotropic etching and fluorocarbon-based protective film deposition. The SF6 plasma cycle etches the substrate material (e.g., silicon), and the C4F8 plasma cycle forms the protective layer. In embodiments of the present invention, the SF6 plasma cycle and the C4F8 plasma cycle are optimized to achieve deep silicon etching with a high aspect ratio.

[0027] The use of patterned lithography operations and etching operations to form isolation trenches enables the isolation trenches to have a shape and feature resolution ranges (i.e., feature dimension ranges) that match the shape and feature resolution ranges of the patterned lithography operations and etching operations. According to aspects of the present invention, the patterned lithography operations and etching operations enable the formation of isolation trenches having a width dimension of less than about 20 microns. In some embodiments of the present invention, the patterned lithography operations and etching operations enable the formation of isolation trenches having a width dimension of from about 10 microns to about 20 microns. In embodiments of the present invention, the patterned lithography operations and etching operations enable the formation of isolation trenches having a wide variety of shapes, including but not limited to circular, square, rectangular, hexagonal, octagonal, serpentine, and combinations thereof.

[0028] The sputter etching process, the directional RIE process, and the polishing process used in the disclosed novel singulation process result in singulated IC chips (including the IC chip substrate) having a very smooth peripheral edge with a roughness level of less than about 4 μm Ra. The smooth peripheral edge formed in accordance with aspects of the present invention improves the function of packaging tools that rely on the automatic detection of the peripheral edge of the IC chip to accurately align the IC chip with its support substrate (e.g., motherboard) during packaging. The sputter etching process, the directional RIE process, and the polishing process used in the disclosed novel singulation process also do not generate debris (e.g., molten debris or slag) that deposits on the surface of the semiconductor wafer, thereby not damaging the IC chips to be singulated.

[0029] Turning now to a more detailed description of aspects of the present invention, FIG. 1 illustrates a flow diagram showing a chip singulation method 100 in accordance with an embodiment of the present invention. Method 100 can be implemented using semiconductor manufacturing systems of various known types and configurations. An exemplary semiconductor manufacturing system 900 capable of implementing aspects of the present invention is depicted in FIG. 9 and is further described in greater detail hereinafter. For the sake of brevity, conventional manufacturing systems or apparatus associated with the implementation of aspects of the present invention may or may not be described in detail herein. In particular, various aspects of the manufacturing system used to implement the various technical features described herein are well known. Accordingly, for the sake of brevity, many conventional details of such manufacturing systems / apparatus are only briefly mentioned herein or are omitted entirely without providing details of well-known systems / apparatus.

[0030] According to an embodiment of the present invention, method 100 includes, at block 102, accessing a wafer having an IC chip formed thereon. At block 104, a lithography process is used to apply a layer of a photosensitive material known as a photoresist onto the wafer. A laser light source is projected onto the photoresist to create a pattern (or, an opening) that defines the position, size, and shape of the separation channel, where the separation channel defines the position, size, and shape of a separation trench that will be formed under the separation channel. Since the light source can directly define a pattern on the photoresist that is as small as the wavelength of the light, a very small pattern resolution can be achieved in the lithography operation performed at block 104 by exposing the photoresist to light having a relatively small wavelength. In some embodiments of the present invention, the lithography performed at block 104 can be extreme ultraviolet (EUV) lithography, which uses a light source having an EUV wavelength (e.g., a wavelength of about 13.5 nanometers) to define the photoresist pattern. According to an aspect of the present invention, the photoresist pattern applied at block 104 and the etching operations applied at blocks 106 and 108 enable the formation of separation channels / trenches having a width dimension of less than about 20 microns. In some embodiments of the present invention, the photoresist pattern applied at block 104 and the etching operations applied at blocks 106 and 108 enable the formation of separation channels / trenches having a width dimension of from about 10 microns to about 20 microns. In some embodiments of the present invention, the photoresist pattern applied at block 104 and the etching operations applied at blocks 106 and 108 enable the formation of separation trenches having a wide variety of shapes, including, but not limited to, circular, square, rectangular, hexagonal, serpentine, and combinations thereof.

[0031] In some embodiments of the present invention, the method 100 uses two etching operations performed at blocks 106 and 108 to form isolation trenches. The first etching operation performed at block 106 is a sputter etching operation. The sputter etching at block 106 forms a first segment of the isolation trench, where the first segment of each isolation trench separates a portion of the FEOL and BEOL layers of the wafer that is part of a given IC chip from the FEOL and BEOL layers that are not part of the given IC chip. The sputter etching is a directional etching configured (e.g., through the selection of impact ions) to effectively etch a plurality of different types of materials (e.g., metals, dielectrics, doped semiconductors, etc.) in the FEOL and BEOL layers of the wafer. According to an aspect of the present invention, the sputter etching also results in a smooth surface and smooth peripheral edges within the first segment of the isolation trench.

[0032] At this stage of method 100, according to an aspect of the present invention, the bottom surface of the first segment of each chip isolation trench is an exposed portion of the underlying substrate. The second etching operation performed at block 108 is a directional reactive ion etching (RIE) operation that forms a second segment of the isolation trench by etching directionally through the exposed portion of the wafer substrate that forms the bottom surface of the isolation trench. Thus, the directional RIE partially segments sections of the wafer substrate such that the segmented wafer substrates function as respective IC chip substrates. The directional RIE operation is also configured to form smooth edges while removing the substrate material (e.g., silicon) underlying the first segment of the isolation trench. After forming the first and second segments of the isolation trench using the etching operations at blocks 106 and 108, all of the surfaces that form each IC chip are separated from the remaining portion of the wafer, except that the bottom of each IC chip substrate is still connected to the remaining portion of the underlying wafer substrate.

[0033] At this stage of method 100, each IC chip substrate is connected at one end to one of the IC chips and at the opposite end to the remainder of the base wafer substrate. A mechanical polishing operation, indicated at block 110, is performed to release each IC chip and its IC chip substrate from the remainder of the base wafer substrate. The mechanical polishing operation at block 110 removes the remainder of the base wafer substrate to open the bottom ends of the extended chip isolation trenches, thereby producing the singulated IC chips at block 112, each with its own FEOL / BEOL layers and substrate. In an embodiment of the invention, at least the latter stage of mechanical polishing performed at block 110 includes a fine polishing process, thereby resulting in the singulated IC chips having IC chip substrates with very smooth peripheral edges. In an embodiment of the invention, the IC chip substrate peripheral edges resulting from the mechanical polishing operation at block 110 each have a roughness level of less than about 4 μm Ra.

[0034] Additional details of how the operations of method 100 can be implemented in accordance with aspects of the present invention are illustrated in FIGS. 2-7 and are further described in more detail hereinbelow. Turning first to FIG. 2, a simplified top-down view of wafer 200 is shown after a photoresist layer 230 has been deposited on the upper major surface of the wafer 200 and patterned to create a photoresist pattern 230A. The photoresist pattern 230A defines a plurality of chip separation channels 220 on the major surface of the wafer 200. The plurality of chip separation channels 220 define the footprint of chip separation trenches 220A and 220A' (shown in FIGS. 3A, 3B, 4A, 4B) that would be formed by etching through the exposed portions of the wafer 200 defined by the plurality of chip separation channels 220. In the top-down view shown in FIG. 2, the plurality of chip separation channels 220 surround various IC chips 212A, 214, 212B, 212C disposed beneath the photoresist layer 230. In an embodiment of the present invention, the IC chips shown in FIG. 2 comprise a processor IC chip 212A combined with a memory IC chip 214; a processor IC chip 212B; and a processor IC chip 212C. For ease of illustration, three IC chips (212A combined with 214; 212B; and 212C) are shown, but any number of IC chips can be provided. Further, the shape and contour of the photoresist pattern 230A in the top-down view can be any shape or contour or combination thereof that can be formed in the photoresist layer, such as, but not limited to, square, rectangular, circular, oval, octagonal, hexagonal, triangular, straight line, elliptical, and combinations thereof.

[0035] In an embodiment of the present invention, the photoresist layer 230 can be a positive photoresist or a negative photoresist or a combination thereof. In a positive photoresist, UV light strikes the material strategically in the areas the semiconductor provider intends to remove. When the photoresist is exposed to UV light, its chemical structure changes and it becomes more soluble in the photoresist developer. Next, the exposed areas are rinsed away with a solvent of the photoresist developer, leaving the underlying material. Areas of the photoresist not exposed to UV light remain insoluble in the photoresist developer, meaning that after exposure, the same copy of the pattern remains on the wafer as a mask. In a negative photoresist, exposure to UV light causes the chemical structure of the photoresist to polymerize, which is the opposite of how a positive photoresist reacts to UV light. Instead of becoming more soluble, the negative photoresist becomes very insoluble. As a result, the UV-exposed negative photoresist remains on the surface while the photoresist developer removes the unexposed areas. This leaves a mask consisting of the original inverse pattern, which is thereby applied onto the wafer. In an embodiment of the present invention described herein, the photoresist layer 230 can be a negative photoresist and thereby can have an inherent advantage for patterning narrow trench shapes.

[0036] In an embodiment of the present invention, the photoresist layer 230 is made robust enough to withstand the sputter etching process and the directional RIE process executed in blocks 106 and 108. From the perspective of the present invention, the photoresist layer 230 is made robust by providing the photoresist layer 230 with a sufficient thickness D1 (shown in FIG. 3A) and curing to withstand the sputter etching process and the directional RIE process executed in blocks 106 and 108. Accordingly, the photoresist layer 230 is provided with a predetermined thickness D1 (shown in FIG. 3A), and can be cured using an appropriate photoresist curing process, including but not limited to, an appropriate photoresist curing process such as exposing the photoresist layer 230 to ultraviolet (UV) light and subsequent baking. In an embodiment of the present invention, the photoresist layer 230 can be formed by spinning on a hexamethyldisilazane (HMDS) adhesion promoter and then hot plate baking; after spinning, spinning on a negative photoresist (for example, a negative photoresist commercially available from JSR) until the thickness of D1 (shown in FIG. 3A) reaches about 50 μm and oven baking; exposing (for example, using a MA-8 contact aligner from SUS MicroTec) and developing the photoresist 230; and post-exposure UV curing and oven baking to solidify the photoresist layer 230. The resulting photoresist pattern 230A of the photoresist layer 230 can define a separation channel 220 having a width of about 20 μm or less.

[0037] FIG. 3A illustrates a top-down view and a cross-sectional view of a semiconductor wafer 200 after applying an example of a sputter etching operation performed at block 106 of method 100, according to an embodiment of the present invention. The top-down view of wafer 200 shown in FIG. 3A is substantially the same as the top-down view of wafer 200 shown in FIG. 2, except that an example sputter etching operation has been applied to wafer 200 to etch through isolation channels 220 (shown in FIG. 2) to form chip separation trenches 220A and 220B. For ease of illustration, the cross-sectional view of semiconductor wafer 200 shown in FIG. 3A is drawn along line A-A of the top-down view shown in FIG. 3A to separate IC chip 212A. However, it is understood that the manufacturing operations shown at cross-sectional view line A-A in the drawing are equally applicable to all of the IC chips (e.g., 214, 212B, 212C) formed in / on wafer 200. As shown in the cross-sectional view of FIG. 3A, wafer 200 includes a wafer substrate 302; FEOL structures and layers 304; MOL structures and layers 306; BEOL structures and layers 308; and Far-BEOL structures and layers 310, which are configured and arranged as shown. Generally, the FEOL structures and layers 304 are device elements (e.g., transistors, capacitors, resistors, etc.) patterned in semiconductor substrate 302. The processes used to form the FEOL structures and layers 304 include wafer preparation; isolation; gate patterning; well formation; source / drain (S / D) region formation; extension junction formation; silicide region formation; and liner formation. The FEOL structures and layers 304 form the main functional circuits of IC chip 212A. The process flow used to form the MOL structures and layers 306 can include forming interconnect structures (e.g., lines, wires, metal-filled vias, contacts, etc.) communicatively connected to the active regions (e.g., gates, sources, and drains) of the device elements. The processes used to form the BEOL structures and layers 308 include forming layers of interconnect structures over the logic and functional layers.To support increased component density, a hierarchical wiring method can be applied in which multiple levels of interconnect wiring are fabricated for each level. In this situation, the BEOL structure and layer 308 can comprise multiple wiring levels for providing interconnections for the MOL structure and layer 306, and a series of Far-BEOL (Far-Back End of Line) structures and layer 310 can be provided that comprise a metal layer (e.g., under-bump-metal or redistribution layer), and an associated interconnect structure for forming connections between on-chip wiring connections and off-chip wiring connections. The photoresist layer 230 is formed over the Far-BEOL structure and layer 310 and is hardened using a suitable photoresist hardening process, including but not limited to suitable photoresist hardening processes that utilize a photoresist hardening process such as exposure of the photoresist layer 230 to ultraviolet (UV) light and subsequent baking. In the context of the present invention, the photoresist layer 230 is fortified by a sufficient thickness D1 to withstand the sputter etching and directional RIE processes executed at blocks 106 and 108 and by imparting hardening to the photoresist layer 230.

[0038] The cross-sectional view shown in FIG. 3A illustrates a cross-section of a plurality of chip separation trenches 220A resulting from the application of the sputter etching process 106 of method 100. As shown, the sputter etching process of block 106 was used to form the chip separation trenches 220A through various materials (e.g., metals, dielectrics, doped semiconductor materials, etc.) where the structures / layers 304, 306, 308, 310 of the Far-BEOL structure, BEOL structure, MOL structure, or FEOL structure or combinations thereof are formed. The sputter etching process of block 106 is continued until the surface of the wafer substrate 302 is exposed at the bottom of the chip separation trenches 220A. Prior to the directional reactive ion etching executed at block 108, a small amount of the wafer substrate 302 is also expected to be removed by the sputter etching process of block 106.

[0039] 3B illustrates a cross-sectional view of the semiconductor wafer 200 shown in FIG. 3A along with a diagram illustrating a sputter etching process 302A that can be used to form the chip isolation trenches 220A and 220B (shown in FIGS. 2 and 3A). In accordance with an aspect of the present invention, the sputter etching process 302A is a non-limiting example of how the sputter etching operation performed in block 106 of the method 100 can be performed. As shown in FIG. 3B, the sputter etching process 302A can be performed in a vacuum chamber 304. Within the chamber 304, a cathode electrode 306 is separated from a grounded anode electrode 308, and the wafer 200 having the photoresist layer 230 formed thereon is secured to the cathode electrode 306.

[0040] Under the influence of the pumping action, a path is provided for the plasma gas to enter and exit the vacuum chamber 304. The plasma gas carries high-energy or ionized particles (e.g., argon). By applying a voltage to the cathode electrode 306 where the wafer 200 is fixed, an electric field is formed within the chamber 304. The ionized particles in the plasma gas will move at a very high speed under the influence of the electric field. More specifically, the ions in the plasma gas are attracted towards the cathode electrode 306 and are thus attracted onto the exposed surface of the photoresist layer 230 and the surface of the wafer 200 exposed or opened by the chip separation channel 220A. The ionized particles are attracted towards the cathode electrode 306 with an energy (in electron volts) similar to the applied voltage. According to an embodiment of the present invention, the voltage applied to the cathode electrode 306 is high enough to provide sufficient kinetic energy to the accelerated ionized particles to expel atoms and sputter the material of the exposed portion of the wafer 200. In an embodiment of the present invention, the ionized particles are argon ions (argon ions have the technical advantages of being chemically inert, being easily ionized, and being relatively inexpensive), and various materials, specifically, heavy ions effective for separating various materials including the Far-BEOL structure, BEOL structure, MOL structure, and FEOL structure, as well as the various materials (e.g., metals, dielectrics, doped semiconductors, etc.) in which the layers 304, 306, 308, 310 are formed. The sputter etching process 302A is particularly beneficial in that many of the materials used in the Far-BEOL structure, BEOL structure, MOL structure, and FEOL structure, as well as the layers 304, 306, 308, 310 (e.g., wiring of cobalt or copper or combinations thereof) are resistant to chemical etching.As already described herein, the photoresist layer 230 is sufficiently hardened by giving it a sufficient thickness D1 and curing (e.g., UV curing following baking) so as to remain intact during the etching of the Far - BEOL structure, BEOL structure, MOL structure, and FEOL structure by the sputter - etching process 302A, and the etching of layers 304, 306, 308, 310. By using very small ionized atoms as the bombardment agent of the sputter - etching process 302A, the process 302A is very effective for etching a photoresist etching pattern 230A (shown in FIG. 3A) with very fine resolution and for forming a very smooth surface and surrounding edges of the channel - isolation trench 220A. The material or debris removed by the ionized particles is discharged from the wafer 200 (which is fixed to the cathode electrode 306) and accumulates on the grounded anode electrode 308 or is removed from the outlet of the chamber 304 by the gas - pumping action of the chamber.

[0041] FIG. 4A illustrates a top - down view and a cross - sectional view of a semiconductor wafer 200 after applying an example of a directional RIE operation executed at block 108 of method 100 according to an embodiment of the present invention. The top - down view of the wafer 200 shown in FIG. 4A is substantially the same as the top - down view of the wafer 200 shown in FIG. 3A, except that the directional RIE operation at block 108 of method 100 is used to etch through the exposed surface of the wafer substrate 302 located at the bottom of the chip - separation trenches 220A and 220B (shown in FIG. 3A) to form the chip - separation trenches 220A' and 220B'.

[0042] The cross-sectional view of the semiconductor wafer 200 shown in FIG. 4A is drawn along the line A-A of the top-down view shown in FIG. 4A. The cross-sectional view shown in FIG. 4A illustrates a cross-sectional view of the chip separation trench 220A' resulting from the application of the directional RIE operation 108 of method 100. As shown, the directional RIE operation of block 108 of method 100 forms the chip separation trench 220A' to extend into the wafer substrate 302, thereby being used to form the sidewalls and some of the surrounding edges of the IC chip substrate 302A of the IC chip 212A. At the manufacturing stage illustrated in the cross-sectional view of FIG. 4A, the IC chip 212A is separated from all sides of the wafer 200 but remains connected to the wafer 200 at the interface between the IC chip substrate 302A and the wafer substrate 302. The directional RIE operation performed in block 108 of method 100 is continued until the desired height dimension (D2) of the IC chip substrate 302A is achieved. The operation performed in block 108 has the additional advantage of forming a very smooth surface and surrounding edges of the portion of the channel separation trench 220A' that extends into the wafer substrate 302.

[0043] FIG. 4B illustrates a cross-sectional view of the semiconductor wafer 200 shown in FIG. 4A, along with a diagrammatic illustration of the so-called Bosch deep RIE process 402A, which is a non-limiting example of how the directional RIE operation performed in block 108 of method 100 can be implemented. The Bosch deep RIE process 402A is well-suited for embodiments of the present invention when the wafer substrate 302 is silicon, as it is efficient for etching high aspect ratio trench-type structures in silicon. Generally, process 402A includes periodic isotropic silicon etching and a fluorocarbon-based protective film. The plasma etching gas for silicon is typically SF6, and the plasma etching gas for the protective layer is typically C4F8. Due to the directionality of the silicon etching, the protective layer is removed only from the bottom of the feature, while the sidewalls remain protected. The Bosch deep RIE process 402A is illustrated in FIG. 4B as six diagrams showing exemplary operations of process 402A applied to a silicon substrate, where the operations include exposing and curing a resist on the silicon substrate, performing a first etching step, performing a first deposition of a protective fluorocarbon layer, performing a first removal of the bottom portion of the protective fluorocarbon layer deposition, completing a second cycle of steps 2 - 4, and completing a third cycle of steps 2 - 4. In embodiments of the present invention, the surface and the peripheral edges of the resulting IC chip substrate 302A from process 402A each include a roughness level of less than about 4 μm Ra.

[0044] FIG. 5 shows a bottom-up view and a cross-sectional view of a semiconductor wafer 200 after applying an example of a mechanical polishing operation performed at block 110 of method 100 according to an embodiment of the present invention. The bottom-up view of wafer 200 shows chip separation trenches 220A', chip separation trenches 220B', IC processor chip substrates 302A, IC memory chip substrates 302A', IC processor chip substrates 302B, and IC processor chip substrates 302C. The bottom-up view of wafer 200 shown in FIG. 5 is substantially the same as the top-down view of wafer 200 shown in FIG. 4A, except that the mechanical polishing operation at block 110 of method 100 is used to remove the bottom of wafer substrate 302, thereby separating the bottom ends of IC chip substrates 302A, 302A', 302B, 302C from wafer substrate 302 and singulating or removing IC chips 212A, 214, 212B, 212C from wafer 200. Similarly, the cross-sectional view of wafer 200 shown in FIG. 5 is substantially the same as the cross-sectional view of wafer 200 shown in FIG. 4B, except that the mechanical polishing operation at block 110 of method 100 is used to remove the bottom of wafer substrate 302, thereby separating the bottom end of IC chip substrate 302A from wafer substrate 302 and singulating or removing IC chip 212A from wafer 200.

[0045] In an embodiment of the present invention, the mechanical polishing operation used in block 110 of method 100 to remove the bottom end of the wafer substrate 302 can be performed using a polishing pad and slurry. In some embodiments of the present invention, wax is applied to the front surface of the wafer 200, and the front surface of the wafer 200 is attached to the holder through the wax. The polishing pad and a coarse slurry or grit can be used to uniformly erode the bottom end of the wafer substrate 302 until the bottom end of the wafer substrate 302 is within a predetermined distance from the bottom of the channel isolation trench 220A'. The polishing pad is switched to a finer slurry / grit, and the remaining portion of the bottom end of the wafer substrate 302 is removed until the bottom of the channel isolation trench 220A' is visible. According to an embodiment of the present invention, the finer slurry / grit is configured to provide a smooth peripheral edge to the bottom surface of the wafer substrate 302A. In an embodiment of the present invention, the surface and the peripheral edge of the bottom surface of the resulting IC chip substrate 302A by using fine grit / slurry can each include a roughness level of less than about 4 μm Ra.

[0046] FIG. 6 illustrates a bottom-up view and a cross-sectional view of a semiconductor wafer 200 after the mechanical polishing operation 110 has singulated (or removed) the IC chips 212A, 214, 212B, 212C from the wafer 200, thereby leaving a wafer substrate opening 602 within the wafer 200, and configured and arranged as shown. The remaining wafer 200 after singulation shown in FIG. 6 includes an inert Far-BEOL structure, a BEOL structure, a MOL structure, a FEOL structure, and regions of layers 304, 306, 308, 310 formed on the polished segment of the wafer substrate 302.

[0047] FIG. 7 illustrates a top-down view of the simulated IC chips 702 (formed from a combination of IC chip 212A and IC chip 214), 212B, and 212C generated at block 112 of method 100. In some non-limiting embodiments of the present invention, method 100 can be used to manufacture an irregularly shaped IC chip 702 having a width dimension of about 0.45 mm, along with two processor IC chips 212B and 212C each having a top surface area of about 0.45 mm × about 0.35 mm. The dimensions of the chips are exemplary and do not limit the scope of the embodiments of the present invention described herein. FIG. 8 illustrates a top-down view of the simulated IC chips 702, 212B, and 212C after an alignment tool has utilized the smooth peripheral edges of the simulated IC chips 702, 212B, and 212C to achieve proper alignment of the solder posts (not shown separately) on the IC chips 702, 212B, and 212C with the pads on the motherboard 802 as part of the final packaging operation. In an embodiment of the present invention, the surfaces and peripheral edges of the IC chips 702, 212B, and 212C resulting from method 100 in accordance with the aspects of the present invention can each include a roughness level of less than about 4 μm Ra.

[0048] The polishing operation used to remove the first section of the remaining portion under the first portion of the substrate is configured to form a smooth edge during the polishing operation. The smooth peripheral edge formed during the etching and polishing operations improves the function of the packaging tool that relies on the automatic detection of the peripheral edge of the IC chip to accurately align the IC chip to its support substrate (e.g., motherboard) during packaging. In an embodiment of the present invention, the sputter etching operation, the directional etching operation, and the polishing operation result in a singulated IC chip having a very smooth peripheral edge with a roughness level of less than about 4 μm Ra. The sputter etching is used to form a first segment of the isolation trench, where the first segment of the isolation trench separates the FEOL layer and the BEOL layer, which are part of the active region of the IC chip, from the FEOL layer and the BEOL layer that are not part of the active region of the IC chip. The sputter etching is a directional etching (e.g., through the selection of impact ions) configured to effectively etch a plurality of different types of materials (e.g., metals, dielectrics, doped semiconductors, etc.) in the FEOL and BEOL layers. The sputter etching also results in a smooth surface and a smooth peripheral edge within the first segment of the isolation trench.

[0049] FIG. 9 illustrates a block diagram showing a semiconductor manufacturing system 900 that aids a semiconductor manufacturing process capable of incorporating aspects of the present invention. The semiconductor manufacturing system 900 includes an IC design support algorithm 902, a mask design support algorithm 904, manufacturing support equipment 906, assembly support equipment 908, and test support equipment 910, configured and arranged as shown. The IC design support algorithm 902 is configured and arranged to provide computer-aided-design (CAD) assistance for the design of logic circuits (AND gates, OR gates, and NOR gates) that form various logic components of an IC. Similarly, the mask design support algorithm 904 is configured and arranged to provide CAD assistance for generating a mask design that represents an IC in terms of planar geometric shapes corresponding to patterns of metal, oxide, or semiconductor layers that make up the components of the IC. The mask design arranges and connects all the components that make up the IC to meet certain criteria, such as performance, size, density, and manufacturability. The manufacturing support equipment 906 is equipment used when performing FEOL processes, MOL processes, BEOL processes, and Far-BEOL processes (including simulation processes) used to form completed wafers and IC chips (or semiconductor dies). Generally, there are various forms of wafer manufacturing support equipment 906, many of which are specialized in growing, depositing, or removing materials from wafers. Examples of wafer manufacturing support equipment 906 include oxidation systems, epitaxial reactors, diffusion systems, ion implantation devices, physical vapor deposition systems, chemical vapor deposition systems, photolithography devices, etching devices, polishing devices, and the like. Various types of manufacturing equipment 902 alternately deposit and remove different materials on and from the wafer 912 (e.g., using chemical 914) in a specific pattern until the circuit is fully constructed on the wafer 912. The assembly support equipment 908 is used to package the IC chip into a completed IC package that is physically ready for use in a customer's application.The assembly support equipment 908 can include wafer back-grind systems, wafer saw equipment, die attach machines, wire bonders, die overcoat systems, molding equipment, hermetic sealing equipment, metal can welding machines, de-flash, trim, form, and singulation (DTFS) machines, branding equipment, and lead finishing equipment. Major components used by the machines include, but are not limited to, lead frames 916 and substrates 918. The test support equipment 910 is used to test IC packages to ensure that only known good devices are shipped to customers. The test support equipment 910 can include automatic test equipment (ATE), test handlers, tape and reel equipment, marking equipment, burn-in ovens, retention bake ovens, UV erase equipment, and vacuum sealers.

[0050] Thus, from the foregoing detailed description, it can be seen that embodiments of the present invention provide technical effects and advantages. For example, technical effects and advantages of embodiments of the present invention described herein include the use of patterned lithography and etching operations to form an isolation trench, thereby enabling the first isolation trench to have a shape and feature resolution range (i.e., feature dimension range) that matches the shape and feature resolution range of the etching operation. In accordance with aspects of the present invention, the patterned lithography and etching operations enable the formation of isolation trenches having width dimensions of less than about 20 microns. In some embodiments of the present invention, the patterned lithography and etching operations enable the formation of isolation trenches having width dimensions of about 10 microns to about 20 microns. In embodiments of the present invention, the patterned lithography and etching operations enable the formation of isolation trenches having a wide variety of shapes, including, but not limited to, circular, square, rectangular, hexagonal, octagonal, serpentine, and combinations thereof.

[0051] Additional technical effects and advantages of the embodiments of the present invention described herein include the use of a sputter etching operation and a directional RIE operation to form isolation trenches. The sputter etching operation is configured to remove multiple different types of materials (e.g., metals, dielectrics, doped semiconductors, etc.) from which the FEOL and BEOL layers of the wafer can be formed. The sputter etching operation is also configured to form smooth edges while removing multiple different kinds of materials (e.g., metals, dielectrics, doped semiconductors, etc.) from which the FEOL and BEOL layers of the wafer can be formed. The directional RIE operation is configured to directionally remove selected segments of semiconductor material (e.g., silicon) from which the substrate can be formed. The directional RIE operation is also configured to form smooth edges while removing the semiconductor material (e.g., silicon) from which the substrate can be formed. The polishing operation used to remove selected portions of the substrate as a final singulation operation is configured to form smooth edges during the polishing operation. The smooth peripheral edges formed during the etching operation and the polishing operation improve the functionality of the packaging tool that relies on the automatic detection of the peripheral edges of the IC chip to accurately align the IC chip to its support substrate (e.g., motherboard) during packaging. In embodiments of the present invention, the sputter etching operation, the directional etching operation, and the polishing operation result in a singulated IC chip having very smooth peripheral edges with a roughness level of less than about 4 μm Ra.

[0052] Additional technical effects and advantages of the embodiments of the present invention described herein are that the sputter etching operation is applied in parallel to all of the IC chips on the host semiconductor wafer, the directional RIE operation is applied in parallel to all of the IC chips on the host semiconductor wafer, and the substrate polishing operation is applied across all of the IC chips on the host semiconductor wafer. Applying etching and polishing operations in parallel to each IC chip on the host semiconductor wafer improves efficiency and reduces costs compared to known singulation operations that are applied in series to each IC chip on the host semiconductor wafer.

[0053] An additional technical effect and advantage of the above-described embodiments of the present invention is that the curing process and predetermined thickness improve the resistance of the photoresist layer to damage caused by etching operations (e.g., sputter etching and directional RIE) used to form the isolation trenches.

[0054] The methods and resulting structures described herein can be used in the manufacture of IC chips. The resulting IC chips can be distributed by manufacturers as bare dies, in raw wafer form (i.e., as a single wafer containing multiple unpackaged chips), or in packaged form. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers with leads attached to either surface or buried wiring, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be anything incorporating IC chips, from toys and other low-end products to sophisticated computer products with displays, keyboards or other input devices, and central processing units.

[0055] Various embodiments of the present invention are described herein with reference to the accompanying drawings. Alternative embodiments of the present invention can be devised without departing from the scope of the present invention. In the description and drawings herein, various connection relationships and positional relationships between elements (e.g., above, below, adjacent, etc.) are defined. These connection relationships or positional relationships or combinations thereof can be direct or indirect, unless otherwise specified, and the present invention is not intended to be limited in this regard. Thus, the connection of entities can refer to either a direct or an indirect connection, and the positional relationship between entities can be a direct or an indirect positional relationship. As an example of an indirect positional relationship, a reference herein to forming layer "A" on layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant characteristics and functionality of layer "A" and layer "B" are not substantially changed by the one or more intermediate layers.

[0056] The following definitions and abbreviations are used for the interpretation of the claims and the specification. As used herein, the words "comprising", "comprises", "including", "has", "have", or other variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements, but can include other elements not expressly listed or elements inherent to such composition, mixture, process, method, article, or apparatus.

[0057] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations or designs. The terms "at least one" and "one or more" may be understood to include any integer number greater than one, i.e., 1, 2, 3, 4, etc. The word "plurality" may be understood to include any integer number greater than two, i.e., 2, 3, 4, 5, etc. The word "connected" may include both an indirect "connected" and a direct "connected."

[0058] References herein to "one embodiment," "an embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but that all embodiments may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0059] For purposes of description herein, the terms "above," "below," "right," "left," "vertical," "horizontal," "up," "down," and their derivatives refer to the structures and methods described as oriented in the drawings. The terms "overlapping," "atop," "overlying," or "atop" mean that a first element, e.g., a first structure, is above a second element, e.g., a second structure, and that an intervening element, e.g., an interface structure, may be present between the first and second elements. "Direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0060] Spatially relative terms, such as "below", "lower than", "less than", "above", "higher than", etc., may be used herein for the purpose of facilitating the description of the relationship of one or more elements or features of an element or feature to another, as illustrated in the drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if the device in the drawing is turned over, an element described as "lower than" or "below" another element or feature will then be oriented "above" the other element or feature. Thus, the term "lower than" can encompass both upper and lower orientations. The device may be in other orientations (a 90-degree rotated orientation, or other orientations), and the spatially relative descriptors used herein are to be interpreted accordingly.

[0061] As used herein, "planarization" and "planarize" refer to a material removal process that uses at least mechanical force, a friction medium, to produce a substantially two-dimensional surface. The planarization process may include chemical mechanical polishing (CMP) or grinding. CMP is a material removal process that uses both a chemical reaction and mechanical force to remove material and planarize the surface.

[0062] The phrase "selective to", such as "a first element selective to a second element", means that the first element can be etched and the second element can function as an etch stop.

[0063] The terms "about", "substantially", "nearly" and their variants are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing. For example, "about" can include a range of ±8% or ±5% or ±2% of a given value.

[0064] The term "conformal" (e.g., conformal layer) means that the thickness of the layer is substantially the same on all surfaces or that the thickness varies by less than 15% of the nominal thickness of the layer.

[0065] The terms "epitaxial growth or deposition, or a combination thereof" and "epitaxially formed or grown, or a combination thereof" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), where the growing semiconductor material (crystalline beyond a layer) has substantially the same crystalline properties as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, chemical reactants supplied by a supply gas can be controlled and system parameters can be set so that the depositing atoms have sufficient energy to reach the deposition surface of the semiconductor substrate and move around on the surface so as to orient themselves in the crystalline arrangement of the atoms of the deposition surface. Epitaxially grown semiconductor material can have substantially the same crystalline properties as the deposition surface on which it was formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystalline surface can adopt a {100} orientation. In some embodiments of the present invention, the epitaxial growth process or deposition process, or a combination thereof, can be selective to formation on the semiconductor surface and cannot deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0066] As previously noted herein, for the sake of brevity, conventional techniques associated with semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. However, by way of background, a more general description of semiconductor device manufacturing processes that may be utilized in practicing one or more embodiments of the present invention will now be provided. While the specific manufacturing operations used in practicing one or more embodiments of the present invention may be individually known, the inventive operations or resulting structures, or combinations thereof, are unique. Thus, the unique combinations of operations described in connection with fabricating semiconductor devices in accordance with the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described herein.

[0067] Generally, the various processes for forming microchips that will be packaged within an IC fall into the following four categories: deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and, more recently, atomic layer deposition (ALD). Removal / etching is any process of removing material from a wafer. Examples include etching processes (either wet or dry), chemical-mechanical planarization (CMP), etc. For example, reactive ion etching (RIE) is a type of dry etching that uses a chemically reactive plasma to remove a material, such as a mask pattern of a semiconductor material, by exposing the material to the impact of ions that peel a portion of the material from the exposed surface. The plasma is typically generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping refers to changing the electrical properties, for example, by doping the source and drain of a transistor, generally by diffusion, ion implantation, or a combination thereof. After these doping processes, furnace annealing or rapid thermal annealing (RTA) is performed. Annealing serves to activate the implanted dopants. Films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components.Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed by applying a voltage to be charged. By creating structures of these various components, millions of transistors can be created and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography involves forming a three-dimensional relief image or pattern on a semiconductor substrate and subsequently transferring the pattern to the substrate. In semiconductor lithography, the pattern is formed using a light-sensitive polymer called a photoresist. The pattern transfer process of lithography and etching is repeated multiple times to create the complex structures that make up transistors and the many wires that connect the millions of transistors in a circuit. Each pattern printed on the wafer is aligned with previously formed patterns, and in this way, conductors, insulators, and selectively doped regions are built up to form the final device.

[0068] The flowcharts and block diagrams in the figures illustrate possible implementations of manufacturing or operating methods, or combinations thereof, according to various embodiments of the present invention. Various functions / operations of the methods are represented in the block flow diagrams. In some alternative implementations, the functions noted in the block diagrams may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved.

[0069] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for singulating integrated circuit (IC) chips from a host semiconductor wafer, comprising: receiving the host semiconductor wafer comprising a substrate and an active layer formed on the substrate, wherein the host semiconductor wafer further comprises a first IC chip including a first portion of the active layer and a first portion of the substrate; forming a first isolation trench by removing, using a plurality of stages of etching operations, a first segment of the active layer and a first segment of the substrate that are both below a first isolation channel of the host semiconductor wafer, wherein the first isolation trench separates the first portion of the active layer from the remaining portion of the active layer, and separates the first portion of the substrate from the remaining portion of the substrate; wherein the active layer comprises a front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) layer, wherein the plurality of stages of etching operations includes a first etching operation and a second etching operation, wherein the first etching operation includes a sputter etching operation that removes a plurality of different types of materials in the FEOL layer and the BEOL layer, wherein the second etching operation includes a directional reactive ion etching operation that directionally removes semiconductor material in the substrate; and singulating the first IC chip from the host semiconductor wafer by removing, using a substrate removal operation, a first section of the remaining portion of the substrate that is both below the first portion of the substrate. ; and The method as described above.

2. The method of claim 1, wherein the first isolation trench comprises a first segment and a second segment.

3. The method of claim 2, wherein the first segment of the first isolation trench separates the first portion of the active layer from the remaining portion of the active layer.

4. The method of claim 3, wherein the second segment of the first isolation trench separates the first portion of the substrate from the remaining portion of the substrate.

5. The first etching operation is configured to form the first segment of the first isolation trench; and ​ The second etching operation is configured to form the second segment of the first isolation trench. The method according to claim 4. **Claim 6** The substrate removal operation includes polishing the first section of the remaining portion of the substrate that is underneath the first portion of the substrate. The method according to claim 5. **Claim 7** The host semiconductor wafer further includes a second IC chip including a second portion of the active layer and a second portion of the substrate. The method includes removing the first segment of the active layer and the first segment of the substrate that are both underneath the first isolation channel of the host semiconductor wafer, and, in parallel therewith, removing the second segment of the active layer and the second segment of the substrate that are both underneath the second isolation channel of the host semiconductor wafer, by performing the etching operation, to form a second isolation trench, where the second isolation trench separates the second portion of the active layer from the remaining portion of the active layer, and separates the second portion of the substrate from the remaining portion of the substrate; and further singulating the second IC chip from the host semiconductor wafer by performing the substrate removal to remove the first section of the remaining portion of the substrate that is underneath the first portion of the substrate, and, in parallel therewith, removing the second section of the remaining portion of the substrate that is underneath the second portion of the substrate. The method of claim 1 further includes. The method according to claim 1. **Claim 8** forming a photoresist layer on the host semiconductor wafer, where the photoresist layer defines the first isolation channel of the host semiconductor wafer. The method of claim 1 further includes. **Claim 9** The photoresist layer has a predetermined thickness, and the method of claim 8 further includes subjecting the photoresist layer to a curing process. **Claim 10** A system for singulating an integrated circuit (IC) chip from a host semiconductor wafer, the system comprising a configuration of a semiconductor manufacturing apparatus configured to perform a singulation operation, the singulation operation comprising ​ Receiving the host semiconductor wafer comprising a substrate and an active layer formed on the substrate, wherein the host semiconductor wafer further comprises a first IC chip including a first portion of the active layer and a first portion of the substrate; Forming a first isolation trench by removing, using a plurality of stages of etching operations, a first segment of the active layer and a first segment of the substrate that are both beneath a first isolation channel of the host semiconductor wafer, wherein the first isolation trench separates the first portion of the active layer from the remaining portion of the active layer, and separates the first portion of the substrate from the remaining portion of the substrate ; wherein the active layer comprises a front-end-of-line (FEOL) layer and a back-end-of-line (BEOL) layer, wherein the plurality of stages of etching operations includes a first etching operation and a second etching operation, wherein the first etching operation includes a sputter etching operation that removes a plurality of different types of materials in the FEOL layer and the BEOL layer, wherein the second etching operation includes a directional reactive ion etching operation that directionally removes semiconductor material in the substrate, ; and singulating the first IC chip from the host semiconductor wafer by removing, using a substrate removal operation, a first section of the remaining portion of the substrate that is both beneath the first portion of the substrate comprising the system.

11. wherein the first isolation trench comprises a first segment and a second segment, wherein the first segment of the first isolation trench separates the first portion of the active layer from the remaining portion of the active layer, wherein the second segment of the first isolation trench separates the first portion of the substrate from the remaining portion of the substrate, wherein the first etching operation is configured to form the first segment of the first isolation trench; and wherein the second etching operation is configured to form the second segment of the first isolation trench; and wherein the substrate removal operation includes polishing a first section of the remaining portion of the substrate that is both beneath the first portion of the substrate; The host semiconductor wafer further comprises a second IC chip including the second portion of the active layer and the second portion of the substrate; The singulation operation uses the etching operation to form a second separation trench by removing the second segment of the active layer and the second segment of the substrate, which are both under the second separation channel of the host semiconductor wafer, in parallel with removing the first segment of the active layer and the first segment of the substrate, which are both under the first separation channel of the host semiconductor wafer, where the second separation trench separates the second portion of the active layer from the remaining portion of the active layer, and the second portion of the substrate from the remaining portion of the substrate ; and further includes; and the singulation operation singulates the second IC chip from the host semiconductor wafer by performing the substrate removal to remove the second section of the remaining portion of the substrate, which is both under the second portion of the substrate, in parallel with removing the first section of the remaining portion of the substrate, which is both under the first portion of the substrate further includes. The system according to claim 10.

12. The singulation operation further includes forming a photoresist layer on the host semiconductor wafer, where the photoresist layer defines the first separation channel of the host semiconductor wafer. further includes. The system according to claim 10.

Images