Switch circuit

Abstract

To provide a switch circuit capable of increasing a breakdown voltage and increasing switching speed for an RF switch.SOLUTION: A switch circuit of an embodiment includes a high frequency switch and a level shifter circuit. The high frequency switch includes a first switch group and a second switch group, each of them provides a plurality of switches, and switches transmission / reception of a high frequency signal. The level shifter circuit outputs a first signal for performing on / off control for each switch of the first switch group and a second signal for performing on / off control for each switch of the second switch group.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to a switch circuit.

Background Art

[0002] A high-frequency switch (hereinafter referred to as an RF switch) is used for switching on and off (for switching transmission and reception), impedance tuning switching, and frequency band change switching when transmitting and receiving radio signals in a mobile base station or the like.

[0003] Since the RF switch is used in a mobile base station or the like, there is a demand for higher breakdown voltage and faster switching time of the switch. However, there has been a problem that it is difficult to achieve both higher breakdown voltage and faster switching time of the switch.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, an object of the embodiment is to provide a switch circuit capable of increasing the breakdown voltage and accelerating the switching of the RF switch.

Means for Solving the Problems

[0006] The switch circuit of the embodiment includes a high-frequency switch, a level shifter circuit, a first charge pump circuit, a second charge pump circuit, and a comparator. The high-frequency switch includes a plurality of transistors with their sources and drains connected in series, divides the plurality of transistors connected in multiple stages into two groups, and has a first switch group including a plurality of transistors in one group and a second switch group including a plurality of transistors in the other group, and switches the transmission and reception of high-frequency signals. The level shifter circuit outputs a first signal for controlling the on / off of each transistor in the first switch group and a second signal for controlling the on / off of the transistors in the second switch group. The first charge pump circuit generates a positive voltage or a negative voltage that is the source of the first signal and the second signal output by the level shifter circuit. The comparator compares the positive voltage or the negative voltage output from the first charge pump circuit with a reference voltage preset in the switch circuit, and determines whether the first charge pump circuit is lower than the reference voltage. The second charge pump circuit operates to temporarily increase the driving ability of the first charge pump circuit when the comparator determines that the first charge pump circuit cannot output the reference voltage. combined with the second charge pump circuit Operates to temporarily increase the driving ability.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a configuration diagram showing an example of the configuration of a switch device including a switch circuit according to an embodiment.

[0009] The switch device 1 includes a switch circuit 10, a transceiver circuit 11, and a control circuit 12. An antenna ANT is connected to the switch device 1. The control circuit 12 is connected to the switch circuit 10 and the transceiver circuit 11. By the control circuit 12 controlling the switch circuit 10 and the transceiver circuit 11, the transmission and reception of a high-frequency signal (hereinafter referred to as an RF signal) are controlled. Thereby, the switch device 1 can perform the transmission and reception of RF signals and the like.

[0010] The control circuit 12 outputs a control signal CTRL, which will be described later, to the switch circuit 10. The switching of the switch circuit 10 is performed according to the control signal CTRL from the control circuit 12.

[0011] FIG. 2 is a configuration diagram showing an example of the configuration of the switch circuit. The switch circuit 10 includes a boost signal generation circuit 20, an OR circuit 21, an oscillator (hereinafter referred to as OSC) 22, a charge pump section 23 including charge pump circuits 24 and 25, a level shifter circuit 26, a filter circuit 27, an RF switch 28, and comparators 29 and 30.

[0012] A control signal CTRL from the control circuit 12 is input to the boost signal generation circuit 20. The control signal CTRL is a signal with an L level of 0V and an H level of 1.8V. When the boost signal generation circuit 20 detects either a rising edge at which the control signal CTRL transitions from the L level to the H level or a falling edge at which it transitions from the H level to the L level, it outputs a boost signal (first boost signal) of the H level to the OR circuit 21.

[0013] In addition to the boost signal from the boost signal generation circuit 20, as will be described later, H-level signal boost signals (second and third boost signals) from the comparators 29 and 30 are input to the OR circuit 21. When any one of the boost signals from the boost signal generation circuit 20, the comparators 29 and 30 is at the H level, the OR circuit 21 outputs a boost signal of the H level to the OSC 22 and the charge pump circuit 25.

[0014] The OSC 22 can generate a clock signal (pulse signal) CLK with a predetermined frequency. The OSC 22 outputs the generated clock signal CLK with the predetermined frequency to the charge pump circuits 24 and 25. When a boost signal, which will be described later, is input, the OSC 22 generates a clock signal CLK with a temporarily increased frequency compared to the predetermined frequency and outputs it to the charge pump circuits 24 and 25.

[0015] Charge pump circuit 24, which constitutes a first charge pump circuit, receives, for example, a 3V power supply VDD or a 0V ground GND. Charge pump circuit 24 boosts or lowers the power supply VDD or ground GND in response to clock signal CLK, and outputs +4.3V (first voltage) or −3V (second voltage). The +4.3V output is input to level shifter circuit 26 and comparator 29. The −3V output is input to level shifter circuit 26 and comparator 30.

[0016] Charge pump circuit 25, which constitutes the second charge pump circuit, operates only when a boost signal is input. That is, when the driving capability of charge pump circuit 24 is reduced and it is no longer possible to output +4.3V and −3V, charge pump circuit 25 increases the current supply capability to improve the driving capability.

[0017] The level shifter circuit 26 receives a control signal CTRL having an L level of 0 V and an H level of 1.8 V from the control circuit 12. When 1.8 V is input as the control signal CTRL, the level shifter circuit 26 shifts the level to +4.3 V and outputs it to the filter circuit 27. When 0 V is input as the control signal CTRL, the level shifter circuit 26 shifts the level to −3 V and outputs it to the filter circuit 27. As will be described in detail later, the level shifter circuit 26 outputs two signals OUT1 and OUT2 that have been level-shifted to +4.3 V or −3 V to the filter circuit 27.

[0018] The filter circuit 27 isolates (separates) noise and the like from the input signals OUT1 and OUT2, and outputs the two signals from which noise and the like have been isolated to the RF switch .

[0019] The RF switch 28 switches based on the two input signals. One end of the RF switch 28 is connected to the antenna ANT, and the other end is connected to the transmission / reception circuit 11. With this configuration, the switch circuit 10 can output an RF signal received via the antenna ANT to the transmission / reception circuit 11, and can transmit an RF signal input from the transmission / reception circuit 11 via the antenna ANT.

[0020] Comparator 29 compares the +4.3V output voltage of the charge pump circuit 24 with the reference voltage ref1, and outputs a boost signal (H-level signal) to the OR circuit 21 when the output voltage drops below the reference voltage ref1.

[0021] Comparator 30 compares the -3V output voltage of the charge pump circuit 24 with the reference voltage ref2, and outputs a boost signal (H-level signal) to the OR circuit 21 when the output voltage rises above the reference voltage ref2.

[0022] The switch circuit 10 may be formed on an SOI (Silicon on Insulator). By forming the switch circuit 10 on the SOI, high breakdown voltage can be achieved. Furthermore, by forming the switch circuit 10 on the SOI, the parasitic capacitance becomes smaller compared to bulk CMOS, or high-speed switching of the RF switch can be realized compared to a silicon substrate.

[0023] FIG. 3 is a configuration diagram showing an example of the configuration of the filter circuit and the RF switch of the switch circuit. The filter circuit 27 has isolation resistors Ra and Rb. The isolation resistors Ra and Rb prevent noise and the like from being input from the filter circuit 27 side to the RF switch 28. Resistor Ra isolates the signal OUT1 output from the level shifter circuit 26, and resistor Rb isolates the signal OUT2 output from the level shifter circuit 26.

[0024] The RF switch 28 includes a plurality of transistors Tr1a and Tr1b whose sources and drains are connected in series. One end of a breakdown voltage resistor R1a for preventing the RF signal from leaking to the filter circuit 27 side is connected to the gate of each transistor Tr1a. The other ends of the plurality of resistors R1a are connected to the isolation resistor Ra.

[0025] Also, one end of a withstand voltage resistor R1b for preventing RF signals from leaking to the filter circuit 27 side is connected to the gate of each transistor Tr1b. The other ends of the plurality of resistors R1b are connected to an isolation resistor Rb.

[0026] With such a configuration, the plurality of transistors Tr1a constituting the first switch group are turned on / off under the control of the signal OUT1 output from the level shifter circuit 26, and the plurality of transistors Tr1b constituting the second switch group are turned on / off under the control of the signal OUT2 output from the level shifter circuit 26.

[0027] The transistors Tr1a and Tr1b, which are switches configured in multiple stages, are divided into two groups and turned on / off by different signals OUT1 and OUT2 from the level shifter circuit 26. As a result, the number of stages of the switches operating with the signal OUT1 and the number of stages of the switches operating with the signal OUT2 can be made less than the number of stages of the entire switch, so that the switching time in the RF switch 28 can be shortened as a whole.

[0028] The RF signal is input from the antenna ANT or output to the antenna ANT. As described above, one end of the RF switch 28 is connected to the antenna ANT, and the other end is connected to the transceiver circuit 11. When the switch circuit 10 is used for switching during impedance tuning, tuning elements such as capacitors and inductors are connected to the other end of the RF switch 28.

[0029] FIG. 4 is a circuit diagram showing an example of the circuit configuration of the OSC. The OSC22 is configured by connecting a plurality of inverters INV capable of varying the delay amount in a ring shape. When a boost signal is input, the OSC22 increases the current supplied to each inverter INV via a plurality of transistors Tr2 and increases the frequency of the clock signal CLK.

[0030] Note that OSC22 is not limited to a ring oscillator in which a plurality of inverters INV are connected in a ring shape, but may be any other type of oscillator as long as it is configured to generate a clock signal CLK of a desired frequency.

[0031] Fig. 5 is a configuration diagram showing an example of the configuration of a charge pump section, and Fig. 6 is a circuit diagram showing an example of the circuit configuration of a charge pump circuit. The charge pump circuit 24 boosts or drops the power supply VDD or ground GND to output +4.3V or -3V. If a single charge pump circuit 24 cannot boost or drop the voltage to +4.3V or -3V, the charge pump circuit 24 may be configured with multiple charge pump circuits 24a connected in series. The charge pump circuit 25 may also be configured with multiple charge pump circuits 25a connected in series.

[0032] The clock signal CLK(+) from the OSC 22 and an inverted clock signal CLK(-) inverted by, for example, an inverter circuit are input to the charge pump circuits 24 and 25. The charge pump circuit 25 is provided with a switching circuit 25b on the signal lines of the clock signal CLK(+) and the inverted clock signal CLK(-).

[0033] When an H-level boost signal is input, the switching circuit 25b switches so that the clock signal CLK and the inverted clock signal CLK(-) are input to the charge pump circuit 25 (or 25a). As a result, only when a boost signal is input, the chirp pump circuit 25 (or 25a) operates, thereby enhancing the driving capability of the charge pump circuit 24.

[0034] 6, the charge pump circuit 24 is configured to include p-type transistors Tr3 and Tr4, n-type transistors Tr5 and Tr6, and capacitors C1 and C2. The transistors Tr3 to Tr6 are turned on and off by a clock signal CLK(+) and an inverted clock signal CLK(-), and the charge pump circuit 24 outputs an output signal that is a boosted or dropped input signal by storing or discharging electric charge in or from the capacitors C1 and C2.

[0035] The configuration of the charge pump circuit 25 is the same as the configuration of the charge pump circuit 24 shown in Fig. 6. Note that the configuration of the charge pump circuits 24 and 25 is not limited to the configuration having p-type transistors Tr3 and Tr4, n-type transistors Tr5 and Tr6, and capacitors C1 and C2 shown in Fig. 6, and other configurations may be used.

[0036] Fig. 7 is a circuit diagram showing an example of the circuit configuration of a boost signal generating circuit, and Fig. 8 is a waveform diagram showing an example of the waveforms of input and output signals of the boost signal generating circuit. As shown in FIG. 7, the boost signal generating circuit 20 includes a delay circuit 31 and an XOR circuit 32.

[0037] The input signal (control signal CTRL) input to the boost signal generating circuit 20 is input to a delay circuit 31 and one terminal of an XOR circuit 32. The delay circuit 31 delays the input signal by a predetermined time and outputs the delayed signal to the XOR circuit 32. The delayed input signal delayed by the delay circuit 31 by the predetermined time is input to the other terminal of the XOR circuit 32.

[0038] 8 are input to the XOR circuit 32. The input signal switches from L level to H level at time t1, and switches from H level to L level at time t3. The delayed input signal is delayed by the delay circuit 31, switches from L level to H level at time t2, and switches from H level to L level at time t4.

[0039] The XOR circuit 32 outputs an H-level signal when the input signal levels are different. Therefore, the XOR circuit 32 outputs an H-level output signal (boost signal) to the OR circuit 21 between time t1 and time t2, and between time t3 and time t4.

[0040] In this way, when the control signal CTRL switches from the L level to the H level or from the H level to the L level, the boost signal generation circuit 20 immediately outputs an output signal (boost signal) to the OR circuit 21. In other words, when the boost signal generation circuit 20 detects the rising edge or falling edge of the control signal CTRL, it immediately outputs an H-level output signal (boost signal) to the OR circuit 21. The pulse width of the output signal can be arbitrarily determined by the time (delay amount) by which the delay circuit 31 delays the input signal. Note that the configuration of the boost signal generation circuit 20 is not limited to the configuration of FIG. 7 as long as it can detect the edge of the control signal CTRL, and other configurations may also be used.

[0041] FIG. 9 is a circuit diagram showing an example of the circuit configuration of the level shifter circuit. The level shifter circuit 26 is configured with a plurality of transistors. The level shifter circuit 26 receives the control signal CTRL as an input and the inverted control signal CTRL as an inverted input.

[0042] When an H-level (1.8V) control signal CTRL is input to the level shifter circuit 26, the p-type transistors Tr7 and Tr8 are turned on, and a signal OUT1 level-shifted to +4.3V is output.

[0043] Similarly, when an H-level (1.8V) control signal CTRL is input to the level shifter circuit 26, the p-type transistors Tr11 and Tr12 are turned on, and a signal OUT2 level-shifted to +4.3V is output.

[0044] On the one hand, when the control signal CTRL at the L level (0V) is input, the level shifter circuit 26 turns on the n-type transistors Tr9 and Tr10 and outputs a signal OUT1 that has been level-shifted to -3V.

[0045] Similarly, when the control signal CTRL at the L level (0V) is input, the level shifter circuit 26 turns on the n-type transistors Tr13 and Tr14 and outputs a signal OUT2 that has been level-shifted to -3V.

[0046] With such a configuration, the level shifter circuit 26 can output the signals OUT1 and OUT2 that have been level-shifted to +4.3V or -3V to the transistors Tr1a and Tr1b of the RF switch 28.

[0047] Note that the configuration of the level shifter circuit 26 is not limited to the configuration in FIG. 9 as long as it can level-shift the control signals CTRL at the H level and L level to +4.3V and -3V, and other configurations may also be used.

[0048] Here, the simulation results of the switch switching time when the switches of the RF switch 28 are not divided into two groups and when they are divided into two groups will be described with reference to FIGS. 10 and 11.

[0049] FIG. 10 is a waveform diagram showing the simulation results of the switch switching time when the switches of the RF switch are not divided into two groups. FIG. 11 is a waveform diagram showing the simulation results of the switch switching time when the switches of the RF switch are divided into two groups.

[0050] As shown in FIG. 10, when the switches of the RF switch 28 are not divided into two groups, the switch switching start time is T1, and the time when the gate voltage of the switch reaches the on voltage is T2. Therefore, when the switches of the RF switch 28 are not divided into two groups, the switch switching time is T3 (usec).

[0051] On the other hand, as shown in FIG. 11, when each switch of the RF switch 28 is divided into two groups, the start time of switch switching is T1, and the time when the gate voltage of the switch becomes the on voltage is T4. Therefore, when each switch of the RF switch 28 is divided into two groups, the switching time of the switch is T5 (usec).

[0052] From these simulation results, when each switch of the RF switch 28 is divided into two groups, the switching time of the switch is about 1 / 2 compared to the case where each switch of the RF switch 28 is not divided into two groups, and the switching speed of the switch is increased.

[0053] As described above, in this embodiment, a plurality of transistors Tr1a and Tr1b of the RF switch 28 are connected in multiple stages, that is, the switches are connected in multiple stages to increase the withstand voltage. Generally, connecting the switches in multiple stages can increase the withstand voltage, but the switching time of the switch becomes slow.

[0054] In contrast, in this embodiment, a plurality of switches of the RF switch 28 are divided into two groups, and the switches are switched with different signals, thereby increasing the switching speed of the switches as described above.

[0055] Therefore, according to the switch circuit 10 of this embodiment, the withstand voltage of the RF switch 28 can be increased and the switching can be speeded up.

[0056] Note that in this embodiment, a plurality of transistors of the RF switch 28 are divided into two groups, here, the group of transistors Tr1a and the group of transistors Tr1b, but they may be divided into three or more groups.

[0057] In this case, for each of the groups of transistors into which the level shifter circuit 26 is divided, it may be configured to output a signal for controlling on / off. By dividing the plurality of transistors of the RF switch 28 into three or more groups and controlling on / off with different signals, it is possible to further speed up the switching time of the RF switch 28.

[0058] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0059] 1... Switch device, 10... Switch circuit, 11... Transceiver circuit, 12... Control circuit, 20... Boost signal generation circuit, 21... OR circuit, 22... OSC, 23... Charge pump section, 24, 25... Charge pump circuit, 26... Level shifter circuit, 27... Filter circuit, 28... RF switch, 29, 30... Comparator, 31... Delay circuit, 32... XOR circuit.

Claims

1. In a switch circuit, including a plurality of transistors with source-drain connected in series, dividing the plurality of transistors connected in multiple stages into two groups, having a first switch group including a plurality of transistors in one group and a second switch group including a plurality of transistors in the other group, and a high-frequency switch for switching the transmission and reception of high-frequency signals; a level shifter circuit that outputs a first signal for controlling on / off of each transistor in the first switch group and a second signal for controlling on / off of the transistors in the second switch group; a first charge pump circuit that generates a positive voltage or a negative voltage that is the source of the first signal and the second signal output by the level shifter circuit; a comparator that compares the positive voltage or negative voltage output from the first charge pump circuit with a reference voltage preset in the switch circuit and determines whether the first charge pump circuit is lower than the reference voltage; and a second charge pump circuit, wherein the second charge pump circuit operates to temporarily increase the driving ability of the combined first charge pump circuit and the second charge pump circuit when the comparator determines that the first charge pump circuit cannot output the reference voltage. A switch circuit.

2. The high-frequency switch according to claim 1, wherein each transistor in the first switch group and each transistor in the second switch group are connected in series.

3. The switch circuit according to claim 1 or 2, having a filter circuit that separates noise from the first and second signals and supplies it to the high-frequency switch.

4. The switch circuit according to claim 3, wherein the filter circuit has a first resistor for separating noise from the first signal and a second resistor for separating noise from the second signal.

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