Semiconductor device and electronic equipment

Abstract

Provided is a novel semiconductor device comprising a structure extending in a first direction, a first electrical conductor extending in a second direction, and a second electrical conductor extending in the second direction. The structure and the first electrical conductor intersect each other in a first intersecting portion in which the structure comprises a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator which are disposed concentrically on the outside of a third electrical conductor. The structure and the second electrical conductor intersect each other in a second intersecting portion in which the structure comprises a first insulator, a first semiconductor, a second insulator, a fourth electrical conductor, a second semiconductor, and a third insulator which are disposed concentrically on the outside of the third electrical conductor.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof.

Background Art

[0003] In recent years, electronic components such as a central processing unit (CPU), a graphics processing unit (GPU), a storage device, and a sensor have been used in various electronic devices such as personal computers, smartphones, and digital cameras, and the electronic components have been improved in various aspects such as miniaturization and low power consumption.

[0004] In particular, the amount of data handled in the above-described electronic devices and the like has been increasing, and a storage device having a large storage capacity is required. As a means for increasing the storage capacity, for example, Patent Document 1 and Patent Document 2 disclose a three-dimensional NAND memory element using a metal oxide as a channel formation region.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present invention aims to provide a highly reliable memory device. Or, one aspect of the present invention aims to provide a memory device with a large storage capacity. Or, one aspect of the present invention aims to provide a novel memory device. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with a large storage capacity. Or, one aspect of the present invention aims to provide a novel semiconductor device.

[0007] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are those not mentioned in this item but described below. Problems not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the problems listed above and other problems. Note that one aspect of the present invention does not necessarily need to solve all of the problems listed above and other problems.

Means for Solving the Problems

[0008] One aspect of the present invention has a structure extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction. The structure has a third conductor extending in the first direction, a first insulator adjacent to the third conductor, a first semiconductor adjacent to the first insulator, and a second insulator adjacent to the first semiconductor. At a first intersection where the structure and the first conductor intersect, the structure has a second semiconductor adjacent to the second insulator, a third insulator adjacent to the second semiconductor, a functional body adjacent to the third insulator, and a fourth insulator adjacent to the functional body. At a second intersection where the structure and the second conductor intersect, the structure has a fourth conductor adjacent to the second insulator, a second semiconductor adjacent to the fourth conductor, and a third insulator adjacent to the second semiconductor. At the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor, the third insulator, the functional body, and the fourth insulator are provided concentrically outside the third conductor when viewed from the first direction. At the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth conductor, the second semiconductor, and the third insulator are provided concentrically outside the third conductor when viewed from the first direction. It is a semiconductor device.

[0009] The first direction is a direction orthogonal to the second direction. Also, the first intersection functions as a first transistor, and the second intersection functions as a second transistor and a capacitor element. At least one of the first semiconductor and the second semiconductor may be silicon.

[0010] An insulator or a semiconductor can be used as the functional body. For example, by using silicon nitride (an insulator containing nitrogen and silicon) as the functional body, the first transistor can be made into a MONOS type transistor. Also, for example, by using silicon nitride (an insulator containing nitrogen and silicon) as the functional body, the first transistor can be made into an FG type transistor.

[0011] By injecting charge into the functional body, the threshold voltage of the first transistor can be increased, and the first transistor can be made into a normally-off transistor. Therefore, the first transistor can be made into a normally-off transistor, and the second transistor can also be made into a normally-on transistor.

[0012] Further, at least one of the first semiconductor and the second semiconductor may be an oxide semiconductor. The oxide semiconductor preferably contains at least one of indium or zinc.

[0013] Another aspect of the present invention is an electronic device having the above semiconductor device and at least one of an operation switch, a battery, and a display unit.

Advantages of the Invention

[0014] According to one aspect of the present invention, a highly reliable memory device can be provided. Or, a memory device with a large storage capacity can be provided. Or, a novel memory device can be provided. Or, a highly reliable semiconductor device can be provided. Or, a semiconductor device with a large storage capacity can be provided. Or, a novel semiconductor device can be provided.

[0015] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are the effects not mentioned in this item described below. The effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

Brief Description of the Drawings

[0016] FIG. 1A is a perspective view of a memory cell. FIG. 1B is a cross-sectional view of a memory cell. Figures 2A and 2B are cross-sectional views of a memory cell. Figure 3 is a perspective view of a structure. Figures 4A to 4C are equivalent circuit diagrams of a memory cell. Figures 5A and 5B are equivalent circuit diagrams of a memory cell. Figure 6 is a cross-sectional view of a memory string. Figure 7 is an equivalent circuit diagram of a memory string. Figure 8 is an equivalent circuit diagram of a memory string. Figure 9 is an equivalent circuit diagram of a memory string. Figure 10 is an equivalent circuit diagram of a memory string. Figures 11A and 11B are top views of a memory string. Figures 12A and 12B are cross-sectional views of a memory cell. Figure 13 is a cross-sectional view of a memory cell. Figure 14A is a diagram for explaining the classification of crystal structures. Figure 14B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film. Figure 14C is a diagram for explaining the selected area electron diffraction pattern of a CAAC-IGZO film. Figures 15A and 15B are cross-sectional views for explaining a method of manufacturing a memory cell. Figures 16A and 16B are cross-sectional views for explaining a method of manufacturing a memory cell. Figures 17A and 17B are cross-sectional views for explaining a method of manufacturing a memory cell. Figures 18A and 18B are cross-sectional views for explaining a method of manufacturing a memory cell. Figures 19A and 19B are cross-sectional views for explaining a method of manufacturing a memory cell. Figures 20A and 20B are cross-sectional views for explaining a method of manufacturing a memory cell. Figures 21A and 21B are cross-sectional views for explaining a method of manufacturing a memory cell. Figures 22A and 22B are cross-sectional views for explaining a method of manufacturing a memory cell. Figure 23 is a circuit diagram of a semiconductor device. Figure 24 is a timing chart for explaining an operation example of a semiconductor device. Figures 25A and 25B are timing charts for explaining an operation example of a semiconductor device. Figure 26A is a perspective view for explaining a configuration example of a semiconductor device. Figure 26B is a top view for explaining a configuration example of a semiconductor device. Figure 26C is a cross-sectional view for explaining a configuration example of a semiconductor device. Figure 27A is a perspective view for explaining a configuration example of a semiconductor device. Figure 27B is a top view for explaining a configuration example of a semiconductor device. Figure 27C is a cross-sectional view for explaining a configuration example of a semiconductor device. Figures 28A and 28B are cross-sectional views for explaining a semiconductor device. Figures 29A and 29B are cross-sectional views for explaining a semiconductor device. Figure 30 is a block diagram for explaining a configuration example of a semiconductor device. Figure 31 is a diagram for explaining a configuration example of a semiconductor device. Figure 32 is a diagram for explaining an example of constructing an information processing system using a plurality of storage devices. Figure 33 is a block diagram for explaining a CPU. Figures 34A and 34B are perspective views of a semiconductor device. Figures 35A and 35B are perspective views of a semiconductor device. Figures 36A and 36B are perspective views of a semiconductor device. Figure 37A is a perspective view showing an example of a semiconductor wafer, Figure 37B is a perspective view showing an example of a chip, and Figures 37C and 37D are perspective views showing an example of an electronic component. Figures 38A and 38B are diagrams showing various storage devices by hierarchy. Figures 39A to 39J are perspective views or schematic diagrams for explaining an example of an electronic device. Figures 40A to 40E are perspective views or schematic diagrams for explaining an example of an electronic device. Figures 41A to 41C are diagrams for explaining an example of an electronic device. Figure 42 is a diagram for explaining a configuration example of a computer system. Figure 43 is a diagram showing the hierarchical structure of an IoT network and trends in requirement specifications. FIG. 44 is an image diagram of factory automation. FIG. 45A is a perspective conceptual diagram of a semiconductor device. FIG. 45B is an equivalent circuit diagram of a memory cell. FIG. 46 is a timing chart for explaining the operation of a 3DOS NAND string. FIG. 47A is a diagram showing the Id-Vwg characteristics of transistor WTr. FIG. 47B is a diagram showing the relationship between the threshold voltage of transistor WTr and Vpre. FIGS. 48A and 48B are diagrams showing the retention characteristics of a 3DOS NAND string. FIGS. 49A and 49B are diagrams showing the simulation results of the retention characteristics of a memory cell. FIG. 50 is a diagram showing the simulation results of the retained data of a memory cell and the read current Irbl.

DETAILED DESCRIPTION OF THE INVENTION

[0017] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (such as transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip provided with an integrated circuit, or an electronic component in which a chip is housed in a package is an example of a semiconductor device. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc., are semiconductor devices themselves and may have semiconductor devices.

[0018] Also, in this specification and the like, when it is described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected, as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in a figure or text, and those other than the connection relationship shown in the figure or text are also considered to be disclosed in the figure or text. It is assumed that X and Y are objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0019] As an example of the case where X and Y are electrically connected, one or more elements that enable the electrical connection between X and Y (for example, a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) can be connected between X and Y. Note that the switch has a function of controlling the on-state and the off-state. That is, the switch has a function of becoming a conductive state (on-state) or a non-conductive state (off-state) and controlling whether to allow current to flow or not.

[0020] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit (a digital-analog conversion circuit, an analog-digital conversion circuit, a gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (a boost circuit, a buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or the amount of current, an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, it is considered that X and Y are functionally connected.

[0021] Note that when it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, when they are connected with another element or another circuit interposed between X and Y) and the case where X and Y are directly connected (that is, when they are connected without another element or another circuit interposed between X and Y).

[0022] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and they are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By stipulating the connection order in the circuit configuration using an expression method similar to these examples, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0023] Note that even when components that are independent on the circuit diagram are shown as being electrically connected, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring component and the electrode component. Therefore, the electrically connected in this specification includes such cases where one conductive film has the functions of multiple components within its scope.

[0024] In addition, in this specification and the like, the "resistive element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the "resistive element" includes wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, a coil, and the like. Therefore, the term "resistive element" can be replaced with terms such as "resistance", "load", "region having a resistance value", and conversely, the terms "resistance", "load", "region having a resistance value" can be replaced with terms such as "resistive element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0025] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value, parasitic capacitance, the gate capacitance of a transistor, and the like. Therefore, in this specification and the like, the "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also parasitic capacitance that appears between wirings, gate capacitance that appears between one of the source or drain of a transistor and the gate, and the like. Also, the terms "capacitive element", "parasitic capacitance", "gate capacitance", etc. can be replaced with terms such as "capacitance", and conversely, the term "capacitance" can be replaced with terms such as "capacitive element", "parasitic capacitance", "gate capacitance". Also, the term "pair of electrodes" of "capacitance" can be replaced with "pair of conductors", "pair of conductive regions", "pair of regions", etc. Note that the capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 μF or less.

[0026] Also, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Which of the two input / output terminals becomes the source and which becomes the drain depends on the conductivity type of the transistor (n-channel type, p-channel type) and the magnitudes of the potentials applied to the three terminals of the transistor. Therefore, in this specification and the like, the terms source and drain are considered interchangeable. Also, in this specification and the like, when explaining the connection relationship of a transistor, the notations "one of the source or the drain" (or the first electrode, or the first terminal), and "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, it may have a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Further, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, when a transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0027] Also, in this specification and the like, a node can be equivalently referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on the circuit configuration, device structure, etc. Also, it is possible to equivalently refer to a terminal, a wiring, etc. as a node.

[0028] Also, in this specification and the like, "voltage" and "electric potential" can be appropriately rephrased. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earthing potential), "voltage" can be rephrased as "electric potential". Note that the ground potential does not necessarily mean 0V. Also, electric potential is relative, and when the reference potential changes, the potential applied to a wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc. also change.

[0029] Also, in this specification and the like, the terms "high-level potential (also referred to as "high potential", "H potential", or "H")" and "low-level potential (also referred to as "low potential", "L potential", or "L")" do not mean specific potentials. For example, in two wirings, if both are described as "functioning as wirings that supply high-level potentials", the respective high-level potentials provided by the two wirings do not have to be equal to each other. Similarly, in two wirings, if both are described as "functioning as wirings that supply low-level potentials", the respective low-level potentials provided by the two wirings do not have to be equal to each other.

[0030] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, unless otherwise specified, "current" shall refer to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers. The carriers mentioned here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Also, the "direction of current" in wiring, etc., is defined as the direction in which positive carriers move, and the current amount is described as a positive value. In other words, the direction in which negative carriers move is the opposite direction of the current direction, and the current amount is described as a negative value. Therefore, in this specification and the like, when there is no indication regarding the positive or negative of the current (or the direction of the current), descriptions such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, descriptions such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0031] Also, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0032] Also, terms such as "above" and "below" do not limit the positional relationship of components to be directly above or directly below and in direct contact. For example, in the expression "electrode B above insulating layer A", it is not necessary for electrode B to be formed directly in contact above insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0033] Also, the positional relationship of the components changes appropriately according to the direction of depicting each component. Therefore, it is not limited to the terms described in the specification or the like, and can be appropriately rephrased according to the situation. For example, in this specification or the like, terms indicating arrangements such as "above" and "below" may be used for convenience in order to explain the positional relationship of the components with reference to the drawings. Thus, the expression "the insulator located on the upper surface of the conductor" can be rephrased as "the insulator located on the lower surface of the conductor" by rotating the direction of the shown drawing by 180 degrees. Also, in the expression "the insulator located on the upper surface of the conductor", by rotating the direction of the shown drawing by 90 degrees, it can be rephrased as "the insulator located on the left surface (or right surface) of the conductor".

[0034] Similarly, in this specification or the like, terms such as "overlap" do not limit the state such as the stacking order of the components. For example, in the expression "electrode B overlapping insulating layer A", it is not limited to the state where "electrode B is formed on insulating layer A", and states such as "electrode B is formed under insulating layer A" or "electrode B is formed on the right side (or left side) of insulating layer A" are not excluded.

[0035] Also, in this specification or the like, terms such as "adjacent" and "proximate" do not limit that the components are in direct contact. For example, in the expression "electrode B adjacent to insulating layer A", it is not necessary that insulating layer A and electrode B are formed in direct contact, and those including other components between insulating layer A and electrode B are not excluded.

[0036] Also, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases, or depending on the situation, it is possible to interchange with another term without using terms such as "film" and "layer". For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0037] Also, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and, for example, a "terminal" can be part of "wiring" or "electrode". Also, terms such as "electrode", "wiring", "terminal", etc. may be replaced with terms such as "region" in some cases.

[0038] Also, in this specification and the like, terms such as "wiring", "signal line", and "power supply line" can be interchanged with each other depending on the case or the situation. For example, the term "wiring" may be changed to the term "signal line". Also, for example, the term "wiring" may be changed to terms such as "power supply line". Conversely, terms such as "signal line" and "power supply line" may be changed to the term "wiring". Terms such as "power supply line" may be changed to terms such as "signal line". Conversely, terms such as "signal line" may be changed to terms such as "power supply line". Also, the term "potential" applied to the wiring may be changed to terms such as "signal" depending on the case or the situation. Conversely, terms such as "signal" may be changed to the term "potential".

[0039] In this specification and the like, the impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, there are hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements excluding oxygen and hydrogen, etc.

[0040] In this specification and the like, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether current flows or not. Or, a switch refers to a device that has a function of selecting and switching a current path. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, the switch only needs to be able to control current and is not limited to a specific one.

[0041] As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When operating a transistor merely as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, it controls conduction and non-conduction to operate.

[0043] Also, in this specification and the like, "on-current" may refer to the current flowing between the source and the drain when the transistor is in the on state. Also, "off-current" may refer to the current flowing between the source and the drain when the transistor is in the off state.

[0044] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" or "approximately parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" or "approximately perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0045] In this specification and the like, regarding numerical values and measured values, or regarding things, methods, and events that can be converted into numerical values or measured values, when terms such as "identical", "the same", "equal", or "uniform" are used, unless otherwise specified, they shall include an error of plus or minus 20%.

[0046] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Also, when referring to an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0047] Also, in this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Also, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0048] In addition, in this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, when multiple configuration examples are shown within one embodiment, it is possible to appropriately combine the configuration examples with each other.

[0049] Note that the content described in one embodiment (even a part of the content) can be applied to, combined with, or replaced with at least one of the content described in another part of the same embodiment (even a part of the content) and the content described in one or more other embodiments (even a part of the content).

[0050] Note that the content described in the embodiments refers to the content described using various figures in each embodiment (or example) or the content described using the text described in the specification.

[0051] Note that the figure (even a part of it) described in one embodiment can be combined with at least one of another part of the figure, another figure (even a part of it) described in the same embodiment, and the figure (even a part of it) described in one or more other embodiments to form more figures.

[0052] The embodiments described in this specification will be explained with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways and that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention should not be construed as being limited to the content described in the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used for the same part or parts having the same or similar functions among different drawings, and the repeated description may be omitted. Also, for ease of understanding the drawings, in perspective views or top views, etc., the description of some components may be omitted.

[0053] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to its size, aspect ratio, etc. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it can include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0054] In this specification, etc., when the same reference numerals are used for a plurality of elements, especially when it is necessary to distinguish them, a distinguishing reference numeral such as “_1”, “[n]”, “[m,n]”, etc. may be appended to the reference numeral for description. For example, one of the two wirings GL may be described as wiring GL[1], and the other may be described as wiring GL[2].

[0055] (Embodiment 1) In this embodiment, a configuration example and a manufacturing method example of a memory cell 100 that functions as a memory device according to one aspect of the present invention will be described with reference to the drawings.

[0056] <Configuration example of the memory device> FIG. 1A shows a perspective view of a memory cell 100 according to one aspect of the present invention. The memory cell 100 is a memory device having a three-dimensional stacked structure. In FIG. 1A, a part of the memory cell 100 is omitted in order to show the internal structure of the memory cell 100. In the drawings, arrows indicating the X direction, Y direction, and Z direction may be attached. The X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification, etc., one of the X direction, Y direction, or Z direction may be referred to as the “first direction” or “first direction”. Also, another one may be referred to as the “second direction” or “second direction”. Also, the remaining one may be referred to as the “third direction” or “third direction”. In this embodiment, etc., the direction in which the structure 130 described later extends is defined as the Z direction.

[0057] FIG. 1B is a cross-sectional view showing a part of the memory cell 100 shown in FIG. 1A. Further, FIG. 1B is a cross-sectional view of a part of the memory cell 100 viewed from the Y direction. Further, FIG. 1B is a cross-sectional view of the XZ plane passing through the central axis 108. FIG. 2A is a cross-sectional view of the part A1-A2 indicated by the dashed line in FIG. 1B viewed from the Z direction. FIG. 2B is a cross-sectional view of the part B1-B2 indicated by the dashed line in FIG. 1B viewed from the Z direction.

[0058] The memory cell 100 has a plurality of insulators 101 disposed above a substrate (not shown). The plurality of insulators 101 are stacked in order from the substrate side. In the present embodiment and the like, the i-th (i is an integer of 1 or more) insulator 101 is denoted as insulator 101[i]. In FIG. 1B, the insulator 101[i+1] disposed above the insulator 101[i] and the insulator 101[i+2] disposed above the insulator 101[i+1] are shown. Further, a conductor 102 is provided between the insulator 101[i] and the insulator 101[i+1], and a conductor 103 is provided between the insulator 101[i+1] and the insulator 101[i+2]. Note that the insulator 101, the conductor 102, and the conductor 103 extend along the Y direction. Further, the memory cell 100 has an insulator 121 so as to cover the side surfaces of the insulator 101, the conductor 102, and the conductor 103.

[0059] Further, the memory cell 100 has a structure 130. The structure 130 extends in the Z direction along the central axis 108. A perspective view of the structure 130 is shown in FIG. 3. The structure 130 has a columnar shape. In FIG. 3, a part of the structure 130 is omitted in order to show the internal structure of the structure 130. A part of the structure 130 functions as a part of the memory cell 100. Further, as shown in FIGS. 1 and 3, the structure 130 has irregularities on the side surface extending in the Z direction.

[0060] In the present embodiment, the case where the outer peripheral shape of the structure 130 is circular when the structure 130 is viewed from the Z direction is shown, but the outer peripheral shape of the structure 130 may not be circular. For example, it may be a polygon such as a triangle or a quadrangle. Further, the outer peripheral shape of the structure 130 may be composed of a curve, or may be composed of a combination of a curve and a straight line.

[0061] The structure 130 has a region that intersects with the conductor 102 (also referred to as the "intersection R") and a region that intersects with the conductor 103 (also referred to as the "intersection W"). Further, the structure 130 includes an insulator 111, a functional body 112, an insulator 113, a semiconductor 114, a conductor 115, an insulator 116, a semiconductor 117, an insulator 118, and a conductor 119.

[0062] Specifically, the conductor 119 extends in the Z direction along the central axis 108, and the insulator 118 is provided adjacent to the conductor 119. Also, the semiconductor 117 is provided adjacent to the insulator 118. Further, the insulator 116 is provided adjacent to the semiconductor 117.

[0063] Also, in the intersection W of the structure 130, a semiconductor 114 is provided adjacent to the insulator 116, an insulator 113 is provided adjacent to the semiconductor 114, a functional body 112 is provided adjacent to the insulator 113, and an insulator 111 is provided adjacent to the functional body 112. FIG. 2A is a cross-sectional view in a direction perpendicular to the Z direction at the intersection W. In the intersection W, the insulator 111, the functional body 112, the insulator 113, the semiconductor 114, the insulator 116, the semiconductor 117, and the insulator 118 are provided concentrically outside the conductor 119.

[0064] Also, in the intersection R of the structure 130, a conductor 115 is provided adjacent to the insulator 116, a semiconductor 114 is provided adjacent to the conductor 115, and an insulator 113 is provided adjacent to the semiconductor 114. FIG. 2B is a cross-sectional view in a direction perpendicular to the Z direction at the intersection R. In the intersection R, the insulator 113, the semiconductor 114, the conductor 115, the insulator 116, the semiconductor 117, and the insulator 118 are provided concentrically outside the conductor 119.

[0065] In the intersection W, the insulator 111, the functional body 112, the insulator 113, the semiconductor 114, and the conductor 103 function as a transistor WTr. Thus, it can be said that the transistor WTr is formed at the intersection W.

[0066] At the intersection W, the conductor 103 functions as the gate electrode of the transistor WTr. Therefore, the insulator 111, the functional body 112, and the insulator 113 function as the gate insulator of the transistor WTr. The semiconductor 114 functions as the semiconductor in which the channel of the transistor WTr is formed.

[0067] Also, at the intersection W, the conductor 119 may function as the back gate electrode of the transistor WTr. Therefore, the insulator 116, the semiconductor 117, and the insulator 118 may function as the back gate insulator of the transistor WTr. FIG. 2A is also a cross-sectional view of the transistor WTr viewed from the Z direction.

[0068] At the intersection R, the conductor 119, the insulator 118, the semiconductor 117, the insulator 116, and the conductor 115 function as the transistor RTr. Also, the conductor 115, the semiconductor 114, the insulator 113, and the conductor 102 function as the capacitor element Cs. Therefore, it can be said that the transistor RTr and the capacitor element Cs are formed at the intersection R.

[0069] At the intersection R, the conductor 115 functions as the gate electrode of the transistor RTr. Therefore, the insulator 116 functions as the gate insulator. The semiconductor 117 functions as the semiconductor in which the channel of the transistor RTr is formed. Also, the conductor 119 may function as the back gate electrode of the transistor RTr. Therefore, the insulator 118 may function as the back gate insulator of the transistor RTr. FIG. 2B is also a cross-sectional view of the transistor RTr viewed from the Z direction.

[0070] Also, the functional body 112 included in the transistor WTr can function as a charge storage layer. By storing charges in the functional body 112, the threshold voltage of the transistor WTr can be controlled. For example, by increasing the threshold voltage of the transistor WTr, the transistor WTr can be made into a normally-off type transistor.

[0071] The injection of charge into the functional body 112 can be performed from the conductor 103 through the insulator 111. In this case, the insulator 111 functions as an injection layer, and the insulator 113 functions as a blocking layer. Also, the injection of charge into the functional body 112 can be performed from the semiconductor 114 through the insulator 113. In this case, the insulator 113 functions as an injection layer, and the insulator 111 functions as a blocking layer. The thickness of the injection layer when viewed from a direction perpendicular to the Z direction is preferably thinner than that of the blocking layer.

[0072] When the insulator 111 is made of an oxide, the functional body 112 is made of a nitride, and the insulator 113 is made of an oxide, the transistor WTr can be called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistor.

[0073] Also, in a MONOS type transistor, when n-type silicon or p-type silicon is used for the gate electrode, it can be called a SONOS (Silicon Oxide Nitride Oxide Semiconductor) type transistor.

[0074] Similarly, when tantalum nitride is used for the gate electrode and aluminum oxide is used for the blocking layer, it can be called a TANOS (Tantalum nitride Aluminium oxide Nitride Oxide Semiconductor) type transistor.

[0075] Also, when tantalum nitride is used for the gate electrode and hafnium oxide is used for the blocking layer, it can be called a THNOS (Tantalum nitride Hafnium oxide Nitride Oxide Semiconductor) type transistor.

[0076] For the functional body 112 that functions as a charge storage layer, it is preferable to use a material with a smaller bandgap than the insulator 111 and the insulator 113. For example, silicon oxide may be used for the insulator 111 and the insulator 113, and an insulator such as silicon nitride may be used for the functional body 112. When silicon nitride is used for the functional body 112, it is preferable to use silicon-rich silicon nitride. For example, when silicon nitride is used for the insulator 111 and the insulator 113, for the functional body 112, silicon nitride with a higher silicon content than the silicon nitride used for the insulator 111 and the insulator 113 may be used.

[0077] Also, the functional body 112 that functions as a charge storage layer may be a semiconductor. For example, a semiconductor such as silicon may be used for the functional body 112. A transistor WTr using a semiconductor for the functional body 112 can be called a FG (Floating Gate) type transistor.

[0078] The insulator 111, the functional body 112, and the insulator 113 may each be a stack of multiple layers. For example, the insulator that functions as a block layer may be a stack of silicon oxide and aluminum oxide.

[0079] FIG. 4A shows an equivalent circuit diagram of the memory cell 100. In FIG. 4A, one of the source or drain of the transistor WTr is electrically connected to the semiconductor 114, and the other of the source or drain is electrically connected to the gate of the transistor RTr. The gate of the transistor WTr is electrically connected to the conductor 103. The transistor WTr is a transistor having a charge storage layer between the gate and the semiconductor layer.

[0080] A part of the semiconductor 114 functions as a channel formation region of the transistor WTr. Another part of the semiconductor 114 functions as a source or drain of the transistor WTr. Also, the semiconductor 114 can also function as an electrode or wiring. Also, a part of the conductor 103 functions as the gate of the transistor WTr.

[0081] The transistor RTr shown in FIG. 4A is a transistor having a back gate. In the present embodiment, a part of the conductor 119 functions as the back gate of the transistor RTr. Also, another part of the semiconductor 114 and the conductor 115 function as the gate of the transistor RTr. Also, a part of the conductor 102 functions as the other electrode of the capacitor element Cs. Also, a part of the semiconductor 117 functions as one of the source or drain of the transistor RTr. Also, another part of the semiconductor 117 functions as the other of the source or drain of the transistor RTr. Also, the semiconductor 117 can also function as an electrode or a wiring.

[0082] Also, as shown in FIG. 4B, it is not necessary to provide a back gate for the transistor RTr. FIG. 4B corresponds to an equivalent circuit diagram of the memory cells 100B and 100C described later. Also, as shown in FIG. 4C, a back gate may be provided for the transistor WTr. FIG. 4C shows an example of a circuit configuration in which the back gate of the transistor WTr is electrically connected to the conductor 119, but a conductor electrically connected to the back gate of the transistor WTr may be provided other than the conductor 119. Alternatively, the circuit configuration may be as shown in FIG. 5A or FIG. 5B.

[0083] The conductor 102 functions as one electrode of the capacitor element Cs. The conductor 115 and the semiconductor 114 have another part that functions as the other electrode of the capacitor element Cs. In this specification and the like, a node where the gate of the transistor RTr, the other of the source or drain of the transistor WTr, and the other electrode of the capacitor element Cs are electrically connected is referred to as the node ND.

[0084] FIG. 6 shows a cross-sectional view of a memory string 200 including four memory cells 100 (memory cells 100[1] to 100[4]). The memory string 200 shown in FIG. 6 includes nine layers of insulators 101 (insulators 101[1] to 101[9]), four layers of conductors 102 (conductors 102[1] to 102[4]), and four layers of conductors 103 (conductors 103[1] to 103[4]).

[0085] FIG. 7 shows an equivalent circuit diagram of the memory string 200. The memory string 200 has a configuration in which four memory cells 100 are connected in series. Therefore, the memory string 200 is a NAND-type storage device.

[0086] Also, in an equivalent circuit diagram or the like, in order to clarify that a transistor is an OS transistor, "OS" may be appended to the circuit symbol of the transistor. Similarly, in order to clarify that a transistor is a Si transistor (a transistor using silicon for the semiconductor layer in which a channel is formed), "Si" may be appended to the circuit symbol of the transistor. In FIG. 7, it is shown that the transistor WTr and the transistor RTr are OS transistors.

[0087] In FIG. 7, the transistor WTr, the transistor RTr, and the capacitor element Cs included in the memory cell 100[1] are shown as the transistor WTr[1], the transistor RTr[1], and the capacitor element Cs[1], respectively. The transistors WTr, the transistors RTr, and the capacitor elements Cs included in the memory cells 100[2] to 100[4] are shown in the same manner.

[0088] Note that the number of memory cells 100 included in the memory string 200 is not limited to 4. If the number of memory cells 100 included in the memory string 200 is n, n may be an integer of 2 or more.

[0089] Also, the "configuration in which a plurality of memory cells 100 are connected in series" means that the drain (or source) of the transistor WTr[k] (k is an integer of 1 or more and n or less) included in the memory cell 100[k] is electrically connected to the source (or drain) of the transistor WTr[k+1] included in the memory cell 100[k+1], and the drain (or source) of the transistor RTr[k] included in the memory cell 100[k] is electrically connected to the source (or drain) of the transistor RTr[k+1] included in the memory cell 100[k+1].

[0090] The semiconductor in which the channels of transistor WTr and transistor RTr are formed can be used singly or in combination, such as single-crystalline semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, for example, silicon, germanium, etc. can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductor, nitride semiconductor, etc. may be used.

[0091] Note that the semiconductor used for the transistor may be a stack of semiconductors. When laminating semiconductor layers, semiconductors having different crystal states may be used, or semiconductors made of different semiconductor materials may be used.

[0092] Also, the same material may be used for semiconductor 114 and semiconductor 117, or different materials may be used. For example, both semiconductor 114 and semiconductor 117 may be oxide semiconductors. Also, both semiconductor 114 and semiconductor 117 may be silicon. Also, semiconductor 114 may be an oxide semiconductor and semiconductor 117 may be silicon. Also, semiconductor 114 may be silicon and semiconductor 117 may be an oxide semiconductor.

[0093] In particular, transistor WTr is preferably a transistor using an oxide semiconductor, which is a kind of metal oxide, for the semiconductor layer in which the channel is formed. Since the oxide semiconductor has a bandgap of 2 eV or more, the off-current is extremely small. When an OS transistor is used for transistor WTr, the charge written in node ND (also referred to as "memory node") can be retained for a long time. When an OS transistor is used for the transistor constituting memory cell 100, the memory cell 100 can be called an "OS memory". Also, the memory string 200 including the memory cell 100 can also be called an "OS memory".

[0094] A NAND-type storage device including an OS memory is also referred to as an "OS NAND-type" or "OS NAND-type storage device". Further, an OS NAND-type storage device having a configuration in which a plurality of OS memories are stacked in the Z direction is also referred to as a "3D OS NAND-type" or "3D OS NAND-type storage device".

[0095] Further, the transistor RTr may be a transistor using silicon for the semiconductor layer in which a channel is formed (also referred to as a "Si transistor"). The transistor RTr may be formed of a Si transistor, and the transistor WTr may be formed of an OS transistor. FIG. 8 shows an equivalent circuit diagram of the memory string 200 when an OS transistor is used as the transistor WTr and a Si transistor is used as the transistor RTr.

[0096] The OS memory can retain information written over a period of one year or more, and even ten years or more, even when the power supply is stopped. Therefore, the OS memory can also be regarded as a non-volatile memory.

[0097] Further, since the amount of charge written in the OS memory hardly changes over a long period of time, the OS memory can retain not only binary (1-bit) but also multi-valued (multi-bit) information.

[0098] Further, since the OS memory writes charges to the node via an OS transistor, a high voltage required in a conventional flash memory is not necessary, and a high-speed write operation can also be realized. Also, an erase operation before data rewriting performed in a flash memory is not necessary in the OS memory. Further, since charge injection and extraction to the floating gate or charge trapping layer are not performed, the OS memory can perform data writing and reading substantially an unlimited number of times. The OS memory has less degradation and higher reliability compared to a conventional flash memory.

[0099] In addition, the OS memory, such as magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), does not involve structural changes at the atomic level during data rewriting. Therefore, the OS memory is more resistant to rewriting than magnetoresistive memory and resistive random access memory.

[0100] Also, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current is less likely to decrease even in a high-temperature environment. A storage device including the OS memory operates stably even in a high-temperature environment and has high reliability. Also, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor for the transistors constituting the semiconductor device, a semiconductor device that operates stably and has good reliability can be realized even in a high-temperature environment.

[0101] As shown in FIG. 9, depending on the purpose or application, etc., an Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr. Also, as shown in FIG. 10, depending on the purpose or application, etc., Si transistors may be used for both the transistor WTr and the transistor RTr.

[0102] By continuously providing a plurality of memory cells 100 in the Z direction, like the memory string 200, the storage capacity per unit area can be increased.

[0103] Also, when it is desired to increase the storage capacity of a semiconductor device using the memory cell 100 or the memory string 200, a plurality of memory cells 100 or a plurality of memory strings 200 may be provided in a staggered pattern (see FIG. 11A) or a lattice pattern (see FIG. 11B). FIG. 11 is a top view of the memory string.

[0104] Table 1 shows a comparison table between a 3D NAND-type storage device fabricated with Si transistors and a 3D OS NAND-type storage device.

[0105]

Table 1

[0106] 〔Modification Example〕 Subsequently, a modification example of the memory cell 100 will be described. The modification examples of the memory cell described below can be appropriately combined with other memory cells shown in this specification and the like.

[0107] FIG. 12A shows a cross-sectional view of the memory cell 100A. The memory cell 100A is a modification example of the memory cell 100. Therefore, in this embodiment and the like, the differences between the memory cell 100A and the memory cell 100 will be mainly described.

[0108] A memory cell according to an aspect of the present invention may be provided with a semiconductor 114 adjacent to an insulator 116, a conductor 115 adjacent to the semiconductor 114, and an insulator 113 adjacent to the conductor 115 at an intersection R, like the memory cell 100A shown in FIG. 12A.

[0109] In the memory cell 100A, the conductor 119, the insulator 118, the semiconductor 117, the insulator 116, the semiconductor 114, and the conductor 115 function as a transistor RTr. The semiconductor 114 may function as a gate electrode. Also, the semiconductor 114 may function as a gate insulator. Further, the conductor 115, the insulator 113, and the conductor 102 function as a capacitor element Cs.

[0110] FIG. 12B shows a cross-sectional view of the memory cell 100B. The memory cell 100B is a modification example of the memory cell 100. As in the memory cell 100B, the formation of the conductor 119 that functions as a back gate may be omitted and filled with the insulator 118. By not providing the conductor 119, the manufacturing process can be simplified and the productivity of the memory device can be improved.

[0111] Fig. 13 shows a cross-sectional view of the memory cell 100C. The memory cell 100C is a modified example of the memory cell 100 and also a modified example of the memory cell 100B. Like the memory cell 100C, the formation of the conductor 119 that functions as a back gate may be omitted, and the region where the conductor 119 is planned to be formed may be made into a cavity 120 without filling it. By providing no conductor 119 and making it a cavity, the manufacturing process can be simplified, and the productivity of the memory device can be further enhanced.

[0112] [Constituent Materials of Memory Cell] Subsequently, the constituent materials that can be used for the memory cell 100 and the like will be described.

[0113] [Substrate] The memory cell 100 and the memory string 200 can be provided on a substrate. As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, and the like. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, gallium nitride (GaN), and the like. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Or, those with elements provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0114] [Insulator] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. that have insulating properties.

[0115] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it becomes possible to lower the operating voltage during transistor operation while maintaining the physical film thickness. On the other hand, for the insulator that functions as the interlayer film, by using a material with a low relative permittivity, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is advisable to select the material according to the function of the insulator.

[0116] Examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0117] Examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0118] In addition, the OS transistor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0119] In the present specification and the like, "oxynitride" refers to a material having a higher oxygen content than nitrogen as a main component. For example, "silicon oxynitride" refers to a material containing silicon, nitrogen, and oxygen, with a higher oxygen content than nitrogen. Also, in the present specification and the like, "nitroxide" refers to a material having a higher nitrogen content than oxygen as a main component. For example, "aluminum oxynitride" refers to a material containing aluminum, nitrogen, and oxygen, with a higher nitrogen content than oxygen.

[0120] When an oxide semiconductor is used for the semiconductor 114 and / or the semiconductor 117, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the semiconductor 114 and / or the semiconductor 117, the oxygen deficiency of the semiconductor 114 and / or the semiconductor 117 can be compensated.

[0121] Also, an insulating layer formed of the above material may be used as a single layer, or a plurality of insulating layers formed of the above material may be stacked and used.

[0122] For example, when providing an insulator in contact with a conductor, in order to prevent oxidation of the conductor, it is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator. For example, it is preferable to use hafnium oxide, aluminum oxide, silicon nitride, or the like as the insulator.

[0123] Also, when laminating and providing an insulator adjacent to a conductor, it is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator in contact with the conductor. For example, an insulator in contact with the conductor may be formed using hafnium oxide, and an insulator using silicon oxynitride may be formed in contact with the insulator.

[0124] [Conductor] As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. is preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Also, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Also, a semiconductor having a high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0125] Also, a single conductive layer formed of the above material may be used as the conductor, or a plurality of conductive layers formed of the above material may be laminated and used. For example, a laminated structure combining the material containing the above-described metal element and the conductive material containing oxygen may be used. Further, a laminated structure combining the material containing the above-described metal element and the conductive material containing nitrogen may be used. Further, a laminated structure combining the material containing the above-described metal element, the conductive material containing oxygen, and the conductive material containing nitrogen may be used.

[0126] In addition, when an oxide semiconductor, which is a kind of metal oxide, is used in the channel formation region of the transistor, it is preferable to use a laminated structure combining the material containing the above-described metal element and the conductive material containing oxygen as the conductor functioning as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0127] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the oxide semiconductor in which the channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the oxide semiconductor in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0128] [Oxide semiconductor] As the semiconductor 114 and / or the semiconductor 117, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. In particular, it is preferable to use an oxide semiconductor for the semiconductor 114. Hereinafter, the oxide semiconductor applicable to the memory cell 100 will be described.

[0129] The oxide semiconductor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Also, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0130] Here, consider the case where the oxide semiconductor is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is one or more selected from aluminum, gallium, yttrium, and tin. Applicable elements for other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0131] 〔Classification of crystal structure〕 First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 14A. FIG. 14A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0132] As shown in Fig. 14A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". In addition, "Amorphous" includes completely amorphous. In addition, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". In addition, "Crystal" includes single crystal and poly crystal.

[0133] Note that the structure within the thick frame shown in Fig. 14A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as an energetically unstable "Amorphous" or a structure completely different from "Crystal".

[0134] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, Fig. 14B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Fig. 14B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 14B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In addition, the thickness of the CAAC-IGZO film shown in Fig. 14B is 500 nm.

[0135] As shown in FIG. 14B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating clear crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in FIG. 14B, the peak near 2θ = 31° is asymmetric about the axis of the angle at which the peak intensity is detected.

[0136] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 14C. FIG. 14C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 14C is near In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0137] As shown in FIG. 14C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0138] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 14A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) and nc-OS (nanocrystalline Oxide Semiconductor). Also, the non-single crystal oxide semiconductor includes polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0139] Next, the details of the above-described CAAC-OS, nc-OS, and a-like OS will be described.

[0140] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and in the plurality of crystal regions, the c-axis is oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that strain refers to a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0141] Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0142] Also, in an In-M-Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Thus, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0143] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal element constituting the CAAC-OS.

[0144] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0145] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0146] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to the capture of carriers. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that to form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0147] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to crystal grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0148] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also called nano-crystals. Also, nc-OS does not show regularity in the crystal orientation between different nano-crystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also called limited field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nano-crystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also called nano-beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nano-crystals (for example, 1 nm or more and 30 nm or less) is performed on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0149] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0150] [Constitution of Oxide Semiconductor] Next, the details of the above-mentioned CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0151] [CAC-OS] The CAC-OS is, for example, a constituent of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0152] Furthermore, the CAC-OS is a structure in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0153] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0154] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0155] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0156] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0157] When CAC-OS is used in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily to endow CAC-OS with a switching function (on / off function). That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximally enhanced. Therefore, by using CAC-OS in a transistor, a high on-current (I on )、high field-effect mobility (μ), and good switching operation can be realized.

[0158] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0159] [Transistor having an oxide semiconductor] Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0160] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0161] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 or less, more preferably 1×10 17 cm -3 or less, even more preferably 1×10 16 cm -3 or less, even more preferably 1×10 13 cm -3 or less, even more preferably 1×10 12 cm-3 It is more preferable that it is less than that. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. Further, being highly pure intrinsic or substantially highly pure intrinsic may be referred to as type i or substantially type i.

[0162] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0163] In addition, the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is long, and it may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0164] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

[0165] 〔Impurity〕 Here, the influence of each impurity in the oxide semiconductor will be described.

[0166] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0167] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0168] In addition, in an oxide semiconductor, when nitrogen is contained, carriers, i.e., electrons, are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, when nitrogen is contained in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17atoms / cm 3 Make it as follows.

[0169] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is made less than 1×10 20 atoms / cm 3 less than, preferably less than 5×10 19 atoms / cm 3 less than, more preferably less than 1×10 19 atoms / cm 3 less than, even more preferably less than 5×10 18 atoms / cm 3 less than, even more preferably less than 1×10 18 atoms / cm 3 Make it less than.

[0170] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0171] 〔Other semiconductor materials〕 The semiconductor materials that can be used for the semiconductor 114 and the semiconductor 117 are not limited to the above-described oxide semiconductors. As the semiconductor 114 and the semiconductor 117, a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) may be used as the semiconductor material. In particular, it is preferable to use a layer material that functions as a semiconductor as the semiconductor material.

[0172] In this specification and the like, the layer material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0173] Examples of the layer material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16 and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0174] As the semiconductor material used in the semiconductor device according to one aspect of the present invention, for example, a transition metal chalcogenide that functions as a semiconductor may be used. Specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be mentioned.

[0175] 〔Regarding the film formation method〕 The formation of conductors, insulators, and semiconductors can be performed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0176] Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, and the like. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

[0177] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0178] Also, the ALD method is a film-forming method capable of reducing plasma damage to the object to be processed. Also, since plasma damage does not occur during film formation in the ALD method, a film with few defects can be obtained.

[0179] Unlike film-forming methods in which particles emitted from a target or the like are deposited, the CVD method and the ALD method are film-forming methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is hardly affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film-forming rate, it may be preferably used in combination with other film-forming methods such as the CVD method with a high film-forming rate.

[0180] In the CVD method and the ALD method, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Also, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, compared with the case of forming a film using a plurality of film-forming chambers, the time required for film formation can be shortened by the time required for transfer and pressure adjustment. Therefore, it may be possible to improve the productivity of semiconductor devices.

[0181] Also, in the ALD method, the inside of the chamber may be under atmospheric pressure or reduced pressure, and the source gases for the reaction may be sequentially introduced into the chamber, and film formation may be performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced simultaneously or after the first source gas so that the plurality of types of source gases do not mix, and then the second source gas is introduced. When introducing an inert gas simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when introducing the second source gas. Also, instead of introducing an inert gas, the first source gas may be exhausted by vacuum pumping and then the second source gas may be introduced. The first source gas adsorbs on the surface of the substrate to form a first thin layer, and reacts with the second source gas introduced later, and the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached while controlling the sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing fine FETs.

[0182] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. Moreover, it is not limited to these combinations, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0183] For example, when forming a hafnium oxide film by a film forming apparatus using ALD, two types of gases, a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizing agent, are used. Also, as other materials, there are tetrakis(ethylmethylamide)hafnium and the like.

[0184] For example, when forming an aluminum oxide film by a film forming apparatus using ALD, two types of gases, a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent, are used. Also, as other materials, there are tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

[0185] For example, when forming a silicon oxide film by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film-forming surface, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbate.

[0186] For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF6 gas and H2 gas are sequentially and repeatedly introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0187] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In-O layer, and then Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed oxide layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed using these gases. Note that H2O gas obtained by bubbling water with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(C2H5)2 gas may be used instead of Zn(CH3)2 gas.

[0188] <Example of manufacturing method of memory device> Next, an example of the manufacturing method of the memory cell 100 will be described.

[0189] First, a laminate 140 shown in FIG. 15A is manufactured. The laminate 140 includes an insulator 101, a conductor 102, and a conductor 103. The insulator 101[i] is disposed above a substrate (not shown), the conductor 102 is disposed on the insulator 101[i], the insulator 101[i + 1] is disposed on the conductor 102, the conductor 103 is disposed on the insulator 101[i + 1], and the insulator 101[i + 2] is disposed on the conductor 103.

[0190] As the insulator 101, a material with a reduced impurity concentration such as water or hydrogen is preferred. For example, the desorption amount per unit area of hydrogen molecules in the insulator 101 is 2×10 15 molecules / cm 2 or less, preferably 1×10 15 molecules / cm 2 or less, more preferably 5×10 14 molecules / cm 2 or less in the temperature range of 50°C or higher and 500°C or lower in the temperature programmed desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). Also, as the insulator 101, an insulator that releases oxygen upon heating may be used. However, the materials applicable to the insulator 101 are not limited to the above description.

[0191] Note that the insulator 101 may have a laminated structure of a plurality of insulators. For example, the insulator 101 may be a laminate of hafnium oxide and silicon oxynitride. Among the plurality of insulators constituting the insulator 101, it is preferable to use an insulator having the function of suppressing the permeation of oxygen for the insulator in contact with the conductor 103.

[0192] Next, a resist mask is formed on the laminate 140, and by an etching process using the resist mask as a mask, a part of the insulator 101, the conductor 103, and the conductor 102 is removed to form an opening 131 in the laminate 140 (see FIG. 15B).

[0193] The formation of the resist mask can be performed by appropriately using, for example, a lithography method, a printing method, an inkjet method, etc. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost may be reduced in some cases. Also, for the etching process, either a dry etching method or a wet etching method may be used, or both may be used. Processing by the dry etching method is suitable for microfabrication.

[0194] In the formation of a resist mask by lithography, first, a resist is formed, and then the resist is exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask.

[0195] By performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing a resist using a KrF excimer laser beam, an ArF excimer laser beam, EUV (Extreme Ultraviolet) light, or the like. Further, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between a substrate and a projection lens for exposure. Instead of the light described above, an electron beam or an ion beam may also be used. Note that when an electron beam or an ion beam is used, a photomask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process.

[0196] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material.

[0197] As a dry etching apparatus for performing etching processing by a dry etching method, for example, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power source to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency power sources to one of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0198] Next, a part of the conductor 103 exposed on the side surface of the opening 131 is etched to retract the conductor 103 from the side surface of the opening 131 (see FIG. 16A). The etching of the conductor 103 may be performed under conditions where a selectivity ratio with respect to the insulator 101 and the conductor 102 can be obtained.

[0199] Next, an insulator 111 is formed along the side surface of the opening 131 (see FIG. 16B). The surfaces of the insulator 101, the conductor 103, and the conductor 102 exposed in the opening 131 are covered with the insulator 111. As the insulator 111, for example, silicon oxide is used. Note that the insulator 111 may have a laminated structure of a plurality of insulators.

[0200] Next, a functional body 112 is formed along the surface of the insulator 111 (see FIG. 17A). As the insulator 111, for example, silicon nitride is used. Note that the functional body 112 may have a laminated structure of a plurality of insulators.

[0201] Next, a part of the insulator 111 and the functional body 112 in the opening 131 is etched. The insulator 111 and the functional body 112 are etched except for the part that overlaps with the insulator 101 when viewed from the Z direction (see Fig. 17B).

[0202] Next, a part of the conductor 102 exposed on the side surface of the opening 131 is etched to retract the conductor 102 from the side surface of the opening 131 (see Fig. 18A). The etching of the conductor 102 may be performed under conditions where a selectivity ratio with the insulator 101 and the conductor 103 can be obtained.

[0203] Next, an insulator 113 is formed along the side surface of the opening 131 (see Fig. 18B). The surfaces of the insulator 101, the insulator 111, the functional body 112, and the conductor 102 exposed in the opening 131 are covered with the insulator 113.

[0204] When an oxide semiconductor is used for the semiconductor 114, for example, silicon oxide, silicon oxynitride, etc. may be appropriately used as the insulator 113. By providing an oxygen-containing insulator in contact with the semiconductor 114, oxygen vacancies in the semiconductor 114 can be reduced, and the reliability of the transistor can be improved.

[0205] Specifically, as the insulator 113, it is preferable to use an oxide material in which some oxygen is desorbed by heating, in other words, an insulator material having an excess oxygen region. The oxide that desorbs oxygen by heating means that in TDS analysis, the desorption amount of oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less. Note that the insulator 113 may have a laminated structure of a plurality of insulators.

[0206] After the formation of the insulator 113, an oxygen addition treatment described later may be performed.

[0207] Next, a semiconductor 114 and a conductor 115 are formed along the side surface of the opening 131 (see FIG. 18B). In the present embodiment, an oxide semiconductor having a composition of In:Ga:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof is used as the semiconductor 114.

[0208] Note that, as the semiconductor material used for the semiconductor 114, for example, metal oxides having compositions of In:Ga:Zn = 4:2:3 to 4.1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:3, or In:Ga:Zn = 10:1:3 and compositions in the vicinity thereof may be used. Further, as the semiconductor material used for the semiconductor 114, metal oxides having compositions of In:Zn = 5:1 or In:Zn = 10:1 and compositions in the vicinity thereof may be used. Further, indium oxide may be used for the semiconductor 114.

[0209] Further, the semiconductor 114 may have a multilayer stacked structure. For example, the semiconductor 114 may be a stack of a metal oxide having a composition of In:Ga:Zn = 1:3:4, In:Ga:Zn = 1:3:2, or In:Ga:Zn = 1:1:1 and a composition in the vicinity thereof, and a metal oxide having a composition of In:Ga:Zn = 4:2:3 to 4.1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:3, or In:Ga:Zn = 10:1:3 and compositions in the vicinity thereof.

[0210] Further, the semiconductor 114 may have a three-layer structure in which a metal oxide having a composition of In:Ga:Zn = 1:3:4, In:Ga:Zn = 1:3:2, or In:Ga:Zn = 1:1:1 and a composition in the vicinity thereof is sandwiched between two layers of the same, and a metal oxide having a composition of In:Ga:Zn = 4:2:3 to 4.1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 5:1:6, In:Ga:Zn = 5:1:3, or In:Ga:Zn = 10:1:3 and compositions in the vicinity thereof.

[0211] Also, during the manufacturing process of the memory cell, it is preferable to perform heat treatment with the surface of the semiconductor 114 exposed. The heat treatment may be performed, for example, at 100°C or higher and 600°C or lower, more preferably at 350°C or higher and 550°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the semiconductor 114 to reduce oxygen vacancies (V O ). The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0212] Note that by performing a process of supplying oxygen to the semiconductor 114 (also referred to as "oxygen addition treatment"), the oxygen vacancies in the semiconductor 114 are repaired by the supplied oxygen, in other words, the reaction of "V O +O→null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the semiconductor 114, the hydrogen can be removed (dehydrated) as H2O. Thereby, it is possible to suppress the recombination of the hydrogen remaining in the semiconductor 114 with oxygen vacancies to form V O H.

[0213] In addition, an oxygenation treatment can be performed by performing microwave treatment in an atmosphere containing oxygen. In this case, the semiconductor 114 is irradiated with microwaves, high-frequency waves such as RF, oxygen plasma, oxygen radicals, etc. For the microwave treatment, it is preferable to use a microwave treatment apparatus having a power source for generating high-density plasma using microwaves. Further, the microwave treatment apparatus may have a power source for applying RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. Also, by applying RF to the substrate (not shown) side, oxygen ions generated by the high-density plasma can be efficiently guided into the aperture 131. Further, the above microwave treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. Also, the oxygen flow ratio O2 / (O2+Ar) is preferably 50% or less, preferably 10% or more and 30% or less. Also, the treatment temperature may be 750 °C or less, preferably 500 °C or less, for example, about 400 °C. Further, after performing the oxygen plasma treatment, heat treatment may be continuously performed without exposing to the outside air.

[0214] Due to the action of plasma, microwaves, etc., the V O H contained in the semiconductor 114 can be cleaved, and hydrogen H can be removed from the semiconductor 114. That is, in the semiconductor 114, "V O H→H+V O )", and further, the reaction "V O +O→null" occurs, and the hydrogen concentration of the semiconductor 114 can be reduced. Therefore, oxygen vacancies and V O H in the semiconductor 114 can be reduced, and the carrier concentration can be decreased.

[0215] After forming the semiconductor 114, a conductor 115 is formed. In the present embodiment, tungsten is formed as the conductor 115.

[0216] Next, a part of the conductor 115 in the opening 131 is etched. The conductor 115 is etched except for the part that overlaps the semiconductor 114 when viewed from the Z direction (see Fig. 19A). As a result, the semiconductor 114 and the conductor 115 are exposed in the opening 131. An oxygen addition treatment may be performed after the semiconductor 114 and the conductor 115 are exposed.

[0217] Next, an insulator 116 is formed along the side surface of the opening 131 (see Fig. 19B). The surfaces of the semiconductor 114 and the conductor 115 exposed in the opening 131 are covered with the insulator 116. When an oxide semiconductor is used for the semiconductor 114, for example, silicon oxide, silicon oxynitride, etc. may be appropriately used as the insulator 116. By providing an oxygen-containing insulator in contact with the semiconductor 114, oxygen deficiency in the semiconductor 114 can be reduced, and the reliability of the transistor can be improved. As the insulator 116, the same material as the insulator 113 may be used. The insulator 116 may have a laminated structure of a plurality of insulators.

[0218] In particular, when an oxide semiconductor is used for the semiconductor 114 and the semiconductor 117, the insulator 116 is preferably an insulator having a region containing oxygen that can be desorbed by heating. Also, the insulator 116 may have a laminated structure of a plurality of insulators. For example, when an oxide semiconductor is used for the semiconductor 114 and the semiconductor 117, the insulator 116 may have a three-layer structure of silicon oxide or silicon oxynitride, hafnium oxide or aluminum oxide, and silicon oxide or silicon oxynitride. That is, a structure in which one layer of hafnium oxide or aluminum oxide is sandwiched between two layers of silicon oxide or silicon oxynitride may be used. Note that the insulator 116 may have a two-layer laminated structure or a laminated structure of four or more layers.

[0219] An oxygen addition treatment may be performed after the formation of the insulator 116 (see Fig. 20A).

[0220] Next, a semiconductor 117 is formed along the side surface of the opening 131 (see FIG. 20B). The surface of the insulator 116 exposed in the opening 131 is covered with the semiconductor 117. When an oxide semiconductor is used for the semiconductor 117, an oxygen addition treatment may be performed in the same manner as when an oxide semiconductor is used for the semiconductor 114.

[0221] Next, an insulator 118 is formed along the side surface of the opening 131 (see FIG. 21A). The surface of the semiconductor 117 exposed in the opening 131 is covered with the insulator 118. When an oxide semiconductor is used for the semiconductor 117, for example, silicon oxide, silicon oxynitride, or the like may be appropriately used as the insulator 118. By providing an oxygen-containing insulator in contact with the semiconductor 117, oxygen deficiency in the semiconductor 117 can be reduced, and the reliability of the transistor can be improved. As the insulator 118, a material similar to the insulator 113 or the insulator 116 may be used.

[0222] The insulator 118 may have a stacked structure of a plurality of insulators. When an oxide semiconductor is used for the semiconductor 117, among the plurality of insulators constituting the insulator 118, it is preferable to use an insulator having a region containing oxygen that desorbs by heating for the insulator in contact with the semiconductor 117. Also, it is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator in contact with the conductor 119. For example, among the plurality of insulators constituting the insulator 118, silicon oxide or silicon oxynitride may be used as the insulator in contact with the semiconductor 117. Also, among the plurality of insulators constituting the insulator 118, hafnium oxide or aluminum oxide may be used as the insulator in contact with the conductor 119.

[0223] Alternatively, for example, the insulator 118 may be a laminate of silicon oxide or silicon oxynitride, aluminum oxide, and silicon nitride. When silicon nitride is used for the insulator 118, it is preferable to use silicon nitride having a low hydrogen content.

[0224] Next, a conductor 119 is formed after the insulator 118 is formed (see Fig. 21B). In this embodiment, tungsten is used as the conductor 119. Note that the conductor 119 may have a stacked structure of a plurality of conductors. Among the plurality of conductors constituting the conductor 119, it is preferable to use a conductive material that is less likely to be oxidized for the conductor in contact with the insulator 118. For example, titanium nitride may be used as the conductor in contact with the insulator 118 among the conductors 119. For example, the conductor 119 may be a stack of titanium nitride and tungsten.

[0225] In this way, the structure 130 is formed in the opening 131. Next, a part of the laminate 140 is removed in a region that does not overlap with the structure 130 when viewed from the Z direction to form a region 132 (see Fig. 22A). The region 132 can be formed in the same manner as the opening 131. In the region 132, the side surfaces of the insulator 101, the conductor 102, and the conductor 103 are exposed.

[0226] Next, an insulator 121 that covers the exposed side surfaces of the insulator 101, the conductor 102, and the conductor 103 is formed (see Fig. 22B). As the insulator 121, it is preferable to use an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, aluminum oxide or the like may be used as the insulator 121.

[0227] Note that the insulator 121 may have a stacked structure of a plurality of insulators. For example, the insulator 121 may be a stack of hafnium oxide and silicon oxynitride. Among the plurality of insulators constituting the insulator 121, it is preferable to use an insulator having a function of suppressing the permeation of oxygen for the insulator in contact with the conductor 102 and the conductor 103.

[0228] In this way, the memory cell 100 can be manufactured.

[0229] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0230] (Embodiment 2) In this embodiment, a circuit configuration example and an operation method example of a semiconductor device 300 including a plurality of memory strings 200 will be described with reference to the drawings.

[0231] <Circuit configuration example> The circuit configuration of the semiconductor device 300 will be described with reference to FIG. 23. The semiconductor device 300 has m memory strings 200. In this embodiment and the like, the first memory string 200 is denoted as memory string 200[1], and the m-th memory string 200 is denoted as memory string 200[m] (m is an integer of 1 or more). Also, the j-th memory string 200 is denoted as memory string 200[j] (j is an integer of 1 or more and m or less).

[0232] Also, as described in the above embodiment, the memory string 200 has n memory cells 100. In FIG. 23, the memory cell 100 having the circuit configuration shown in FIG. 4A is shown as the memory cell 100, but the memory cell 100 having the circuit configurations shown in FIGS. 4B, 4C, 5A, and 5B may also be used. In this embodiment and the like, the k-th (k is an integer of 1 or more and n or less) memory cell 100 included in the j-th memory string 200 is denoted as memory cell 100[k, j].

[0233] The semiconductor device 300 shown in FIG. 23 has n wiring lines WWL, n wiring lines RWL, m wiring lines WBL, m wiring lines RBL, and m wiring lines BGL. In this embodiment and the like, the k-th wiring line WWL and the wiring line RWL are denoted as wiring line WWL[k] and wiring line RWL[k], respectively. Also, the j-th wiring line WBL, wiring line RBL, and wiring line BGL are denoted as wiring line WBL[j], wiring line RBL[j], and wiring line BGL[j], respectively.

[0234] The wiring WWL[1] is electrically connected to the gates (conductors 103) of the transistors WTr included in each of the memory cells 100[1,1] to 100[1,m]. The wiring WWL[k] is electrically connected to the gates (conductors 103) of the transistors WTr included in each of the memory cells 100[k,1] to 100[k,m]. The wiring WWL[n] is electrically connected to the gates (conductors 103) of the transistors WTr included in each of the memory cells 100[n,1] to 100[n,m].

[0235] The wiring RWL[1] is electrically connected to the capacitor elements Cs included in each of the memory cells 100[1,1] to 100[1,m]. The wiring RWL[k] is electrically connected to the capacitor elements Cs included in each of the memory cells 100[k,1] to 100[k,m]. The wiring RWL[n] is electrically connected to the capacitor elements Cs included in each of the memory cells 100[n,1] to 100[n,m]. The wiring RWL is electrically connected to the gate (conductor 115) of the transistor RTr via the capacitor element Cs.

[0236] The wiring WBL[1] is electrically connected to one of the source or drain (semiconductor 114) of the transistor WTr included in the memory cell 100[n,1]. The wiring WBL[j] is electrically connected to one of the source or drain (semiconductor 114) of the transistor WTr included in the memory cell 100[n,j]. The wiring WBL[m] is electrically connected to one of the source or drain (semiconductor 114) of the transistor WTr included in the memory cell 100[n,m].

[0237] The wiring RBL[1] is electrically connected to one of the source or drain (semiconductor 117) of the transistor RTr included in the memory cell 100[1,1]. The wiring RBL[j] is electrically connected to one of the source or drain (semiconductor 117) of the transistor RTr included in the memory cell 100[1,j]. The wiring RBL[m] is electrically connected to one of the source or drain (semiconductor 117) of the transistor RTr included in the memory cell 100[1,m].

[0238] The wiring BGL[1] is electrically connected to the back gate (conductor 119) of the transistor RTr included in each of the memory cells 100[1,1] to 100[n,1]. The wiring BGL[j] is electrically connected to the back gate (conductor 119) of the transistor RTr included in each of the memory cells 100[1,j] to 100[n,j]. The wiring BGL[m] is electrically connected to the back gate (conductor 119) of the transistor RTr included in each of the memory cells 100[1,m] to 100[n,m].

[0239] The wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0240] Also, in the memory string 200[1] shown in FIG. 23, the region electrically connected to the other of the source or drain of the transistor RTr included in the memory cell 100[1,1] is shown as node N1[1], and the region electrically connected to one of the source or drain of the transistor RTr included in the memory cell 100[n,1] is shown as node N2[1]. Similarly, the nodes N1 and N2 of the memory string 200[j] are shown as nodes N1[j] and N2[j], respectively. Also, the nodes N1 and N2 of the memory string 200[m] are shown as nodes N1[m] and N2[m], respectively.

[0241] <Example of operation method> Next, an example of the operation method of the semiconductor device 300 shown in FIG. 23 will be described. In the present embodiment, an example of the operation of writing data to the memory cell 100 included in the memory string 200[1] and an example of the operation of reading data will be described.

[0242] Note that the low-level potential (Low) and high-level potential (High) used in the following description do not mean specific potentials, and if the wiring is different, the specific potentials may also be different. For example, each of the low-level potential and high-level potential applied to the wiring WWL may be a potential different from the low-level potential and high-level potential applied to the wiring RWL.

[0243] Also, in this example of the operation method, it is assumed that a potential within the range in which the transistors RTr and WTr operate normally is applied to the wiring BGL in advance.

[0244] FIG. 25A is a timing chart for explaining an example of the operation of writing data to the memory string 200[1], and FIG. 25B is a timing chart for explaining an example of the operation of reading data from the memory string 200[1]. The timing chart shown in FIG. 25 shows the changes in the magnitudes of the potentials of the wirings WWL[1], WWL[2], WWL[n - 1], WWL[n], RWL[1], RWL[2], RWL[n - 1], RWL[n], node N1[1], and node N2[1]. Also, the wiring WBL[1] shows the data supplied to the wiring WBL[1].

[0245] Also, FIG. 25A shows an example of writing each of the data D[1] to D[n] to the memory cells 100[1,1] to 100[n,1]. Note that the data D[1] to D[n] can be binary or multi-valued. And the data D[1] to D[n] are assumed to be supplied from the wiring WBL[1].

[0246] Writing data to the memory string 200[1] is sequentially performed from the memory cell 100[n,1] to the memory cell 100[1,1]. Note that after writing data to the memory cell 100[1,1], if an attempt is made to write data to the memory cell 100[2,1], the data held in the memory cell 100[1,1] will be lost when writing data to the memory cell 100[2,1]. Therefore, it is necessary to perform an operation of reading the data written in the memory cell 100[1,1] and saving it in another location.

[0247] In the circuit configuration of the memory string 200, when writing data to the memory cell 100[k,1], in order to prevent rewriting of the data held in the memory cells 100[n,1] to 100[k + 1,1], a low-level potential is supplied to the wirings WWL[n] to WWL[k + 1] to turn off the transistors WTr each of the memory cells 100[n,1] to 100[k + 1,1] has. Thereby, each data held in the memory cells 100[n,1] to 100[k + 1,1] can be protected.

[0248] Also, when writing data to the memory cell 100[k,1], since the data is supplied from the wiring WBL[1], a high-level potential is supplied to the wirings WWL[1] to WWL[k] to turn on the transistors WTr each of the memory cells 100[1,1] to 100[k,1] has sufficiently. Thereby, data can be held in the storage node of the memory cell 100[k,1].

[0249] Note that when writing data to the memory cells 100[1,1] to 100[n,1], since the wiring RBL[1] can be controlled independently, there is no need to set it to a specific potential. For example, the potential of the wiring RBL[1] may be set to a low-level potential. Also, the potentials of the nodes N1[1] and N2[1] may be set to low-level potentials.

[0250] Based on the above, an example of the operation method of the semiconductor device 300 will be described.

[0251] <<Charge injection operation>> An example of a charge injection operation will be described using the timing chart of FIG. 24. First, an operation example of injecting charge into the functional body 112 to increase the threshold voltage of the transistor WTr will be described. In the present embodiment, an operation of injecting charge into the functional body 112 of the transistor WTr included in the memory cell 100[k,j] will be described.

[0252] During period T1, a program potential (Prog) is supplied to the wiring WBL[j]. The program potential is a potential higher than the high-level potential.

[0253] During period T2, a program potential is supplied to the wiring WWL other than the wiring WWL[k]. Also, a low-level potential is supplied to the wiring WWL[k]. Then, charge is injected from the wiring WWL[k] into the functional body 112 through the insulator 111.

[0254] During period T3, a low-level potential is supplied to the wiring WWL and the wiring WBL. The wirings RWL[1] to RWL[n] may have any potential during the charge injection operation, but in the present embodiment, a low-level potential is supplied.

[0255] In this way, charge can be injected into the functional body 112 from the wiring WWL side. The charge injection operation may be performed at the initial startup of the semiconductor device 300. Note that the charge injection operation may be performed every time the semiconductor device 300 is started up, or may be performed at regular intervals. By injecting charge into the functional body 112 to increase the threshold voltage of the transistor WTr, the transistor WTr can be made into a normally-off type transistor. For example, by making the transistor RTr into a normally-on type transistor, a normally-off type transistor and a normally-on type transistor can be separately formed in the memory cell 100.

[0256] <<Writing operation>> An example of a write operation will be described using the timing chart of FIG. 25A. In period T10, the potentials of each of wiring WWL[1] to wiring WWL[n], wiring RWL[1] to wiring RWL[n], wiring WBL[1], node N1[1], and node N2[1] are at a low level potential.

[0257] In period T11, a high level potential is supplied to wiring WWL[1] to wiring WWL[n]. As a result, the transistor WTr included in each of memory cells 100[1,1] to memory cells 100[n,1] is in a sufficient on state. Then, data D[n] is supplied to wiring WBL[1]. Since the transistor WTr included in each of memory cells 100[1,1] to memory cells 100[n,1] is in a sufficient on state, data D[n] is supplied to the storage node of memory cell 100[n,1].

[0258] In period T12, a low level potential is supplied to wiring WWL[n], and a high level potential is continuously supplied to wiring WWL[n - 1] to wiring WWL[1]. As a result, the transistor WTr included in memory cell 100[n,1] is turned off, and the transistors WTr included in each of memory cells 100[n - 1,1] to memory cells 100[1,1] maintain the on state. Then, data D[n - 1] is supplied to wiring WBL[1]. Since the transistors WTr included in each of memory cells 100[n - 1,1] to memory cells 100[1,1] are in a sufficient on state, data D[n - 1] is supplied to the storage node of memory cell 100[n - 1,1]. Also, since the transistor WTr of memory cell 100[n,1] is in the off state, the data D[n] written to memory cell 100[n,1] in period T11 is retained.

[0259] In period T13, in the same manner as in periods T11 and T12, data D[n - 2] to data D[2] are sequentially written to each of memory cells 100[n - 2,1] to memory cells 100[2,1].

[0260] Specifically, the transistors WTr of the memory cells 100[n,1] to 100[k + 1,1] in which data has already been written are turned off, the transistors WTr of the memory cells 100[k,1] to 100[1,1] in which data has not been written are turned on sufficiently, data D[k] is supplied from the wiring WBL, and written to the storage node of the memory cell 100[k,1]. After the writing of the data D[k] to the memory cell 100[k,1] is completed, the transistor WTr of the memory cell 100[k,1] is turned off. Subsequently, the operation of supplying the data D[k - 1] from the wiring WBL[1] and writing it to the storage node of the memory cell 100[k - 1,1] is performed.

[0261] Note that the writing operation when k is 1 will be described in the period T14. In the period T14, low-level potentials are supplied to the wirings WWL[n] to WWL[2], and a high-level potential is continuously supplied to the wiring WWL[1]. As a result, the transistors WTr of the memory cells 100[n,1] to 100[2,1] are turned off, and the transistor WTr of the memory cell 100[1,1] remains turned on. Then, the data D[1] is supplied to the wiring WBL[1]. Since the transistor WTr of the memory cell 100[1,1] is in a sufficiently turned-on state, the data D[1] reaches and is written to the storage node of the memory cell 100[1,1]. Also, since the transistors WTr of the memory cells 100[n,1] to 100[2,1] are turned off, the data D[n] to D[2] held in each of the memory cells 100[n,1] to 100[2,1] are retained.

[0262] In this way, data can be written to the memory cells 100[1,1] to 100[n,1].

[0263] In this embodiment, the write operation has been described by focusing on the memory string 200[1]. However, in the circuit configuration of the semiconductor device 300, when a high-level potential is supplied to the wiring WWL[k], all the transistors WTr electrically connected to the wiring WWL[k] are turned on. Therefore, data writing is performed not only to the memory string 200[1] but also to the memory strings 200[2] to 200[m] simultaneously.

[0264] The memory cell 100 shown in this embodiment is an OS memory. Therefore, the semiconductor device 300 including the memory cell 100 does not require an erase operation before data rewriting, and a high-speed write operation can be realized.

[0265] Also, when writing (rewriting) data to the memory cell 100 close to the wiring WBL, the data write operation to the memory cell 100 on the side farther from the wiring WBL than the said memory cell 100 can be omitted. For example, when writing (rewriting) data to the memory cell 100[1,1], the data write operation to the memory cells 100[2,1] to 100[n,1] can be omitted. Also, when writing data to the memory cell 100[2,1], the data write operation to the memory cells 100[3,1] to 100[n,1] can be omitted.

[0266] By storing data with a high rewrite frequency in the memory cell 100 close to the wiring WBL, the time required for data writing (rewriting) can be shortened. That is, the data writing (rewriting) speed can be increased.

[0267] By operating in this way, a storage device of the OS NAND type (including the 3D OS NAND type) can be operated like a RAM.

[0268] <<Read Operation>> Figure 25B shows an example of reading each of data D[1] to D[n] from memory cells 100[1,1] to 100[n,1]. At this time, in order to maintain the data held in each memory cell 100, the transistor WTr is required to be in the off state. Therefore, during the operation of reading data from memory cells 100[1,1] to 100[n,1], the potentials of wirings WWL[1] to WWL[n] are set to low-level potentials.

[0269] In the circuit configuration of the semiconductor device 300 shown in FIG. 23, when reading data of a specific memory cell 100, after turning on the transistors RTrs of other memory cells 100 sufficiently, the transistor RTr of the memory cell 100 to be read is operated in the saturation region. That is, the magnitude of the current flowing between the source and drain of the transistor RTr of the memory cell 100 to be read is determined according to the voltage between the source and drain and the data held in the memory cell 100 to be read.

[0270] For example, consider the case of reading the data held in the memory cell 100[k,1]. In the read operation, in order to turn on the transistors RTrs of each of the memory cells 100[1,1] to 100[n,1] except for the memory cell 100[k,1] sufficiently, high-level potentials are supplied to the wirings RWL[1] to RWL[n] except for the wiring RWL[k].

[0271] On the other hand, since the transistor RTr of the memory cell 100[k,1] switches between the on state and the off state according to the data held in the memory cell 100[k,1], the potential of the wiring RWL[k] needs to be the same potential as when the data was written to the memory cell 100[k,1]. Here, the potential of the wiring RWL[k] during the write operation and the read operation is considered to be a low-level potential.

[0272] For example, a potential of +3V is applied to node N1[1], and a potential of 0V is applied to node N2[1]. Then, node N2[1] is put in a floating state, and the potential of node N2[1] is measured thereafter. When the potentials of wirings RWL[1] to RWL[n] excluding wiring RWL[k] are set to a high-level potential, the transistors RTr included in each of memory cells 100[1,1] to 100[n,1] excluding memory cell 100[k,1] are in a sufficient on state.

[0273] On the other hand, since the voltage between the source and drain of the transistor RTr included in memory cell 100[k,1] is determined by the potential of the gate of the transistor RTr and the potential of node N1[1], the potential of node N2[1] is determined according to the data held in the storage node of memory cell 100[k,1].

[0274] In this way, the data held in memory cell 100[k,1] can be read out.

[0275] Based on the above, a read operation example will be described using the timing chart of FIG. 25B. In period T20, the potentials of wirings WWL[1] to WWL[n], wirings RWL[1] to RWL[n], wiring WBL, node N1[1], and node N2[1] are all at a low-level potential. In particular, node N2[1] is in a floating state. It is assumed that data D[1] to data D[n] are respectively held in the storage nodes of memory cells 100[1,1] to 100[n,1].

[0276] In period T21, a low-level potential is supplied to wiring RWL[1], and high-level potentials are supplied to wirings RWL[2] to RWL[n]. As a result, the transistors RTr included in each of memory cells 100[2,1] to 100[n,1] are in a sufficient on state. Then, the on / off state of the transistor RTr of memory cell 100[1,1] is determined according to the data D[1] held in the storage node of memory cell 100[1,1].

[0277] Also, a potential VR is supplied to the wiring RBL[1]. As a result, the potential of the node N1[1] becomes VR, and the potential of the node N2[1] is determined according to the potential VR of the node N1[1] and the data held in the memory node of the memory cell 100[1,1]. Here, the potential of the node N2[1] is set to VD[1]. Then, by measuring the potential VD[1] of the node N2[1], the data D[1] held in the memory node of the memory cell 100[1,1] can be read out.

[0278] During the period T22, low-level potentials are supplied to the wirings RWL[1] to RWL[n]. Also, a low-level potential is supplied to the node N2[1], and then the node N2[1] becomes a floating state. That is, during the period T22, the potentials of the wirings RWL[1] to RWL[n] and the node N2[1] are the same as those in the period T20. Note that a potential VR may be continuously supplied to the wiring RBL[1], or a low-level potential may be supplied. In this operation example, it is assumed that the potential VR is continuously supplied to the wiring RBL[1] after the period T21. Therefore, it is assumed that the potential VR is continuously supplied to the node N1[1].

[0279] During period T23, a low-level potential is supplied to wiring RWL[2], and high-level potentials are supplied to wiring RWL[1], wiring RWL[3], and up to wiring RWL[n]. As a result, the transistors RTr included in each of memory cells 100[1,1], 100[3,1], and up to 100[n,1] are in a sufficient on state. Then, the on / off state of the transistor RTr of memory cell 100[2,1] is determined according to the data D[2] held in the storage node of memory cell 100[2,1]. Also, a potential VR is supplied to wiring RBL[1]. As a result, the potential of node N2[1] is determined according to the potential VR of node N1[1] and the data held in the storage node of memory cell 100[2,1]. Here, the potential of node N2[1] is defined as VD[2]. By measuring the potential VD[2] of node N2[1], the data D[2] held in the storage node of memory cell 100[2,1] can be read out.

[0280] In period T24, in the same manner as the read operations in periods T22 and T23, data D[3] to D[n - 1] are sequentially read out from each of memory cells 100[3,1] to 100[n - 1,1].

[0281] Specifically, when reading data D[k] from memory cell 100[k,1], after setting the potential of node N2[1] to a low-level potential and putting node N2[1] in a floating state, a high-level potential is supplied to wirings RWL[1] to RWL[n] excluding wiring RWL[k], turning on transistors RTr of memory cells 100[1,1] to 100[n,1] excluding memory cell 100[k,1] sufficiently, and turning on the transistor RTr of memory cell 100[k,1] to an on state according to data D[k]. Next, by setting the potential of node N1[1] to VR, the potential of node N2[1] becomes a potential according to data D[k], and by measuring this potential, data D[k] can be read. After the reading of data D[k] held in memory cell 100[k,1] is completed, as preparation for the next reading operation, a low-level potential is supplied to wirings RWL[1] to RWL[n], a low-level potential is supplied to node N2[1], and then node N2[1] is put in a floating state.

[0282] During period T25, a low-level potential is supplied to wirings RWL[1] to RWL[n]. Also, a low-level potential is supplied to node N2[1], and then node N2[1] is put in a floating state. That is, during period T25, the potentials of wirings RWL[1] to RWL[n] and node N2[1] each become the same as the situation in period T20.

[0283] During period T26, a low-level potential is supplied to wiring RWL[n], and high-level potentials are supplied to wirings RWL[1] to RWL[n - 1]. As a result, the transistors RTr included in each of memory cells 100[1,1] to 100[n - 1,1] are in a sufficient on state. And the transistor RTr of memory cell 100[n,1] is in an on state according to the data D[n] held in the storage node of memory cell 100[n,1]. Also, potential VR continues to be supplied to wiring RBL[1]. Thereby, the potential of node N2[1] is determined according to the potential VR of node N1[1] and the data held in the storage node of memory cell 100[n,1]. Here, let the potential of node N2[1] be VD[n]. Then, by measuring the potential VD[n] of node N2[1], the data D[n] held in the storage node of memory cell 100[n,1] can be read out.

[0284] In this way, the data held in memory cells 100[1,1] to 100[n,1] can be read out.

[0285] Note that in this embodiment, the read operation has been described by focusing on memory string 200[1]. However, in the circuit configuration of semiconductor device 300, not only memory string 200[1] but also data reading of memory strings 200[2] to 200[m] can be performed simultaneously. Also, by turning off transistor WTr, the data held in the storage node is not damaged even during the data read operation. Therefore, only the data included in an arbitrary memory string 200 can be read out.

[0286] <Structural Example of Semiconductor Device> Next, a structural example of semiconductor device 300 will be described.

[0287] FIGS. 26A to 26C are examples of schematic diagrams showing a part of the semiconductor device 300. FIG. 26A shows a perspective view of a part of the semiconductor device, and FIG. 26B shows a top view of a part of the semiconductor device. Further, FIG. 26C shows a cross-sectional view corresponding to the dashed line Z1-Z2 in FIG. 26B.

[0288] The semiconductor device has a structure in which wiring WL (wiring WWL or wiring RWL) and an insulator (a region not hatched in FIGS. 26A to 26C) are laminated.

[0289] An opening is formed in the structure so as to penetrate the insulator and the wiring WL at once. And, in order to provide the memory cell 100 in the region AR through which the wiring WL penetrates, the structure 130 is formed in the opening.

[0290] In FIG. 26A, the structure 130 inside the structure is shown by a dashed line. The region where the structure 130 is formed is shown as the region SA. Since the memory string 200 is formed along the structure 130, the memory string 200 is formed in the region SA.

[0291] By the way, the region TM where the wiring WL is exposed functions as a connection terminal for applying a potential to the wiring WL. That is, by electrically connecting the wiring WL and the wiring in the region TM, a potential can be applied to the gate of the transistor included in the memory cell 100. Note that the wiring WL corresponds to the conductor 103 or the conductor 102.

[0292] Note that the shape of the region TM is not limited to the configuration example shown in FIGS. 26A to 26C. The configuration of the semiconductor device 300 according to an aspect of the present invention may be, for example, a configuration in which an insulator is formed on the region TM, an opening is provided in the insulator, and a conductor PG is formed so as to fill the opening, as shown in FIGS. 27A to 27C.

[0293] FIG. 27A shows a perspective view of a part of the semiconductor device, and FIG. 27B shows a top view of a part of the semiconductor device. Further, FIG. 27C shows a cross-sectional view corresponding to the dashed-dotted line Z1-Z2 in FIG. 27B. On the conductor PG, a wiring ER is formed, whereby the wiring ER and the wiring WL are electrically connected. In FIG. 27A, the conductor PG provided inside the structure is illustrated by a dashed line.

[0294] <Example of connection to peripheral circuit> In the semiconductor device 300 according to one aspect of the present invention, peripheral circuits such as a read circuit and a precharge circuit may be formed in a lower layer thereof. In this case, Si transistors may be formed on a silicon substrate or the like to constitute the peripheral circuit, and then the semiconductor device 300 according to one aspect of the present invention may be formed on the peripheral circuit. FIG. 28A is a cross-sectional view in which a peripheral circuit is constituted by planar-type Si transistors and the semiconductor device 300 according to one aspect of the present invention is formed on an upper layer thereof. Further, FIG. 29A is a cross-sectional view in which a peripheral circuit is constituted by FIN-type Si transistors and the semiconductor device 300 according to one aspect of the present invention is formed on an upper layer thereof.

[0295] In FIGS. 28A and 29A, the Si transistors constituting the peripheral circuit are formed on a substrate 1700. An element isolation layer 1701 is formed between a plurality of Si transistors. A conductor 1712 is formed as a source and a drain of the Si transistor. The conductor 1730 is formed to extend in the channel width direction and is connected to another Si transistor or the conductor 1712 (not shown).

[0296] As the substrate 1700, the substrates shown in the above embodiments can be used. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

[0297] As the substrate 1700, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a laminated film, paper containing fibrous materials, or a base film may be used. Further, a semiconductor element may be formed using a certain substrate and then the semiconductor element may be transferred to another substrate. FIGS. 28A and 29A show, as an example, an example in which a single crystal silicon wafer is used as the substrate 1700.

[0298] In FIGS. 28A and 29A, in the region SA, conductors 1221, 1222, 1223 provided on the memory string 200, and the insulator 1202 are shown. The conductor 1221 is electrically connected to, for example, the source or drain of the transistor RTr located at the end of the memory string 200.

[0299] The insulator 1202 is provided to cover the conductor 1221. The conductor 1222 is provided so as to be embedded in the insulator 1202 in a region overlapping the conductor 119. The conductor 1223 is provided above the insulator 1202 and is electrically connected to the conductor 119 via the conductor 1222.

[0300] Further, in FIGS. 28A and 29A, an insulator 1203 is formed so as to cover the conductor 1223, the insulator 1202, the memory string 200, etc. As the insulator 1203, it is preferable to use an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. By using an insulator having a function of suppressing the permeation of impurities such as hydrogen in the insulator 1203, the diffusion of impurities from the outside (for example, water molecules, hydrogen atoms, hydrogen molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2)) into the memory string 200 can be suppressed.

[0301] Here, the details of the Si transistor will be described. The planar Si transistor shown in FIG. 28A shows a cross-sectional view in the channel length direction, and the planar Si transistor shown in FIG. 28B shows a cross-sectional view in the channel width direction. The Si transistor includes a channel formation region 1793 provided in a well 1792, a low-concentration impurity region 1794 and a high-concentration impurity region 1795 (collectively also simply referred to as an impurity region), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surfaces of the gate electrode 1790. Note that a metal silicide or the like may be used for the conductive region 1796.

[0302] Also, the FIN-type Si transistor shown in FIG. 29A shows a cross-sectional view in the channel length direction, and the FIN-type Si transistor shown in FIG. 29B shows a cross-sectional view in the channel width direction. The Si transistors shown in FIGS. 29A and 29B have a convex channel formation region 1793, and a gate insulating film 1797 and a gate electrode 1790 are provided along the side surfaces and the upper surface thereof. In the present embodiment, a case where a part of the semiconductor substrate is processed to form a convex portion is shown, but an SOI substrate may be processed to form a semiconductor layer having a convex shape. Note that the reference numerals shown in FIGS. 29A and 29B are the same as those shown in FIGS. 28A and 28B.

[0303] The present embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0304] (Embodiment 3) In the present embodiment, a semiconductor device 400 having a memory device or a semiconductor device according to an aspect of the present invention will be described.

[0305] FIG. 30 shows a block diagram illustrating a configuration example of a semiconductor device 400. The semiconductor device 400 shown in FIG. 30 includes a drive circuit 410 and a memory array 420. The memory array 420 includes one or more memory strings 200. FIG. 30 shows an example in which the memory array 420 includes a plurality of memory strings 200 arranged in a matrix.

[0306] The drive circuit 410 includes a PSW241 (power switch), a PSW242, and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411 (Row Decoder), a control circuit 412 (Control Circuit), and a voltage generation circuit 428.

[0307] In the semiconductor device 400, each circuit, each signal, and each voltage can be appropriately selected or discarded as necessary. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

[0308] Also, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 412.

[0309] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit logically operates signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates control signals for the peripheral circuit 411 so that this operation mode is executed.

[0310] The voltage generation circuit 428 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 428. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 428, and the voltage generation circuit 428 generates a negative voltage.

[0311] The peripheral circuit 411 is a circuit for writing and reading data to and from the memory string 200. The peripheral circuit 411 includes a row decoder 441, a column decoder 442, a row driver 423, a column driver 424, an input circuit 425, an output circuit 426, and a sense amplifier 427.

[0312] The row decoder 441 and the column decoder 442 have a function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying the row to be accessed, and the column decoder 442 is a circuit for specifying the column to be accessed. The row driver 423 has a function of selecting the wiring WL specified by the row decoder 441. The column driver 424 has functions such as writing data to the memory string 200, reading data from the memory string 200, and holding the read data.

[0313] The input circuit 425 has a function of holding the signal WDA. The data held by the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is the data (Din) to be written to the memory string 200. The data (Dout) read by the column driver 424 from the memory string 200 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. In addition, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is the signal RDA.

[0314] PSW241 has a function of controlling the supply of VDD to the peripheral circuit 415. PSW242 has a function of controlling the supply of VHM to the row driver 423. Here, the high power supply voltage of the semiconductor device 400 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW241 is controlled by the signal PON1, and the on / off of PSW242 is controlled by the signal PON2. In FIG. 30, in the peripheral circuit 415, the number of power supply domains to which VDD is supplied is set to 1, but it can also be plural. In this case, a power switch may be provided for each power supply domain.

[0315] The drive circuit 410 and the memory array 420 included in the semiconductor device 400 may be provided on the same plane. Also, as shown in FIG. 31, the drive circuit 410 and the memory array 420 may be provided in an overlapping manner. By providing the drive circuit 410 and the memory array 420 in an overlapping manner, the signal propagation distance can be shortened. Also, in FIG. 31, a perspective view of an enlarged part of the semiconductor device 400 is appended.

[0316] Also, in the semiconductor device 400, an arithmetic processing device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) may be used for the control circuit 412 included in the drive circuit 410. By using a CPU and / or a GPU or the like, a semiconductor device 400 having an arithmetic processing function can be realized.

[0317] As described above, the memory string 200 can function as a RAM. Therefore, a part of the memory array 420 can be made to function as a main memory or a cache memory. Also, as described above, the memory string 200 can function as a flash memory. Therefore, a part of the memory array 420 can be made to function as a flash memory. The semiconductor device 400 according to one aspect of the present invention can function as a universal memory.

[0318] Also, according to one aspect of the present invention, the functions of a CPU, a NAND flash memory, and a cache memory can be fabricated on the same chip.

[0319] The semiconductor device 400 shown in FIG. 31 includes a drive circuit 410 including a CPU and a memory array 420 having a 3D OS NAND type storage device according to one aspect of the present invention. The 3D OS NAND type storage device according to one aspect of the present invention has a function as a cache memory and a function as a flash memory.

[0320] FIG. 32 shows a state in which a host 450 manages a plurality of semiconductor devices 400. Each semiconductor device 400 has an arithmetic processing function and can parallelize writing and reading to and from a flash memory and a cache memory. By the host 450 managing a plurality of semiconductor devices 400, an information processing system that realizes non-Neumann computing can be constructed.

[0321] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0322] (Embodiment 4) In this embodiment, an example of an arithmetic processing device that can include a semiconductor device such as the storage device shown in the above embodiment will be described.

[0323] FIG. 33 shows a block diagram of a central processing unit 1100. FIG. 33 shows a configuration example of a CPU as a configuration example that can be used for the central processing unit 1100.

[0324] The central processing unit 1100 shown in FIG. 33 has, on a substrate 1190, an ALU 1191 (ALU: Arithmetic Logic Unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may have a rewritable ROM and a ROM interface. Also, the cache 1199 and the cache interface 1189 may be provided on a separate chip.

[0325] The cache 1199 is connected via the cache interface 1189 to a main memory provided on a separate chip. The cache interface 1189 has a function of supplying a part of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding the said data.

[0326] The central processing unit 1100 shown in FIG. 33 is merely an example showing a simplified configuration thereof, and the actual central processing unit 1100 has various configurations depending on its application. For example, a configuration including the central processing unit 1100 or the arithmetic circuit shown in FIG. 33 may be regarded as one core, and a configuration including a plurality of such cores each operating in parallel, i.e., a configuration such as a GPU, may be adopted. Also, the number of bits that the central processing unit 1100 can handle with its internal arithmetic circuit and data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0327] Instructions input to the central processing unit 1100 via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0328] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194, during the execution of a program by the central processing unit 1100, determines and processes interrupt requests from external input / output devices and peripheral circuits based on their priorities and mask states. The register controller 1197 generates the addresses of the registers 1196 and reads from and writes to the registers 1196 according to the state of the central processing unit 1100.

[0329] In addition, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0330] In the central processing unit 1100 shown in FIG. 33, a storage device is provided in the registers 1196 and the cache 1199. As the storage device, for example, the storage device shown in the previous embodiment can be used.

[0331] In the central processing unit 1100 shown in FIG. 33, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cells of the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage is performed to the memory cells in the register 1196. When holding data by a capacitive element is selected, data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0332] The semiconductor device 400 and the central processing unit 1100 shown in the above embodiment can be provided overlapping each other. FIGS. 34A and 34B show perspective views of the semiconductor device 1150A. The semiconductor device 1150A has a semiconductor device 400 that functions as a storage device on the central processing unit 1100. The central processing unit 1100 and the semiconductor device 400 have overlapping regions. To make the configuration of the semiconductor device 1150A easy to understand, in FIG. 34B, the central processing unit 1100 and the semiconductor device 400 are shown separately.

[0333] By providing the semiconductor device 400 and the central processing unit 1100 overlapping each other, the connection distance between the two can be shortened. Therefore, the communication speed between the two can be increased. Also, since the connection distance is short, the power consumption can be reduced.

[0334] As shown in the above embodiment, by using an OS NAND type storage device for the semiconductor device 400, some or all of the plurality of memory strings 200 of the semiconductor device 400 can function as a RAM. Therefore, the semiconductor device 400 can function as a main memory. The semiconductor device 400 that functions as a main memory is connected to the cache 1199 via the cache interface 1189.

[0335] Whether the semiconductor device 400 functions as a main memory (RAM) or as a storage is controlled by the control circuit 412 shown in FIG. 30. Based on the signal supplied from the central processing unit 1100, the control circuit 412 can cause part or all of the plurality of memory strings 200 included in the semiconductor device 400 to function as a RAM.

[0336] Of the plurality of memory strings 200, the semiconductor device 400 can cause some of the memory strings 200 to function as a RAM and other memory strings 200 to function as a storage. By using an OS NAND type storage device for the semiconductor device 400, it can have functions as a cache, as a main memory, and as a storage. The semiconductor device 400 according to one aspect of the present invention can function as, for example, a universal memory.

[0337] Also, when the semiconductor device 400 is used as a main memory, its storage capacity can be increased or decreased as needed. Also, when the semiconductor device 400 is used as a cache, its storage capacity can be increased or decreased as needed.

[0338] Also, when moving or replicating data between the area that functions as a storage of the semiconductor device 400 and the area that functions as a main memory, the control circuit 412 shown in FIG. 30 may have a function of performing error detection and correction (also referred to as ECC: Error Check and Correct). Also, when moving or replicating data between the area that functions as a main memory of the semiconductor device 400 and the cache 1199, the control circuit 412 may have a function of performing ECC.

[0339] In addition, a plurality of semiconductor devices 400 may be provided on top of the central processing unit 1100. FIGS. 35A and 35B show perspective views of the semiconductor device 1150B. The semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the central processing unit 1100. The central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. To make the configuration of the semiconductor device 1150B easier to understand, in FIG. 35B, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately.

[0340] The semiconductor devices 400a and 400b function as storage devices. For example, a NOR type storage device may be used as the semiconductor device 400a. Also, a NAND type storage device may be used as the semiconductor device 400b. Both the semiconductor device 400a and the semiconductor device 400b may be NAND type storage devices. Since a NOR type storage device can operate faster than a NAND type storage device, for example, a part of the semiconductor device 400a can also be used as the main memory and / or cache 1199. Note that the stacking order of the semiconductor device 400a and the semiconductor device 400b may be reversed.

[0341] FIGS. 36A and 36B show perspective views of the semiconductor device 1150C. The semiconductor device 1150C has a configuration in which the central processing unit 1100 is sandwiched between the semiconductor device 400a and the semiconductor device 400b. Thus, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. To make the configuration of the semiconductor device 1150C easier to understand, in FIG. 36B, the central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately.

[0342] By adopting the configuration of the semiconductor device 1150C, both the communication speed between the semiconductor device 400a and the central processing unit 1100 and the communication speed between the semiconductor device 400b and the central processing unit 1100 can be increased. Also, the power consumption can be reduced compared to the semiconductor device 1150B.

[0343] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0344] (Embodiment 5) In this embodiment, an example of a semiconductor wafer on which a semiconductor device or the like shown in the above embodiment is formed, and an electronic component in which the semiconductor device is incorporated are shown.

[0345] <Semiconductor Wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 37A.

[0346] The semiconductor wafer 4800 shown in FIG. 37A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion without the circuit portions 4802 is a spacing 4803, which is a dicing region.

[0347] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the side opposite to the side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warpage and the like of the wafer 4801 can be reduced, and miniaturization as a component can be achieved.

[0348] As the next step, a dicing step is performed. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. Note that the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel, a plurality of scribe lines SCL2 are parallel, and the scribe line SCL1 and the scribe line SCL2 are perpendicular in order to facilitate the dicing step.

[0349] By performing a dicing process, a chip 4800a as shown in FIG. 37B can be cut out from a semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately equal to the cut width of the scribe line SCL1 or the cut width of the scribe line SCL2.

[0350] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 37A. For example, a semiconductor wafer having a rectangular shape may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0351] <Electronic component> FIG. 37C shows a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 37C has a chip 4800a in a mold 4711. As the chip 4800a, a storage device or the like according to one aspect of the present invention can be used.

[0352] FIG. 37C omits a part to show the inside of the electronic component 4700. The electronic component 4700 has lands 4712 outside the mold 4711. The lands 4712 are electrically connected to electrode pads 4713, and the electrode pads 4713 are electrically connected to the chip 4800a by wires 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0353] FIG. 37D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). An interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.

[0354] As the semiconductor device 4710, for example, a chip 4800a, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), etc. can be used. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a storage device can be used.

[0355] As the package substrate 4732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. can be used. As the interposer 4731, a silicon interposer, a resin interposer, etc. can be used.

[0356] The interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or a multilayer. Further, the interposer 4731 has a function of electrically connecting an integrated circuit provided on the interposer 4731 to an electrode provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate". Further, a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as the through electrode.

[0357] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation of a silicon interposer can be performed by a semiconductor process, formation of fine wiring, which is difficult in a resin interposer, is easy.

[0358] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, fine and high-density wiring formation is required for the interposer on which HBM is mounted. Therefore, it is preferable to use a silicon interposer for the interposer on which HBM is mounted.

[0359] In addition, in a SiP, an MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer hardly occurs. Further, since the silicon interposer has high flatness on the surface, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer hardly occurs. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0360] Further, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to make the heights of the semiconductor device 4710 and the semiconductor device 4735 uniform.

[0361] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. FIG. 37D shows an example in which the electrodes 4733 are formed of solder balls. By providing solder balls in a matrix pattern at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed of conductive pins. By providing conductive pins in a matrix pattern at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0362] The electronic component 4730 can be mounted on another substrate using various mounting methods not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0363] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0364] (Embodiment 6) In this embodiment, an application example of a storage device according to an aspect of the present invention will be described.

[0365] Generally, in semiconductor devices such as computers, various storage devices are used according to the application. FIG. 38A shows various storage devices used in a semiconductor device by layer. The storage devices located in the upper layer are required to have a faster operating speed, and the storage devices located in the lower layer are required to have a larger storage capacity and a higher recording density. In FIG. 38A, from the top layer in order, a memory mounted as a register in an arithmetic processing device such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory are shown.

[0366] Memory integrated as a register in a computing device such as a CPU is frequently accessed by the computing device because it is used for temporarily storing calculation results, etc. Therefore, a faster operating speed than the storage capacity is required. In addition, the register also has a function of holding setting information of the computing device, etc.

[0367] SRAM is used, for example, as a cache. The cache has a function of replicating and holding a part of the data held in the main memory. By replicating and holding frequently used data in the cache, the access speed to the data can be increased. The storage capacity required for the cache is less than that of the main memory, but a faster operating speed than the main memory is required. In addition, the data rewritten in the cache is replicated and supplied to the main memory.

[0368] DRAM is used, for example, as the main memory. The main memory has a function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 Gbit / mm 2 to 0.3 Gbit / mm 2 is.

[0369] 3D NAND memory is used, for example, as storage. Storage has a function of holding data that needs to be stored long-term, various programs used in the computing device, etc. Therefore, storage requires a larger storage capacity and a higher recording density than the operating speed. The recording density of the storage device used for storage is approximately 0.6 Gbit / mm 2 to 6.0 Gbit / mm 2 is.

[0370] The memory device according to one aspect of the present invention has a high operating speed and can retain data for a long period of time. The memory device according to one aspect of the present invention can be suitably used as a memory device located in a boundary region 901 including both a layer where a cache is located and a layer where a main memory is located. Further, the memory device according to one aspect of the present invention can be suitably used as a memory device located in a boundary region 902 including both a layer where a main memory is located and a layer where a storage is located.

[0371] Further, the memory device according to one aspect of the present invention can be suitably used in both a layer where a main memory is located and a layer where a storage is located. Further, the memory device according to one aspect of the present invention can be suitably used in a layer where a cache is located. FIG. 38B shows the layers of various memory devices different from FIG. 38A.

[0372] In FIG. 38B, in order from the top layer, a memory mixed as a register in an arithmetic processing device such as a CPU, an SRAM used as a cache, and a 3D OS NAND memory are shown. The memory device according to one aspect of the present invention can be used for a cache, a main memory, and a storage. When a high-speed memory of 1 GHz or more is required as a cache, the cache is mixed in an arithmetic processing device such as a CPU.

[0373] The memory device according to one aspect of the present invention can be applied to, for example, memory devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game machines, etc.). It can also be used for image sensors, IoT (Internet of Things), healthcare, etc. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large computers such as server systems.

[0374] An example of an electronic device having a memory device according to an aspect of the present invention will be described. FIGS. 39A to 39J and FIGS. 40A to 40E illustrate how an electronic component 4700 or an electronic component 4730 having the memory device is included in each electronic device.

[0375] [Mobile phone] The information terminal 5500 shown in FIG. 39A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0376] By applying the memory device according to an aspect of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated during the execution of applications.

[0377] [Wearable terminal] In addition, FIG. 39B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0378] Similar to the aforementioned information terminal 5500, the wearable terminal can hold temporary files generated during the execution of applications by applying the memory device according to an aspect of the present invention.

[0379] [Information terminal] In addition, FIG. 39C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0380] The desktop information terminal 5300 can hold temporary files generated during the execution of an application by applying the storage device according to an aspect of the present invention, similar to the information terminal 5500 described above.

[0381] In the above description, smartphones, wearable terminals, and desktop information terminals are exemplified as electronic devices and illustrated in FIGS. 39A to 39C, respectively. However, information terminals other than smartphones, wearable terminals, and desktop information terminals can be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0382] [Home Appliance] In addition, FIG. 39D shows an electric refrigerator-freezer 5800 as an example of a home appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0383] The storage device according to an aspect of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food stored in the electric refrigerator-freezer 5800 and the expiration date of the food to and from an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can hold a temporary file generated when transmitting the information in the storage device.

[0384] In this example, an electric refrigerator-freezer is described as a home appliance. Other home appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, and the like.

[0385] [Game Machine] Further, FIG. 39E shows a portable game machine 5200 which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display unit 5202, buttons 5203, etc.

[0386] Furthermore, FIG. 39F shows a stationary game machine 7500 which is an example of a game machine. The stationary game machine 7500 has a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 39F, the controller 7522 can be provided with a display unit for displaying game images, a touch panel, a stick, a rotary knob, a slide knob, etc. which serve as input interfaces other than buttons. Also, the controller 7522 is not limited to the shape shown in FIG. 39F, and the shape of the controller 7522 may be changed variously according to the genre of the game. For example, in a shooting game such as FPS (First Person Shooter), a controller in the shape of a gun with a trigger as a button can be used. Also, for example, in a music game or the like, a controller in the shape of a musical instrument or a music device can be used. Furthermore, the stationary game machine may be in a form that does not use a controller and instead is provided with a camera, a depth sensor, a microphone, etc. and is operated by the gestures and / or voice of the game player.

[0387] Also, the video of the game machine described above can be output by a display device such as a television set, a personal computer display, a game display, a head-mounted display.

[0388] By applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, a portable game machine 5200 with low power consumption or a stationary game machine 7500 with low power consumption can be realized. In addition, due to the low power consumption, heat generation from the circuit can be reduced, so the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0389] Furthermore, by applying the storage device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, it is possible to hold temporary files and the like necessary for calculations generated during the execution of the game.

[0390] As an example of a game machine, a portable game machine is shown in Fig. 39E. Also, a home stationary game machine is shown in Fig. 39F. Note that the electronic device of one aspect of the present invention is not limited to this. Examples of the electronic device of one aspect of the present invention include, for example, arcade game machines installed in entertainment facilities (such as game centers and amusement parks), and pitching machines for batting practice installed in sports facilities.

[0391] [Mobile object] The storage device described in the above embodiment can be applied to a mobile object, namely an automobile, and the vicinity of the driver's seat of the automobile.

[0392] Fig. 39G shows an automobile 5700 which is an example of a mobile object.

[0393] Around the driver's seat of the automobile 5700, there is an instrument panel that provides various information by displaying a speedometer, tachometer, odometer, fuel gauge, gear state, air conditioner settings, etc. Also, a display device for showing such information may be provided around the driver's seat.

[0394] In particular, the display device can supplement the field of view blocked by a pillar or the like and the blind spot of the driver's seat by projecting the video from an imaging device (not shown) provided in the vehicle 5700, thereby enhancing safety. That is, by displaying an image from an imaging device provided outside the vehicle 5700, the blind spot can be supplemented and safety can be enhanced.

[0395] Since the storage device described in the above embodiment can temporarily hold information, for example, the storage device can be used to hold necessary temporary information in a system for performing an automatic driving system, route guidance, danger prediction, etc. of the vehicle 5700. The display device may be configured to display temporary information such as route guidance and danger prediction. Further, it may be configured to hold the video of a driving recorder provided in the vehicle 5700.

[0396] In the above description, the vehicle is described as an example of the moving body, but the moving body is not limited to the vehicle. For example, examples of the moving body include a train, a monorail, a ship, and an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket).

[0397] [Camera] The storage device described in the above embodiment can be applied to a camera.

[0398] FIG. 39H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0399] By applying the storage device described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0400] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0401] FIG. 39I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0402] When recording the video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the storage device described above, the video camera 6300 can hold temporary files generated during encoding.

[0403] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0404] FIG. 39J is a schematic cross-sectional view showing an example of an ICD. The ICD main body 5400 has at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0405] The ICD main body 5400 is surgically implanted in the body, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0406] The ICD main body 5400 has a function as a pacemaker and paces the heart when the heart rate deviates from the specified range. Also, when the heart rate is not improved by pacing (such as rapid ventricular tachycardia or ventricular fibrillation), treatment by electric shock is performed.

[0407] The ICD main body 5400 needs to constantly monitor the heart rate in order to perform pacing and electric shock appropriately. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Also, the ICD main body 5400 can store in the electronic components 4700 data on the heart rate obtained by the sensor and the like, the number of times and time of treatment by pacing, and the like.

[0408] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, the ICD main body 5400 can have a plurality of batteries, thereby enhancing safety. Specifically, even if some of the batteries of the ICD main body 5400 become inoperable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0409] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. For example, a system for monitoring heart activity may be configured such that physiological signals such as pulse, respiratory rate, heart rate, and body temperature can be confirmed by an external monitoring device.

[0410] [Expansion Device for PC] The storage device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0411] FIG. 40A shows an expansion device 6100 that can be carried and is externally attached to a PC and is equipped with a chip capable of storing information as an example of the expansion device. The expansion device 6100 can store information by the chip by connecting to the PC, for example, via USB (Universal Serial Bus). Note that FIG. 40A illustrates the expansion device 6100 in a portable form, but the expansion device according to an aspect of the present invention is not limited thereto, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0412] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed in the housing 6101. A circuit for driving the storage device and the like described in the above embodiment is provided on the substrate 6104. For example, an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0413] [SD Card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0414] FIG. 40B is a schematic diagram of the appearance of an SD card, and FIG. 40C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a writing circuit, a loader, a reading circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 4700.

[0415] By providing the electronic component 4700 also on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data of the electronic component 4700 can be read and written.

[0416] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0417] FIG. 40D is a schematic diagram of the appearance of the SSD, and FIG. 40E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. By providing the electronic component 4700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, etc. are incorporated in the controller chip 5156. Note that the circuit configurations of each of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a memory that functions as a work memory may also be provided in the controller chip 5156.

[0418] [Computer] The computer 5600 shown in FIG. 41A is an example of a large computer. A plurality of rack-mounted computers 5620 are stored in the rack 5610 in the computer 5600.

[0419] The computer 5620 can have, for example, the configuration of the perspective view shown in FIG. 41B. In FIG. 41B, the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are respectively connected to the motherboard 5630.

[0420] The PC card 5621 shown in FIG. 41C is an example of a processing board equipped with a CPU, GPU, memory device, etc. The PC card 5621 has a board 5622. The board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Although FIG. 41C shows semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, for those semiconductor devices, reference may be made to the descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0421] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe.

[0422] The connection terminals 5623, 5624, and 5625 can be used as interfaces for, for example, supplying power to and inputting signals to the PC card 5621. Also, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Also, when outputting video signals from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark).

[0423] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminals into sockets (not shown) provided on the board 5622.

[0424] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, a CPU, etc. As the semiconductor device 5627, for example, the electronic component 4730 can be used.

[0425] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5628 include a storage device, etc. As the semiconductor device 5628, for example, the electronic component 4700 can be used.

[0426] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0427] By using the semiconductor device according to one aspect of the present invention in the above various electronic devices, etc., miniaturization, high-speed operation, or low power consumption of the electronic device can be achieved. Also, since the semiconductor device according to one aspect of the present invention consumes little power, heat generation from the circuit can be reduced. Therefore, the adverse effects of such heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Also, by using the semiconductor device according to one aspect of the present invention, an electronic device with stable operation even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be enhanced.

[0428] Next, a configuration example of a computer system applicable to the computer 5600 will be described. FIG. 42 is a diagram for explaining a configuration example of the computer system 700. The computer system 700 is configured to include software and hardware. Note that the hardware included in the computer system may sometimes be referred to as an information processing device.

[0429] Examples of the software that makes up the computer system 700 include an operating system including a device driver, middleware, various development environments, an application program related to AI (AI Application), and an application program unrelated to AI (Application).

[0430] The device driver includes an application program for controlling external connection devices such as an auxiliary storage device, a display device, and a printer.

[0431] The hardware that makes up the computer system 700 includes a first arithmetic processing unit, a second arithmetic processing unit, and a first storage device. The second arithmetic processing unit also has a second storage device.

[0432] As the first arithmetic processing unit, for example, a central arithmetic processing unit such as a Noff OS CPU may be used. The Noff OS CPU has a storage means (for example, a non-volatile memory) using an OS transistor, and has a function of holding necessary information in the storage means and stopping the power supply to the central arithmetic processing unit when operation is not required. By using the Noff OS CPU as the first arithmetic processing unit, the power consumption of the computer system 700 can be reduced.

[0433] As the second arithmetic processing unit, for example, a GPU, an FPGA, or the like can be used. Note that it is preferable to use an AI OS Accelerator as the second arithmetic processing unit. The AI OS Accelerator is configured using OS transistors and has arithmetic means such as a multiply-accumulate circuit. The AI OS Accelerator consumes less power than a general GPU or the like. By using the AI OS Accelerator as the second arithmetic processing unit, the power consumption of the computer system 700 can be reduced.

[0434] It is preferable to use the storage device according to an aspect of the present invention as the first storage device and the second storage device. For example, it is preferable to use a 3D OS NAND type storage device. The 3D OS NAND type storage device can function as a cache, a main memory, and a storage. In addition, by using the 3D OS NAND type storage device, it becomes easy to realize a non-Neumann type computer system.

[0435] The 3D OS NAND type storage device consumes less power than a 3D NAND type storage device using Si transistors. By using the 3D OS NAND type storage device as the storage device, the power consumption of the computer system 700 can be reduced. In addition, since the 3D OS NAND type storage device can function as a universal memory, the number of components for configuring the computer system 700 can be reduced.

[0436] By configuring the semiconductor device constituting the hardware with a semiconductor device including OS transistors, it becomes easy to monolithically integrate the hardware including the central processing unit, the arithmetic processing unit, and the storage device. By monolithically integrating the hardware, not only miniaturization, weight reduction, and thickness reduction but also further reduction of power consumption becomes easy.

[0437] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0438] (Embodiment 7) Using the OS memory shown in this specification and the like, a normally-off CPU (also referred to as a "Noff-CPU") can be realized. Note that a Noff-CPU is an integrated circuit including a normally-off type transistor that is in a non-conductive state (also referred to as an off state) even when the gate voltage is 0V.

[0439] The Noff-CPU can stop the power supply to the circuits in the Noff-CPU that are not required for operation and put the circuits in a standby state. In the circuits where the power supply is stopped and the standby state is entered, no power is consumed. Therefore, the Noff-CPU can minimize the power consumption. In addition, the Noff-CPU can retain information necessary for operations such as set conditions for a long period even when the power supply is stopped. The return from the standby state only requires restarting the power supply to the circuits, and no rewriting such as set conditions is necessary. That is, a high-speed return from the standby state is possible. In this way, the Noff-CPU can reduce the power consumption without significantly reducing the operating speed.

[0440] The Noff-CPU can be suitably used, for example, in small-scale systems such as IoT (Internet of Things) endpoint devices (also referred to as "endpoint microcontrollers") 803 in the IoT (Internet of Things) field.

[0441] Fig. 43 shows the hierarchical structure of the IoT network and the trend of the required specifications. In Fig. 43, the power consumption 804 and the processing performance 805 are shown as the required specifications. The hierarchical structure of the IoT network is roughly divided into the upper cloud field 801 and the lower embedded field 802. The cloud field 801 includes, for example, servers. The embedded field 802 includes, for example, machines, industrial robots, in-vehicle devices, home appliances, and the like.

[0442] Higher up in the hierarchy, higher processing performance is required rather than lower power consumption. Therefore, in the cloud field 801, high-performance CPUs, high-performance GPUs, large-scale SoCs (System on a Chip), etc. are used. Also, lower down in the hierarchy, lower power consumption is required rather than higher processing performance, and the number of devices also explodes. The semiconductor device according to one aspect of the present invention can be suitably used for a communication device of an IoT terminal device that requires low power consumption.

[0443] Note that "endpoint" refers to the terminal area of the embedded field 802. Examples of devices used for endpoints include microcontrollers used in factories, home appliances, infrastructure, agriculture, etc.

[0444] Fig. 44 shows an image diagram of factory automation as an application example of an endpoint microcontroller. Factory 884 is connected to cloud (server) 883 via an Internet line (Internet). Also, cloud 883 is connected to home 881 and office 882 via the Internet line. The Internet line may be a wired communication method or a wireless communication method. For example, in the case of a wireless communication method, wireless communication conforming to a communication standard such as the 4th generation mobile communication system (4G) or the 5th generation mobile communication system (5G) may be performed using the semiconductor device according to one aspect of the present invention in the communication device. Also, factory 884 may be connected to factories 885 and 886 via the Internet line.

[0445] Factory 884 has a master device (control device) 831. The master device 831 is connected to the cloud 883 and has a function of exchanging information. Also, the master device 831 is connected to a plurality of industrial robots 842 included in the IoT terminal device 841 via an M2M (Machine to Machine) interface 832. As the M2M interface 832, for example, industrial Ethernet (Ethernet is a registered trademark), which is a type of wired communication method, or local 5G, which is a type of wireless communication method, may be used.

[0446] The factory manager can connect to the factory 884 via the cloud 883 from the home 881 or the office 882, and can know the operating status and the like. In addition, it is possible to perform defective product / missing product checks, location instructions, tact time measurement, and the like.

[0447] In recent years, factories labeled as "smart factories" have been globally promoting the introduction of IoT into factories. In the case of smart factories, there have been reports of cases where not only simple inspections and audits are performed by endpoint microcontrollers, but also fault detection and anomaly prediction are carried out.

[0448] In the case of small-scale systems such as endpoint microcontrollers, since the overall power consumption of the system during operation is often small, the proportion of power consumption occupied by the CPU tends to be large. For this reason, in small-scale systems such as endpoint microcontrollers, the power reduction effect during the standby operation by Noff-CPU becomes significant. On the other hand, although immediacy may be required in the field of IoT integration, high-speed recovery from the standby operation can be achieved by using Noff-CPU.

[0449] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

Example

[0450] Regarding the rewrite resistance of a NAND memory string using an OS memory according to an aspect of the present invention, it was evaluated using device simulation software. In this example, the evaluation results will be described. The evaluation of the rewrite resistance was performed using the device simulation software TCAD sentaurus manufactured by Synopsys.

[0451] FIG. 45A shows a perspective conceptual view of a semiconductor device including a plurality of NAND-type memory strings (also referred to as "3D OS NAND strings") using an OS memory. The semiconductor device shown in FIG. 45A is a 3D OS NAND-type storage device described in the above embodiment. In FIG. 45A, NAND-type memory strings, control gates CG (Control gates), writing gates WG (Writing gates), etc. are shown.

[0452] The structure of the memory cells (OS memory) constituting the memory string is assumed to be the structure of the memory cell 100A (see FIG. 12A) described in the above embodiment. FIG. 45B shows an equivalent circuit diagram of the memory cell. The memory cell shown in FIG. 45B is a 2T-1C type memory cell having two transistors (transistor WTr and transistor RTr) and one capacitor element Cs. Note that FIG. 45B is equivalent to the circuit diagram shown in FIG. 5A described in the above embodiment.

[0453] The transistors WTr and RTr shown in FIG. 45B are OS transistors. In addition, the transistor WTr is a transistor having a floating gate (FG). In this embodiment, polycrystalline silicon containing boron is assumed as the FG.

[0454] The gate of the transistor WTr is electrically connected to the write gate WG, and one of the source or drain is electrically connected to the write bit line WBL. The other of the source or drain of the transistor WTr is electrically connected to one electrode of the capacitor element Cs and the gate of the transistor RTr. The node where the other of the source or drain of the transistor WTr, one electrode of the capacitor element Cs, and the gate of the transistor RTr are electrically connected functions as the holding node SN. The holding node SN is also electrically connected to the wiring BWBL. The other electrode of the capacitor element Cs is electrically connected to the control gate CG. One of the source or drain of the transistor RTr is electrically connected to the read bit line RBL and the back gate of the transistor WTr. The back gate of the transistor RTr is electrically connected to the back gate line BG. The other of the source or drain of the transistor RTr is electrically connected to the wiring BRBL.

[0455] FIG. 46 shows a timing chart of the write and read operations of the 3D OS NAND string. FIG. 46 shows the case where four memory cells are connected as the 3D OS NAND string. During the write operation, the potential of the read bit line RBL is written to all the cells located on the drain terminal (read bit line RBL) side of the memory cell to be written. Therefore, the write operation needs to be performed in order from the cell farthest from the read bit line RBL. The read operation can follow the read operation of the NAND type flash memory.

[0456] Table 2 shows the set parameters of the oxide semiconductor used in the simulation.

[0457] [Table 2]

[0458] Table 3 shows the power supply voltages used in simulations such as the write operation (Writing) / read operation (Reading).

[0459]

Table 3

[0460] To adjust the threshold of the transistor WTr, charge injection into the FG is performed only once at 15V, while the power supply voltage used in other operations is 4V. That is, a high power supply voltage such as that of a NAND flash memory is not used during the write operation.

[0461] Fig. 47A shows the Id-Vwg characteristics of the transistor WTr. Fig. 47A shows the Id-Vwg characteristics for each voltage (Vpre: pre-charge voltage) when charging the FG of the transistor WTr. Fig. 47B is a diagram showing the relationship between the threshold voltage (Vth) of the transistor WTr and Vpre. It can be seen that as Vpre increases, Vth shifts to the positive side.

[0462] Retention characteristics are important in a memory device. The retention characteristics of a 3D OS NAND type memory device are determined by the Vth of the transistor WTr and the magnitude of the current (off-current) flowing between the source and drain when a voltage smaller than Vth is applied to the gate. Since the OS transistor has an extremely small off-current, it is suitable for the transistor WTr.

[0463] The simulation according to this embodiment was performed assuming a 3D OS NAND memory string in which eight memory cells are connected in series. Fig. 48 shows the retention characteristics of the 3D OS NAND memory string. Fig. 48 shows the retention characteristics of six memory cells out of the eight memory cells connected in series, excluding the two central ones. Fig. 48A shows the retention characteristics when Vpre = 12.5V, and Fig. 48B shows the retention characteristics when Vpre = 15V. Note that, as data patterns to be written during the retention characteristic evaluation, two types were used: a checker pattern (writing "1" to odd-numbered memory cells and "0" to even-numbered memory cells) and an inverted checker pattern (writing "0" to odd-numbered memory cells and "1" to even-numbered memory cells).

[0464] In Figs. 48A and 48B, the horizontal axis represents the elapsed time (Time), and the vertical axis represents the voltage Vsn of the retention node SN. As can be seen from Figs. 48A and 48B, in order to achieve a retention of 10 years (3.2×10 8 s) with the device structure used in the simulation, it is necessary to set Vpre to 15V and set the Vth of the transistor WTr to about 2V. Hereinafter, in this embodiment, the simulation results when Vpre is 15V will be described.

[0465] Figs. 49A and 49B show the simulation results of the retention characteristics of the memory cells when a checker pattern and an inverted checker pattern are alternately written to the memory string. Here, "alternately writing a checker pattern and an inverted checker pattern to the memory string" means repeating the operation of writing "1" to one memory cell and then writing "0" to the same memory cell after a certain period of time has elapsed. At this time, different data are always written to adjacent memory cells.

[0466] In the write operation, it is expected that the farther a memory cell is from the write bit line WBL, the more time it takes to write. Therefore, by examining the retention characteristics of the memory cells close to the wiring BWBL, the worst case of the retention characteristics can be predicted.

[0467] In FIGS. 49A and 49B, the horizontal axis indicates the elapsed time (Time), and the vertical axis indicates the voltage Vsn of the holding node SN. FIG. 49A shows the holding characteristics of the holding node SN (holding node SN[1]) of the memory cell closest to the wiring BWBL. FIG. 49B shows the holding characteristics of the holding node SN (holding node SN[2]) of the memory cell second closest to the wiring BWBL.

[0468] In FIGS. 49A and 49B, the change in the voltage Vsn of the node SN when “0” is written after 10 μs from writing “1” and the change in the voltage Vsn of the node SN when “1” is written after 10 μs from writing “0” are shown. It can be seen that the potential difference between “1” and “0” is smaller in the holding node SN[1] compared to the holding node SN[2].

[0469] FIG. 50 shows the simulation results of the read current Irbl (the magnitude of the current flowing through the read bit line RBL during the read operation) when the holding nodes SN[1] to SN[8] hold “0” and the read current Irbl when they hold “1”. Note that the holding node SN[8] is the holding node SN included in the memory cell closest to the write bit line WBL in this embodiment.

[0470] From FIG. 50, it can be seen that almost the same read current Irbl is obtained in each memory cell including the holding nodes SN[2] to SN[8]. On the other hand, in the memory cell including the holding node SN[1], although a difference in the read current Irbl is seen between “1” and “0”, it can be seen that the value of the read current Irbl is much larger than that of the other memory cells. Therefore, it is preferable not to use the memory cell closest to the wiring BWBL in actual operation and to treat it as a dummy cell.

[0471] Table 4 shows a comparison table of a general DRAM and NAND flash memory and a 3D OS NAND type storage device.

[0472]

Table 4

[0473] From the simulation results, it was found that the 3D OS NAND type memory device can be expected to reduce the power supply voltage while ensuring the characteristics of 10-year retention. In addition, since the 3D OS NAND type memory device holds data in the holding node via a transistor, the rewrite resistance is expected to be comparable to that of DRAM. Thus, the 3D OS NAND type memory device has both the advantages of NAND flash memory and DRAM. Therefore, the 3D OS NAND type memory device can be used as universal memory.

Explanation of symbols

[0474] 100: Memory cell, 101: Insulator, 102: Conductor, 103: Conductor, 108: Central axis, 111: Insulator, 112: Functional body, 113: Insulator, 114: Semiconductor, 115: Conductor, 116: Insulator, 117: Semiconductor, 118: Insulator, 119: Conductor, 120: Cavity, 121: Insulator, 130: Structure, 131: Opening, 132: Region, 140: Stacked body, 200: Memory string

Claims

【Claim 1】 A structure extending in a first direction, A first conductor extending in a second direction, A second conductor extending in the second direction, and having, The structure is, A third conductor extending in the first direction, A first insulator adjacent to the third conductor, A first semiconductor adjacent to the first insulator, A second insulator adjacent to the first semiconductor, And having, At a first intersection where the structure and the first conductor intersect, The structure is, A second semiconductor adjacent to the second insulator, A third insulator adjacent to the second semiconductor, A functional body adjacent to the third insulator, A fourth insulator adjacent to the functional body, And having, The functional body is a semiconductor, At a second intersection where the structure and the second conductor intersect, The structure is, A fourth conductor adjacent to the second insulator, The second semiconductor adjacent to the fourth conductor, The third insulator adjacent to the second semiconductor, And having, At the first intersection, The first insulator, the first semiconductor, the second insulator, the second semiconductor, the third insulator, the functional body, and the fourth insulator are, Provided concentrically outside the third conductor when viewed from the first direction, At the second intersection, The first insulator, the first semiconductor, the second insulator, the fourth conductor, the second semiconductor, and the third insulator are, Provided concentrically outside the third conductor when viewed from the first direction, The first direction is a direction orthogonal to the second direction, The functional body contains silicon, [[ID=3 ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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