Method for manufacturing a solar cell

Abstract

To provide a method for manufacturing a solar cell, capable of improving performance of the solar cell while simplifying a manufacturing process.SOLUTION: A method for manufacturing a solar cell includes, in the following order: a step of forming material films of ground layers 29l and 39l; a step of forming a resist on the material films of the ground layers at a boundary between a first region 7 and a second region 8; a step of forming patterned plating layers 29u, 39u using a plating method in which the resist is used as a mask; a step of removing the resist; an annealing step of heating the plating layers and the material films of the ground layers; and a step of forming patterned ground layers 29I, 39I using an etching method in which the plating layers are used as a mask. In the annealing step, an oxide film is formed on the exposed surface of the plating layers and the exposed surface of the material films of the ground layers, and in the step of forming the ground layers, the oxide films formed on the exposed surface of the plating layers and the exposed surface of the material films of the ground layers are removed.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a back contact type solar cell.

Background Art

[0002] As a solar cell, a back contact type (also referred to as a back contact type or a back junction type) solar cell in which electrodes are formed only on the back side is known. Such a solar cell includes a semiconductor substrate, a first conductivity type semiconductor layer and a first electrode layer sequentially laminated on the back side of the semiconductor substrate, and a second conductivity type semiconductor layer and a second electrode layer sequentially laminated on another part of the back side of the semiconductor substrate. The first electrode layer and the second electrode layer include a metal electrode layer and are separated from each other to prevent short circuit.

[0003] Patent Document 1 discloses a manufacturing process for forming a metal electrode layer using an electroplating method using a resist as a mask. In this manufacturing process, · A resist is formed at the electrode layer separation location on the underlying layer (seed layer) formed on the entire back surface, · Then, a separated plating layer is formed using the resist as a mask, · Then, the resist is removed and the underlying layer at the electrode layer separation location is etched. Thereby, a separated metal electrode layer composed of the underlying layer and the plating layer is formed. Thus, according to the manufacturing process for forming a metal electrode layer using an electroplating method, the manufacturing process of the solar cell can be simplified.

[0004] On the other hand, Patent Document 2 discloses a technique for heating a plating layer for the purpose of promoting crystallization of the plating layer. Thus, by heating the plating layer, crystallization of the plating layer is promoted and the plating layer can be made to have a lower resistance.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] It is conceivable to apply the technology of crystallization of the plating layer described in Patent Document 2 to the manufacturing process of the solar cell described in Patent Document 1 to reduce the resistance of the metal electrode layer (plating layer and underlayer), thereby improving the output of the solar cell, that is, improving the performance of the solar cell.

[0007] However, for example, if the technology of crystallization of the plating layer described in Patent Document 2 is applied at the end of the manufacturing process of the solar cell described in Patent Document 1, in the heating process (annealing process), the exposed surface of the metal electrode layer (plating layer and underlayer) is oxidized, and an oxide film is formed on the exposed surface of the metal electrode layer. Therefore, the contact resistance between the metal electrode layer and the wiring member increases, resulting in a decrease in the output of the solar cell, that is, a decrease in the performance of the solar cell. Then, due to the decrease in the performance of the solar cell caused by the increase in the contact resistance between the metal electrode layer and the wiring member, the effect of improving the performance of the solar cell due to the reduction of the resistance of the metal electrode layer is reduced.

[0008] An object of the present invention is to provide a method for manufacturing a solar cell capable of improving the performance of the solar cell while simplifying the manufacturing process. [Means for Solving the Problems]

[0009] The manufacturing method of a solar cell according to the present invention is a method for manufacturing a back electrode type solar cell including a semiconductor substrate, a first conductivity type semiconductor layer and a first metal electrode layer sequentially laminated on a first region which is a part on one main surface side of the semiconductor substrate, and a second conductivity type semiconductor layer and a second metal electrode layer sequentially laminated on a second region which is another part on the one main surface side of the semiconductor substrate. Each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer. The manufacturing method of the solar cell includes a step of forming a material film of a series of the underlayers across the first region and the second region on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the one main surface side of the semiconductor substrate (underlayer material film forming step), a step of forming a resist on the material film of the underlayer at the boundary between the first region and the second region (resist forming step), a step of forming the patterned plating layer on the material film of the underlayer in each of the first region and the second region by using a plating method using the resist as a mask (plating layer forming step), a step of removing the resist (resist removing step), an annealing step of heating the plating layer and the material film of the underlayer, and a step of forming the patterned underlayer in each of the first region and the second region by etching the material film of the underlayer by using an etching method using the plating layer as a mask (underlayer forming step) in this order. In the annealing step, an oxide film is formed on the exposed surface of the plating layer and the exposed surface of the material film of the underlayer. In the underlayer forming step, the oxide film formed on the exposed surface of the plating layer and the exposed surface of the material film of the underlayer is removed.

Effect of the Invention

[0010] According to the present invention, it is possible to improve the performance of the solar cell while simplifying the manufacturing process.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 5

Figure 6

Figure 7A

Figure 7B

Figure 7C

Figure 7D

Mode for Carrying Out the Invention

[0012] Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals. Also, for the sake of convenience, hatching, member reference numerals, etc. may be omitted, but in such a case, other drawings shall be referred to.

[0013] (Solar Cell) FIG. 1 is a view of the solar cell according to the present embodiment as seen from the back side, and FIG. 2 is a cross-sectional view taken along line II-II in the solar cell shown in FIG. 1. The solar cell 1 shown in FIGS. 1 and 2 is a back-contact type (also referred to as a back-contact type or a back-junction type) and a heterojunction type solar cell.

[0014] The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surfaces of the semiconductor substrate 11. Hereinafter, among the main surfaces of the semiconductor substrate 11, the light-receiving side main surface is defined as the light-receiving surface, and the main surface on the opposite side of the light-receiving surface of the semiconductor substrate 11 (one main surface) is defined as the back surface.

[0015] The first region 7 has a so-called comb shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to the support portion of the comb teeth. The bus bar portion 7b extends in the first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portions 7f extend from the bus bar portion 7b in the second direction (Y direction) intersecting the first direction.

[0016] Similarly, the second region 8 has a so-called comb shape, and has a plurality of finger portions 8f corresponding to comb teeth and a bus bar portion 8b corresponding to the support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion facing one side portion of the semiconductor substrate 11, and the finger portions 8f extend from the bus bar portion 8b in the second direction (Y direction).

[0017] The finger portions 7f and 8f form a strip extending in the second direction (Y direction) and are alternately provided in the first direction (X direction). Note that the first region 7 and the second region 8 may be formed in a stripe shape.

[0018] As shown in FIG. 2, the solar cell 1 includes a passivation layer 13 and an optical adjustment layer 15 laminated in order on the light-receiving surface side of the semiconductor substrate 11. Further, the solar cell 1 includes a passivation layer 23, a first conductivity type semiconductor layer 25, and a first electrode layer 27 laminated in order on a part (first region 7) on the back surface side of the semiconductor substrate 11. Further, the solar cell 1 includes a passivation layer 33, a second conductivity type semiconductor layer 35, and a second electrode layer 37 laminated in order on another part (second region 8) on the back surface side of the semiconductor substrate 11.

[0019] The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate doped with an n-type dopant in a crystalline silicon material. Note that the semiconductor substrate 11 may be, for example, a p-type semiconductor substrate doped with a p-type dopant in a crystalline silicon material. Examples of the n-type dopant include phosphorus (P). Examples of the p-type dopant include boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates optical carriers (electrons and holes).

[0020] By using crystalline silicon as the material of the semiconductor substrate 11, the dark current is relatively small, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of the incident light is low.

[0021] The semiconductor substrate 11 may have a pyramidal fine concavo-convex structure called a texture structure on the back surface side. Thereby, the light recovery efficiency of the light that has passed through without being absorbed by the semiconductor substrate 11 is increased.

[0022] Further, the semiconductor substrate 11 may have a pyramidal fine concavo-convex structure called a texture structure on the light-receiving surface side. Thereby, reflection of incident light is reduced on the light-receiving surface, and the light confinement effect in the semiconductor substrate 11 is improved.

[0023] The passivation layer 13 is formed on the light-receiving surface side of the semiconductor substrate 11. The passivation layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The passivation layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The passivation layers 13, 23, and 33 are formed of a material mainly composed of, for example, an intrinsic (i-type) amorphous silicon material. The passivation layers 13, 23, and 33 suppress recombination of carriers generated in the semiconductor substrate 11 and enhance the carrier collection efficiency.

[0024] The optical adjustment layer 15 is formed on the passivation layer 13 on the light-receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light and also functions as a protective layer that protects the light-receiving surface side of the semiconductor substrate 11 and the passivation layer 13. The optical adjustment layer 15 is formed of an insulator material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

[0025] The first conductivity type semiconductor layer 25 is formed on the passivation layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. On the other hand, the second conductivity type semiconductor layer 35 is formed on the passivation layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. That is, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 have a strip shape and extend in the Y direction. The first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 are alternately arranged in the X direction. A part of the second conductivity type semiconductor layer 35 may overlap a part of the adjacent first conductivity type semiconductor layer 25 (not shown).

[0026] The first conductivity type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductivity type semiconductor layer 25 is a p-type semiconductor layer in which, for example, a p-type dopant (e.g., boron (B) described above) is doped into an amorphous silicon material.

[0027] The second conductivity type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductivity type semiconductor layer 35 is an n-type semiconductor layer in which, for example, an n-type dopant (e.g., phosphorus (P) described above) is doped into an amorphous silicon material. Note that the first conductivity type semiconductor layer 25 may be an n-type semiconductor layer and the second conductivity type semiconductor layer 35 may be a p-type semiconductor layer.

[0028] The first electrode layer 27 is formed on the first conductivity type semiconductor layer 25, that is, in the first region 7 on the back side of the semiconductor substrate 11. On the other hand, the second electrode layer 37 is formed on the second conductivity type semiconductor layer 35, that is, in the second region 8 on the back side of the semiconductor substrate 11. That is, the first electrode layer 27 and the second electrode layer 37 have a strip shape and extend in the Y direction. The first electrode layer 27 and the second electrode layer 37 are alternately provided in the X direction.

[0029] The first electrode layer 27 includes a first transparent electrode layer 28 and a first metal electrode layer 29 laminated in order on the first conductivity type semiconductor layer 25. On the other hand, the second electrode layer 37 includes a second transparent electrode layer 38 and a second metal electrode layer 39 laminated in order on the second conductivity type semiconductor layer 35. The first metal electrode layer 29 has a two-layer structure of an underlayer 29l and a plating layer 29u, and the second metal electrode layer 39 has a two-layer structure of an underlayer 39l and a plating layer 39u.

[0030] The first transparent electrode layer 28 and the second transparent electrode layer 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide), ZnO (Zinc Oxide: zinc oxide), and the like.

[0031] The underlayer 29l in the first metal electrode layer 29 and the underlayer 39l in the second metal electrode layer 39 contain metal materials such as silver, copper, and aluminum formed by a PVD method such as sputtering. On the other hand, the plating layer 29u in the first metal electrode layer 29 and the plating layer 39u in the second metal electrode layer 39 contain metal materials such as silver, copper, and nickel formed by, for example, a plating method.

[0032] The first electrode layer 27 and the second electrode layer 37 are in the form of strips extending in the second direction (Y direction) and are arranged alternately in the first direction (X direction). That is, the first transparent electrode layer 28 and the second transparent electrode layer 38 are in the form of strips extending in the second direction (Y direction) and are arranged alternately in the first direction (X direction). Further, the first metal electrode layer 29 and the second metal electrode layer 39 are in the form of strips extending in the second direction (Y direction) and are arranged alternately in the first direction (X direction). The first transparent electrode layer 28 and the second transparent electrode layer 38 are separated from each other, and the first metal electrode layer 29 and the second metal electrode layer 39 are also separated from each other.

[0033] FIG. 3 is an enlarged cross-sectional view of an example of part III in the solar cell shown in FIG. 2. As will be described later, when a pattern printing resist is used as the resist for forming the plating layer 29u in the first metal electrode layer 29 and the plating layer 39u in the second metal electrode layer 39, the structure shown in FIG. 3 may be obtained.

[0034] As shown in FIG. 3, a resin film 41 may be unevenly distributed at least at the end portion on the boundary side of at least the first region 7 and the second region 8 between the underlayer 29l and the plating layer 29u in the first metal electrode layer 29.

[0035] Specifically, the underlying layer 29l is relatively thin and has an uneven structure corresponding to the uneven structure (texture structure) of the semiconductor substrate 11. The resin film 41 is interposed between the troughs of the uneven structure at at least the ends of the underlying layer 29l and the plating layer 29u. The resin film 41 may be formed in a sea-like (i.e., continuous) form of the sea-island structure or in an island-like (i.e., discontinuous) form of the sea-island structure. It is preferable that the troughs of the uneven structure at at least the ends of the underlying layer 29l are planarized by the resin film 41.

[0036] On the other hand, the peaks of the uneven structure at at least the ends of the underlying layer 29l are in contact with the plating layer 29u. Also, the troughs and peaks of the uneven structure other than the ends of the underlying layer 29l are in contact with the plating layer 29u.

[0037] Similarly, the resin film 41 may be unevenly distributed at least at the ends on the boundary side between the first region 7 and the second region 8 in the underlying layer 39l and the plating layer 39u in the second metal electrode layer 39.

[0038] Specifically, the underlying layer 39l is relatively thin and has an uneven structure corresponding to the uneven structure (texture structure) of the semiconductor substrate 11. The resin film 41 is interposed between the troughs of the uneven structure at at least the ends of the underlying layer 39l and the plating layer 39u. The resin film 41 may be formed in a sea-like (i.e., continuous) form of the sea-island structure or in an island-like (i.e., discontinuous) form of the sea-island structure. It is preferable that the troughs of the uneven structure at at least the ends of the underlying layer 39l are planarized by the resin film 41.

[0039] On the other hand, the peaks of the uneven structure at at least the ends of the underlying layer 39l are in contact with the plating layer 39u. Also, the troughs and peaks of the uneven structure other than the ends of the underlying layer 39l are in contact with the plating layer 39u.

[0040] (Method for manufacturing a solar cell) Next, with reference to FIGS. 4A to 4G, a method for manufacturing a solar cell according to the present embodiment will be described. FIG. 4A is a diagram showing a semiconductor layer formation step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 4B is a diagram showing a transparent electrode layer material film formation step and a base layer material film formation step of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment. Further, FIG. 4C is a diagram showing a resist formation step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 4D is a diagram showing a plating layer formation step of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment. Further, FIG. 4E is a diagram showing a resist removal step in the method for manufacturing a solar cell according to the present embodiment, and FIG. 4F is a diagram showing an annealing step in the method for manufacturing a solar cell according to the present embodiment. Further, FIG. 4G is a diagram showing a transparent electrode layer formation step and a base layer formation step of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment. In FIGS. 4A to 4G, the back side of the semiconductor substrate 11 is shown, and the front side of the semiconductor substrate 11 is omitted.

[0041] First, as shown in FIG. 4A, a passivation layer 23 and a first conductivity type semiconductor layer 25 are formed on a part of the back side of the semiconductor substrate 11, specifically in the first region 7 (semiconductor layer formation step). For example, after forming a passivation layer material film and a first conductivity type semiconductor layer material film on the entire back side of the semiconductor substrate 11 using a CVD method or a PVD method, a resist generated using photolithography technology or printing technology, or a metal mask, may be used to pattern the passivation layer 23 and the first conductivity type semiconductor layer 25 by an etching method.

[0042] Examples of the etching solution for the p-type semiconductor layer material film include acidic solutions such as hydrofluoric acid containing ozone or a mixed solution of nitric acid and hydrofluoric acid, and examples of the etching solution for the n-type semiconductor layer material film include alkaline solutions such as an aqueous potassium hydroxide solution.

[0043] Alternatively, when laminating the passivation layer and the first conductivity type semiconductor layer on the back side of the semiconductor substrate 11 using the CVD method or the PVD method, a mask may be used to simultaneously perform film formation and patterning of the passivation layer 23 and the first conductivity type semiconductor layer 25.

[0044] Next, a passivation layer 33 and a second conductivity type semiconductor layer 35 are formed on another part of the back side of the semiconductor substrate 11, specifically in the second region 8 (semiconductor layer formation step). For example, as described above, after forming a passivation layer material film and a second conductivity type semiconductor layer material film on the entire back side of the semiconductor substrate 11 using the CVD method or the PVD method, an etching method using a resist generated using photolithography technology or printing technology, or a metal mask, may be used to pattern the passivation layer 33 and the second conductivity type semiconductor layer 35.

[0045] Alternatively, when laminating the passivation layer and the second conductivity type semiconductor layer on the back side of the semiconductor substrate 11 using the CVD method or the PVD method, a mask may be used to simultaneously perform film formation and patterning of the passivation layer 33 and the second conductivity type semiconductor layer 35.

[0046] In this semiconductor layer formation step, a passivation layer 13 may be formed on the entire light receiving surface side of the semiconductor substrate 11 (not shown).

[0047] Next, as shown in FIG. 4B, a series of transparent electrode layer material films 28Z are formed across the first region 7 and the second region 8 on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 (transparent electrode layer material film formation step). As a method for forming the transparent electrode layer material film 28Z, for example, the CVD method, the PVD method, or the like is used.

[0048] Next, a series of underlying layer material films 29lZ are formed across the first region 7 and the second region 8 on the transparent electrode layer material film 28Z, that is, on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 (underlying layer material film forming step). As a method for forming the underlying layer material film 29lZ, for example, a PVD method such as sputtering is used.

[0049] Next, as shown in FIG. 4C, a resist 40 is formed on the underlying layer material film 29lZ at the boundary between the first region 7 and the second region 8 (resist forming step). The method for forming the resist 40 is not particularly limited, and examples include a photolithography method or a printing method. Among these, from the viewpoint of simplifying the manufacturing process, a printing method is preferable. In particular, a pattern printing method such as press printing like screen printing or gravure printing, or ejection printing like inkjet printing is preferable.

[0050] In the pattern printing method, a patterned resist 40 is formed by printing and baking (curing) a printing material containing a resin material and a solvent. The temperature during baking (curing) of the resist is, for example, 80°C or higher and 140°C or lower. At this time, as shown in FIG. 5, a resin film 41 formed by the resin material in the printing material seeping out is formed in the valleys of the uneven structure (texture structure) of the underlying layer material film 29lZ.

[0051] As shown in FIG. 5, the resin film 41 may be formed in the valleys of the uneven structure between the resists 40, that is, in all of the first region 7 and the second region 8, or as shown in FIG. 3, in the valleys of the uneven structure at the end portions on the boundary side between the first region 7 and the second region 8 between the resists 40.

[0052] Next, as shown in FIG. 4D, using an electroplating method that utilizes the resist 40 as a mask, a patterned plating layer 29u is formed on the underlying layer material film 29lZ in the first region 7, and a patterned plating layer 39u is formed on the underlying layer material film 29lZ in the second region 8 (electroplated metal electrode layer forming step). When the resist 40 is a pattern printing resist, as shown in FIG. 5, the plating layer 29u is formed on the resin film 41 in the valley portion of the uneven structure at at least the end portion of the underlying layer material film 29lZ and on the peak portion of the uneven structure in the underlying layer material film 29lZ.

[0053] Next, as shown in FIG. 4E, the resist 40 is removed (resist removal step). As the resist removal solution, an alkaline aqueous solution such as an aqueous sodium hydroxide solution is used.

[0054] Next, as shown in FIG. 4F, in an air atmosphere, annealing is performed by heating the semiconductor substrate 11 to heat the plating layers 29u, 39u and the underlying layer material film 29lZ (annealing step). Thereby, crystallization of the plating layers 29u, 39u and the underlying layer material film 29lZ (that is, the underlying layers 29l, 39l) is promoted. The heating temperature in the annealing step is preferably higher than the temperature at the time of baking (curing) of the resist in the above-described resist forming step. For example, the heating temperature is preferably 110° C. or higher and 250° C. or lower, more preferably 130° C. or higher and 200° C. or lower, and even more preferably 140° C. or higher and 170° C. or lower. If the heating temperature is less than 110° C., the annealing effect cannot be obtained sufficiently. On the other hand, if the heating temperature exceeds 250° C., the film quality of the amorphous silicon may deteriorate. At this time, the exposed surfaces of the plating layers 29u, 39u and the exposed surface of the underlying layer material film 29lZ are oxidized, and an oxide film 29O is formed on the exposed surfaces of the plating layers 29u, 39u and the exposed surface of the underlying layer material film 29lZ.

[0055] Next, as shown in FIG. 4G, by using an etching method that utilizes the plating layers 29u and 39u as masks, the base layer material film 29lZ and the transparent electrode layer material film 28Z are etched to form a patterned first transparent electrode layer 28 and a base layer 29l in the first region 7, and a patterned second transparent electrode layer 38 and a base layer 39l in the second region 8 (transparent electrode layer forming step and base layer forming step). At this time, the oxide film 29O formed on the exposed surfaces of the plating layers 29u and 39u and the exposed surface of the base layer material film 29lZ is removed. As a result, a first metal electrode layer 29 composed of the base layer 29l and the plating layer 29u, and a second metal electrode layer 39 composed of the base layer 39l and the plating layer 39u are formed. Also, a first electrode layer 27 composed of the first transparent electrode layer 28 and the first metal electrode layer 29, and a second electrode layer 37 composed of the second transparent electrode layer 38 and the second metal electrode layer 39 are formed.

[0056] As an etching solution for the simultaneous etching of the base layer material film 29lZ and the transparent electrode layer material film 28Z, for example, when the transparent electrode layer material film 28Z is ITO and the base layer material film 29lZ is copper, a mixed solution of an oxidizing agent such as ammonium persulfate (ammonium persulfate) and an acidic solution such as hydrochloric acid (HCl) can be mentioned.

[0057] Thereafter, an optical adjustment layer 15 is formed on the entire light-receiving surface side of the semiconductor substrate 11 (not shown). Through the above steps, the back electrode type solar cell 1 of the present embodiment shown in FIGS. 1 and 2 is obtained.

[0058] As described above, according to the method for manufacturing a solar cell of the present embodiment, the plating layers 29u and 39u in the metal electrode layers 29 and 39 are formed by using a plating method. Furthermore, by using a plating method that uses the resist 40 as a mask, the plating layers 29u and 39u in the metal electrode layers 29 and 39 are directly formed (film formation and patterning are performed simultaneously). Thereby, simplification and cost reduction of the solar cell manufacturing process are possible.

[0059] Further, according to the method for manufacturing a solar cell of the present embodiment, in the plating method, a printing material containing a resin material and a solvent is printed and fired (cured) using a pattern printing method, so that a patterned resist 40 may be directly formed (performing film formation and patterning simultaneously). Thereby, for example, compared with resist formation using photolithography technology, simplification and cost reduction of resist formation are possible. Therefore, simplification and cost reduction of the manufacturing process of the solar cell are possible.

[0060] Also, according to the method for manufacturing a solar cell of the present embodiment, as the material of the metal electrode layers 29 and 39, a relatively inexpensive metal such as Cu may be used instead of a relatively expensive known Ag paste. Thereby, cost reduction of the solar cell is possible.

[0061] Furthermore, according to the method for manufacturing a solar cell of the present embodiment, since crystallization of the metal electrode layers 29 and 39 (plating layers 29u and 39u and underlayers 29l and 39l) is promoted by the annealing process, the electrode layers 27 and 37 can be made to have a lower resistance, and the output of the solar cell 1, that is, the performance of the solar cell 1 can be improved.

[0062] By the way, if the purpose is crystallization of the metal electrode layer (plating layer and underlayer), generally, it is considered that the annealing process is performed at the end of the manufacturing process, that is, after the etching process of the underlayer. However, when the annealing process is performed after the etching process of the underlayer, as shown in FIG. 6, in the annealing process, the exposed surfaces of the metal electrode layers 29 and 39 (plating layers 29u and 39u and underlayers 29l and 39l) are oxidized, and an oxide film 29O is formed on the exposed surfaces of the metal electrode layers 29 and 39. Therefore, the contact resistance between the electrode layers 27 and 37 and the wiring member increases, and the output of the solar cell 1, that is, the performance of the solar cell 1 decreases. Then, due to the decrease in the performance of the solar cell 1 caused by the increase in the contact resistance between the electrode layers 27 and 37 and the wiring member, the effect of improving the performance of the solar cell 1 due to the reduction in the resistance of the electrode layers 27 and 37 is reduced (Problem 1).

[0063] After the etching process of the underlying layer, the semiconductor layers 25(23) and 35(33) are exposed in the boundary region between the first region 7 and the second region 8. Therefore, when the annealing process is performed after the etching process of the underlying layer, as shown in FIG. 6, in the annealing process, Cu constituting the metal electrode layers 29 and 39 diffuses into the semiconductor layers 25(23) and 35(33) and the semiconductor substrate 11. When Cu diffuses into the semiconductor layers 25(23) and 35(33) and the semiconductor substrate 11, the photoelectric conversion characteristics of the solar cell 1 deteriorate, that is, the reliability of the solar cell 1 deteriorates (Problem 2).

[0064] Regarding Problem 1 described above, according to the method for manufacturing a solar cell of the present embodiment, since the annealing process is performed before the etching process of the underlying layer, in the annealing process, even if the exposed surfaces of the metal electrode layers 29 and 39 (the plating layers 29u and 39u and the underlying layers 29l and 39l) are oxidized and an oxide film 29O is formed on the exposed surfaces of the metal electrode layers 29 and 39 (FIG. 4F), in the subsequent etching process of the underlying layer, the oxide film 29O on the exposed surfaces of the metal electrode layers 29 and 39 is removed (FIG. 4G). Therefore, due to the oxide film 29O on the exposed surfaces of the metal electrode layers 29 and 39, the contact resistance between the electrode layers 27 and 37 and the wiring member does not increase, and the output of the solar cell 1 does not decrease, that is, the performance of the solar cell 1 does not deteriorate. Therefore, the effect of improving the performance of the solar cell 1 due to the reduction of the resistance of the electrode layers 27 and 37 is not reduced.

[0065] Regarding Problem 2 described above, according to the method for manufacturing a solar cell of the present embodiment, since the annealing process is performed before the etching process of the underlying layer, that is, before the etching process of the underlying layer in which the semiconductor layers 25(23) and 35(33) are not exposed in the boundary region between the first region 7 and the second region 8 (FIG. 4F), even if Cu constituting the metal electrode layers 29 and 39 diffuses in the annealing process, it does not diffuse into the semiconductor layers 25(23) and 35(33) and the semiconductor substrate 11. Therefore, due to the diffusion of Cu, the photoelectric conversion characteristics of the solar cell 1 do not deteriorate, that is, the reliability of the solar cell 1 does not deteriorate.

[0066] Also, according to the method for manufacturing a solar cell of the present embodiment, since crystallization of the plating layers 29u and 39u is promoted in the annealing step, in the subsequent etching step of the underlying layer, the plating layers 29u and 39u are difficult to be etched and function suitably as a mask.

[0067] By the way, when the annealing step is performed before the resist stripping step, in the annealing step, the resist is heated and it becomes difficult to strip the resist.

[0068] Regarding this point, according to the method for manufacturing a solar cell of the present embodiment, since the annealing step is performed after the resist stripping step, in the annealing step, the resist is not heated and it does not become difficult to strip the resist.

[0069] By the way, if there is remaining resist after the resist stripping step, in the subsequent etching step of the underlying layer, there may be a region where the underlying layer (and the transparent electrode layer) is not etched. As a result, current leakage may occur in the solar cell.

[0070] Regarding this point, according to the method for manufacturing a solar cell of the present embodiment, in the annealing step between the resist stripping step and the etching step of the underlying layer, if there is remaining resist after the resist stripping step, the Cu constituting the underlying layer does not oxidize and does not change color. Therefore, for example, if the resist is transparent, before the etching step of the underlying layer, the remaining resist portions can be found by visual observation. When the resist is colored, the optical properties before and after the annealing step are measured, and the portions where the optical properties before and after the annealing step do not change can be found as the remaining resist portions. In this way, the remaining resist portions can be easily confirmed by the annealing step.

[0071] As described above, the embodiments of the present invention have been explained. However, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible. For example, in the above-described embodiment, as shown in FIG. 3, between the underlying layer 29l and the plating layer 29u in the first metal electrode layer 29, and between the underlying layer 39l and the plating layer 39u in the second metal electrode layer 39, a solar cell in which the resin film 41 is unevenly distributed in the valleys of the concavo-convex structure was exemplified. However, the present invention is not limited to this, and various forms of solar cells can be considered depending on the etching degree in the manufacturing process of the solar cell. Here, for comparison with a comparative example of the solar cell described below, a partially enlarged cross-sectional view of an example of the solar cell according to the present embodiment shown in FIG. 3, which is an enlarged cross-sectional view of part III shown in FIG. 2, is redrawn in FIG. 7A. In FIG. 7A, in FIG. 3, the first conductive semiconductor layer 25 and the passivation layer 23 are shown together. FIGS. 7B to 7D are partially enlarged cross-sectional views of an example of a solar cell according to a modified example of the present embodiment, which are enlarged cross-sectional views corresponding to part III shown in FIG. 2.

[0072] As shown in FIG. 7B, in the solar cell 1, the resin film 41 that was unevenly distributed in the valleys of the concavo-convex structure may be etched and removed between the underlying layer 29l and the plating layer 29u in the first metal electrode layer 29, and between the underlying layer 39l and the plating layer 39u in the second metal electrode layer 39. For example, in the resist removal process described above, the resin film 41 is etched and removed.

[0073] As a result, in the solar cell 1, at least at the end portion on the boundary side of the first region 7 and the second region 8 in the first metal electrode layer 29, a space may exist under the plating layer 29u in the valley of the concavo-convex structure. More specifically, at least at the end portion of the first metal electrode layer 29, the underlying layer 29l exists under the plating layer 29u in the valley of the concavo-convex structure, and a resin film 41 may not be interposed between the underlying layer 29l and the plating layer 29u in the valley of the concavo-convex structure, and a space may be interposed.

[0074] Similarly, in the solar cell 1, in the second metal electrode layer 39, at least at the end portion on the boundary side between the first region 7 and the second region 8, a space may exist under the plating layer 39u in the trough portion of the concavo-convex structure. More specifically, at least at the end portion of the second metal electrode layer 39, an underlying layer 39l exists under the plating layer 39u in the trough portion of the concavo-convex structure, and a space may intervene between the underlying layer 39l and the plating layer 39u in the trough portion of the concavo-convex structure without the resin film 41 intervening.

[0075] Alternatively, as shown in FIG. 7C, in the solar cell 1, further, the underlying layers 29l, 39l may be etched and removed, and further, the transparent electrode layers 28, 38 may be etched and removed. For example, in the above-described transparent electrode layer formation step and underlying layer formation step, the underlying layers 29l, 39l and the transparent electrode layers 28, 38 are etched and removed.

[0076] Thereby, in the solar cell 1, at least at the end portion of the first metal electrode layer 29, a resin film 41 and an underlying layer 29l do not exist under the plating layer 29u in the trough portion of the concavo-convex structure, and a space may exist. Alternatively, in the solar cell 1, at least at the end portion of the first metal electrode layer 29, a resin film 41, an underlying layer 29l, and a transparent electrode layer 28 do not exist under the plating layer 29u in the trough portion of the concavo-convex structure, and a space may exist.

[0077] Similarly, in the solar cell 1, at least at the end portion of the second metal electrode layer 39, a resin film 41 and an underlying layer 39l do not exist under the plating layer 39u in the trough portion of the concavo-convex structure, and a space may exist. Alternatively, in the solar cell 1, at least at the end portion of the second metal electrode layer 39, a resin film 41, an underlying layer 39l, and a transparent electrode layer 38 do not exist under the plating layer 39u in the trough portion of the concavo-convex structure, and a space may exist.

[0078] Alternatively, as shown in FIG. 7D, in the solar cell 1, between the underlayer 29l and the plating layer 29u in the first metal electrode layer 29 and between the underlayer 39l and the plating layer 39u in the second metal electrode layer 39, the resin film 41 that was unevenly distributed in the valleys of the concavo-convex structure remains without being etched, and the underlayers 29l and 39l may be etched and removed. Further, the transparent electrode layers 28 and 38 may be etched and removed. As described above, for example, in the above-described transparent electrode layer forming step and underlayer forming step, the underlayers 29l and 39l and the transparent electrode layers 28 and 38 are etched and removed.

[0079] As a result, in the solar cell 1, at least at the end of the first metal electrode layer 29, under the plating layer 29u in the valley of the concavo-convex structure, the resin film 41 exists and the underlayer 29l does not exist. Under the resin film 41 in the valley of the concavo-convex structure, a space may exist. Alternatively, in the solar cell 1, at least at the end of the first metal electrode layer 29, under the plating layer 29u in the valley of the concavo-convex structure, the resin film 41 exists, the underlayer 29l and the transparent electrode layer 28 do not exist, and under the resin film 41 in the valley of the concavo-convex structure, a space may exist.

[0080] Similarly, in the solar cell 1, at least at the end of the second metal electrode layer 39, under the plating layer 39u in the valley of the concavo-convex structure, the resin film 41 exists and the underlayer 39l does not exist. Under the resin film 41 in the valley of the concavo-convex structure, a space may exist. Alternatively, in the solar cell 1, at least at the end of the second metal electrode layer 39, under the plating layer 39u in the valley of the concavo-convex structure, the resin film 41 exists, the underlayer 39l and the transparent electrode layer 38 do not exist, and under the resin film 41 in the valley of the concavo-convex structure, a space may exist.

[0081] Further, in the above-described embodiment, a method for manufacturing a solar cell including an electrode layer including a transparent electrode layer and a metal electrode layer was exemplified. However, the present invention is not limited to this, and is also applicable to a method for manufacturing a solar cell including an electrode layer including only a metal electrode layer.

[0082] In addition, in the above-described embodiments, a method for manufacturing a solar cell using a crystalline silicon material has been exemplified, but the present invention is not limited thereto. For example, the present invention is also applicable to a method for manufacturing a solar cell using various materials such as gallium arsenide (GaAs).

[0083] In addition, in the above-described embodiments, a method for manufacturing a heterojunction solar cell has been exemplified as shown in FIG. 2. However, the present invention is not limited thereto, and the present invention is also applicable to a method for manufacturing various solar cells such as a homojunction solar cell.

Explanation of Reference Numerals

[0084] 1 Solar cell 7 First region 7f Finger portion 7b Bus bar portion 8 Second region 8f Finger portion 8b Bus bar portion 11 Semiconductor substrate 13, 23, 33 Passivation layer 15 Optical adjustment layer 25 First conductivity type semiconductor layer 27 First electrode layer 28 First transparent electrode layer 28Z Transparent electrode layer material film 29 First metal electrode layer 29l Underlayer 29lZ Underlayer material film 29u Plating layer 29O Oxide film 35 Second conductivity type semiconductor layer 37 Second electrode layer 38 Second transparent electrode layer 39 Second metal electrode layer 39l Underlayer 39u Plating layer 40 Resist 41 Resin film

Claims

1. A method for manufacturing a back electrode type solar cell, comprising: a semiconductor substrate; a first conductivity type semiconductor layer and a first metal electrode layer sequentially stacked on a first region which is a part of one main surface side of the semiconductor substrate; and a second conductivity type semiconductor layer and a second metal electrode layer sequentially stacked on a second region which is another part of the one main surface side of the semiconductor substrate, wherein each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer, and the method for manufacturing the solar cell comprises: an underlayer material film forming step of forming a material film of a series of the underlayers across the first region and the second region on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the one main surface side of the semiconductor substrate; a resist forming step of forming a resist on the material film of the underlayer at a boundary between the first region and the second region; a plating layer forming step of forming the patterned plating layer on the material film of the underlayer in each of the first region and the second region by using a plating method using the resist as a mask; a resist removing step of removing the resist; an annealing step of heating the plating layer and the material film of the underlayer; an underlayer forming step of forming the patterned underlayer in each of the first region and the second region by etching the material film of the underlayer by using an etching method using the plating layer as a mask, which are included in this order, wherein in the annealing step, an oxide film is formed on an exposed surface of the plating layer and an exposed surface of the material film of the underlayer, and in the underlayer forming step, the oxide film formed on the exposed surface of the plating layer and the exposed surface of the material film of the underlayer is removed, A method for manufacturing a solar cell.

2. In the resist forming step, a patterned resist is formed by printing and curing a printing material containing a resin material and a solvent by using a pattern printing method. The method for manufacturing a solar cell according to Claim 1.

3. The method for manufacturing a solar cell according to Claim 2, wherein a heating temperature in the annealing step is higher than a temperature at the time of curing in the resist forming step.

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