Indicating device

Abstract

To provide a display device capable of suppressing flare.SOLUTION: Embodiments of the present disclosure relate to a display device, specifically, a display device capable of suppressing flare when a camera is in use by including an anode extension line having a curved shape.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present disclosure relates to a display device.

Background Art

[0002] With the development of technology, in addition to the image display function, a display device can provide a photographing function and various sensing functions. For this purpose, the display device can be provided with optoelectronic devices (also referred to as light receiving devices or sensors) such as cameras and / or sensing sensors.

[0003] Since the optoelectronic device has to receive light from the front of the display device, it has to be installed in a place where light reception is advantageous. Therefore, conventionally, a camera (camera lens) and a sensing sensor have to be provided on the front of the display device so as to be exposed. For this reason, the bezel of the display panel becomes wider, or a notch or a physical hole is formed in the display area of the display panel, and a camera or a sensing sensor is provided therein.

[0004] Therefore, by providing an optoelectronic device such as a camera or a sensing sensor that receives light from the front and performs a predetermined function in the display device, the bezel of the front portion of the display device may become larger, or there may be a restriction on the front design of the display device.

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the field of display technology, technologies for providing an optoelectronic device such as a camera or a sensing sensor without reducing the area of the display region of a display panel have been studied. A display device can be provided that includes an optoelectronic device under the display region of the display panel and has a light transmission structure that allows the optoelectronic device to normally receive light without the optoelectronic device being exposed on the front surface of the display device. However, when using the optoelectronic device of such a display device, there has been a problem that it is difficult to smoothly receive light due to the wiring structure of the display device. In particular, when a camera is used under the display region, there has been a problem that flare occurs due to the wiring structure of the display device. Therefore, the inventors of the present specification have invented a display device that can suppress the occurrence of flare even when using a camera while not reducing the area of the display region.

[0006] Generally, the present disclosure provides a display device suitable for use with a camera. The display device is designed to effectively transmit light through the optical region of the display device. In particular, the display device can have the ability to suppress flare by including an anode extension line having a curved shape.

Means for Solving the Problem

[0007] Embodiments of the present disclosure can provide a display device including a display region, a cathode electrode, a first light-emitting element, a first sub-pixel circuit portion, and an anode extension line.

[0008] The display area can include a first optical area and a first optical bezel area. The first optical bezel area can be located on the outer contour of the first optical area. The display area can include the first optical area and the first optical bezel area. The first optical bezel area may be disposed outside the first optical area, for example, it may surround the first optical area. The first optical area can be configured to effectively transmit light. The first optical area can have a higher light transmittance than the first optical bezel area. The first optical bezel area can be configured to not allow light to pass through. The display area can further include a general area. The general area can surround the first optical bezel area. Each of the general area, the first optical area, and the first optical bezel area can be configured to diverge light, for example, it can display an image. That is, the first optical area, the first optical bezel area, and the general area can form the display area of the device. The general area can be configured to not allow light to pass through. The non-display area can be provided outside the display area (for example, the peripheral edge). The non-display area can be configured to not diverge light.

[0009] The cathode electrode can include a plurality of cathode holes within the first optical area. The cathode holes can include enlarged open holes for transmitting light through the cathode. The cathode can extend into the first optical bezel area and the general area, and there may be no cathode holes in the first optical bezel area and the general area.

[0010] The first light-emitting element is located in the first optical area and can include a first anode electrode. The first light-emitting element can be an element (for example, a pixel or a sub-pixel) configured to diverge light. The first light-emitting element can define a corresponding light-emitting area in the display device.

[0011] The first sub-pixel circuit unit can be disposed in the first optical bezel area. The first sub-pixel circuit unit can be a circuit configured to drive the first sub-pixel.

[0012] The anode extension line can electrically connect the first sub-pixel circuit portion and the first anode electrode. The anode extension line can be arranged so as not to overlap with the cathode hole.

[0013] The shape of the anode extension line can be curved.

[0014] The anode extension line can extend in a first direction across the first optical region, and each anode extension line can terminate at a connection point with the anode electrode.

[0015] The number of anode extension lines per unit area can decrease from the edge of the first optical region towards the center of the first optical region.

[0016] The plurality of anode extension lines can be divided into a plurality of groups, and the thickness of each plurality of groups can decrease from the edge of the first optical region towards the center of the first optical region.

[0017] The present invention is defined in the appended claims.

Advantages of the Invention

[0018] According to the present disclosure, by including a curved anode extension line, a display device capable of suppressing the occurrence of flare during the use of a camera provided under the display device can be provided.

[0019] According to the present disclosure, without introducing additional processes, by forming the anode extension line, a display device with optimized processes can be provided.

Brief Description of the Drawings

[0020]

Figure 1a

Figure 1b

Figure 1c

Figure 2

Figure 3

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Figure 6

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

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Figure 14

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Figure 17

Figure 18

Figure 19

Figure 20

Embodiments for Carrying Out the Invention

[0021] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, for the same components, as much as possible, the same numerals can be used even if they are shown on other drawings. In addition, when explaining the present disclosure, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added as long as "only" is not used. When a component is expressed in the singular, it can include the case where a plurality are included unless otherwise explicitly stated.

[0022] Also, when explaining the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. can be used. These terms are merely used as arbitrary labels for distinguishing the components from other components, and the essence, order, sequence, number, etc. of the components are not limited by these terms.

[0023] In the description of the positional relationship of components, when it is described that two or more components are "connected", "coupled", or "joined", it should be understood that the two or more components can be directly "connected", "coupled", or "joined", but it is also possible that two or more components and other components are further "interposed" and "connected", "coupled", or "joined". Here, the other components may be included in one or more of the two or more components that are "connected", "coupled", or "joined" to each other.

[0024] In the description of the relationship of the time flow regarding components, operation methods, manufacturing methods, etc., for example, when the time sequence relationship or the flow sequence relationship is described by "after ~", "subsequent to ~", "next to ~", "before ~", etc., it may include cases where it is not continuous unless "immediately" or "directly" is used.

[0025] On the other hand, when a numerical value regarding a component or its corresponding information (for example, level, etc.) is mentioned, the numerical value or its corresponding information can be interpreted as including the range of errors that can occur due to various factors (for example, process factors, internal or external impacts, noise, etc.) even without a separate explicit description.

[0026] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0027] FIG. 1a, FIG. 1b, and FIG. 1c show a display device 100 according to an embodiment of the present disclosure.

[0028] Referring to FIGS. 1a, 1b, and 1c, a display device 100 according to an embodiment of the present disclosure can include a display panel 110 that displays an image, and one or more optoelectronic devices 11, 12.

[0029] The display panel 110 can include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed.

[0030] In the display area DA, a plurality of sub-pixels can be arranged, and various signal lines for driving the plurality of sub-pixels can be arranged.

[0031] The non-display area NDA may be an outer area of the display area DA. In the non-display area NDA, various signal lines can be arranged, and various driving circuits can be connected. The non-display area NDA is bent so as not to be visible from the front, or is covered by a case (not shown). The non-display area NDA is also called a bezel or a bezel area.

[0032] Referring to FIGS. 1a, 1b, and 1c, in the display device 100 according to an embodiment of the present disclosure, one or more optoelectronic devices 11, 12 are provided and installed separately from the display panel 110, and are electronic components located below the display panel 110 (on the side opposite to the viewing surface).

[0033] Light can enter the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to one or more optoelectronic devices 11, 12 located below the display panel 110 (on the side opposite to the viewing surface). For example, the light passing through the display panel 110 may include visible light, infrared rays, or ultraviolet rays.

[0034] One or more optoelectronic devices 11, 12 may be devices that receive the light transmitted through the display panel 110 and perform a predetermined function according to the received light. For example, one or more of the optoelectronic devices 11, 12 may include one or more of imaging devices such as cameras (image sensors), proximity sensors, and sensing sensors such as illuminance sensors. Here, for example, the sensing sensor may be an infrared sensor.

[0035] Referring to FIGS. 1a, 1b, and 1c, in the display panel 110 according to an embodiment of the present disclosure, the display area DA may include a general area NA and one or more optical areas OA1, OA2. The one or more optical areas OA1, OA2 may be areas that overlap with the one or more optoelectronic devices 11, 12.

[0036] According to the illustration of FIG. 1a, the display area DA may include a general area NA and a first optical area OA1. Here, at least a part of the first optical area OA1 may overlap with the first optoelectronic device 11.

[0037] According to the illustration of FIG. 1b, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of FIG. 1b, a general area NA may exist between the first optical area OA1 and the second optical area OA2. Here, at least a part of the first optical area OA1 overlaps with the first optoelectronic device 11, and at least a part of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0038] According to the illustration of FIG. 1c, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the illustration of FIG. 1c, there is no general area NA between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 are in contact with each other. Here, at least a part of the first optical area OA1 overlaps with the first optoelectronic device 11, and at least a part of the second optical area OA2 may overlap with the second optoelectronic device 12.

[0039] Both a video display structure and a light transmission structure must be formed in one or more optical areas OA1, OA2. That is, since one or more optical areas OA1, OA2 are part of the display area DA, light-emitting areas of sub-pixels for video display must be arranged in one or more optical areas OA1, OA2. And a light transmission structure for transmitting light to one or more optoelectronic devices 11, 12 must be formed in one or more optical areas OA1, OA2.

[0040] One or more optoelectronic devices 11, 12 are devices that require light reception. They are located behind the display panel 110 (below, on the opposite side of the viewing surface) and are configured to receive the light that has passed through the display panel 110. The one or more optoelectronic devices 11, 12 are not exposed on the front surface (viewing surface) of the display panel 110. Therefore, when the user looks at the front of the display device 110, the optoelectronic devices 11, 12 are not visible to the user.

[0041] For example, the first optoelectronic device 11 may be a camera, and the second optoelectronic device 12 may be a sensing sensor such as a proximity sensor or an illuminance sensor. For example, the sensing sensor may be an infrared sensor that senses infrared rays. Conversely, the first optoelectronic device 11 may be a sensing sensor, and the second optoelectronic device 12 may be a camera.

[0042] Hereinafter, for the sake of convenience of explanation, an example will be described in which the first optoelectronic device 11 is a camera and the second optoelectronic device 12 is an infrared-based sensing sensor. Here, the camera may be a camera lens or an image sensor.

[0043] When the first optoelectronic device 11 is a camera, this camera is located behind (below) the display panel 110, but may also be a front camera that captures the front direction of the display panel 110. Therefore, the user can take a picture through a camera that is not visible on the viewing surface while looking at the viewing surface of the display panel 110.

[0044] The general area NA and one or more optical areas OA1, OA2 included in the display area DA are areas where video can be displayed. However, the general area NA is an area where a light transmission structure does not need to be formed, and the one or more optical areas OA1, OA2 are areas where a light transmission structure should be formed.

[0045] Therefore, the one or more optical areas OA1, OA2 should have a transmittance of a certain level or higher, and the general area NA can have no light transmittance or a low transmittance of less than a certain level.

[0046] For example, in one or more optical regions OA1 and OA2 and the general region NA, the resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure, etc. may be different from each other.

[0047] For example, the number of sub-pixels per unit area in one or more optical regions OA1 and OA2 may be smaller than the number of sub-pixels per unit area in the general region NA. That is, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the general region NA. Here, the number of sub-pixels per unit area may have the same meaning as resolution or pixel density or pixel integration degree. For example, the unit of the number of sub-pixels per unit area can also be said to be PPI (Pixels Per Inch) which means the number of pixels within 1 inch.

[0048] For example, the number of sub-pixels per unit area in the first optical region OA1 may be less than the number of sub-pixels per unit area in the general region NA. The number of sub-pixels per unit area in the second optical region OA2 may be equal to or more than the number of sub-pixels per unit area in the first optical region OA1, and may be less than the number of sub-pixels per unit area in the general region NA.

[0049] On the other hand, as one method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, as described above, the pixel density difference design method can be applied. According to the pixel density difference design method, the display panel 110 can be designed such that the number of sub-pixels per unit area of at least one of the first optical region OA1 and the second optical region OA2 is less than the number of sub-pixels per unit area of the general region NA.

[0050] However, in some cases, different from this, as another method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2, a pixel size difference design method can be applied. According to the pixel size difference design method, although the number of sub-pixels per unit area of at least one of the first optical region OA1 and the second optical region OA2 is the same as or similar to the number of sub-pixels per unit area of the general region NA, the size of each sub-pixel SP (i.e., the light-emitting region size) arranged in at least one of the first optical region OA1 and the second optical region OA2 is smaller than the size of each sub-pixel SP (i.e., the size of the light-emitting region) arranged in the general region NA, and the display panel 110 can be designed accordingly.

[0051] Hereinafter, for the convenience of explanation, it is assumed that the pixel density difference design method among the two methods (pixel density difference design method, pixel size difference design method) for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2 is applied and explained. Therefore, hereinafter, the fact that the number of sub-pixels per unit area is small may be an expression corresponding to the fact that the size of the sub-pixels is small, and the fact that the number of sub-pixels per unit area is large may be an expression corresponding to the fact that the size of the sub-pixels is large.

[0052] The first optical region OA1 can have various shapes such as circular, elliptical, square, hexagonal, or octagonal. The second optical region OA2 can have various shapes such as circular, elliptical, square, hexagonal, or octagonal. The first optical region OA1 and the second optical region OA2 may have the same shape or different shapes.

[0053] Referring to FIG. 1c, when the first optical region OA1 and the second optical region OA2 are in contact, the entire optical region including the first optical region OA1 and the second optical region OA2 can also have various shapes such as circular, elliptical, square, hexagonal, or octagonal. Hereinafter, for the sake of convenience of explanation, it is exemplified that the first optical region OA1 and the second optical region OA2 are each circular.

[0054] In the display device 100 according to an embodiment of the present disclosure, when the first optoelectronic device 11, which is not exposed to the outside and is hidden under the display device 100, is a camera, the display device 100 according to an embodiment of the present disclosure can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0055] According to this, in the case of the display device 100 according to an embodiment of the present disclosure, since a notch or a camera hole for camera exposure does not have to be formed in the display panel 110, a decrease in the area of the display area DA does not occur. As a result, since a notch or a camera hole for camera exposure does not have to be formed in the display panel 110, the size of the bezel area can be reduced, there are no design constraints, and the degree of freedom in design can be increased.

[0056] In the display device 100 according to an embodiment of the present disclosure, although one or more optoelectronic devices 11, 12 are arranged hidden behind the display panel 110, the one or more optoelectronic devices 11, 12 must receive light normally and execute a predetermined function normally.

[0057] Further, in the display device 100 according to an embodiment of the present disclosure, although one or more optoelectronic devices 11, 12 are arranged hidden behind the display panel 110 and overlap with the display area DA, in the display area DA, normal video display must be possible in one or more optical regions OA1, OA2 that overlap with the one or more optoelectronic devices 11, 12.

[0058] Since the first optical region OA1 mentioned above is designed as a transmissible region, the video display characteristics in the first optical region OA1 may be different from those in the general region NA.

[0059] Also, when designing the first optical region OA1 to improve the video display characteristics, there is a possibility that the transmittance of the first optical region OA1 may decrease.

[0060] Therefore, the embodiment of the present disclosure presents a structure of the first optical region OA1 that can improve the transmittance in the first optical region OA1 without causing variations in video quality between the first optical region OA1 and the general region NA.

[0061] Furthermore, the embodiment of the present disclosure presents a structure of the second optical region OA2 that can improve the video quality in the second optical region OA2 and improve the transmittance in the second optical region OA2, not only for the first optical region OA1 but also for the second optical region OA2.

[0062] Note that in the display device 100 according to the embodiment of the present disclosure, the first optical region OA1 and the second optical region OA2 are similar in that they are light transmissible regions, but their usage examples may be different. Therefore, in the display device 100 according to the embodiment of the present disclosure, the structure of the first optical region OA1 and the structure of the second optical region OA2 may be designed to be different from each other.

[0063] FIG. 2 is a system configuration diagram of the display device 100 according to the embodiment of the present disclosure.

[0064] Referring to FIG. 2, the display device 100 may include a display panel 110 and a display driving circuit as components for video display.

[0065] The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 220, a gate driving circuit 230, a display controller 240, and the like.

[0066] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The non-display area NDA may be an outer area of the display area DA, which can also be referred to as a bezel area. All or part of the non-display area NDA may be an area visible from the front of the display device 100 or an area that is bent and not visible from the front of the display device 100.

[0067] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. Further, the display panel 110 may further include various types of signal lines for driving the plurality of sub-pixels SP.

[0068] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element. For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting element is composed of an organic light-emitting diode (OLED). As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is composed of an inorganic-based light-emitting diode. As yet another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting element is a quantum dot, which is a semiconductor crystal that emits light by itself.

[0069] Depending on the type of the display device 100, the structure of each of the plurality of sub-pixels SP may vary. For example, when the display device 100 is a self-emitting display device that emits light from the sub-pixels SP by itself, each sub-pixel SP may include a light-emitting element that emits light by itself, one or more transistors, and one or more capacitors.

[0070] For example, some types of signal lines may include a plurality of data lines DL that transmit data signals (also referred to as data voltages or video signals), a plurality of gate lines GL that transmit gate signals (also referred to as scan signals), and the like.

[0071] The plurality of data lines DL and the plurality of gate lines GL can intersect each other. Each of the plurality of data lines DL can be arranged while extending in a first direction. Each of the plurality of gate lines GL can be arranged while extending in a second direction that may be perpendicular to the first direction. Here, the first direction can be the column direction, and the second direction can be the row direction. Or, the first direction may be the row direction, and the second direction may be the column direction.

[0072] The data driving circuit 220 is a circuit for driving a plurality of data lines DL and can output a data signal to the plurality of data lines DL. The gate driving circuit 230 is a circuit for driving a plurality of gate lines GL and can output a gate signal to the plurality of gate lines GL.

[0073] The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing for the plurality of data lines DL and the driving timing for the plurality of gate lines GL.

[0074] The display controller 240 can supply a data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220, and can supply a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230.

[0075] The display controller 240 can receive input video data from the host system 250 and supply video data Data to the data driving circuit 220 based on the input video data.

[0076] The data driving circuit 220 can receive digital video data Data from the display controller 240, convert the received video data Data into an analog data signal, and output it to a plurality of data lines DL.

[0077] The gate driving circuit 230 is supplied with a first gate voltage corresponding to the turn-on level voltage and a second gate voltage corresponding to the turn-off level voltage together with various gate driving control signals GCS, generates a gate signal, and can supply the generated gate signal to a plurality of gate lines GL.

[0078] For example, the data driving circuit 220 may be connected to the display panel 110 by a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or may be configured by a chip on film (COF) method and can be connected to the display panel 110.

[0079] The gate driving circuit 230 may be connected to the display panel 110 by a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel 110 according to a chip on film (COF) method. Alternatively, the gate driving circuit 230 may be of a gate in panel (GIP) type and formed in the non-display area NDA of the display panel 110. The gate driving circuit 230 may be disposed on the substrate or connected to the substrate. That is, in the case of the GIP type, the gate driving circuit 230 can be disposed in the non-display area NDA of the substrate. The gate driving circuit 230 can be connected to the substrate if it is of a chip on glass (COG) type, a chip on film (COF) type, etc.

[0080] On the one hand, at least one of the data driving circuit 220 and the gate driving circuit 230 may be arranged in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be arranged so as not to overlap with the sub-pixel SP, or may be arranged so as to partially or entirely overlap with the sub-pixel SP.

[0081] The data driving circuit 220 may be connected to one side (for example, the upper side or the lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 220 may be entirely connected to both sides (for example, the upper side and the lower side) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110.

[0082] The gate driving circuit 230 may be connected to one side (for example, the left side or the right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 230 may be entirely connected to both sides (for example, the left side and the right side) of the display panel 110, or may be connected to two or more sides of the four sides of the display panel 110.

[0083] The display controller 240 can be configured as a component separate from the data driving circuit 220, or can be integrated with the data driving circuit 220 and configured as an integrated circuit.

[0084] The display controller 240 may be a timing controller used in ordinary display technology, or a control device that can further execute other control functions including the timing controller, or a control device different from the timing controller, or a circuit within the control device. The display controller 240 can be realized as various circuits and electronic components such as an IC (Integrated Circuit), an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a processor (Processor).

[0085] The display controller 240 is mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data driving circuit 220 and the gate driving circuit 230 via the printed circuit board, the flexible printed circuit, etc.

[0086] The display controller 240 can transmit and receive signals with the data driving circuit 220 according to one or more predetermined interfaces. For example, the interface may include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Embedded Clock Point-Point Interface), an SPI (Serial Peripheral Interface), etc.

[0087] The display device 100 according to an embodiment of the present disclosure may further include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred or detect a touch position by a touch object such as a finger or a pen in order to provide not only a video display function but also a touch sensing function.

[0088] The touch sensing circuit may include a touch driving circuit 260 that drives and senses a touch sensor to generate and output touch sensing data, and a touch controller 270 that can sense touch occurrence or detect a touch position using the touch sensing data.

[0089] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit 260.

[0090] The touch sensor may exist in the form of a touch panel outside the display panel 110, or may exist inside the display panel 110. When the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is of the external type, the touch panel and the display panel 110 are manufactured separately and can be combined in the assembly process. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0091] When the touch sensor exists inside the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0092] The touch driving circuit 260 can supply a touch driving signal to at least one of the plurality of touch electrodes, sense at least one of the plurality of touch electrodes, and generate touch sensing data.

[0093] The touch sensing circuit can perform touch sensing in a self-capacitance sensing method or a mutual-capacitance sensing method.

[0094] When the touch sensing circuit performs touch sensing in the self - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self - capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0095] When the touch sensing circuit performs touch sensing in the mutual - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual - capacitance sensing method, the plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0096] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented by separate devices or may be implemented by one device. Also, the touch driving circuit 260 and the data driving circuit 220 may be implemented by separate devices or may be implemented by one device.

[0097] The display device 100 may further include a power supply circuit that supplies various power supplies to the display driving circuit and / or the touch sensing circuit.

[0098] The display device 100 according to the embodiments of the present disclosure may be a portable terminal such as a smartphone or a tablet, or may be a monitor or a television (TV) of various sizes, etc., and is not limited thereto, and may be a display of various types and various sizes that can represent information and images.

[0099] As described above, the display area DA in the display panel 110 may include a general area NA and one or more optical areas OA1, OA2. The general area NA and the one or more optical areas OA1, OA2 are areas where video display is possible. However, the general area NA is an area where a light transmission structure does not need to be formed, and the one or more optical areas OA1, OA2 are areas where a light transmission structure should be formed.

[0100] As described above, the display area DA in the display panel 110 may include one or more optical areas OA1, OA2 together with the general area NA. For the sake of convenience of explanation, it is assumed that the display area DA includes both the first optical area OA1 and the second optical area OA2 (FIGS. 1b and 1c).

[0101] FIG. 3 is a schematic diagram of the display panel 110 according to an embodiment of the present disclosure.

[0102] Referring to FIG. 3, a plurality of sub-pixels SP may be arranged in the display area DA of the display panel 110. The plurality of sub-pixels SP may be arranged in the general area NA, the first optical area OA1, and the second optical area OA2 included in the display area DA.

[0103] Referring to FIG. 3, each of the plurality of sub-pixels SP may include a light-emitting element ED and a sub-pixel circuit unit SPC configured to drive the light-emitting element ED.

[0104] Referring to FIG. 3, the sub-pixel circuit unit SPC may include a driving transistor DT for driving the light-emitting element ED, a scan transistor ST for transmitting a data voltage Vdata to the first node N1 of the driving transistor DT, and a storage capacitor Cst for maintaining a constant voltage during one frame, etc.

[0105] The driving transistor DT may include a first node N1 to which a data voltage can be applied, a second node N2 electrically connected to the light-emitting element ED, and a third node N3 to which a driving voltage ELVDD is applied from a driving voltage line DVL. In the driving transistor DT, the first node N1 is a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for convenience of explanation, in the driving transistor DT, the case where the first node N1 is a gate node, the second node N2 is a source node, and the third node N3 is a drain node will be taken as an example.

[0106] The light-emitting element ED may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The anode electrode AE is a pixel electrode disposed in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DT of each sub-pixel SP. The cathode electrode CE is a common electrode commonly disposed in a plurality of sub-pixels SP, and a base voltage ELVSS may be applied thereto.

[0107] For example, the anode electrode AE may be a pixel electrode and the cathode electrode CE may be a common electrode. Conversely, the anode electrode AE may be a common electrode and the cathode electrode CE may be a pixel electrode. Hereinafter, for convenience of explanation, it is assumed that the anode electrode AE is a pixel electrode and the cathode electrode CE is a common electrode.

[0108] The light-emitting element ED can have a predetermined light-emitting region EA, and the light-emitting region EA of the light-emitting element ED can be defined as a region where the anode electrode AE, the light-emitting layer EL, and the cathode electrode CE overlap.

[0109] For example, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. When the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED may include an organic light-emitting layer EL containing an organic substance.

[0110] The scan transistor ST is controlled to be turned on or off by a scan signal SCAN of a gate signal applied through a gate line GL, and can be electrically connected between a first node N1 of the drive transistor DT and a data line DL.

[0111] The storage capacitor Cst can be electrically connected between a first node N1 of the drive transistor DT and a second node N2.

[0112] The sub-pixel circuit unit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DT and ST and one capacitor Cst as shown in FIG. 3. In some cases, it may further include one or more transistors, or may further include one or more capacitors.

[0113] The storage capacitor Cst is not a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor (Internal Capacitor) existing between a first node N1 of the drive transistor DT and a second node N2, but can be an external capacitor (External Capacitor) intentionally designed outside the drive transistor DT. Each of the drive transistor DT and the scan transistor ST may be an n-type transistor or a p-type transistor.

[0114] Circuit elements (especially, a light-emitting element ED composed of an organic light-emitting diode OLED containing an organic substance) in each sub-pixel SP are vulnerable to external moisture, oxygen, etc. Therefore, a sealing layer ENCAP for preventing external moisture and oxygen from penetrating into the circuit elements (especially, the light-emitting element ED) can be disposed on the display panel 110. The sealing layer ENCAP can be disposed so as to cover the light-emitting element ED.

[0115] FIG. 4 schematically shows a general area NA, a first optical bezel area OBA1, and a first optical area OA1 in the display panel 110 according to an embodiment of the present disclosure.

[0116] Referring to FIG. 4, the display panel 110 according to an embodiment of the present disclosure may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed.

[0117] Referring to FIG. 4, the display area DA may include a first optical area OA1, a first optical bezel area OBA1, and a general area NA.

[0118] Referring to FIG. 4, the first optical area OA1 is an area overlapping with the first optoelectronic device 11 and may be a transmissive area through which light necessary for the operation of the first optoelectronic device 11 can pass. Here, the light passing through the first optical area OA1 may include light in a single wavelength band or light in various wavelength bands. For example, the light passing through the first optical area OA1 may include one or more of visible light, infrared light, or ultraviolet light. For example, when the first optoelectronic device 11 is a camera, the light passing through the first optical area OA1 and used by the first optoelectronic device 11 may include visible light. As another example, when the first optoelectronic device 11 is an infrared-based sensor, the light passing through the first optical area OA1 and used by the first optoelectronic device 11 may include infrared light (also referred to as infrared light).

[0119] Referring to FIG. 4, the first optical bezel area OBA1 may be an area located on the outer contour of the first optical area OA1. The general area NA may be an area located on the outer contour of the first optical bezel area OBA1. The first optical bezel area OBA1 may be disposed between the first optical area OA1 and the general area NA.

[0120] For example, the first optical bezel area OBA1 may be disposed only on the outer contour of a part of the boundary of the first optical area OA1 or on the outer contour of the entire boundary of the first optical area OA1.

[0121] When the first optical bezel region OBA1 is disposed along the outline of the entire boundary of the first optical region OA1, the first optical bezel region OBA1 can have an annular shape surrounding the first optical region OA1.

[0122] For example, the first optical region OA1 can have various shapes such as circular, elliptical, polygonal, or irregular shapes. The first optical bezel region OBA1 can have various annular shapes (e.g., annular shape, elliptical ring shape, polygonal ring shape, or irregular ring shape, etc.) surrounding the first optical region OA1 having various shapes.

[0123] Referring to FIG. 4, the display region DA may include a plurality of light-emitting regions EA. Since the first optical region OA1, the first optical bezel region OBA1, and the general region NA are regions included in the display region DA, each of the first optical region OA1, the first optical bezel region OBA1, and the general region NA may include a plurality of light-emitting regions EA.

[0124] For example, the plurality of light-emitting regions EA may include a first-color light-emitting region that emits light of a first color, a second-color light-emitting region that emits light of a second color, and a third-color light-emitting region that emits light of a third color.

[0125] At least one of the first-color light-emitting region, the second-color light-emitting region, and the third-color light-emitting region can have an area different from that of the others.

[0126] The first color, the second color, and the third color can be various colors as different colors. For example, the first color, the second color, and the third color may include red, green, and blue.

[0127] Hereinafter, for the sake of convenience of explanation, an example will be given in the case where the first color is red, the second color is green, and the third color is blue. However, it is not limited thereto.

[0128] When the first color is red, the second color is green, and the third color is blue, the area of the blue light-emitting region EA_B may be the largest among the areas of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B.

[0129] The light-emitting element ED disposed in the red light-emitting region EA_R may include a light-emitting layer EL that emits red light. The light-emitting element ED disposed in the green light-emitting region EA_G may include a light-emitting layer EL that emits green light. The light-emitting element ED disposed in the blue light-emitting region EA_B may include a light-emitting layer EL that emits blue light.

[0130] Among the light-emitting layer EL that emits red light, the light-emitting layer EL that emits green light, and the light-emitting layer EL that emits blue light, the organic substances contained in the light-emitting layer EL that emits blue light may be most likely to deteriorate materially.

[0131] By designing the area of the blue light-emitting region EA_B to be the largest, the current density supplied to the light-emitting element ED disposed in the blue light-emitting region EA_B may be the lowest. Therefore, the degree of deterioration of the light-emitting element ED disposed in the blue light-emitting region EA_B may be similar to the degree of deterioration of the light-emitting element ED disposed in the red light-emitting region EA_R and the degree of deterioration of the light-emitting element ED disposed in the green light-emitting region EA_G.

[0132] Therefore, the variation in deterioration among the light-emitting element ED disposed in the red light-emitting region EA_R, the light-emitting element ED disposed in the green light-emitting region EA_G, and the light-emitting element ED disposed in the blue light-emitting region EA_B can be eliminated or reduced, so that the image quality can be improved. In addition, by eliminating or reducing the variation in deterioration among the light-emitting element ED disposed in the red light-emitting region EA_R, the light-emitting element ED disposed in the green light-emitting region EA_G, and the light-emitting element ED disposed in the blue light-emitting region EA_B, it is possible to have the effect of reducing the variation in the lifetimes among the light-emitting element ED disposed in the red light-emitting region EA_R, the light-emitting element ED disposed in the green light-emitting region EA_G, and the light-emitting element ED disposed in the blue light-emitting region EA_B.

[0133] Referring to FIG. 4, the first optical region OA1 is a transmissive region and should have a high transmittance. For this purpose, the cathode electrode CE may include a plurality of cathode holes CH in the first optical region OA1. That is, in the first optical region OA1, the cathode electrode CE may include a plurality of cathode holes CH.

[0134] Referring to FIG. 4, the cathode electrode CE does not include a cathode hole CH in the general region NA. That is, in the general region NA, the cathode electrode CE does not include a cathode hole CH.

[0135] Also, the cathode electrode CE does not include a cathode hole CH in the first optical bezel region OBA1. That is, in the first optical bezel region OBA1, the cathode electrode CE does not include a cathode hole CH.

[0136] In the first optical region OA1, the plurality of cathode holes CH formed in the cathode electrode CE can also be referred to as a plurality of first transmission regions TA1 or a plurality of openings. Here, in FIG. 4, one cathode hole CH has a circular shape, but in addition to the circular shape, it may also have various shapes such as an elliptical shape, a polygonal shape, or an irregular shape.

[0137] Referring to FIG. 4, the second optical region OA2 can be arranged adjacent to the first optical region OA1. The arrangement of the light-emitting region EA in the second optical region OA2 will be described in more detail with reference to FIG. 11.

[0138] FIG. 5 shows the light-emitting elements ED1, ED2, ED3, ED4 arranged in the general region NA, the first optical bezel region OBA1, and the first optical region OA1, and the sub-pixel circuit portions SPC1, SPC2, SPC3, SPC4 for driving the light-emitting elements ED1, ED2, ED3, ED4 in the display panel 110 according to an embodiment of the present disclosure.

[0139] However, each of the sub-pixel circuit portions SPC1, SPC2, SPC3, and SPC4 may include transistors DT, ST, and a storage capacitor Cst as shown in FIG. 3. However, for the sake of convenience of explanation, the sub-pixel circuits SPC1, SPC2, SPC3, and SPC4 are each abbreviated as driving transistors DT1, DT2, DT3, and DT4.

[0140] Referring to FIG. 5, the general region NA, the first optical region OA1, and the first optical bezel region OBA1 may have not only positional differences but also structural differences.

[0141] As structural differences, sub-pixel circuit portions SPC1, SPC2, SPC3, and SPC4 may be arranged in the first optical bezel region OBA1 and the general region NA, but no sub-pixel circuit portion is arranged in the first optical region OA1. That is, transistors DT1, DT2, DT3, and DT4 may be arranged in the first optical bezel region OBA1 and the general region NA, but no transistor is arranged in the first optical region OA1.

[0142] The transistors and the storage capacitors included in the sub-pixel circuit portions SPC1, SPC2, SPC3, and SPC4 are configured to be able to reduce the transmittance. Thereby, by not arranging the sub-pixel circuit portions SPC1, SPC2, SPC3, and SPC4 in the first optical region OA1, the transmittance of the first optical region OA1 can be further increased.

[0143] The sub-pixel circuit portions SPC1, SPC2, SPC3, and SPC4 are arranged only in the general region NA and the first optical bezel region OBA1, but the light-emitting elements ED1, ED2, ED3, and ED4 can be arranged in all of the general region NA, the first optical bezel region OBA1, and the first optical region OA1.

[0144] Referring to FIG. 5, in the first optical region OA1, the first light-emitting element ED1 is disposed, but in the first optical region OA1, the first pixel circuit portion SPC1 for driving the first light-emitting element ED1 is not disposed.

[0145] Referring to FIG. 5, the first sub-pixel circuit portion SPC1 for driving the first light-emitting element ED1 disposed in the first optical region OA1 is not disposed in the first optical region OA1 and may be disposed in the first optical bezel region OBA1.

[0146] Hereinafter, the general region NA, the first optical region OA1, and the first optical bezel region OBA1 will be described in more detail.

[0147] Referring to FIG. 5, the plurality of light-emitting regions EA included in the display panel 110 according to the embodiment of the present disclosure may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. Here, the first light-emitting region EA1 may be included in the first optical region OA1, the second light-emitting region EA2 may be included in the first optical bezel region OBA1, and the third light-emitting region EA3 may be included in the general region NA. Hereinafter, it is assumed that the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are light-emitting regions of the same color.

[0148] Referring to FIG. 5, the display panel 110 according to the embodiment of the present disclosure includes a first light-emitting element ED1 disposed in the first optical region OA1 and having the first light-emitting region EA1, a second light-emitting element ED2 disposed in the first optical bezel region OBA1 and having the second light-emitting region EA2, and a third light-emitting element ED3 disposed in the general region NA and having the third light-emitting region EA3.

[0149] Referring to FIG. 5, the display panel 110 according to the embodiment of the present disclosure may further include a first sub-pixel circuit portion SPC1 configured to drive the first light-emitting element ED1, a second sub-pixel circuit portion SPC2 configured to drive the second light-emitting element ED2, and a third sub-pixel circuit portion SPC3 configured to drive the third light-emitting element ED3.

[0150] Referring to FIG. 5, the first sub-pixel circuit portion SPC1 may include a first driving transistor DT1. The second sub-pixel circuit portion SPC2 may include a second driving transistor DT2. The third sub-pixel circuit portion SPC3 may include a third driving transistor DT3.

[0151] Referring to FIG. 5, in the display panel 110 according to an embodiment of the present disclosure, the second sub-pixel circuit portion SPC2 may be disposed in a first optical bezel region OBA1 where a corresponding second light-emitting element ED2 is disposed, and the third sub-pixel circuit portion SPC3 may be disposed in a general region NA where a corresponding third light-emitting element ED3 is disposed.

[0152] Referring to FIG. 5, in the display panel 110 according to an embodiment of the present disclosure, the first sub-pixel circuit portion SPC1 is not disposed in the first optical region OA1 where the corresponding first light-emitting element ED1 is disposed, but can be disposed in a first optical bezel region OBA1 located on the outer contour of the first optical region OA1. Thereby, the transmittance of the first optical region OA1 can be increased.

[0153] Referring to FIG. 5, the display panel 110 according to an embodiment of the present disclosure may further include an anode extension line AEL that electrically connects the first sub-pixel circuit portion SPC1 disposed in the first optical bezel region OBA1 and the first light-emitting element ED1 disposed in the first optical region OA1.

[0154] The anode extension line AEL can electrically extend the anode electrode AE of the first light-emitting element ED1 to the second node N2 of the first driving transistor DT1 in the first sub-pixel circuit portion SPC1.

[0155] As described above, in the display panel 110 according to an embodiment of the present disclosure, the first sub-pixel circuit portion SPC1 for driving the first light-emitting element ED1 disposed in the first optical region OA1 may be disposed not in the first optical region OA1 but in the first optical bezel region OBA1. Such a structure is also referred to as an Anode Extension Structure.

[0156] When the display panel 110 according to an embodiment of the present disclosure has an anode extension structure, all or part of the anode extension line AEL can be disposed in the first optical region OA1, and the anode extension line AEL may include a transparent wiring. Thereby, even when the first sub-pixel circuit portion SPC1 and the anode extension line AEL connecting the first light-emitting element ED1 are disposed in the first optical region OA1, it is possible to prevent a decrease in the transmittance of the first optical region OA1.

[0157] Referring to FIG. 5, the plurality of light-emitting regions EA may emit light of the same color as the first light-emitting region EA1 and may further include a fourth light-emitting region EA4 included in the first optical region OA1.

[0158] Referring to FIG. 5, the fourth light-emitting region EA4 may be disposed adjacent to the first light-emitting region EA1 in the row direction or the column direction.

[0159] Referring to FIG. 5, the display panel 110 according to an embodiment of the present disclosure may further include a fourth light-emitting element ED4 disposed in the first optical region OA1 and having the fourth light-emitting region EA4, and a fourth sub-pixel circuit portion SPC4 configured to drive the fourth light-emitting element ED4.

[0160] Referring to FIG. 5, the fourth sub-pixel circuit portion SPC4 may include a fourth driving transistor DT4. For convenience of explanation, the scan transistor ST, the storage capacitor Cst, etc. included in the fourth sub-pixel circuit portion SPC4 are omitted from FIG. 5.

[0161] Referring to FIG. 5, the fourth sub-pixel circuit portion SPC4 is a circuit for driving the fourth light-emitting element ED4 disposed in the first optical region OA1, but it may be disposed in the first optical bezel region OBA1.

[0162] Referring to FIG. 5, the display panel 110 according to the embodiment of the present disclosure may further include an anode extension line AEL that electrically connects the fourth pixel circuit SPC4 and the fourth light-emitting element ED4.

[0163] All or part of such an anode extension line AEL can be disposed in the first optical region OA1, and the anode extension line AEL may include a transparent wiring.

[0164] As described above, the first sub-pixel circuit portion SPC1 disposed in the first optical bezel region OBA1 can drive one light-emitting element ED1 disposed in the first optical region OA1. Such a circuit portion connection method is called a one-to-one (1:1) circuit portion connection method.

[0165] Thereby, the number of sub-pixel circuit portions SPC disposed in the first optical bezel region OBA1 can be significantly increased. The structure of the first optical bezel region OBA1 becomes complicated, and the aperture ratio (or light-emitting area) of the first optical bezel region OBA1 can be decreased.

[0166] In order to increase the aperture ratio (or light-emitting area) of the first optical bezel region OBA1 despite having an anode extension structure, the display device 100 according to the embodiment of the present disclosure can have a 1:N (N is 2 or more) circuit portion connection method.

[0167] According to the 1:N circuit portion connection method, the first sub-pixel circuit portion SPC1 disposed in the first optical bezel region OBA1 can drive two or more light-emitting elements ED disposed in the first optical region OA1 simultaneously.

[0168] In FIG. 6, for the sake of convenience of explanation, when a 1:2 circuit unit connection method is applied, that is, when the first sub-pixel circuit unit SPC1 arranged in the first optical bezel region OBA1 drives two or more light-emitting elements ED1 and ED4 arranged in the first optical region OA1 at the same time, this case is taken as an example.

[0169] FIG. 6 shows the light-emitting elements ED1, ED2, ED3, and ED4 arranged in the general region NA, the first optical bezel region OBA1, and the first optical region OA1, and the sub-pixel circuit units SPC1, SPC2, and SPC3 for driving the light-emitting elements ED1, ED2, ED3, and ED4 in the display panel 110 according to the embodiment of the present disclosure.

[0170] Referring to FIG. 6, the fourth light-emitting element ED4 arranged in the first optical region OA1 can be driven by the first sub-pixel circuit unit SPC1 for driving the first light-emitting element ED1 arranged in the first optical region OA1. That is, the first sub-pixel circuit unit SPC1 arranged in the first optical bezel region OBA1 can be configured to drive both the first light-emitting element ED1 and the fourth light-emitting element ED4 arranged in the first optical region OA1.

[0171] Thereby, although the display panel 110 has an anode extension structure, by reducing the number of sub-pixel circuit units SPC arranged in the first optical bezel region OBA1, the aperture and light-emitting area of the first optical bezel region OBA1 can be increased.

[0172] In FIG. 6, the first light-emitting element ED1 and the fourth light-emitting element ED4 that are driven together by the first sub-pixel circuit unit SPC1 arranged in the first optical bezel region OBA1 are light-emitting elements that emit light of the same color and can be light-emitting elements adjacent in the row direction or the column direction.

[0173] Referring to FIG. 6, the anode extension line AEL can connect the first sub-pixel circuit unit SPC1 arranged in the first optical bezel region OBA1 to the first light-emitting element ED1 and the fourth light-emitting element ED4 arranged in the first optical region OA1.

[0174] FIG. 7 is a plan view of the general area NA, the optical bezel area OBA, and the optical area OA in the display panel 110 according to an embodiment of the present disclosure.

[0175] Referring to FIG. 7, in the display panel 110 according to an embodiment of the present disclosure, the plurality of light-emitting areas EA disposed in each of the general area NA, the optical bezel area OBA, and the optical area OA may include a red light-emitting area EA_R, a green light-emitting area EA_G, and a blue light-emitting area EA_B.

[0176] Referring to FIG. 7, in the display panel 110 according to an embodiment of the present disclosure, the cathode electrode CE may be commonly disposed in the general area NA, the optical bezel area OBA, and the optical area OA.

[0177] The cathode electrode CE can include a plurality of cathode holes CH, and the plurality of cathode holes CH of the cathode electrode CE can be disposed in the optical area OA.

[0178] The general area NA and the optical bezel area OBA are areas where light cannot pass through, and the optical area OA can be an area where light can pass through. Thereby, the transmittance in the optical area OA can be higher than the transmittance in the optical bezel area OBA and the general area NA.

[0179] The entire optical area OA is an area where light can pass through, and the plurality of cathode holes CH in the optical area OA can be a transmission area TA where light can pass through better. That is, the remaining area in the optical area OA excluding the plurality of cathode holes CH is an area where light can pass through, and the transmittance of the plurality of cathode holes CH in the optical area OA may be higher than the transmittance of the remaining area in the optical area OA excluding the plurality of cathode holes CH.

[0180] In contrast, the plurality of cathode holes CH in the optical area OA are a transmission area TA where light can pass through, and the remaining area in the optical area OA excluding the plurality of cathode holes CH can be an area where light does not pass through.

[0181] Referring to FIG. 7, the arrangement of the light-emitting regions EA in the optical region OA, the arrangement of the light-emitting regions EA in the optical bezel region OBA, and the arrangement of the light-emitting regions EA in the general region NA may be the same as each other.

[0182] Referring to FIG. 7, the plurality of light-emitting regions EA may include a first light-emitting region EA1 included in the optical region OA, a second light-emitting region EA2 included in the optical bezel region OBA that emits light of the same color as the first light-emitting region EA1, and a third light-emitting region EA3 included in the general region NA that emits light of the same color as the first light-emitting region EA1.

[0183] Referring to FIG. 7, the plurality of light-emitting regions EA may further include a fourth light-emitting region EA4 included in the optical region OA that emits light of the same color as the first light-emitting region EA1.

[0184] Referring to FIG. 7, the display panel 110 according to an embodiment of the present disclosure may include a first anode electrode AE1 disposed in the optical region OA, a second anode electrode AE2 disposed in the optical bezel region OBA, a third anode electrode AE3 disposed in the general region NA, and a fourth anode electrode AE4 disposed in the optical region OA1.

[0185] The display panel 110 according to an embodiment of the present disclosure may further include a cathode electrode CE commonly disposed in the general region NA, the optical bezel region OBA, and the optical region OA.

[0186] The display panel 110 according to an embodiment of the present disclosure may include a first light-emitting layer EL1 disposed in the optical region OA, a second light-emitting layer EL2 disposed in the optical bezel region OBA, a third light-emitting layer EL3 disposed in the general region NA, and a fourth light-emitting layer EL4 disposed in the optical region OA, and the like.

[0187] The first to fourth light-emitting layers EL4 may be light-emitting layers that emit light of the same color. In this case, the first to fourth light-emitting layers EL4 may be separately arranged individually, or may be integrally arranged as one.

[0188] Referring to FIG. 7, a first anode electrode AE1, a first light-emitting layer EL1, and a cathode electrode CE can constitute a first light-emitting element ED1, a second anode electrode AE2, a second light-emitting layer EL2, and a cathode electrode CE can constitute a second light-emitting element ED2, a third anode electrode AE3, a third light-emitting layer EL3, and a cathode electrode CE can constitute a third light-emitting element ED3, and a fourth anode electrode AE4, a fourth light-emitting layer EL4, and a cathode electrode CE can constitute a fourth light-emitting element ED4.

[0189] Hereinafter, the cross-sectional structure along the X-Y line in FIG. 7 will be described in more detail with reference to FIGS. 8 and 9.

[0190] The portion where the X-Y line in FIG. 7 is shown includes a part of the optical bezel region OBA and a part of the optical region OA with reference to the boundary between the optical bezel region OBA and the optical region OA.

[0191] The portion where the X-Y line in FIG. 7 is shown may include a first light-emitting region EA1 and a fourth light-emitting region EA4 included in the optical region OA, and a second light-emitting region EA2 included in the optical bezel region OBA. The first light-emitting region EA1, the fourth light-emitting region EA4, and the second light-emitting region EA2 are examples of the light-emitting region EA that emits light of the same color.

[0192] FIG. 8 is a cross-sectional view of the display panel 110 according to an embodiment of the present disclosure, and is a cross-sectional view of the optical bezel region OBA and the optical region OA of the display panel 110. However, FIG. 8 is a cross-sectional view when the 1:1 circuit portion connection method is applied, similar to FIG. 5.

[0193] Referring to FIG. 8, the display panel 110 may include a transistor forming part, a light emitting element forming part, and an encapsulation part when viewed from a vertical structure.

[0194] The transistor forming part may include a substrate SUB, a first buffer layer BUF1 on the substrate SUB, and various transistors DT1, DT2, a storage capacitor Cst, and various electrodes or signal wirings formed on the first buffer layer BUF1.

[0194] The substrate SUB may include a first substrate SUB1 and a second substrate SUB2, and may include an intermediate film INTL between the first substrate SUB1 and the second substrate SUB2. Here, for example, the intermediate film INTL is an inorganic film and can block moisture penetration.

[0195] A lower shield metal BSM can be disposed on the substrate SUB. The lower shield metal BSM can be located under the first active layer ACT1 of the first driving transistor DT1.

[0196] The first buffer layer BUF1 may be a single film or a multiple film. When the first buffer layer BUF1 is a multiple film, the first buffer layer BUF1 may include a multi-buffer layer MBUF and an active buffer layer ABUF.

[0197] Various transistors DT1, DT2, a storage capacitor Cst, and various electrodes or signal wirings can be formed on the first buffer layer BUF1.

[0198] For example, the transistors DT1, DT2 formed on the first buffer layer BUF1 can be composed of the same material and located in the same layer. In contrast, as shown in FIG. 8, among the transistors DT1, DT2, the first driving transistor DT1 and the second driving transistor DT2 may be composed of different materials and arranged in different layers.

[0199] Referring to FIG. 8, the first driving transistor DT1 is a driving transistor DT for driving the first light-emitting element ED1 included in the optical region OA, and the second driving transistor DT2 can be a driving transistor DT for driving the second light-emitting element ED2 included in the optical bezel region OBA.

[0200] In other words, the first driving transistor DT1 is a driving transistor included in the first sub-pixel circuit portion SPC1 for driving the first light-emitting element ED1 included in the optical region OA, and the second driving transistor DT2 can be a driving transistor included in the second sub-pixel circuit portion SPC2 for driving the second light-emitting element ED2 included in the optical bezel region OBA.

[0201] Regarding the formation of the first driving transistor DT1 and the second driving transistor DT2, it is as follows.

[0202] The first driving transistor DT1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0203] The second driving transistor DT2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0204] The second active layer ACT2 of the second driving transistor DT2 can be positioned higher than the first active layer ACT1 of the first driving transistor DT1.

[0205] Under the first active layer ACT1 of the first driving transistor DT1, a first buffer layer BUF1 can be disposed, and under the second active layer ACT2 of the second driving transistor DT2, a second buffer layer BUF2 can be disposed.

[0206] That is, the first active layer ACT1 of the first drive transistor DT1 can be located on the first buffer layer BUF1, and the second active layer ACT2 of the second drive transistor DT2 can be located on the second buffer layer BUF2. Here, the second buffer layer BUF2 may be located higher than the first buffer layer BUF1.

[0207] The first active layer ACT1 of the first drive transistor DT1 is disposed on the first buffer layer BUF1, and a first gate insulating film GI1 can be disposed on the first active layer ACT1 of the first drive transistor DT1. A first gate electrode G1 of the first drive transistor DT1 is disposed on the first gate insulating film GI1, and a first interlayer insulating film ILD1 can be disposed on the first gate electrode G1 of the first drive transistor DT1.

[0208] Here, the first active layer ACT1 of the first drive transistor DT1 may include a first channel region overlapping with the first gate electrode G1, a first source connection region located on one side of the first channel region, and a first drain connection region located on the other side of the channel region.

[0209] A second buffer layer BUF2 can be disposed on the first interlayer insulating film ILD1.

[0210] The second active layer ACT2 of the second drive transistor DT2 is disposed on the second buffer layer BUF2, and a second gate insulating film GI2 can be disposed on the second active layer ACT2. A second gate electrode G2 of the second drive transistor DT2 is disposed on the second gate insulating film GI2, and a second interlayer insulating film ILD2 can be disposed on the second gate electrode G2.

[0211] Here, the second active layer ACT2 of the second drive transistor DT2 may include a second channel region overlapping with the second gate electrode G2, a second source connection region located on one side of the second channel region, and a second drain connection region located on the other side of the channel region.

[0212] The first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 may be disposed on the second interlayer insulating film ILD2. Also, the second source electrode S2 and the second drain electrode D2 of the second driving transistor DT2 may be disposed on the second interlayer insulating film ILD2.

[0213] The first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 may be connected to the first source connection region and the first drain connection region of the first active layer ACT1, respectively, through through-holes in the second interlayer insulating film ILD2, the second gate insulating film GI2, the second buffer layer BUF2, the first interlayer insulating film ILD1, and the first gate insulating film GI1.

[0214] The second source electrode S2 and the second drain electrode D2 of the second driving transistor DT2 may be connected to the second source connection region and the second drain connection region of the second active layer ACT2, respectively, through through-holes in the second interlayer insulating film ILD2 and the second gate insulating film GI2.

[0215] In FIG. 8, only the first driving transistor DT1 included in the second sub-pixel circuit portion SPC2 and the storage capacitor Cst are illustrated, and other transistors are omitted. Also, in FIG. 8, only the first driving transistor DT1 included in the first sub-pixel circuit portion SPC1 is shown, and other transistors and the storage capacitor are omitted.

[0216] Referring to FIG. 8, the storage capacitor Cst included in the second sub-pixel circuit portion SPC2 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0217] The first capacitor electrode PLT1 may be electrically connected to the second gate electrode G2 of the second driving transistor DT2, and the second capacitor electrode PLT2 may be electrically connected to the second source electrode S2 of the second driving transistor DT2.

[0218] On the other hand, referring to FIG. 8, a lower metal BML may be disposed under the second active layer ACT2 of the second driving transistor DT2. The lower metal BML can overlap all or part of the second active layer ACT2.

[0219] For example, the lower metal BML can be electrically connected to the second gate electrode G2. As another example, the lower metal BML can function as a light shield that blocks light flowing in from below. In this case, the lower metal BML may be electrically connected to the second source electrode S2.

[0220] The first driving transistor DT1 is a transistor for driving the first light-emitting element ED1 disposed in the optical region OA, but may be disposed in the optical bezel region OBA.

[0221] The second driving transistor DT2 is a transistor for driving the second light-emitting element ED2 disposed in the optical bezel region OBA, and may be disposed in the optical bezel region OBA.

[0222] Referring to FIG. 8, a first planarization layer PLN1 may be disposed on the first driving transistor DT1 and the second driving transistor DT2. That is, the first planarization layer PLN1 can be disposed on the first source electrode S1 and the first drain electrode D2 of the first driving transistor DT1, and on the second source electrode S2 and the second drain electrode D2 of the second driving transistor DT2.

[0223] Referring to FIG. 8, a first relay electrode RE1 and a second relay electrode RE2 may be disposed on the first planarization layer PLN1.

[0224] Here, the first relay electrode RE1 can be an electrode that relays the electrical connection between the first source electrode S1 of the first driving transistor DT1 and the first anode electrode AE1 of the first light-emitting element ED1. And the second relay electrode RE2 can be an electrode that relays the electrical connection between the second source electrode S2 of the second driving transistor DT2 and the second anode electrode AE2 of the second light-emitting element ED2.

[0225] The first relay electrode RE1 can be electrically connected to the first source electrode S1 of the first driving transistor DT1 through the hole of the first planarization layer PLN1. The second relay electrode RE2 can be electrically connected to the second source electrode S2 of the second driving transistor DT2 through another hole of the first planarization layer PLN1.

[0226] Referring to FIG. 8, the first relay electrode RE1 and the second relay electrode RE2 may be disposed in the first optical bezel region OBA1.

[0227] On the other hand, referring to FIG. 8, the anode extension line AEL can be connected to the first relay electrode RE1 and extended from the optical bezel region OBA to the optical region OA.

[0228] Referring to FIG. 8, the anode extension line AEL is a metal layer formed on the first relay electrode RE1 and can be composed of a transparent material.

[0229] Referring to FIG. 8, the second planarization layer PLN2 can be disposed while covering the first relay electrode RE1, the second relay electrode RE2, and the anode extension line AEL.

[0230] Referring to FIG. 8, the light emitting element forming part can be located on the second planarization layer PNL2.

[0231] Referring to FIG. 8, the light-emitting element forming portion may include a first light-emitting element ED1, a second light-emitting element ED2, and a fourth light-emitting element ED4 formed on the second planarization layer PNL2.

[0232] Referring to FIG. 8, the first light-emitting element ED1 and the fourth light-emitting element ED4 may be disposed in the optical region OA, and the second light-emitting element ED2 may be disposed in the optical bezel region OBA.

[0233] In the example of FIG. 8, the first light-emitting element ED1, the second light-emitting element ED2, and the fourth light-emitting element ED4 are light-emitting elements that emit light of the same color. Hereinafter, although each light-emitting layer EL of the first light-emitting element ED1, the second light-emitting element ED2, and the fourth light-emitting element ED4 may be formed separately, it is assumed that they are formed in common.

[0234] Referring to FIG. 8, the first light-emitting element ED1 can be composed of a region where the first anode electrode AE1, the light-emitting layer EL, and the cathode electrode CE overlap. The second light-emitting element ED2 can be composed of a region where the second anode electrode AE2, the light-emitting layer EL, and the cathode electrode CE overlap. The fourth light-emitting element ED4 can be composed of a region where the fourth anode electrode AE4, the light-emitting layer EL, and the cathode electrode CE overlap.

[0235] Referring to FIG. 8, the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 can be disposed on the second planarization layer PLN2.

[0236] The second anode electrode AE2 can be connected to the second relay electrode RE2 through a hole in the second planarization layer PLN2.

[0237] The first anode electrode AE1 can be connected to an anode extension line AEL extending from the optical bezel region OBA to the optical region OA through another hole in the second planarization layer PLN2.

[0238] The fourth anode electrode AE4 can be connected to another anode extension line AEL that extends from the optical bezel region OBA to the optical region OA1 through yet another hole in the second planarization layer PLN2.

[0239] Referring to FIG. 8, the bank BK can be disposed on the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4.

[0240] The bank BK can include a plurality of bank holes, and through the plurality of bank holes, a part of each of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 may be exposed. That is, the plurality of bank holes formed in the bank BK may overlap with a part of each of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4.

[0241] Referring to FIG. 8, the light-emitting layer EL can be disposed on the bank BK. The light-emitting layer EL can contact a part of the first anode electrode AE1, a part of the second anode electrode AE2, and a part of the fourth anode electrode AE4 through the plurality of bank holes.

[0242] Referring to FIG. 8, at least one space SPC may exist between the light-emitting layer EL and the bank BK.

[0243] Referring to FIG. 8, the cathode electrode CE can be disposed on the light-emitting layer EL. The cathode electrode CE can include a plurality of cathode holes CH. The plurality of cathode holes CH formed in the cathode electrode CE can be disposed in the optical region OA.

[0244] One cathode hole CH illustrated in FIG. 8 is a cathode hole located between the first light-emitting region EA1 and the fourth light-emitting region EA4.

[0245] Referring to FIG. 8, an encapsulation part can be disposed on the cathode electrode CE. The encapsulation part may include an encapsulation layer ENCAP formed on the cathode electrode CE.

[0246] Referring to FIG. 8, the encapsulation layer ENCAP can be a layer that prevents moisture and oxygen from penetrating into the light-emitting elements ED1, ED2, and ED4 disposed under the encapsulation layer ENCAP. In particular, the encapsulation layer ENCAP can prevent moisture or oxygen from penetrating into the light-emitting layer EL that may include an organic film. Here, the encapsulation layer ENCAP may be composed of a single film or a multiple film.

[0247] Referring to FIG. 8, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2. The first encapsulation layer PAS1 and the third encapsulation layer PAS2 may be inorganic films, and the second encapsulation layer PCL may be an organic film.

[0248] Since the second encapsulation layer PCL is composed of an organic film, the second encapsulation layer PCL can also serve as a planarization layer.

[0249] On the other hand, the display panel 110 according to an embodiment of the present disclosure can incorporate a touch sensor. In this case, the display panel 110 according to an embodiment of the present disclosure may include a touch sensor part formed on the encapsulation layer ENCAP.

[0250] Referring to FIG. 8, the touch sensor part can include a touch sensor metal TSM and a bridge metal BRG, and may further include a configuration of insulating films such as a sensor buffer layer S-BUF, a sensor interlayer insulating film S-ILD, and a sensor protection layer S-PAC.

[0251] The sensor buffer layer S-BUF can be disposed on the encapsulation layer ENCAP. The bridge metal BRG is disposed on the sensor buffer layer S-BUF, and the sensor interlayer insulating film S-ILD can be disposed on the bridge metal BRG.

[0252] The touch sensor metal TSM can be disposed on the sensor interlayer insulating film S-ILD. A part of the touch sensor metal TSM may be connected to the bridge metal BRG through a hole in the sensor interlayer insulating film S-ILD.

[0253] Referring to FIG. 8, the touch sensor metal TSM and the bridge metal BRG can be disposed in the optical bezel region OBA. The touch sensor metal TSM and the bridge metal BRG can be disposed so as not to overlap with the second light emitting region EA2 of the optical bezel region OBA.

[0254] A plurality of touch sensor metals TSM can form one touch electrode (or one touch electrode line), are arranged in a mesh form, and can be electrically connected. A part of the touch sensor metal TSM and another part of the touch sensor metal TSM can be electrically connected through the bridge metal BRG to form one touch electrode (or one touch electrode line).

[0255] The sensor protection layer S-PAC can be disposed while covering the touch sensor metal TSM and the bridge metal BRG.

[0256] On the other hand, when the display panel 110 is of a type incorporating a touch sensor, in the display region DA, at least a part of the touch sensor metal TSM located on the encapsulation layer ENCAP extends and is arranged along the outer contour inclined surface of the encapsulation layer ENCAP, and can be electrically connected to a pad located outside the outer contour inclined surface of the encapsulation layer ENCAP. Here, the pad may be disposed in the non-display region NDA or may be a metal pattern to which the touch drive circuit 260 is electrically connected.

[0257] The display panel 110 according to an embodiment of the present disclosure may further include a bank BK having a bank hole that is located on the first anode electrode AE1 but exposes a part of the first anode electrode AE1, and a light-emitting layer EL that is located on the bank BK and contacts a part of the first anode electrode AE1 exposed through the bank hole.

[0258] The bank hole formed in the bank BK may not overlap with the plurality of cathode holes CH. That is, at the point where there is a cathode hole CH, the bank BK does not sink or penetrate. Therefore, at the point where there is a cathode hole CH, the second planarization layer PLN2 and the first planarization layer PLN1 located under the bank BK also do not sink or penetrate.

[0259] The upper surface of the bank BK located under the plurality of cathode holes CH can be in a flat state without being damaged. This can mean that the insulating layer or metal pattern (such as electrodes and wirings) or the light-emitting layer EL located under the cathode electrode CE is not damaged by the process of forming the plurality of cathode holes CH in the cathode electrode CE.

[0260] A process of forming the plurality of cathode holes CH in the cathode electrode CE will be briefly described as follows. A specific mask pattern (a vapor deposition prevention pattern, not shown) is vapor-deposited at the position where the plurality of cathode holes CH are to be formed, and then a cathode electrode material is vapor-deposited thereon. As a result, the cathode electrode material is vapor-deposited only in the region without the specific mask pattern, and the cathode electrode CE having the plurality of cathode holes CH can be formed. For example, the specific mask pattern may include an organic substance. The cathode electrode material may include a magnesium-silver (Mg-Ag) alloy.

[0261] On the other hand, after the cathode electrode CE having the plurality of cathode holes CH is formed, the display panel 110 may be in a state where the specific mask pattern is completely removed, or may be in a state where all or part of the specific mask pattern remains.

[0262] According to an embodiment of the present disclosure, the display panel 110 may include a first driving transistor DT1 disposed in the optical bezel region OBA to drive a first light-emitting element ED1 disposed in the optical region OA, and a second driving transistor DT2 disposed in the optical bezel region OBA to drive a second light-emitting element ED2 disposed in the optical bezel region OBA.

[0263] According to an embodiment of the present disclosure, the display panel 110 may further include a first planarization layer PLN1 disposed on the first driving transistor DT1 and the second driving transistor DT2, a first relay electrode RE1 located on the first planarization layer PLN1 and electrically connected to a first source electrode S1 of the first driving transistor DT1 through a via hole in the first planarization layer PLN1, a second relay electrode RE2 located on the first planarization layer PLN1 and electrically connected to a second source electrode S2 of the second driving transistor DT2 through another via hole in the first planarization layer PLN1, and a second planarization layer PLN2 disposed on the first relay electrode RE1 and the second relay electrode RE2.

[0264] According to an embodiment of the present disclosure, the display panel 110 may further include an anode extension line AEL that connects the first relay electrode RE1 and the first anode electrode AE1 and is located on the first planarization layer PLN1.

[0265] The second anode electrode AE2 is electrically connected to the second relay electrode RE2 through a via hole in the second planarization layer PLN2, and the first anode electrode AE1 can be electrically connected to the anode extension line AEL through another via hole in the second planarization layer PLN2.

[0266] All or part of the anode extension line AEL is disposed in the optical region OA, and the anode extension line AEL may include a transparent material. The first pixel circuit SPC1 includes a first driving transistor DT1 for driving the first light-emitting element ED1, and the second pixel circuit SPC2 may include a second driving transistor DT2 for driving the second light-emitting element ED2.

[0267] The first active layer ACT1 of the first driving transistor DT1 and the second active layer ACT2 of the second driving transistor DT2 may be different layers.

[0268] The display panel 110 according to an embodiment of the present disclosure may further include a substrate SUB, a first buffer layer BUF1 disposed between the substrate SUB and the first driving transistor DT1, and a second buffer layer BUF2 disposed between the first driving transistor DT1 and the second driving transistor DT2.

[0269] The first active layer ACT1 of the first driving transistor DT1 and the second active ACT2 of the second driving transistor DT2 may include different semiconductor materials.

[0270] For example, the second active layer ACT2 of the second driving transistor DT2 may include an oxide semiconductor material. For example, the oxide semiconductor material may include IGZO (Indium gallium zinc oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), and the like.

[0271] For example, the first active ACT1 of the first driving transistor DT1 may include a semiconductor material different from the second active layer ACT2 of the second driving transistor DT2.

[0272] For example, the first active layer ACT1 of the first driving transistor DT1 may include a silicon-based semiconductor material. For example, the silicon-based semiconductor material may include low-temperature polysilicon (LTPS: Low-Temperature Polycrystalline Silicon), and the like.

[0273] The display panel 110 according to an embodiment of the present disclosure may further include a sealing layer ENCAP on the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, and a touch sensor metal TSM on the sealing layer ENCAP.

[0274] The touch sensor metal TSM may be disposed in the general area NA and the optical bezel area OBA. In the optical area OA, the touch sensor metal TSM may not be disposed, or may be disposed at a lower density than the general area NA and the optical bezel area OBA.

[0275] Referring to FIG. 8, the optical area OA can overlap with the optoelectronic device. The optical bezel area OBA may not overlap with the optoelectronic device. In some cases, a part of the optical bezel area OBA may overlap with the optoelectronic device.

[0276] The optoelectronic device overlapping with the optical area OA may be the first optoelectronic device 11 and / or the second optoelectronic device 12. For example, the optoelectronic device may include a camera, an infrared sensor, or an ultraviolet sensor, etc. For example, the optoelectronic device may be a device that receives visible light and performs a predetermined operation, or a device that receives light different from visible light (e.g., infrared light, ultraviolet light) and performs a predetermined operation.

[0277] Referring to FIG. 8, the cross-sectional structure of the general area NA may be the same as that of the optical bezel area OBA. However, in order to drive the first light-emitting element ED1 disposed in the optical area OA, the first sub-pixel circuit portion SPC1 disposed in the optical bezel area OBA is not disposed in the general area NA.

[0278] FIG. 9 is a cross-sectional view of the display panel 110 according to an embodiment of the present disclosure, and is a cross-sectional view of the optical bezel area OBA and the optical area OA of the display panel 110. However, similar to FIG. 6, FIG. 9 is a cross-sectional view when the 1:2 circuit portion connection method is applied.

[0279] The cross-sectional view of FIG. 9 is basically the same as the cross-sectional view of FIG. 8. However, the cross-sectional view of FIG. 8 is the case where the 1:1 circuit section connection method as shown in FIG. 5 is applied, and the cross-sectional view of FIG. 9 is different only in that the 1:2 circuit section connection method as shown in FIG. 6 is applied. Therefore, in the following description of the cross-sectional structure of FIG. 9, the description will focus on the features that are different from the cross-sectional structure of FIG. 8.

[0280] Referring to FIG. 9, the first light-emitting element ED1 and the fourth light-emitting element ED4 arranged in the optical region OA can be simultaneously driven by the first driving transistor DT1 arranged in the optical bezel region OBA.

[0281] Therefore, as shown in FIG. 9, the anode extension line AEL may be further electrically connected to the first anode electrode AE1 and the other fourth anode electrode AE4. That is, the anode extension line AEL can be electrically connected to both the first anode electrode AE1 of the first light-emitting element ED1 and the fourth anode electrode AE4 of the fourth light-emitting element ED4.

[0282] Referring to FIG. 9, the anode extension line AEL can overlap with the cathode hole CH located between the first light-emitting element ED1 and the fourth light-emitting element ED4 among the plurality of cathode holes CH.

[0283] Referring to FIG. 9, the first light-emitting region EA1 by the first light-emitting element ED1 and the fourth light-emitting region EA4 by the fourth light-emitting element ED4 may be light-emitting regions that emit light of the same color.

[0284] FIG. 10 is a plan view of the first optical region OA1 of the display device according to the comparative example of the present disclosure.

[0285] Referring to FIG. 10, the display device may include a plurality of cathode holes CH in the first optical region OA1.

[0286] The display device may include a plurality of signal lines SL that extend in the second direction D2. The plurality of signal lines SL may be arranged in a plurality in the first direction D1.

[0287] A plurality of signal lines SL arranged in the first direction D1 and extending in the second direction D2 are located in the first optical region OA1, so that on an optoelectronic device such as a camera located below the first optical region OA1, a plurality of signal lines SL are arranged. When the optoelectronic device is a camera, the camera receives the light passing between the plurality of signal lines SL and captures an image, so that the camera can capture flare in a specific direction. For example, when a plurality of signal lines SL extending in the second direction D2 are arranged in the first direction D1, flare may occur in the first direction D1.

[0288] In order to solve such problems, the inventors of the present disclosure invented a display device having a curved anode extension line.

[0289] FIG. 11 is a plan view of a part of a display area of a display device according to an embodiment of the present disclosure.

[0290] Referring to FIGS. 4, 5, 6, 8, 9, and 11, a display device according to an embodiment of the present disclosure may include a display area DA, a cathode electrode CE, a first light-emitting element ED1, a first sub-pixel circuit unit SPC1, and an anode extension line AEL.

[0291] More specifically, referring to FIG. 4, the display area DA may include a first optical area OA1 and a first optical bezel area OBA1 located on the outer contour of the first optical area OA1. More specifically, referring to FIGS. 8 and 9, the cathode electrode CE may include a plurality of cathode holes CH within the first optical area OA1. The first light-emitting element ED1 is located in the first optical area OA1 and may include a first anode electrode AE1. More specifically, referring to FIGS. 5 and 6, the first sub-pixel circuit portion SPC1 may be located in the first optical bezel area OBA1. Referring to FIGS. 5, 6, 8, and 9, the anode extension line AEL can electrically connect the first sub-pixel circuit portion SPC1 and the first anode electrode AE1. Referring to FIG. 11, the shape of the anode extension line AEL may be curved.

[0292] Referring to FIG. 11, when the anode extension line AEL extends in the second direction D2 and is positioned while the shape of the anode extension line AEL is curved, even if a plurality of anode extension lines AEL are arranged and positioned in the first direction D1, when using an optoelectronic device that overlaps with the first optical area OA1, flare can be suppressed from occurring. As shown in FIG. 11, the number of anode extension lines per unit area decreases from the edge of the first optical area toward the center of the first optical area. Further, the plurality of anode extension lines are divided into a plurality of groups, and the thickness of each of the plurality of groups decreases from the edge of the first optical area toward the center of the first optical area.

[0293] The display device may include a plurality of anode extension lines AEL. Since the anode extension line AEL refers to a wiring for electrically connecting a plurality of sub-pixel circuit portions located in the first optical bezel area OBA1 and the anode electrodes of a plurality of light-emitting elements located in the first optical area OA1, the display device may include a plurality of anode extension lines AEL.

[0294] The number of anode extension lines AEL may decrease as it approaches the center of the first optical region OA1. For example, in row A1 of the first optical region OA1, a large number of anode extension lines AEL may overlap and be positioned on one pixel PXL, while in row A8 closer to the center of the first optical region OA1, a smaller number of anode extension lines AEL may overlap and be positioned on one pixel PXL. This is because the number of light-emitting elements and sub-pixel circuit portions to which the anode extension lines AEL must be electrically connected decreases as it progresses from row A1 to row A8.

[0295] The anode extension lines AEL can be arranged so as not to overlap with the cathode holes. Referring to FIG. 11, a plurality of pixels PXL can be arranged in the first optical region OA1 and the first optical bezel region OBA1. Each pixel PXL may include, for example, a red light-emitting region EA_R, a green light-emitting region EA_G, and a blue light-emitting region EA_B. As described above with reference to FIGS. 4 and 7, cathode holes CH can be arranged in the first optical region OA1 to ensure transmittance. However, in FIG. 11, the cathode holes are not shown.

[0296] FIGS. 12 and 13 are enlarged views of the first optical region OA1 of FIG. 11. More specifically, FIG. 12 is an enlarged view of a part of row A6 in the first optical region OA1 of FIG. 11, and FIG. 13 is an enlarged view of a part of row A8 in the first optical region OA1 of FIG. 11.

[0297] Referring to FIGS. 12 and 13, the anode extension lines AEL can be arranged so as not to overlap with the cathode holes CH. By arranging the anode extension lines AEL so as not to overlap with the cathode holes CH, the display device can ensure a higher transmittance in the first optical region OA1. In addition, since the anode extension lines AEL do not overlap with the cathode holes CH and can overlap with other opaque wirings, it is possible to prevent the transmittance of the first optical region OA1 from decreasing due to the anode extension lines AEL.

[0298] Comparing FIGS. 12 and 13, it can be seen that the number of anode extension lines AEL is larger in the portion shown in FIG. 12 than in the portion shown in FIG. 13. FIG. 12 is an enlarged view of a part of row A6 in the first optical region OA1 when referring to FIG. 11, and FIG. 13 is an enlarged view of a part of row A8 in the first optical region OA1 when referring to FIG. 11. Considering such a difference, in FIG. 12, as the anode extension line AEL proceeds in the second direction D2, it is necessary to connect more pixels PXL, so a larger number of anode extension lines AEL may be arranged in the portion shown in FIG. 12.

[0299] When referring to FIGS. 12 and 13, the shape of the anode extension line AEL can be a curved shape that bypasses the cathode hole CH. When the anode extension line AEL bypasses the cathode hole CH, since the anode extension line AEL does not overlap with the cathode hole CH, as described above, the first optical region OA1 can have a high transmittance. Also, when the anode extension line AEL has a curved shape, as described above, when using a camera positioned to overlap with the first optical region OA1, the occurrence of flare can be suppressed.

[0300] The shape of the cathode hole CH can be a circular shape. In this example, the shape of the anode extension line AEL can be an S-shaped that bypasses the cathode hole CH. When the shape of the cathode hole CH is circular and the shape of the anode extension line AEL is an S-shape that bypasses the cathode hole CH, since the anode extension line AEL does not overlap with the cathode hole CH and the anode extension line AEL overlaps with other opaque wirings positioned without overlapping with the cathode hole CH, the transmittance of the first optical region OA1 can be maximized. Also, since a space for positioning the anode extension line AEL can be effectively secured, more anode extension lines AEL can be arranged, so that the first optical region OA1 can have a higher number of pixels per unit area.

[0301] In FIGS. 12 and 13, contact holes connecting the anode electrodes driving the light emitting regions EA_R, EA_G, and EA_B and the anode extension line AEL are not shown.

[0302] The display device may include a first light emitting region EA1, a second light emitting region EA2, and an anode connection line ACL. The first light emitting region EA1 and the second light emitting region EA2 can be located in the first optical region. The anode connection line ACL can connect the first light emitting region EA1 and the second light emitting region EA2. By including such an anode connection line ACL in the display device, a part EA1, EA2 of the light emitting regions EA_R, EA_G, EA_B located in the first optical region can be driven simultaneously via one anode connection line ACL. Therefore, the light emitting regions EA_R, EA_G, EA_B located in the first optical region can be driven using a smaller number of anode extension lines AEL. Thus, a smaller number of sub-pixel circuit portions than the first optical bezel region may be arranged, and the thickness of the first optical bezel region can be reduced. In this example, the first light emitting region EA1 and the second light emitting region EA2 can emit light of the same color. Emitting light of the same color may mean being the same considering common errors that may occur between sub-pixels in the display technology field.

[0303] The anode connection line ACL can be arranged so as not to overlap with the cathode hole CH. Also, the shape of the anode connection line ACL may be a curved shape that bypasses the cathode hole CH. When the anode connection line ACL is positioned so as not to overlap with the cathode hole CH and bypasses the cathode hole CH, the transmittance of the first optical region can be maximized, and thus the optoelectronic device can effectively receive light. Also, when the anode connection line ACL has a curved shape, for example, when using an optoelectronic device such as a camera, flare generated by the anode connection line ACL can be suppressed.

[0304] Figures 14 and 15 are diagrams schematically showing cross-sections of an anode extension line according to an embodiment of the present disclosure. More specifically, FIG. 14 schematically shows cross-sections of a first anode extension line AEL1, a second anode extension line AEL2, and a third anode extension line AEL3 included in the anode extension line AEL shown in FIG. 12, and FIG. 15 schematically shows a cross-section of the first anode extension line AEL1 included in the anode extension line AEL shown in FIG. 13.

[0305] Referring to FIGS. 14 and 15, the first anode extension line AEL1 may include a first metal layer M1, a second metal layer M2 located on the first metal layer M1, and a third metal layer M3 located on the second metal layer M2.

[0306] The first metal layer M1 and the second metal layer M2 can be arranged so as not to overlap each other. By positioning the first metal layer M1 and the second metal layer M2 so as not to overlap each other, it is possible to prevent the formation of unnecessary capacitance in the display device. For example, although the first metal layer M1 and the second metal layer M2 are arranged on different layers, they can be the two closest metal layers with one or more insulating films positioned between the two layers. When such adjacent metal layers, the first metal layer M1 and the second metal layer M2, are positioned overlapping each other, since the distance between the two layers is very short, capacitance that degrades the display quality of the display device may occur. However, in the embodiment of the present disclosure, by positioning the first metal layer M1 and the second metal layer M2 so as not to overlap, it is possible to prevent the display quality from degrading due to the capacitance between the first metal layer M1 and the second metal layer M2.

[0307] The first metal layer M1 and the second metal layer M2 are positioned so as not to overlap each other, and the first slit SLT1 can be formed. In this example, the third metal layer M3 can be arranged so as to overlap the first slit SLT1. By the third metal layer M3 being positioned to overlap the first slit SLT1, it is possible to effectively prevent haze defects from occurring due to the first slit SLT1.

[0308] The display device may further include a fourth metal layer M4. The fourth metal layer M4 may be a layer that does not constitute the anode extension lines AEL1, AEL2, AEL3.

[0309] The first anode extension line AEL1 and the second anode extension line AEL2 can form a second slit SLT2. The second slit SLT2 can refer to a slit formed by the first metal layer M1 and the second metal layer M2 that constitute two adjacent anode extension lines AEL1, AEL2. For example, the second slit SLT2 can refer to a slit formed by the second metal layer M2 that constitutes the first anode extension line AEL1 and the first metal layer M1 that constitutes the second anode extension line AEL2. The second slit SLT2 is different from the first slit SLT1 in that the first slit SLT1 is a slit formed by the metal layers M1, M2 that constitute one anode extension line AEL1, while the second slit SLT2 is a slit formed by the metal layers M1, M2 that constitute two adjacent anode extension lines AEL1, AEL2.

[0310] The fourth metal layer M4 can be positioned so as to overlap the second slit SLT2. By the fourth metal layer M4 being positioned to overlap the second slit SLT2, it is possible to effectively prevent haze defects from occurring due to the second slit SLT2.

[0311] Further, the fourth metal layer M4 can be positioned so as to overlap with the first slit SLT1 as well. When not only the third metal layer M3 but also the fourth metal layer M4 overlap with the first slit SLT1, the haze that may be generated by the first slit SLT1 can be more effectively prevented. In another embodiment, the fourth metal layer M4 covers all of the first to third metal layers M1, M2, M3, and can prevent a parasitic capacitor from occurring between the first to third metal layers M1, M2, M3 and the anode electrode AE.

[0312] FIG. 16 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Hereinafter, when explaining with reference to FIG. 16, matters not specifically specified may be the same as those explained with reference to FIGS. 8 and 9 above.

[0313] Referring to FIG. 16, the line width w1 of the first metal layer M1 constituting the anode extension line AEL in the first optical region OA1 and the line width w2 of the second metal layer M2 constituting the anode extension line AEL in the first optical region OA1 may be the same as each other.

[0314] For example, the line width w1 and the line width w2 may be the minimum line widths determined in consideration of process errors. When both the line width w1 and the line width w2 have the minimum line width, more anode extension lines AEL can be formed. Therefore, since a large number of light-emitting elements can be driven in the first optical region OA1, the display device can have excellent display quality in the first optical region OA1. In this example, since the line width w1 of the first metal layer M1 and the line width w2 of the second metal layer M2 are both the minimum line widths that can be formed in consideration of process errors, they may be the same as each other.

[0315] The anode extension line may include a second anode extension line AEL2. The second anode extension line AEL2 can be positioned adjacent to the first anode extension line AEL1. The distance d1 between the first metal layer M1 of the first anode extension line AEL1 and the first metal layer M1 of the second anode extension line AEL2 may be the same as the distance d2 between the second metal layer M2 of the first anode extension line AEL1 and the second metal layer M2 of the second anode extension line AEL2.

[0316] For example, the distances d1 and d2 can be the minimum distances determined in consideration of process errors. When both the distances d1 and d2 have the minimum distance, more anode extension lines AEL can be formed. Therefore, since a large number of light-emitting elements can be driven in the first optical region OA1, the display device can have excellent display quality in the first optical region OA1. In this example, the distance d1 between the first metal layer M1 of the first anode extension line AEL1 and the first metal layer M1 of the second anode extension line AEL2, and the distance d2 between the second metal layer M2 of the first anode extension line AEL1 and the second metal layer M2 of the second anode extension line AEL2 are both the minimum distances that can be formed in consideration of process errors, so the distances d1 and d2 may be the same as each other.

[0317] The first source-drain electrode SD1 may be the first source electrode or the first drain electrode described with reference to FIGS. 8 and 9 above. The second source-drain electrode SD2 may be the first relay electrode or the second relay electrode described with reference to FIGS. 8 and 9 above.

[0318] The first metal layer M1 can be located in the same layer as the first gate electrode G1 and the first capacitor electrode PLT1. The second metal layer M2 can be located in the same layer as the second capacitor electrode PLT2. The third metal layer M3 can be located in the same layer as the second gate electrode G2. The fourth metal layer M4 can be located in the same layer as the first source-drain electrode SD1.

[0319] FIG. 17 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Hereinafter, when explaining with reference to FIG. 17, matters not specifically stated may be the same as those described with reference to FIGS. 8 and 9 above.

[0320] Referring to FIG. 17, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may be opaque. That is, in the first optical region OA1, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 that constitute the anode extension lines AEL1 and AEL2 may be opaque. For example, the opaque first metal layer M1, second metal layer M2, third metal layer M3, and fourth metal layer M4 may be made of the same material as the opaque metal layer constituting the thin film transistor array substrate.

[0321] When the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are opaque, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 can have higher conductivity, so the efficiency of the display device can be improved.

[0322] Further, when the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are opaque, the third metal layer M3 and the fourth metal layer M4 can effectively block the light passing through or diffracted by the slits SLT1 and SLT2 formed by the adjacent metal layers. Therefore, optoelectronic devices such as a camera located overlapping the first optical region OA1 can receive light more smoothly.

[0323] FIG. 18 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Hereinafter, when explaining with reference to FIG. 18, matters not specifically stated may be the same as those described with reference to FIGS. 8 and 9 above.

[0324] Referring to FIG. 18, the first metal layer M1′, the second metal layer M2′, and the third metal layer M3′ can be transparent. That is, in the first optical region OA1, the first metal layer M1′, the second metal layer M2′, and the third metal layer M3′ that form the anode extension lines AEL1 and AEL2 can be transparent. For example, the transparent first metal layer M1′, the second metal layer M2′, and the third metal layer M3′ can be made of the same material as the transparent conductive metal layer located on top of the thin film transistor array.

[0325] When the first metal layer M1′, the second metal layer M2′, and the third metal layer M3′ are transparent, the first optical region OA1 can have a higher transmittance, so that the optoelectronic device located overlapping the first optical region OA1 can receive light more smoothly.

[0326] FIG. 19 illustrates the flare suppression effect due to the shape of the anode extension line AEL according to an embodiment of the present disclosure.

[0327] Referring to FIG. 19, the display device according to an embodiment of the present disclosure can include anode extension lines AEL of various shapes.More specifically, Example 1 is an example in which the metal layer forming the anode extension line AEL forms a slit, Example 2 is an example in which the slit formed by the metal layer overlaps with different metal layers as described above with reference to FIGS. 14 to 18, and Example 3 is an example in which the phases of some anode extension line patterns in Example 2 are inverted. REF.1 is a comparative example in which only a camera hole is arranged in the first optical region OA1.

[0328] Looking at the flare of Examples 1 to 3, it can be seen that although some flare occurred compared to REF.1, no flare occurred in a specific direction. That is, it can be seen that even if the anode extension line AEL extending in any direction is located, since the shape of the flare is symmetric, it is effectively prevented that the flare is maximized in any direction.

[0329] Specifically, both Examples 1 and 2 have excellent flare suppression effects. In Example 3 where the pattern phase is inverted, there is no significant difference from Examples 1 and 2 in terms of flare suppression ability.

[0330] FIG. 20 is a diagram for explaining the flare suppression effect due to the shape of the anode connection line ACL according to the comparative examples and examples of the present disclosure.

[0331] Referring to FIG. 20, REF.1 is a comparative example where only a camera hole is located in the first optical region OA1, REF.2 is an example where a plurality of cathode hole patterns are arranged, and the example is an example where the anode electrode and the anode connection line ACL are located.

[0332] In REF.2, flares that were not observed in REF.1 are observed due to the cathode hole pattern. In the case of the example, the flare is suppressed compared to REF.2. Therefore, it can be seen that the display device including the curved anode connection line ACL according to the embodiment of the present disclosure suppresses flares.

[0333] Briefly explaining the embodiments of the present disclosure described above, it is as follows.

[0334] The display device 100 according to the embodiment of the present disclosure may include a display area DA, a cathode electrode CE, a first light emitting element ED1, a first sub-pixel circuit unit SPC1, a first anode electrode AE1, and an anode extension line AEL.

[0335] The display area DA may include a first optical area OA1 and a first optical bezel area OBA1 located on the outer contour of the first optical area OA1. The cathode electrode CE may include a plurality of cathode holes CH within the first optical area OA1. The first light-emitting element ED1 is located in the first optical area OA1 and may include a first anode electrode AE1. The first sub-pixel circuit portion SPC1 can be located in the first optical bezel area OBA1. The anode extension line AEL electrically connects the first sub-pixel circuit portion SPC1 and the first anode electrode AE1 and can be positioned so as not to overlap with the cathode hole CH. The shape of the anode extension line AEL can be curved.

[0336] The shape of the anode extension line AEL can be a curved shape that bypasses the cathode hole CH.

[0337] The shape of the cathode hole CH can be circular. Also, the shape of the anode extension line AEL may be an S shape that bypasses the cathode hole CH.

[0338] The display device 100 may include a first light-emitting area EA1 located in the first optical area OA1, a second light-emitting area EA2 located in the first optical area OA1, and an anode connection line ACL connecting the first light-emitting area EA1 and the second light-emitting area EA2. The first light-emitting area EA1 and the second light-emitting area EA2 can emit light of the same color. The anode connection line ACL is positioned so as not to overlap with the cathode hole CH, and the shape of the anode connection line ACL can be a curved shape that bypasses the cathode hole CH.

[0339] The anode extension line AEL may include a first anode extension line AEL1. The first anode extension line AEL1 may include a first metal layer M1, a second metal layer M2 located on the first metal layer M1, and a third metal layer M3 located on the second metal layer M2. The first metal layer M1 and the second metal layer M2 may be positioned so as not to overlap each other, and a first slit SLT1 can be formed. The third metal layer M3 can be positioned so as to overlap the first slit SLT1. The display device 100 may further include a fourth metal layer M4. The first metal layer M1 and the second metal layer M2 may be positioned so as not to overlap each other, and a second slit SLT2 is formed, and the fourth metal layer M4 can be positioned so as to overlap the second slit SLT2. The line width w1 of the first metal layer M1 and the line width w2 of the second metal layer M2 may be the same as each other.

[0340] The anode extension line AEL may include a second anode extension line AEL2. The second anode extension line AEL2 may include a first metal layer M1, a second metal layer M2, and a third metal layer M3. The second anode extension line AEL2 can be positioned adjacent to the first anode extension line AEL1.

[0341] The distance d1 between the first metal layer M1 of the first anode extension line AEL1 and the first metal layer M1 of the second anode extension line AEL2 may be the same as the distance d2 between the second metal layer M2 of the first anode extension line AEL1 and the second metal layer M2 of the second anode extension line AEL2.

[0342] The first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may be opaque.

[0343] The first metal layer M1, the second metal layer M2, and the third metal layer M3 may be transparent.

[0344] The above description merely exemplifies the technical idea of the present disclosure, and those with ordinary knowledge in the technical field to which the present disclosure pertains can make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments shown in the present disclosure are not intended to limit the technical idea of the present disclosure, but are for illustrative purposes, so the scope of the technical idea of the present disclosure is not limited by these embodiments.

Description of Reference Numerals

[0345] 100 Display device 110 Display panel

Claims

1. A display region including a first optical region and a first optical bezel region located on the outer periphery of the first optical region, a cathode electrode including a plurality of cathode holes within the first optical region, a first light-emitting element located in the first optical region and including a first anode electrode, a first sub-pixel circuit portion located in the first optical bezel region, including an anode extension line that electrically connects the first sub-pixel circuit portion and the first anode electrode and is positioned so as not to overlap with the cathode holes, wherein the shape of the anode extension line is curved, the anode extension line includes a first anode extension line including a first metal layer, a second metal layer located on the first metal layer, and a third metal layer located on the second metal layer, the first metal layer and the second metal layer are positioned so as not to overlap with each other to form a first slit, the third metal layer is positioned so as to overlap with the first slit, a display device.

2. The display device according to claim 1, wherein the shape of the anode extension line is a curved shape that bypasses the cathode holes.

3. wherein the shape of the cathode holes is circular, The display device according to claim 1, wherein the shape of the anode extension line is an S-shaped that bypasses the cathode holes.

4. a first light-emitting region located in the first optical region, a second light-emitting region located in the first optical region, The display device according to claim 1, further including an anode connection line that connects the first light-emitting region and the second light-emitting region.

5. The display device according to claim 4, wherein the first light-emitting region and the second light-emitting region emit light of the same color.

6. The anode connection line is arranged so as not to overlap with the cathode holes, The display device according to claim 4, wherein the shape of the anode connection line is a curved shape that bypasses the cathode holes.

7. the anode extension line includes the first metal layer, the second metal layer, and the third metal layer, and further includes a second anode extension line located adjacent to the first anode extension line, a fourth metal layer is disposed on the first anode extension line and the second anode extension line, the first anode extension line and the second anode extension line are positioned so as not to overlap with each other to form a second slit, The display device according to claim 1, wherein the fourth metal layer is positioned to overlap with the second slit.

8. The display device according to claim 1, wherein the line width of the first metal layer is the same as the line width of the second metal layer.

9. The anode extension line includes the first metal layer, the second metal layer, and the third metal layer, and further includes a second anode extension line positioned adjacent to the first anode extension line. The display device according to claim 1, wherein the distance between the first metal layer of the first anode extension line and the first metal layer of the second anode extension line is the same as the distance between the second metal layer of the first anode extension line and the second metal layer of the second anode extension line.

10. The display device according to claim 7, wherein the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are opaque.

11. The display device according to claim 1, wherein the first metal layer, the second metal layer, and the third metal layer are transparent.

12. The display device according to claim 1, wherein the number of the anode extension lines per unit area decreases from the edge of the first optical region toward the center of the first optical region.

13. The display device according to claim 1, including a general region surrounding the first optical bezel region, and optionally, the first optical region has a higher light transmittance than the general region and the first optical bezel region.

14. The display device according to claim 1, wherein a plurality of the anode extension lines are divided into a plurality of groups, and the thickness of each of the plurality of groups decreases from the edge of the first optical region toward the center of the first optical region.

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