Terminal structure with reduced dynamic output capacitance loss

Abstract

In a general aspect, a semiconductor device (100, 400, 700, 900) can include a substrate (110, 410, 710, 910) of a first conductivity type, an active region (120, 420, 720, 920) disposed within the substrate, and a termination region (T) disposed within the substrate adjacent to the active region. The termination region can include a junction termination extension (130, 420, 730, 930) of a second conductivity type, the second conductivity type being opposite the first conductivity type. The junction termination extension can have a first depletion stop region (132, 432, 732, 932) disposed at an upper portion of the junction termination extension, a second depletion stop region (134, 434, 734, 934) disposed at a lower portion of the junction termination extension, and a high carrier mobility region (136, 436, 736, 936) disposed between the first depletion stop region and the second depletion stop region.

Description

Technical Field

[0001] This specification relates to a termination structure, and more particularly to a termination structure that can be implemented in a power semiconductor device to reduce output capacitance switching loss.

Background Art

[0002] Power semiconductor devices (e.g., devices operating at voltages of 20 volts (V) or more) can be used in a variety of applications such as household appliances, automotive applications, and industrial applications. Such power semiconductor devices can include, for example, power diodes, power transistors such as power metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), etc. In some implementations, such power semiconductor devices can be implemented on a silicon carbide substrate, although other semiconductor materials may also be used. One application for such power semiconductor devices is, in some implementations, a resonant power converter implemented using soft switching (e.g., switching using a resonant inductive-capacitive (LC) circuit).

[0003] In such soft-switching applications, dynamic power losses may occur as a result of charging and / or discharging the output capacitance (Coss) of the power semiconductor device using soft switching at high frequencies (e.g., frequencies of several hundred kilohertz or more). Such power (switching) losses are sometimes referred to as dynamic output capacitance losses (DynCoss losses). DynCoss losses reduce the efficiency of the associated circuit (e.g., power conversion efficiency). Therefore, by reducing DynCoss losses, it is possible to achieve, for example, an improvement in efficiency in resonant (soft-switching) power converters and other circuit applications where such DynCoss losses occur.

Summary of the Invention

[0004] In a general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed within the substrate, and a termination region disposed within the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type is opposite to the first conductivity type. The JTE can have a first depletion stop region disposed on top of the JTE, a second depletion stop region disposed below the JTE, and a high carrier mobility region disposed between the first depletion stop region and the second depletion stop region. The high carrier mobility region can have a constant doping region that extends over a certain depth range of the high carrier mobility region within the substrate.

[0005] Implementations can include one or more of the following features, either alone or in combination. For example, the first depletion stop region can have a first doping concentration. The second depletion stop region can have a second doping concentration. The high carrier mobility region can have a third doping concentration. The third doping concentration can be lower than the first doping concentration and lower than the second doping concentration. The first doping concentration and the second doping concentration can be the same doping concentration. The first doping concentration can be different from the second doping concentration. The first doping concentration can be a first average doping concentration, the second doping concentration can be a second average doping concentration, and the third doping concentration can be a third average doping concentration.

[0006] The substrate can be a silicon carbide substrate. The first conductivity type can be n-type. The second conductivity type can be p-type.

[0007] The JTE can be a first JTE, and the high carrier mobility region can be a first high carrier mobility region. The termination region can include a second JTE of a second conductivity type disposed in the substrate adjacent to the first JTE. The second JTE can include a third depletion stop region disposed above the second JTE, a fourth depletion stop region disposed below the second JTE, and a second high carrier mobility region disposed between the third depletion stop region and the fourth depletion stop region.

[0008] The first JTE can extend from the surface of the substrate to a first depth within the substrate. The second JTE can extend from the surface of the substrate to a second depth within the substrate. The second depth can be less than the first depth.

[0009] The first high carrier mobility region and the second high carrier mobility region can be aligned along a common longitudinal axis.

[0010] The first JTE can include a first dopant impurity dose amount. The second JTE can include a second dopant impurity dose amount. The second dopant impurity dose amount can be less than the first dopant impurity dose amount.

[0011] The high carrier mobility region can be a first high carrier mobility region. The termination region can be disposed within the substrate and can include at least one floating ring of a second conductivity type disposed laterally spaced from the JTE. The JTE can be disposed between the active region and the at least one floating ring. One of the at least one floating rings can have a third depletion stop region disposed above the floating ring, a fourth depletion stop region disposed below the floating ring, and a second high carrier mobility region disposed between the third depletion stop region and the fourth depletion stop region. The first high carrier mobility region and the second high carrier mobility region can be aligned along a common longitudinal axis. The first JTE can have a first width along the common longitudinal axis. The second JTE can have a second width along the common longitudinal axis. The second width can be smaller than the first width.

[0012] The active region can include at least one of a power diode or a power transistor.

[0013] In another general aspect, a semiconductor device can include a substrate of a first conductivity type, an active region disposed within the substrate, and a termination region disposed within the substrate adjacent to the active region. The termination region can include a junction termination extension (JTE) of a second conductivity type, where the second conductivity type can be opposite the first conductivity type. The JTE can have a first depletion stop region extending from the surface of the substrate to a first depth within the substrate. The JTE can also include a high carrier mobility region extending from the first depth within the substrate to a second depth within the substrate, where the second depth is greater than the first depth. The high carrier mobility region can have a constant doping region extending over a range of depths between the first depth and the second depth. The JTE can further include a second depletion stop region extending from the second depth within the substrate to a third depth within the substrate, where the third depth is greater than the second depth.

[0014] The implementation form can include one or more of the following features, either alone or in combination. For example, the first depletion stop region can include a first amount of dopant of the second conductivity type. The high carrier mobility region can include a second amount of dopant of the second conductivity type. The second amount of dopant can be less than the first amount of dopant. The second depletion stop region can include a third amount of dopant of the second conductivity type. The third amount of dopant can be more than the second amount of dopant.

[0015] The difference between the second depth and the first depth can be greater than the first depth and greater than the difference between the third depth and the second depth.

[0016] In another general aspect, the semiconductor device can include a highly doped n-type silicon carbide substrate and a lightly doped n-type silicon carbide epitaxial layer disposed on the highly doped n-type silicon carbide substrate. The semiconductor device can also include an active region disposed within the lightly doped n-type silicon carbide epitaxial layer. The active region can include at least one of a power diode or a power n-channel metal oxide semiconductor field effect transistor (MOSFET). The semiconductor device can further include a termination region disposed within the lightly doped n-type silicon carbide epitaxial layer adjacent to the active region. The termination region can include a p-type junction termination extension (JTE). The p-type JTE can have a first depletion stop region extending from the surface of the substrate to a first depth within the substrate. The p-type JTE can also have a high carrier mobility region extending from the first depth within the substrate to a second depth within the substrate, and the second depth is greater than the first depth. The high carrier mobility region can have a constant doping region extending over a certain range of depths between the first depth and the second depth. The p-type JTE can further have a second depletion stop region extending from the second depth within the substrate to a third depth within the substrate, and the third depth is deeper than the second depth.

[0017] The implementation form can include one or more of the following features, either alone or in combination. For example, the p-type JTE can at least partially surround the active region.

[0018] The first depletion stop region can contain a first amount of p-type dopant. The high carrier mobility region can contain a second amount of p-type dopant. The second amount of p-type dopant can be at least one order of magnitude less than the first amount of p-type dopant. The second depletion stop region can contain a third amount of p-type dopant. The third amount of p-type dopant can be at least one order of magnitude greater than the second amount of p-type dopant.

Brief Description of the Drawings

[0019]

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[0020] In drawings that are not necessarily drawn to scale, the same reference numerals in different drawings may indicate the same and / or similar components (elements, structures, etc.). The drawings generally illustrate, by way of example and not limitation, the various implementations discussed in the present disclosure. A reference numeral shown in one drawing may not be repeated for the same and / or similar elements in the associated drawings. Reference numerals that are repeated in multiple drawings may not be specifically discussed for each of those drawings, but are provided for the context between the associated drawings. Also, when multiple examples of an element are shown in a given drawing, not all of the same elements in the drawing are necessarily specifically referenced by one reference numeral.

Embodiments for Carrying Out the Invention

[0021] The present disclosure is directed to termination structures that can be implemented in power semiconductor devices. As described above, the techniques described herein can reduce dynamic output capacitance losses (DynCoss) that can occur in soft-switching applications compared to current techniques. For purposes of illustration and explanation, an exemplary termination structure is described as being implemented in an n-type substrate (e.g., a p-type termination structure), but in some implementations, the conductivity and associated carrier type described may be reversed. Also, the exemplary implementations described herein are generally discussed as being implemented in power semiconductor devices implemented within a silicon carbide (SiC) substrate. However, in some implementations, other types of semiconductor substrates (e.g., silicon, gallium nitride, gallium arsenide, gallium, etc.) may be used.

[0022] In some implementations, the techniques described herein can be used to achieve an improvement (e.g., reduction) of DynCoss losses of approximately 70% or more (e.g., based on experimental data and simulation data). For example, the exemplary termination structure described herein results in an increase in hole conductance during dynamic soft-switching operation relative to the implementation of previous termination structures, and at least partially addresses a contribution (e.g., RC charging of Coss through the termination structure resistance) that can account for 60% - 95% of the DynCoss losses in some implementations. That is, the techniques described herein can reduce DynCoss compared to conventional techniques because they result in an improvement (increase) in hole conductance in the termination structure during dynamic (soft-switching) operation.

[0023] The described implementations of the termination structure also enable a reduction in the overall size of the termination structure for a related power semiconductor device, for example, compared to current techniques. Such a reduction in the size of the termination structure can further increase the hole conductance of the termination structure (e.g., reduce the hole current path resistance), thereby enabling a further improvement (reduction) in DynCoss losses.

[0024] FIG. 1 schematically shows a cross-sectional view of a semiconductor device 100 including an active region A and a termination region T. FIG. 2 schematically shows a plan (top-down) view of the semiconductor device 100 of FIG. 1. A cut line 1-1 is shown in FIG. 2, which corresponds to the cross-sectional view of the semiconductor device 100 shown in FIG. 1. Therefore, FIGS. 1 and 2 are described with reference to each other.

[0025] As shown in FIG. 1, the semiconductor device 100 can be implemented in a semiconductor substrate 110 (e.g., a SiC substrate) including a high-concentration doped (n+) SiC substrate 112 and a low-concentration doped (n-) SiC epitaxial layer (epitaxial layer 114). In this example, in the active region A, the semiconductor device 100 includes an active device region 120 disposed within the epitaxial layer 114 (e.g., within the semiconductor substrate 110). In some implementations, the active device region 120 can include one or more of a power diode, a power transistor (such as a planar MOSFET, a superjunction FET, a trench FET, an IGBT, etc.). In some implementations, the devices included in the active device region 120 can be disposed within a body region (e.g., a p-type body region in this example). The specific devices, or the devices implemented in the active device region 120, depend on the individual implementation.

[0026] Also, as shown in FIG. 1, the semiconductor device 100 also includes a termination region T. The termination region T of the semiconductor device 100 includes, in this example, a (p-type) junction termination extension (JTE 130). As shown in FIG. 1 and further referring to FIG. 2, the termination region T (e.g., the JTE 130 and / or a part of the epitaxial layer 114) can at least partially surround or completely surround the active device region 120, such as surrounding the periphery (or a part) of the active device region 120 as shown in FIG. 2. That is, in some implementations, the termination region T does not have to completely surround the active device region 120.

[0027] As shown in FIG. 1, the JTE 130 can extend along line D (in the vertical direction of FIG. 1) from the surface of the epitaxial layer 114 (e.g., the upper surface of FIG. 1) and can include a plurality of regions or layers. For example, in the semiconductor device 100, the JTE 130 can include a layer 132, a layer 134, and a layer 136. In the examples described herein, the layer 132 can be a first depletion stop layer (e.g., a layer p-doped at a high concentration), and the layer 134 can be a second depletion stop layer (e.g., a layer p-doped at a high concentration). Further, in the semiconductor device 100, the layer 136 can be a high carrier (hole) mobility layer, and the layer 136 is doped at a low concentration (p-type) with respect to the layer 132 and the layer 134. As a result of the lower doping of the layer 136, in this example (e.g., when the semiconductor device 100 is a SiC substrate), the ionization degree of the p-type dopant in the layer 136 can be higher than that in the layer 132 or the layer 134. Further, due to the higher ionization degree of the p-type dopant in the layer 136, the hole mobility in the layer 136 can be higher than that in the layer 132 or the layer 134. Therefore, the hole conductance (e.g., during soft switching) can be improved (e.g., compared to previous methods), and as a result, the DynCoss loss can be reduced.

[0028] In the example of FIG. 1, the JTE 130 can have a width W1, the layer 132 can extend from the surface of the epitaxial layer 114 to a depth D1, the layer 136 can extend from the depth D1 to a depth D2, and the layer 134 can extend from the depth D2 to a depth D3. In this example, the depth D3 can be the overall depth of the JTE 130 within the epitaxial layer 114. The dimensions W1, D1, D2, and D3 (as well as the dimensions shown for other implementations described herein) are given by way of example. These dimensions may vary based on individual implementations and may not be shown to scale in the illustrated implementations. For example, in some implementations of the semiconductor device 100, the layer 136 may be thicker than the layer 132 and / or the layer 134. In other words, the difference between D2 and D1 may be greater than D1 and greater than the difference between D3 and D2. In some implementations, the layer 132, the layer 134, and the layer 134 may each have different thicknesses or may have substantially the same thickness, etc.

[0029] As shown in FIG. 1 and described above, the layer 136 can provide a high-conductance (e.g., low-resistance) conduction path for the hole current Ih (e.g., during resonant soft-switching of the devices included in the active device region 120), and can reduce the associated DynCoss losses. In such implementations, Ih is a displacement current, i.e., a capacitive current. Also, the direction of Ih may be opposite to the directions shown in FIG. 1 and FIGS. 4, 7, and 9, depending on, for example, whether Coss is being charged or discharged. In this exemplary implementation, the layer 132, the layer 134, and the layer 136 can be generated (defined, etc.) using a multi-peak doping concentration profile such as the exemplary doping profiles schematically shown in FIGS. 3A, 3B, and 3C.

[0030] In some implementations, layer 132 can have a first doping concentration (e.g., a first average doping concentration), layer 134 can have a second doping concentration (e.g., a second average doping concentration), and layer 136 can have a third doping concentration (e.g., a third average doping concentration), where the first (average) doping concentration and the second (average) doping concentration are one order of magnitude greater or higher than the third (average) doping concentration.

[0031] Figures 3A - 3C are graphs schematically showing exemplary active p - type impurity distributions of the junction termination extension (JTE) structure (e.g., JTE 130) of respective implementations of the semiconductor devices of FIGS. 1 and 2 along the one - dimensional cut - line 3 - 3 of FIG. 1. In the graphs of FIGS. 3A - 3C, an arbitrary unit of depth (a.u.) (e.g., within the epitaxial layer 114) is represented on the x - axis, and an arbitrary unit of concentration of the active impurity (e.g., p - type impurity) is shown on the y - axis using a logarithmic scale. Again, the graphs of FIGS. 3A - 3C are schematic and are given as examples to show an exemplary doping profile and active p - type impurity concentration in an exemplary implementation of the semiconductor device 100.

[0032] Regarding the correspondence with FIG. 1, note that the depth is shown vertically (e.g., from top to bottom) in FIG. 1, but these depths are shown horizontally (e.g., from left to right) in FIGS. 3A - 3C. In FIGS. 3A - 3C, the respective depth ranges associated with layer 132, layer 134, and layer 136 within the epitaxial layer 114 of the semiconductor device 100 of FIG. 1 are shown along the upper part of the graphs of FIGS. 3A - 3C, and these depth ranges are also illustrated (shown) by the rectangles in FIGS. 3A - 3C.

[0033] Referring to FIG. 3A, a graph 300 is shown that depicts a first active p-type impurity concentration profile that can be used to implement the JTE 130 of the semiconductor device 100. In graph 300, the n-type (constant) active doping concentration of the epitaxial layer 114 is indicated by graph line 305. Graph line 305 is shown in each of FIGS. 3A - 3C for comparison with the respective active p-type impurity concentrations of the JTE 130. In FIG. 3A, graph line 310 indicates the active p-type impurity concentration for this example. Graph line 310 includes a first peak 312 in layer 132 and a second peak 314 in layer 134. The active p-type impurity concentration of layer 136 (high hole mobility layer) has a constant portion 316 between peak 312 and peak 314.

[0034] The active p-type impurity concentration shown in FIG. 3A can be determined (such as generated) using multiple impurity implantations. For example, a first impurity implantation can be performed at a low implantation energy (e.g., corresponding to peak 312), and a second impurity implantation can be performed at a high implantation energy (e.g., corresponding to peak 314). In some implementations, a third implantation can be performed at an intermediate implantation energy (e.g., corresponding to the constant portion 316). In this example, peak 312 and peak 314 are at the same value, or approximately the same value, on the y-axis. In an exemplary implementation, such an impurity profile can be generated using the same implantation dose amount for the first and second impurity implantations described above, and the desired total doping concentration within the JTE 130 can be achieved by appropriately dividing the implantation dose amount among multiple implantations (e.g., 2, 3, or more) used to generate the JTE.

[0035] Referring to FIG. 3B, a graph 320 is shown that depicts a second active p-type impurity concentration profile that can be used to implement the JTE 130 of the semiconductor device 100. Such an impurity concentration can be implemented in a JTE (e.g., JTE 130) included in a semiconductor device that does not deplete (e.g., significantly deplete, etc.) from the top surface (e.g., the top surface of the JTE). In some implementations, such depletion (e.g., from the top surface) can be due to (resulting from) surface charges and an upper metal plate structure. In graph 320, the n-type (constant) active doping concentration of the epitaxial layer 114 is indicated by graph line 305. In FIG. 3B, graph line 330 indicates the active p-type impurity concentration for this example. Graph line 330 includes a first peak 332 in layer 132 and a second peak 334 in layer 134. The active p-type impurity concentration in layer 136 (high hole mobility layer) has a constant portion 336 between peak 332 and peak 334.

[0036] Similar to the active p-type impurity concentration profile of FIG. 3A, the active p-type impurity concentration profile shown in FIG. 3B can be determined (generated, etc.) using multiple impurity implants. For example, a first impurity implant can be performed at a low implant energy (e.g., corresponding to peak 332), and a second impurity implant can be performed at a high implant energy (e.g., corresponding to peak 334). In some implementations, a third implant can be performed at an intermediate implant energy (e.g., corresponding to the constant portion 336).

[0037] In this example, peaks 332 and 334 are at different values (e.g., on the y-axis), and peak 334 indicates a higher active doping concentration than peak 332. In an exemplary implementation, such an impurity profile can be generated by using a lower implant dose for the first implant than the implant dose used for the second implant and considering the relationship between the total doping concentration and the ionization degree. Similar to the active p-type impurity concentration in FIG. 3A, the desired total doping concentration in the JTE 130 for generating the profile of graph 330 can be achieved by appropriately splitting the dose amount among multiple implants (e.g., two, three, or more) used to form the JTE 130.

[0038] Referring to FIG. 3C, a graph 340 is shown that depicts a third active p-type impurity concentration profile that can be used to implement the JTE 130 of the semiconductor device 100. Such an impurity concentration can be implemented to define a high hole mobility layer (layer 136) that covers a depth (e.g., from D1 to D2 in FIG. 1) deeper than the respective depth ranges of layers 132 and 134. In graph 340, the n-type (constant) active doping concentration of the epitaxial layer 114 is indicated by line 305 of the graph. In FIG. 3C, line 350 of the graph indicates the active p-type impurity concentration for this example. Line 350 of the graph includes a first peak 352 in layer 132 and a second peak 354 in layer 134. The active p-type impurity concentration in layer 136 (high hole mobility layer) has an increasing portion 356 between peak 352 and peak 354.

[0039] Similar to the active p-type impurity concentrations of FIGS. 3A and 3B, the active p-type impurity concentration shown in FIG. 3C can be determined (such as generated) using multiple impurity implants. For example, the first impurity implant can be performed at a low implant energy (e.g., corresponding to peak 352), and the second channel impurity implant can be performed to determine (such as generate) peak 354 (e.g., within layer 134) and increasing portion 356 (e.g., within layer 136). Similar to the active p-type impurity concentrations of FIGS. 3A and 3B, the desired total doping concentration in JTE 130 to achieve the profile of graph 340 can be achieved by appropriately splitting the dose amount among multiple implants (e.g., 2, 3, or more) used to form JTE 130.

[0040] FIG. 4 schematically shows a cross-sectional view of a semiconductor device 400 including an active region A and a termination region T. FIG. 5 schematically shows a plan (top-down) view of the semiconductor device 400 of FIG. 4. Cutting line 4-4 is shown in FIG. 5, which corresponds to the cross-sectional view of the semiconductor device 400 shown in FIG. 4. Therefore, FIGS. 4 and 5 are described with reference to each other.

[0041] In some implementations, the techniques shown in FIGS. 4 and 5 can be used to implement a semiconductor device that operates at a higher voltage than semiconductor device 100. For example, an implementation of semiconductor device 100 can operate at a rating (e.g., breakdown voltage rating) in the range of 1.2 kilovolts (kV), while an implementation of semiconductor device 400 can operate at a voltage rating of 1.7 kV or higher (e.g., in part, by using multiple JTEs).

[0042] As shown in FIGS. 4 and 5 and further referring to FIG. 1, semiconductor device 400 includes elements similar to those of semiconductor device 100, which are referred to in FIGS. 4 and 5 by 400-series numbers corresponding to the 100-series reference numbers of FIG. 1. Briefly, the elements of semiconductor device 400 corresponding to the elements of semiconductor device 100 of FIG. 1 are identified below but are not described in detail again here.

[0043] Referring to FIG. 4, corresponding to the elements of the semiconductor device 100 in FIG. 1, the semiconductor device 400 includes a semiconductor substrate 410 (e.g., a SiC substrate) that can include a high-concentration doped (n+) SiC substrate 412 and a low-concentration doped (n-) SiC epitaxial layer (epitaxial layer 414). In the active region A, the semiconductor device 400 includes an active device region 420 disposed in the epitaxial layer 414.

[0044] Also, as shown in FIG. 4, the semiconductor device 400 also includes a termination region T. The termination region T of the semiconductor device 400 includes a (p-type) junction termination extension (first JTE 430). As shown by FIG. 4 and referring further to FIG. 5, the termination region T (e.g., the first JTE 430, as well as other elements within the termination region T) can at least partially surround or completely surround the active device region 420, such as surrounding the periphery of the active device region 420 as shown in FIG. 5.

[0045] As further shown in FIG. 4, the first JTE 430 can extend along line D (in the vertical direction of FIG. 4) from the surface of the epitaxial layer 414 (e.g., the upper surface of FIG. 4) and can include a plurality of regions or layers. For example, the first JTE 430 can include layer 432, layer 434, and layer 436. In the examples described herein, layer 432 can be a first depletion stop layer (e.g., a layer highly doped p-type), and layer 434 can be a second depletion stop layer (e.g., a layer highly doped p-type). Further, in the semiconductor device 400, layer 436 can be a first high-carrier (hole) mobility layer, and layer 436 is doped (p-type) at a lower concentration relative to layer 432 and layer 434. The first JTE 430 having the width W2 shown in FIG. 4 can have width dimensions and depth dimensions similar to those described with respect to the JTE 100 in FIG. 1, and the specific dimensions may depend on the individual implementation forms.

[0046] In addition to the elements of the semiconductor device 400 corresponding to the semiconductor device 100, the semiconductor device 400 also includes a second JTE 440 (e.g., a second p-type JTE) disposed within the termination region T. As shown by FIG. 4 and with further reference to FIG. 5, the second JTE 440 can at least partially surround or completely surround the first JTE 430, such as surrounding (or a part of) the periphery of the first JTE 430 as shown in FIG. 5.

[0047] As shown in FIG. 4, similar to the first JTE 430, the second JTE 440 can extend along line D (in the vertical direction of FIG. 4) from the surface of the epitaxial layer 414 (e.g., the upper surface of FIG. 4) and can include a plurality of regions or layers. For example, in the semiconductor device 400, the second JTE 440 can include layer 432, layer 434, and layer 436. In the example described herein, layer 432 can be the third depletion stop layer (e.g., a layer p-type doped at a high concentration) of the semiconductor device 400, and layer 434 can be the fourth depletion stop layer (e.g., a layer p-type doped at a high concentration) of the second JTE 440. Further, in the semiconductor device 400, layer 436 can be the second high carrier (hole) mobility layer, and layer 436 is doped at a low concentration (p-type) with respect to layer 432 and layer 434. As shown in FIG. 4, layer 436 and layer 446 (high hole mobility layer) can be aligned with each other along the longitudinal axis L. Such an arrangement prevents any blockage in the high mobility hole conduction path for the hole current Ih passing through layer 436 and layer 446. Similar to layer 436, as a result of the lower doping of layer 446, in this example (e.g., when the semiconductor substrate 410 is a SiC substrate and the epitaxial layer 414 is a SiC epitaxial layer), the ionization degree of the p-type dopant in layer 446 can be higher than that in layer 442 or layer 444. Due to the higher ionization degree of the p-type dopant in layer 446, the hole mobility in layer 446 can be higher than that in layer 442 or layer 444. Therefore, the hole conductance (e.g., during soft switching) can be improved (e.g., compared to previous techniques), and as a result, the DynCoss loss can be reduced.

[0048] As shown in FIG. 4, the second JTE 440 can have a width W3, and the width W3 may be the same as or different from the width W2 of the first JTE 430 depending on individual implementation forms. Further, in some implementation forms, the total doping concentration of the second JTE 440 can be made lower than the total doping concentration of the first JTE 430, and the durability and breakdown performance of the semiconductor device 400 can be improved. The layer of the second JTE 440 can have a depth relationship, attributes, etc. similar to those of the layer of the first JTE 430, but other configurations are also possible.

[0049] As shown in FIG. 4 and as described above, the layers 436 and 446 can provide a high-conductance (e.g., low-resistance) conduction path for the hole current Ih (e.g., during resonant soft switching of the devices within the active device region 420), and can reduce the associated DynCoss losses. The layers of the first JTE 430 and the second JTE 440 can be generated (defined, etc.) by respective multi-peak doping concentration profiles such as the exemplary doping profile schematically shown in FIG. 6. That is, each layer of the first JTE 430 and the second JTE 440 can have its own doping concentration profile, and the relative doping concentration levels are the same as those described above for the layers of the JTE 130 of the semiconductor device 100.

[0050] FIG. 6 is a graph 600 schematically showing exemplary active p-type impurity distributions of junction termination extension (JTE) structures (e.g., a first JTE 430 and a second JTE 440) of an exemplary implementation of the semiconductor device 400 of FIGS. 4 and 5 along respective 1D cut lines 6A-6A and 6B-6B of FIG. 4. In the graph 600 of FIG. 6, similar to the graphs of FIGS. 3A-3C, an arbitrary unit of depth (a.u.) (e.g., within the epitaxial layer 414) is represented on the x-axis, and an arbitrary unit of concentration (a.u.) of active impurities (e.g., p-type impurities) is shown logarithmically on the y-axis. Again, the graph 600 is schematic and is provided as an example to show an exemplary doping profile and active p-type impurity concentration in an exemplary implementation of the semiconductor device 400.

[0051] Similar to the graphs of FIGS. 3A-3C, depth is shown vertically (e.g., top to bottom) in FIG. 4, but these depths are represented horizontally (e.g., left to right) in FIG. 6. In FIG. 6, the respective depth ranges associated with the layers of the first JTE 430 and the second JTE 440 within the epitaxial layer 414 of the semiconductor device 400 of FIG. 4 are shown along the upper part of the graph 600, and these depth ranges are also illustrated (shown) by the rectangles in FIG. 6.

[0052] In this example, the graph 600 shows active p-type impurity concentration profiles that can be used to implement the first JTE 430 and the second JTE 440 of the semiconductor device 400, respectively. In the graph 600, the n-type (constant) active doping concentration of the epitaxial layer 414 is shown by a line 605 of the graph, for example, for comparison with the respective active p-type impurity concentrations of the first JTE 430 and the second JTE 440.

[0053] In FIG. 6, the graph line 610 indicates the active impurity concentration of the first JTE 430 in this example, and the graph line 620 indicates the active impurity concentration of the second JTE 440. As shown in FIG. 6, the graph line 610 includes a first peak 612 in layer 432 and a second peak 614 in layer 434. The active impurity concentration of layer 436 (the first high hole mobility layer) has a constant portion 616 between peak 612 and peak 614. The graph line 620 includes a first peak 622 in layer 442 and a second peak 624 in layer 444. The active impurity concentration of layer 446 (the second high hole mobility layer) has a constant portion 626 between peak 622 and peak 624, and as shown in FIG. 4, the constant portion 626 is aligned with the constant portion 616 so that the corresponding high hole mobility layers 436 and 446 are aligned.

[0054] The active impurity concentrations shown in FIG. 6 (e.g., of graph lines 610 and 620) can be determined (such as generated) using a plurality of impurity implantations as described above with respect to FIGS. 3A - 3C. In this example, the total active impurities of the profiles shown by graph lines 610 and 620 are different (e.g., the total p-type impurities included in the second JTE 440 are less than the total p-type impurities included in the first JTE 430). In an exemplary implementation, such active impurity profiles can be generated using a series of implantations at respective energies and doses to generate the active impurity profiles for the first JTE 430 and the second JTE 440 shown in FIG. 6.

[0055] FIG. 7 is a schematic cross-sectional view of a semiconductor device 700 including an active region A and a termination region T similar to those of the semiconductor device 400 in FIG. 4 (and having a top view corresponding to FIG. 5). Also, like the semiconductor device 400, the semiconductor device 700 can be used to implement a semiconductor device that operates at a higher voltage, such as a voltage rating of 1.7 kV or more (e.g., partially by using a plurality of JTEs).

[0056] Semiconductor device 700 includes elements similar to those of semiconductor device 400 and semiconductor device 100. These elements are referenced in FIG. 7 with 700-series numbers corresponding to the 400-series reference numbers in FIG. 4. Briefly, the elements of semiconductor device 700 corresponding to the elements of semiconductor device 400 (and semiconductor device 100) are identified below.

[0057] These corresponding elements in FIG. 7 include a semiconductor substrate 700 that includes a high-concentration doped (n-type SiC) substrate 712 and a low-concentration doped n-type SiC epitaxial layer (epitaxial layer 714). The corresponding elements further include an active region A, an active device region 720, a termination region T, a first JTE 730 (having layers 732, 734, and 736), and a second JTE 740 (having layers 742, 744, and 746). Line D is also shown in FIG. 7 for reference and comparison with FIGS. 1 and 4. These elements will not be described in detail again here, except for the differences from semiconductor device 400 and semiconductor device 100).

[0058] As shown in FIG. 7, the first JTE 730 can have a width W4 and a depth D5, and the second JTE 740 can have a width W5 and a depth D4. As shown in FIG. 7, D4 may be smaller than D5. Similarly, W5 may be smaller than W4 (or may be the same as W4, or larger than it). In this example, even if the depth D4 of the second JTE 740 is smaller than the depth D5 of the first JTE 730, the layers 736 and 746 (high hole mobility layers) are still aligned with each other along the longitudinal axis L so as to efficiently conduct Ih (e.g., during soft switching operation) and reduce DynCoss losses.

[0059] FIG. 8 is a graph 800 schematically showing exemplary active p-type impurity distributions of a first JTE 730 and a second JTE 740 of a semiconductor device 700 along respective 1D cut lines 8A-8A and 8B-8B of FIG. 7. In graph 800, similar to graph 600, an arbitrary unit (a.u.) of depth is represented on the x-axis, and an arbitrary unit (a.u.) of the concentration of active impurities (e.g., p-type impurities) is shown logarithmically on the y-axis. Again, graph 800 is schematic and is given as an example to show an exemplary doping profile and active p-type impurity concentration in an exemplary implementation of semiconductor device 700.

[0060] Similar to the example described above, the vertical depth in FIG. 7 is represented horizontally in FIG. 8. In FIG. 8, the respective depth ranges associated with the layers of the first JTE 730 and the second JTE 740 are shown along the upper and lower parts of graph 800, and at least some of those depth ranges are also illustrated (shown) by the rectangle in FIG. 8.

[0061] In this example, graph 800 shows an active p-type impurity concentration profile that can be used to implement the first JTE 730 and the second JTE 740 of semiconductor device 700, respectively. In graph 800, the n-type (constant) active doping concentration of the epitaxial layer 714 is shown by graph line 805.

[0062] In FIG. 8, the graph line 810 indicates the active impurity concentration of the first JTE 730, and the graph line 820 indicates the active impurity concentration of the second JTE 740. As shown in FIG. 8, the graph line 810 includes a first peak 812 in layer 732 and a second peak 814 in layer 734. The active impurity concentration of layer 736 (the first high hole mobility layer) has a constant portion 816 between peak 812 and peak 814. The graph line 820 includes a first peak 822 in layer 742 and a second peak 824 in layer 744. The active impurity concentration of layer 746 (the second high hole mobility layer) has a constant portion 826 between peak 822 and peak 824, and as shown in FIG. 7, the constant portion 826 is aligned with the constant portion 816 so that the corresponding high hole mobility layers 736 and 746 are aligned. The active impurity concentrations shown in FIG. 8 (e.g., of graph lines 810 and 820) can be determined (such as generated) using multiple impurity implantations such as the techniques described herein.

[0063] FIG. 9 schematically shows a cross-sectional view of a semiconductor device 900 including an active region A and a termination region T. The semiconductor device 900 is similar to the semiconductor device 100 of FIG. 1, but in this example includes two floating (p-type) guard rings and has a top view corresponding to FIG. 10. In some implementations, fewer or additional floating guard rings can be included. In some implementations, the semiconductor device 900 can be used to implement a semiconductor device configured to operate over a voltage range such as 100V to 1200V. In some implementations, the DynCoss loss is improved (e.g., reduced) at a lower voltage (e.g., less than 500V) than in the exemplary implementation of the semiconductor device 100, and the exemplary implementation of the semiconductor device 100 can have better DynCoss loss characteristics at a higher voltage (e.g., greater than 500V).

[0064] Semiconductor device 900 includes elements similar to those of semiconductor device 100. These elements are referenced in FIG. 9 with 900-series numbers corresponding to the 100-series reference numbers in FIG. 1. Briefly, the elements of semiconductor device 900 corresponding to the elements of semiconductor device 100 are identified below.

[0065] These corresponding elements in FIG. 9 include a semiconductor substrate 900 that includes a high-concentration doped (n-type SiC) substrate 912 and a low-concentration doped n-type SiC epitaxial layer (epitaxial layer 914). The corresponding elements further include an active region A, an active device region 920, a termination region T, and a JTE 930 (having layers 932, 934, and 936). Line D is also shown in FIG. 9 for reference and comparison with FIG. 1 (as well as FIGS. 4 and 7). These elements will not be described in detail again here, except for the differences from semiconductor device 100.

[0066] In addition to the elements of semiconductor device 900 corresponding to those of semiconductor device 100, semiconductor device 900 also includes a first (p-type) floating ring 940 and a second (p-type) floating ring 950 disposed within the termination region T. As shown by FIG. 9 and with further reference to FIG. 10, the first floating ring 940 can be spaced from the JTE 930 (e.g., spaced laterally), and the floating ring 950 can be spaced from the first floating ring 940 (e.g., laterally). The floating rings 940 and 950 can at least partially surround or completely surround the JTE 930, such as surrounding (or a part of) the periphery of the first JTE 930 as shown in FIG. 10.

[0067] As shown in FIG. 9, similar to JTE 930, floating rings 940 and 950 can extend along line D (in the vertical direction of FIG. 9) from the upper surface of the epitaxial layer 914 and can each include a plurality of regions or layers. For example, floating rings 940 and 950 can include depletion stop layers 942, 944, 952, and 954, and high hole mobility layers 946 and 956, as shown in FIG. 9. As shown in FIG. 9, layers 936, 946, and 956 (high hole mobility layers) can be aligned with each other along the longitudinal axis L. Such an arrangement can reduce the resistance (e.g., increase the conductance) of the high mobility hole conduction path for the hole current Ih through the aligned layers. That is, in such an implementation form, due to the lower doping concentration of the p-type dopant and the related higher ionization degree in layers 936, 946, and 956, the hole mobility in those layers can be increased, thereby increasing the hole conductance (e.g., during soft switching) and improving (reducing) the DynCoss loss.

[0068] As shown in FIG. 9, JTE 930 can have a width W6, and floating rings 940 and 950 can have a width W7 (or can have different widths from each other), and the width W7 can be made smaller than the width W6 of JTE 930 depending on the individual implementation form. Further, in some implementation forms, the doping concentration of floating rings 940 and 950 can be made lower than the doping concentration of JTE 930 (even when generated using the same implantation as JTE 930). This difference in doping concentration can result from the difference in two-dimensional diffusion in floating rings 940 and 950 compared to JTE 930. In some implementation forms, the layers of floating rings 940 and 950 can have a depth relationship, attributes, etc. similar to those of the layers of JTE 930, but other configurations are also possible.

[0069] FIG. 11 is a graph 1100 schematically showing exemplary active p-type impurity distributions of the JTE 930 and the floating rings 940 and 950 of the semiconductor device 900 along the respective 1D cut lines 11A-11A and 11B-11B of FIG. 9. In graph 1100, similar to the aforementioned active impurity graph, an arbitrary unit of depth (a.u.) is represented on the x-axis, and an arbitrary unit of concentration (a.u.) of the active impurity (e.g., p-type impurity) is shown logarithmically on the y-axis. Again, graph 1100 is schematic and is provided as an example to show an exemplary doping profile and active p-type impurity concentration in an exemplary implementation of the semiconductor device 900.

[0070] Similar to the example described above, the vertical depth in FIG. 9 is represented horizontally in FIG. 11. In FIG. 11, the respective depth ranges associated with the layers of the JTE 930 and the exemplary floating ring 940 (which also represents the floating ring 950 in this example) are shown along the upper part of the graph 1100, and these depth ranges are also illustrated (shown) by the rectangles in FIG. 11.

[0071] In this example, graph 1100 shows the active p-type impurity concentration profiles that can be used to implement the JTE 930 and the floating rings 940 and 950 of the semiconductor device 900, respectively. In graph 1100, the n-type (constant) active doping concentration of the epitaxial layer 914 is shown by the line 1105 of the graph.

[0072] In FIG. 11, the graph line 1110 indicates the active impurity concentration of JTE 930, and the graph line 920 indicates the active impurity concentration of the floating ring 940. As shown in FIG. 11, the graph line 910 includes a first peak 1112 in layer 932 and a second peak 914 in layer 934. The active impurity concentration of layer 936 (high hole mobility layer) has a constant portion 1116 between peak 1112 and peak 1114. The graph line 920 (representing floating rings 940 and 950) includes a first peak 1122 in layer 942 (or layer 952) and a second peak 1124 in layer 944 (or layer 954). The active impurity concentration of layer 946 (or layer 956, high hole mobility layer) has a constant portion 1126 between peak 1122 and peak 1124, and as shown in FIG. 9, the constant portion 1126 is aligned with the constant portion 1116 so that the corresponding high hole mobility layers 936, 946 (and 956) are aligned. The active impurity concentrations shown in FIG. 11 (e.g., the graph lines 1110 and 1120) can be determined (such as generated) using multiple impurity implantations, such as the techniques described herein.

[0073] FIGS. 12A and 12B are graphs schematically showing the relationship between the doping concentration profile and the carrier mobility of the implementation form of the device of FIG. 1, compared with the relationship between the doping concentration profile and the carrier mobility of the conventional technique. Specifically, FIG. 12A shows the schematic doping concentration profile of FIG. 3A (e.g., indicated by the graph line 310) and is referred to by the same reference numerals as in FIG. 3A (e.g., for regions 132, 134, and 136 of the device 100 of FIG. 1). Also, in FIG. 12A, the active doping concentration of the epitaxial layer 114 of the device 100 of FIG. 1 is indicated by the graph line 305 as in FIG. 3A.

[0074] Similar to FIG. 3A, FIG. 12A also shows the active impurities (on a logarithmic scale) versus depth (both shown using arbitrary units a.u.). For the sake of brevity and clarity, the details of the doping concentration indicated by graph line 305 are not explained in detail again with respect to FIGS. 12A and 12B. FIG. 12A also shows a graph line 1210 that represents the doping concentration profile of a conventional technique (e.g., a single-peak profile). In some implementations, the total charge associated with the doping concentration profile indicated by graph line 310 may be approximately the same as the total charge associated with the doping concentration profile indicated by graph line 1210 (this may not be readily apparent from FIG. 12A due to the logarithmic scale on the y-axis).

[0075] Referring next to FIG. 12B, graph 1250 shows the respective carrier (hole) mobility profiles corresponding to the doping concentration profiles of graph line 310 and graph line 1210 of FIG. 12A during a high-frequency switching event (e.g., a fast drain-source voltage charge or discharge). In FIG. 12B, the hole mobility (a.u.) is shown on the y-axis, and the depth (corresponding to the a.u. depth of FIG. 12A) is shown on the x-axis. In FIG. 12B, the carrier (hole) mobility over the depth of the doping profile corresponding to graph line 310 (e.g., the example of FIG. 3A) is indicated by graph line 360, and the carrier (hole) mobility over the depth of the doping profile corresponding to graph line 1210 (e.g., the conventional technique of FIG. 12A) is indicated by graph line 1260.

[0076] As shown in FIG. 12B, the depth range 364 over which the carrier (hole) mobility of graph line 360 increases is larger than the depth range 1264 over which the carrier (hole) mobility of graph line 1260 increases. The depth range, i.e., the expansion of each neutral depletion region during a fast drain-source voltage ramp (hereinafter W termThis difference in (referred to as) can contribute to the reduction of the DynCoss loss. For example, a range of depth 364 (e.g., non-depletion or neutral depletion) partially defines a cross-section through which the capacitive (displacement) current Ih flows during the charging and / or discharging of Coss. In the examples described herein, this current is described as a hole current, but in some implementations, this current may also be an electron current.

[0077] The expansion of the non-depletion (neutral depletion) region in an exemplary implementation can contribute to the reduction of the resistance in the termination region (e.g., during high-frequency switching events) compared to conventional techniques (e.g., a range of depth 364 compared to a range of depth 1264), and thus can reduce the DynCoss loss. For example, the power loss during the charging and / or discharging of Coss is proportional to the resistance along the non-depletion region of the JTE (e.g., JTE 130 in this example). The following equations show to what extent the techniques described herein can reduce the resistance and thus the DynCoss loss.

[0078] Using the following Equation 1, the resistivity (ρ) of an exemplary implementation such as the JTE 130 in FIG. 1 can be calculated. In the following Equation 1, μ avg is the average carrier (e.g., hole) mobility across the cross-section through which Ih flows, NA avg is the average acceptor density across the cross-section, and q is the total charge. In this example, ρ can be given by the following equation.

[0079]

Equation

[0080] As can be seen from Equation 1, an increase in the average carrier mobility associated with line 360 of the graph results in a decrease in the resistivity, and as a result, a decrease in the overall resistance (R) given by the following equation.

[0081]

Equation

[0082] For the purposes of the present disclosure, when an element such as a layer, region, or substrate is said to be on, disposed on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it is understood that the element can be directly disposed on, connected to, or coupled to the other element, or one or more intervening elements may be present. On the other hand, when an element is said to be directly on, directly disposed on, directly connected to, or directly coupled to another element or layer, no intervening element or layer is present. Although the phrases directly disposed on, directly connected to, or directly coupled to may not be used throughout the detailed description of the present invention, elements illustrated as being directly disposed on, directly connected to, or directly coupled to may be referred to as such. The claims of the present application may be amended to state the exemplary relationships described herein or illustrated.

[0083] As used herein, the singular form may include the plural form unless the context clearly dictates otherwise. Terms indicating spatial relativity (e.g., throughout, above, upper, below, lower, beneath, etc.) are intended to include various orientations of the device in use or operation in addition to the directions shown in the drawings. In some implementations, the relative terms upper and lower can each include vertically upward and vertically downward, respectively. In some implementations, the term adjacent can include adjacent laterally, adjacent vertically, or adjacent horizontally.

[0084] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like.

[0085] As described herein, while some features of various exemplary embodiments have been described, those skilled in the art will now find many variations, alternatives, modifications, and equivalents. Accordingly, it will be understood that the appended claims are intended to cover all such modifications and changes within the scope of the implementation. It should be understood that these are presented by way of example only and not limitation, and that various changes in form and detail may be made. Any part of the devices and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The various devices described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the various devices described.

Claims

1. a substrate of a first conductivity type, an active region disposed within the substrate, and a termination region disposed within the substrate adjacent to the active region and including a junction termination extension (JTE) of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the JTE including a first depletion stop region disposed on top of the JTE, a second depletion stop region disposed below the JTE, and a high carrier mobility region disposed between the first depletion stop region and the second depletion stop region, the high carrier mobility region having a constant doping region extending over a depth of a range of the high carrier mobility region within the substrate, a semiconductor device.

2. wherein the JTE is a first JTE, the high carrier mobility region is a first high carrier mobility region, and the termination region further includes a second JTE of the second conductivity type disposed within the substrate adjacent to the first JTE, the second JTE including a third depletion stop region disposed on top of the second JTE, a fourth depletion stop region disposed below the second JTE, and a second high carrier mobility region disposed between the third depletion stop region and the fourth depletion stop region, and the first JTE includes a first dopant impurity dose amount, the second JTE includes a second dopant impurity dose amount, the second dopant impurity dose amount being less than the first dopant impurity dose amount, the semiconductor device according to claim 1.

3. wherein the high carrier mobility region is a first high carrier mobility region, and the termination region further includes at least one floating ring of the second conductivity type disposed within the substrate and laterally spaced from the JTE, the JTE being disposed between the active region and the at least one floating ring, and one of the at least one floating ring including a third depletion stop region disposed on top of the floating ring, a fourth depletion stop region disposed below the floating ring, and a second high carrier mobility region disposed between the third depletion stop region and the fourth depletion stop region. The semiconductor device according to claim 1, wherein the first high carrier mobility region and the second high carrier mobility region are aligned along a common longitudinal axis.

4. A substrate of a first conductivity type, An active region disposed within the substrate, A terminal region disposed within the substrate adjacent to the active region and including a second conductivity type junction termination extension (JTE), wherein the second conductivity type is opposite to the first conductivity type, and the JTE includes A first depletion stop region extending from the surface of the substrate to a first depth within the substrate, A high carrier mobility region extending from the first depth within the substrate to a second depth deeper than the first depth within the substrate, the high carrier mobility region having a constant doping region extending over a certain range of depths between the first depth and the second depth, A semiconductor device having a second depletion stop region extending from the second depth within the substrate to a third depth deeper than the second depth within the substrate.

5. The first depletion stop region includes a first amount of dopant of the second conductivity type, The high carrier mobility region includes a second amount of dopant of the second conductivity type, the second amount of dopant being less than the first amount of dopant, The second depletion stop region includes a third amount of dopant of the second conductivity type, the third amount of dopant being more than the second amount of dopant, The difference between the second depth and the first depth is Greater than the first depth and Greater than the difference between the third depth and the second depth, the semiconductor device according to claim 4.

6. A substrate comprising A highly doped n-type silicon carbide substrate, A substrate including a lowly doped n-type silicon carbide epitaxial layer disposed on the highly doped n-type silicon carbide substrate, An active region disposed within the lowly doped n-type silicon carbide epitaxial layer, the active region including A power diode, or An active region including at least one of a power n-channel metal oxide semiconductor field effect transistor (MOSFET), A terminal region disposed within the lowly doped n-type silicon carbide epitaxial layer adjacent to the active region, the terminal region including a p-type junction termination extension (JTE), the p-type JTE including a first depletion stop region extending from the surface of the substrate to a first depth within the substrate; a high carrier mobility region extending from the first depth within the substrate to a second depth deeper than the first depth within the substrate, the high carrier mobility region having a constant doping region extending over a depth range between the first depth and the second depth; a semiconductor device having a second depletion stop region extending from the second depth within the substrate to a third depth deeper than the second depth within the substrate. **Claim 7** the p-type JTE at least partially surrounds the active region; the first depletion stop region contains a first amount of p-type dopant; the high carrier mobility region contains a second amount of p-type dopant, the second amount of p-type dopant being at least one order of magnitude less than the first amount of p-type dopant; the semiconductor device according to claim 6, wherein the second depletion stop region contains a third amount of p-type dopant, the third amount of p-type dopant being at least one order of magnitude greater than the second amount of p-type dopant.

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