3D Dynamic Random Access Memory (3D DRAM) Gate-All-Around (GAA) Design Using Stacked Si / SiGe

Abstract

A method for forming a three-dimensional dynamic random access memory (3D DRAM) structure is provided herein. In some embodiments, the method for forming the 3D DRAM structure includes forming at least one word line feature in a first stack including a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, the word line feature including: vertically etching a first hole pattern; filling the first hole pattern with a silicon germanium fill; vertically etching a plurality of isolation slots through the first stack; filling the plurality of isolation slots with a dielectric material to form an insulating layer between the silicon germanium fills; etching the silicon germanium fills and the plurality of c-SiGe layers to form a plurality of gate silicon channels including a portion of the plurality of c-Si layers; and depositing a layer of conductive material covering the periphery of the plurality of gate silicon channels.

Description

Technical Field

[0001] Embodiments of the present principle generally relate to semiconductor manufacturing.

Background Art

[0002] The storage and acquisition of data have become limiting factors for various aspects of the computing industry. Memory devices can easily degrade the overall performance of the latest computing devices. To speed up the memory, the memory structure has been shrunk to an extremely small size, and the density of the memory structure has increased dramatically. The two-dimensional memory structure is beginning to reach the theoretical limit regarding the density of the memory structure. The inventors have observed that the memory density can be further increased using a three-dimensional memory structure. However, three-dimensional memory devices require significant changes in structure and processing compared to two-dimensional memory devices.

[0003] Therefore, the inventors have provided a method and structure for a three-dimensional memory having scalable dimensions that enable a memory density beyond the capabilities of current technologies.

Summary of the Invention

[0004] A method of forming a three-dimensional dynamic random access memory (3D DRAM) structure is provided herein. In some embodiments, a method of forming a three-dimensional dynamic random access memory (3D DRAM) includes forming at least one word line feature within a first stack including a plurality of crystalline silicon germanium (c-SiGe) layers alternating with a plurality of crystalline silicon (c-Si) layers, the word line feature including vertically etching a first via pattern through the first stack; filling the first via pattern with a silicon germanium fill having a germanium concentration similar to the germanium concentration of the plurality of c-SiGe layers; vertically etching a plurality of isolation slots through the first stack and dividing the silicon germanium fill within each of the first via patterns; filling the plurality of isolation slots with a dielectric material to form an insulating layer between the silicon germanium fills; etching the silicon germanium fills and the plurality of c-SiGe layers to form a plurality of gate silicon channels including portions of the plurality of c-Si layers; and depositing a layer of conductive material to cover the periphery of the plurality of gate silicon channels, including forming at least one word line feature.

[0005] In some embodiments, a method of forming a three-dimensional dynamic random access memory (3D DRAM) structure includes forming word line features in a first stack including a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, the word line features including vertically etching a first via pattern through the first stack, filling the first via pattern with a silicon germanium fill having a germanium concentration similar to the germanium concentration of the plurality of c-SiGe layers, vertically etching a plurality of isolation slots through the first stack and dividing the silicon germanium fill in each of the first via patterns, filling the plurality of isolation slots with a dielectric material to form an insulating layer between the silicon germanium fills, etching the silicon germanium fills and the plurality of c-SiGe layers to form a plurality of gate silicon channels including portions of the plurality of c-Si layers, depositing a layer of conductive material covering the periphery of the plurality of gate silicon channels, forming bit line features through the first stack extending between rows of the first via pattern, and forming a plurality of capacitor features in the first stack, including forming the word line features.

[0006] In some embodiments, a three-dimensional dynamic random access memory (3D DRAM) structure includes at least one vertical word line feature of a 3D DRAM structure formed in a first stack of alternating crystalline silicon (c-Si) layers and nitride layers, the at least one vertical word line feature including a plurality of gate silicon channels including a plurality of c-Si layers of the alternating c-Si layers, an oxide layer covering the periphery of each of the plurality of gas silicon channels, and a metal layer covering the periphery of the oxide layer to form a gate all around (GAA) structure, the at least one vertical word line feature, at least one horizontal bit line feature disposed at a right angle to the at least one vertical word line feature, and a plurality of capacitor features horizontally extending from at least one vertical word line between the nitride layers.

[0007] Additional further embodiments of the present disclosure will be described below.

[0008] Embodiments of the present disclosure have been briefly summarized above and will be described in more detail below, but can be understood by referring to the exemplary embodiments of the present disclosure shown in the accompanying drawings. However, the accompanying drawings show only typical embodiments of the present disclosure, and therefore, the present disclosure should not be regarded as limiting the scope because it allows other equally effective embodiments.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0010] For ease of understanding, wherever possible, the same reference numbers are used to denote the same elements common to each figure. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further elaboration.

[0011] The methods and structures provided herein enable the manufacture of three-dimensional (3D) dynamic random-access memory (DRAM) cells that include a gate-all-around (GAA) structure around a crystalline silicon (c-Si) channel to properly control the c-Si channel. The scaling of two-dimensional (2D) DRAM has become very difficult to manufacture and the cost continues to rise. Below the D1d DRAM node, the feature size is so small that even self-aligned quadruple patterning (SAQP) is not a viable option. Even if extreme ultraviolet (EUV) lithography is employed, EUV lithography needs to be at least self-aligned double patterning (SADP) if not SAQP at most levels. 3D DRAM is a concept widely studied in the DRAM industry for beyond D1d, but the proposed solutions cannot be processed with economic materials and processes of dimensions required to reach a memory density comparable to 2D DRAM.

[0012] FIG. 1 shows a flowchart of a method of forming a three-dimensional dynamic random access memory (3D DRAM) structure according to at least some embodiments of the present disclosure. At 102, word line features are formed within a first stack that includes a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers to form a structure for 3D DRAM. The first stack can be formed by forming a first c-Si layer, followed by a first c-SiGe layer. This process is repeated with a second c-Si layer, followed by a second c-SiGe layer. Similarly, the layers continue to alternate, allowing for a very flexible response to the design of the memory structure to form the number of layers required for a particular structure. For example, the first stack may include 50 or more layers. In some embodiments, the concentration of germanium in the c-SiGe layer may be from about 10 to about 35 atomic percent.

[0013] Figure 2A shows an isometric view of a first stack 202 on which a lithography stack 204 having a word line hole pattern 212 is disposed, according to at least some embodiments of the present disclosure. The first stack 202 represents a part of an overall 3D DRAM structure that can be extended / repeated in the length and width directions to form an overall 3D DRAM structure. In some embodiments, the first stack 202 includes a base c-Si layer 202A, and alternating c-Si layers 202B and c-SiGe layers 202C are disposed on the base c-Si layer 202A. In some embodiments, the base c-Si layer 202A has a thickness greater than that of the c-SiGe layer 202C. In some embodiments, the first stack 202 includes an upper c-SiGe layer 202D corresponding to the upper part of the first stack 202. In some embodiments, the upper c-SiGe layer 202D has a thickness greater than that of the c-SiGe layer 202C. In some embodiments, the c-Si layer 202B of the first stack 202 may have a thickness of about 20 to about 60 nm. In some embodiments, the c-SiGe layer 202C of the first stack 202 may have a thickness of about 5 nm to about 20 nm. In some embodiments, the c-Si layer 202B may have a thickness of about 50 nm and the c-SiGe layer 202C may have a thickness of about 10 nm. The thickness may vary based on the design of a particular memory structure.

[0014] In some embodiments, the first stack is deposited on a substrate using heteroepitaxy processing. The substrate may include a layer of c-Si or other suitable material. By using alternating heteroepitaxy of silicon and silicon germanium, many memory cell layers can be easily constructed with high cost efficiency. Various etching and filling processes can be performed on the first stack to form 3D DRAM features such as word lines, bit lines, capacitors, etc. In some embodiments, the word lines are vertical word lines and the bit lines are horizontal bit lines.

[0015] In 102A, forming the word line feature includes vertically etching a first via pattern 214 through a first stack 202, for example, etching a word line via pattern 212. Passing through the first stack 202 refers to passing through at least the upper c-SiGe layer 202D, the alternating c-Si layers 202B and c-SiGe layers 202C, and, for example, passing through about 50 nm into and at least partially through the base c-Si layer 202A. Vertically etching refers to etching in a direction substantially perpendicular to the horizontal plane of the layers of the first stack 202. The lithography stack 204 may include one or more layers of materials suitable for performing an etching process on the first stack 202. For example, the lithography stack 204 may include a hard mask 210 disposed on an oxide mask 208 disposed on a carbon mask 206. FIG. 2B shows an isometric view of the first stack 202 after word line via formation, according to at least some embodiments of the present disclosure. The vertical etching of the first pattern of vias 214 may be a non-selective etching that etches both c-Si and c-SiGe. The word line via pattern 212 can be any suitable pattern and may include, for example, multiple circular, rectangular, square, or any other suitable shape.

[0016] In 102B, forming the word line feature further includes filling the first pattern of holes 214 with a silicon germanium (SiGe) filler (e.g., SiGe filler 216) having a germanium concentration similar to the germanium concentration of the plurality of c-SiGe layers. For example, in some embodiments, the germanium concentration in the SiGe filler may be within about 10 percent of the germanium concentration in the c-SiGe layer 202C. FIG. 2C shows an isometric view of the first stack 202 after gap filling the word line hole formation with SiGe fill 216, according to at least some embodiments of the present disclosure. In some embodiments, the SiGe filler 216 is deposited by a chemical vapor deposition (CVD) process. In some embodiments, the SiGe filler 216 includes an amorphous SiGe filler.

[0017] In 102C, forming the word line feature further includes vertically etching a plurality of isolation slots (e.g., isolation slots 226) through the first stack and the SiGe filler to divide the silicon germanium filler at each of the first hole patterns. The similar germanium concentrations of the c-SiGe layer 202C and the SiGe filler 216 have the advantage of facilitating more uniform etching of the plurality of isolation slots. FIG. 2D shows an isometric view of the first stack 202 having a lithography stack 220 with an isolation slot pattern 218, according to at least some embodiments of the present disclosure. The lithography stack 220 may include layers similar to the lithography stack 204. For example, the lithography stack 220 may include a hard mask 220C disposed on an oxide mask 220B disposed on a carbon mask 220A. In some embodiments, as shown in FIG. 2D, the isolation slot pattern 218 has a length 222 longer than the length of the word line hole pattern 212 and a width 224 narrower than the width of the word line hole pattern 212. In some embodiments, the plurality of isolation slots 226 and the first hole pattern 214 are substantially coplanar along one of their sides.

[0018] Figure 2E shows an isometric view of the first stack after formation of the isolation slots, according to at least some embodiments of the present disclosure. The vertical etching of the plurality of isolation slots 226 via the isolation slot pattern 218 may be a non-selective etching that etches both c-Si and c-SiGe. The plurality of isolation slots 226 are sized to divide the SiGe fill 216 for further downstream processing to form word line features. In some embodiments, the plurality of isolation slots 226 extend into the first stack 202 at a depth similar to the depth of the first hole pattern 214. In other words, the plurality of isolation slots 226 and the first hole pattern 214 may be etched to a similar amount.

[0019] In 102D, forming the word line features further includes filling the plurality of isolation slots with a dielectric material to form an insulating layer (e.g., insulating layer 228) between the silicon germanium fills. Figure 2F shows an isometric view of the first stack 202 after gap filling the isolation slots 226 with the insulating layer 228, according to at least some embodiments of the present disclosure. The insulating layer 228 may be composed essentially of a dielectric material. In some embodiments, the insulating layer 228 consists of silicon oxide, silicon nitride, or silicon glass.

[0020] In some embodiments, at 104, method 100 includes forming bit line features via a first stack that extends between rows of a first hole pattern. FIG. 3A shows an isometric view of a first stack 202 having a lithography stack with a bit line slit pattern, according to at least some embodiments of the present disclosure. The first stack 202 is shown as having a single bit line slit 304, but the 3D DRAM structure may have multiple bit line slits as the first stack structure repeats / extends in the width direction to form the overall 3D DRAM structure. In some embodiments, the bit line features are horizontal bit line features. In some embodiments, forming the bit line features includes placing a lithography stack 302 having a bit line slit 304 on the first stack 202, and the lithography stack 302 may include layers similar to the lithography stack 204. For example, the lithography stack 302 may include a hard mask 302C disposed on an oxide mask 302B disposed on a carbon mask 302A. Forming the bit line features further includes etching a bit line slit 306 through the first stack 202, as shown in FIG. 3B. FIG. 3B shows an isometric view of the first stack 202 after bit line slit formation, according to at least some embodiments of the present disclosure. In some embodiments, a portion of the lithography stack 204, e.g., a portion of the carbon mask 302A, may be left until downstream processing after bit line slit formation.

[0021] In some embodiments, forming the bit line feature further includes replacing a conductive c-SiGe layer 202C, which may be proximate to the bit line slit 306, with an insulating material. In some embodiments, the replacement of the c-SiGe layer 202C proximate to the bit line slit 306 begins with performing a lateral etching of a plurality of c-SiGe layers 202C from the bit line slit 306 to form a recess 308 for an insulating layer of the 3D DRAM structure (see bit line insulating layer 310 in FIG. 3D). The recess 308 may be formed by using a selective removal process (SRP) that selectively removes only SiGe. The carbon mask 302A may be used to protect the upper c-SiGe layer 202D from the SiGe SRP. By adjusting the selective removal process, the amount of lateral etching can be accurately controlled. The lateral etching refers to etching in a direction substantially parallel to the c-SiGe layer 202C. FIG. 3C shows an isometric view of the first stack 202 after bit line slit lateral etching, according to at least some embodiments of the present disclosure. In some embodiments, the c-SiGe layer 202C is laterally etched from the bit line slit 306 to a position adjacent to the SiGe fill 216.

[0022] In some embodiments, forming the bit line features further includes depositing a bit line insulating layer 310 within a recess 308 formed by bit line lateral etching. The bit line insulating layer 310 includes a dielectric material and replaces the laterally etched c-SiGe layer 202C proximate to the bit line slit 306. In some embodiments, the bit line insulating layer 310 is a nitride layer, such as titanium nitride (TiN). In some embodiments, the bit line insulating layer 310 is deposited via an atomic layer deposition (ALD) process. In some embodiments, forming the bit line features further includes depositing a sacrificial fill 312 within the bit line slit 306. FIG. 3D shows an isometric view of a first stack 202 after depositing the bit line insulating layer 310 within the recess 308 and performing a sacrificial fill 312 within the bit line slit 306, according to at least some embodiments of the present disclosure. The bit line insulating layer 310 provides a backbone that serves as a framework for supporting bit line features formed within the 3D DRAM. The sacrificial fill 312 may be composed essentially of a dielectric material. In some embodiments, the sacrificial fill 312 consists of silicon oxide, silicon nitride, or silicon glass.

[0023] In some embodiments, at 106, method 100 includes forming a plurality of capacitor features within the first stack 202. Forming a plurality of capacitor features within the first stack 202 can be initiated by placing one or more masks 404 having a capacitor slit patterning 406 over the first stack 202, as shown in FIG. 4A. Forming the plurality of capacitor features is then continued by etching capacitor slits 408 through the first stack 202, as shown in FIG. 4B. In some embodiments, the capacitor slits 408 are etched by non-selective etching, similar to the formation of the bit line slits 306. In some embodiments, the capacitor slits 408 are formed after depositing the sacrificial fill 312 within the bit line slits 306.

[0024] Next, in some embodiments, forming a plurality of capacitor features includes performing a lateral etch of the plurality of c-SiGe layers 202C from the capacitor slit 408 to form recesses 410 for an insulating layer of the 3D DRAM structure (see capacitor insulating layer 412 in FIG. 4D). The lateral etch is performed by an SRP process, and only c-SiGe and not c-Si is selectively removed. FIG. 4C shows an isometric view of the first stack 202 after lateral etching of the capacitor slit according to at least some embodiments of the present disclosure. In some embodiments, the c-SiGe layer 202C is etched back from the capacitor slit 408 to the SiGe fill 216.

[0025] In some embodiments, forming a capacitor feature further includes depositing a capacitor insulating layer 412 within the recesses 410 formed after the lateral etch of the c-SiGe layer from the capacitor slit 408. The capacitor insulating layer 412 includes a dielectric material that fills the recesses 410. In some embodiments, the capacitor insulating layer 412 is an oxide layer or a nitride layer, such as aluminum oxide (Al2O3) or titanium nitride (TiN). In some embodiments, the capacitor insulating layer 412 is deposited via an atomic layer deposition (ALD) process. In some embodiments, forming a capacitor feature further includes depositing a sacrificial fill 414 within each capacitor slit 408. FIG. 4D shows an isometric view of the first stack 202 after depositing the capacitor insulating layer 412 within the recesses 410 and performing sacrificial fill 414 within the capacitor slits 408 according to at least some embodiments of the present disclosure. The capacitor insulating layer 412 provides a backbone that supports the capacitor features formed within the 3D DRAM. The sacrificial fill 414 may be composed essentially of a dielectric material. In some embodiments, the sacrificial fill 414 consists of silicon oxide, silicon nitride, or silicon glass. A planarization process may be performed after the deposition of the sacrificial fill 414.

[0026] Referring back to 102, in some embodiments, forming the word line features at 102E in the first stack 202 further includes etching the SiGe fill 216 and the c-SiGe layer 202C between the bit line insulating layer 310 and the capacitor insulating layer 412. FIG. 5A shows an isometric view of the first stack 202 after performing SiGe vertical and lateral etching of the word line replacement portion, according to at least some embodiments of the present disclosure. The vertical and lateral etching forms vertical recesses 508 and horizontal recesses 510 (i.e., recesses that cover around each of the gate silicon channels 504 to build the basis of the GAA structure) around the plurality of gate silicon channels 504. In some embodiments, the plurality of gate silicon channels 504 includes a portion of a plurality of c-Si layers 202B horizontally disposed between the bit line insulating layer 310 and the capacitor insulating layer 412. In some embodiments, the SiGe fill 216 and the c-SiGe layer 202C are etched via an SRP process to selectively remove only the SiGe. In some embodiments, after etching the SiGe fill 216 and the c-SiGe layer 202C between the bit line insulating layer 310 and the capacitor insulating layer 412, all of the SiGe (from both the SiGe fill 216 and the c-SiGe layer 202C) is removed from the first stack 202.

[0027] In some embodiments, after etching the SiGe fill 216 and the c-SiGe layer 202C, as shown in FIG. 5B, the c-Si layer including the plurality of gate silicon channels 504 can be etched to widen the gaps between the c-Si layers. FIG. 5B shows an isometric view of the first stack 202 after performing thinning Si etching for the word line replacement portion, according to at least some embodiments of the present disclosure. The etching may be an SRP process that selectively removes about 3 to about 8 nm of c-Si. In some embodiments, the etching is a lateral etching such that the horizontal recess 510 is enlarged to the horizontal recess 510A.

[0028] In 102F, forming the word line feature includes depositing a conductive layer 520 that covers the perimeter of a plurality of gate silicon channels to form the GAA structure of the 3D DRAM. FIG. 5C shows an isometric view of the first stack 202 after depositing the conductive layer 520 within the horizontal recesses 510 or 510A and the vertical recess 508 formed by SiGe lateral and vertical etching of the word line replacement portion. In some embodiments, an outer layer 550 is disposed around the conductive layer 520. In some embodiments, the outer layer 550 includes a gate dielectric layer 522 deposited within the horizontal recesses 510 or 510A and the vertical recess 508 prior to depositing the conductive layer 520. In some embodiments, the outer layer 550 includes a liner layer 524 deposited between the gate dielectric layer 522 and the conductive layer 520. In some embodiments, the liner layer 524 is disposed between the gate dielectric layer 522 and the conductive layer 520. The conductive layer 520 includes any suitable metal such as tungsten. The gate dielectric layer 522 may include an oxide layer such as silicon oxide. The liner layer 524 may include a nitride layer such as titanium nitride (TiN). One or more of the conductive layer 520, the gate dielectric layer 522, or the liner layer 524 may be deposited via suitable CVD or ALD processes.

[0029] Referring back to 106, in some embodiments, forming a plurality of capacitor features includes performing a lateral etch of the plurality of c-Si layers 202B from the capacitor slit 408 to expose source / drain doping regions (e.g., source / drain doping region 602) of the 3D DRAM structure. In some embodiments, the lateral etch is performed on both sides of the capacitor slit 408. Prior to the lateral etch of the plurality of c-Si layers 202B, a hard mask may be placed on the first stack 202 and a vertical etch may be performed to etch the sacrificial fill 414 to expose the c-Si layer adjacent to the capacitor slit 408. FIG. 6A shows an isometric view of the first stack 202 after performing a vertical etch of the capacitor slit 408, according to at least some embodiments of the present disclosure. In some embodiments, a partial sacrificial fill 414' may be left to protect the base c-Si layer 202A from unwanted etching. The partial sacrificial fill 414' generally extends under or to the bottom capacitor insulating layer 412A such that the partial sacrificial fill 414' does not cover any of the c-Si layers 202B adjacent to the capacitor slit 408.

[0030] FIG. 6B shows an isometric view of a first stack after performing lateral etching from the capacitor slit 408 to form a recess 606 for capacitor replacement in accordance with at least some embodiments of the present disclosure. In some embodiments, the lateral etching is an SRP process for selectively removing c-Si. The lateral etching can be configured to remove about 300 to about 800 nm of c-Si to expose the source / drain doping region 602. FIG. 6C shows an isometric view of the first stack 202 after performing a drain doping process in accordance with at least some embodiments of the present disclosure. After the drain doping process, the first stack 202 includes a drain 610 disposed between each of the plurality of gate silicon channels 504 and a corresponding one of the recesses 606 disposed on a common horizontal plane. The drain doping process may include doping by selective epitaxy, plasma doping, etc. The drain doping process may include doping c-Si with any suitable material such as phosphorus. In some embodiments, a silicide layer 630 can be formed adjacent to the drain 610. In some embodiments, the silicide layer 630 is formed by a selective reaction. In some embodiments, the silicide layer 630 consists essentially of titanium silicide (TiSi).

[0031] After the drain doping process, forming the capacitor feature includes depositing a metal electrode layer (e.g., metal electrode layer 616) on at least a portion of the region where the plurality of c-Si layers are laterally etched from the capacitor slit (i.e., at least a portion of the recess 606). The metal electrode layer 616 may include any suitable conductive material. In some embodiments, the capacitor feature comprises a stack of alternating layers of a capacitor insulating layer 412 and a metal electrode layer 616.

[0032] In some embodiments, the metal electrode layer 616 is formed by depositing a first metal layer 632. In some embodiments, the metal electrode layer 616 includes a first dielectric layer 634 deposited on the first metal layer 632. In some embodiments, the metal electrode layer 616 includes a second metal layer 638 deposited on the first dielectric layer 634 (see also FIG. 9). In some embodiments, the second metal layer 638 may include a thin metal layer and a gap filling material having a low stress that promotes the expansion and stress relaxation of the second metal layer 638. For example, the gap filling material may be boron-doped SiGe or the like.

[0033] In some embodiments, after filling the recess 606, the capacitor slit 408 is filled with a sacrificial filler 614. In some embodiments, the sacrificial filler 614 includes a material similar to the sacrificial filler 414. FIG. 6D shows an isometric view of the first stack 202 after performing capacitor recess filling and sacrificial filling processes according to at least some embodiments of the present disclosure.

[0034] Referring back to 104, in some embodiments, forming the bit line features further includes performing a lateral etch of the plurality of c-Si layers 202B from the bit line slit 306 to expose source / drain doping regions (e.g., source / drain doping region 708) of the 3D DRAM structure. In some embodiments, the lateral etch is performed on both sides of the bit line slit 306. Prior to performing the lateral etch, a vertical etch of the sacrificial fill 312 is performed to at least partially remove the sacrificial fill 312 to expose the c-Si layer 202B from the bit line slit 306. FIG. 7A shows an isometric view of a first stack 202 with a hard mask 704 having a bit line slit 706 according to at least some embodiments of the present disclosure. The bit line slit 706 exposes the sacrificial fill 312. FIG. 7B shows an isometric view of the first stack 202 after a vertical bit line slit etch process according to at least some embodiments of the present disclosure. A partial sacrificial fill 312' may be left to protect the base c-Si layer 202A. FIG. 7C shows an isometric view of the first stack 202 with a bit line slit lateral etch back process according to at least some embodiments of the present disclosure. The bit line slit lateral etch back forms recesses 712 between the bit line insulating layers 310 that expose the source / drain doping regions 708. In some embodiments, the bit line slit lateral etch includes selectively removing laterally about 30 to about 80 nm of c-Si from the bit line slit 306.

[0035] FIG. 7D shows an isometric view of a first stack 202 with bit line source doping, according to at least some embodiments of the present disclosure. After the source doping process, the first stack 202 includes a source 714 disposed between each of a plurality of gate silicon channels 504 and a corresponding one of recesses 712 disposed on a common horizontal plane. The source doping process may include doping by selective epitaxy, plasma doping, etc. The source doping process may include doping c-Si with any suitable material such as phosphorus. In some embodiments, a silicide layer 730 may be formed adjacent to the source 714. In some embodiments, the silicide layer 730 is formed by a selective reaction. In some embodiments, the silicide layer 730 consists essentially of titanium silicide (TiSi).

[0036] Forming the bit line feature further includes depositing a metal layer (e.g., bit line metal layer 718) on at least a portion of a region where a plurality of c-Si layers are etched laterally from the bit line slit (i.e., depositing a metal layer on at least a portion of the recess 712). FIG. 7E shows an isometric view of a first stack with bit line metal deposition, according to at least some embodiments of the present disclosure. The bit line metal layer 718 may include a material similar to the conductive layer 520.

[0037] In some embodiments, after filling the recess 712, the bit line slit 306 is filled with a sacrificial filler 726. In some embodiments, the sacrificial filler 726 includes a material similar to the sacrificial filler 312. FIG. 7F shows an isometric view of a first stack 202 with gap filling of the bit line slit 306, according to at least some embodiments of the present disclosure. A planarization process can be performed to smooth any surface of the first stack 202 before and after any of the processing steps disclosed herein, for example, before and after an etching or gap filling process.

[0038] FIG. 8 shows an isometric cross-sectional view of a portion of a three-dimensional dynamic random access memory (3D DRAM) structure 800 according to at least some embodiments of the present disclosure. In some embodiments, the 3D DRAM structure 800 is formed via the processes described above and shown in FIGS. 2A through 7F. The 3D DRAM structure 800 includes at least one vertical word line feature 806 of a 3D DRAM structure formed within a first stack 202 of alternating crystalline silicon (c-Si) layers 808 and nitride layers 810. The at least one vertical word line feature 806 extends in a vertical direction 802. The at least one vertical word line feature 806 includes a plurality of gate silicon channels 504 comprising a plurality of c-Si layers 202B, a gate dielectric layer 522 covering each of the plurality of gate silicon channels 504, and a conductive layer 520 covering the gate dielectric layer 522 to form a gate-all-around (GAA) structure. In some embodiments, a liner layer 524 is disposed between the gate dielectric layer 522 and the conductive layer 520. In some embodiments, the liner layer 524 is formed of a nitride layer and the gate dielectric layer 522 is formed of an oxide layer.

[0039] In some embodiments, at least one horizontal bit line feature 826 extends in a horizontal direction 804 that is perpendicular to the at least one vertical word line feature 806. A plurality of capacitor features 816 extend horizontally from the at least one vertical word line 806 between capacitor insulating layers 412. In some embodiments, the source 714 is disposed between the at least one vertical word line and the at least one horizontal bit line, and the drain is disposed between the at least one vertical word line and the plurality of capacitors. In some embodiments, the at least one horizontal bit line feature 826 comprises a plurality of alternating layers of bit line metal layers 718 and bit line insulating layers 732. In some embodiments, the plurality of bit line metal layers 718 are self-aligned perpendicular to the source 714.

[0040] The above relates to embodiments of the present disclosure, but other additional embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure.

Claims

1. A method of forming a three-dimensional dynamic random access memory (3D DRAM) structure, comprising: forming at least one word line in a first stack including a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers; vertically etching a first hole pattern through the first stack; filling the first hole pattern with a silicon germanium filler having a germanium concentration similar to the germanium concentration of the plurality of c-SiGe layers; vertically etching a plurality of isolation slots through the first stack and dividing the silicon germanium filler in each of the first hole patterns; filling the plurality of isolation slots with a dielectric material to form an insulating layer between the silicon germanium fillers; etching the silicon germanium fillers and the plurality of c-SiGe layers to form a plurality of gate silicon channels including a part of the plurality of c-Si layers; depositing a layer of conductive material covering the periphery of the plurality of gate silicon channels; forming at least one word line, including; a method, including.

2. The method according to claim 1, further comprising forming bit lines through the first stack extending between rows of the first hole pattern.

3. Forming the bit lines includes: etching bit line slits through the first stack; performing lateral etching of the plurality of c-Si layers from the bit line slits to expose source / drain doping regions of the 3D DRAM structure; depositing a metal layer on at least a part of the region where the plurality of c-Si layers are laterally etched from the bit line slits; The method according to claim 2, including.

4. Forming the bit lines includes: depositing a bit line insulating layer in recesses formed by the lateral etching of the plurality of c-SiGe layers; The method according to claim 3, further including.

5. The method according to claim 1, further comprising forming a plurality of capacitors in the first stack.

6. Forming the plurality of capacitors includes: etching capacitor slits through the first stack; Performing lateral etching of the plurality of c-Si layers from the capacitor slit to expose the source / drain doping regions of the 3D DRAM structure; Depositing a metal electrode layer on at least a part of the region where the plurality of c-Si layers are laterally etched from the capacitor slit; The method according to claim 5, comprising:

7. Forming the plurality of capacitors includes: Depositing a capacitor insulating layer in the recess formed by the lateral etching of the plurality of c-SiGe layers; The method according to claim 6, further comprising:

8. Forming bit lines through the first stack extending between rows of the first hole pattern; Forming a plurality of capacitors in the first stack; The method according to claim 1, further comprising:

9. The method according to any one of claims 1 to 8, further comprising depositing the first stack on a substrate using heteroepitaxy processing.

10. The method according to any one of claims 1 to 8, further comprising depositing a gate dielectric layer around the plurality of gate silicon channels before depositing the layer of the conductive material.

11. The method according to claim 10, further comprising depositing a liner layer on the gate dielectric layer before depositing the layer of the conductive material.

12. The method according to any one of claims 1 to 8, wherein the silicon germanium filler comprises amorphous silicon germanium deposited via a chemical vapor deposition (CVD) process.

13. The method according to any one of claims 1 to 8, further comprising etching the plurality of c-Si layers to widen the gaps between the plurality of c-Si layers.

14. The method according to any one of claims 1 to 8, wherein the concentration of germanium in the c-SiGe layer can be between about 10 and about 35 atomic percent.

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