Interconnection for Electronic Devices

Abstract

The semiconductor die (94) includes a substrate (110) and an integrated circuit (120) disposed on the substrate (110) and having contacts (121). A conductive layer (130) is disposed on the integrated circuit (120) and defines conductive elements electrically connected to the contacts (121). Conductive interconnects (150) are coupled to each conductive element. The conductive interconnects (150) have at least one of different sizes or shapes.

Description

Technical Field

[0001] This application relates to interconnections for electronic devices.

Summary of the Invention

[0002] In one example, a semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. A conductive layer is provided on the integrated circuit and defines conductive elements that are electrically connected to the contacts. Conductive interconnects are coupled to the respective conductive elements. The conductive interconnects have at least one of different dimensions or shapes from each other.

[0003] In another example, an electronic device package includes a die having a substrate and an integrated circuit provided on the substrate. The integrated circuit includes contacts. A conductive layer is provided on the integrated circuit and defines conductive elements that are electrically connected to the contacts. Conductive interconnects are coupled to the respective conductive elements. The conductive interconnects have at least one of different dimensions or shapes from each other. A lead frame is fixed to the conductive interconnects.

Brief Description of the Drawings

[0004]

Figure 1

[0005]

Figure 2

[0006]

Figure 3A

[0007]

Figure 3B

[0008]

Figure 4

[0009]

Figure 5

[0010]

Figure 6

[0011] FIG. 1 illustrates an exemplary wafer 90 used to form an electronic device. The electronic device can be, for example, a wafer-level chip scale package (WLCSP) of an integrated circuit. Alternatively, the electronic device may be on a chip or dice scale, PCB scale or panel scale, or an electronic equipment package. As a result, the electronic device can be on a millimeter scale or up to several feet in dimension.

[0012] As shown, wafer 90 includes a substrate 110 having a first side 112 and a second side 114. Substrate 110 can be circular and can have a diameter of, for example, about 200 or 300 mm. Alternatively, substrate 110 may be square or rectangular (not shown). Substrate 110 can be formed from a semiconductor material such as silicon. Wafer 90 is diced, for example, by stealth dicing, into individual dice 94 (FIG. 2) to singulate the wafer. When dice 94 are connected to lead frame 147, an electronic equipment package or device 100 is formed.

[0013] Within each die 94, integrated circuit 120 is fabricated or otherwise provided on the second side 114 of substrate 110. Integrated circuit 120 includes one or more contacts schematically shown at 121. Integrated circuit 120 may be arranged in a grid or array pattern equidistantly spaced from each other with respect to the second side 114. Depending on the dimensions of substrate 110 and integrated circuit 120, thousands or tens of thousands of integrated circuits may be fabricated on the second side 114 of the substrate. Each integrated circuit 120 includes a surface or side 108 facing away from substrate 110.

[0014] Referring to FIGS. 2 and 3A, a layer 130 of conductive material is provided on side 108 of integrated circuit 120, defining one or more conductive first, second, and third elements 131, 133, 135 for redistributing and / or routing electrical power. Layer 130 may be formed from a metal such as copper or aluminum. Elements 131, 133, 135 may include conductive lines and / or conductive contacts formed in different patterns.

[0015] As shown in FIG. 3A, elements 131, 133 are formed as first and second lines. Element 135 is formed as a contact. Other transpositions and combinations of lines and contacts are also contemplated. Each element 131, 133 is electrically connected to one or more contacts 121 via vias (not shown) within the integrated circuit. Each element 131, 133 may include at least one base 134 and a plurality of fingers 136 extending from each base in one or more directions. Base 134 may have a polygonal shape such as, for example, square, rectangular, or trapezoidal. Fingers 136 may generally be rectangular and have a length extending away from base 134 that is greater than the width. The illustrated element 131 includes a pair of bases 134 and fingers 136 extending therebetween. At least some of the fingers 136 extend between bases 134 and interconnect the bases 134.

[0016] Each element 133 includes a base 134 and fingers 136 extending from the base. In one example, the fingers 136 extend in opposite directions from the base 134. The base 134 can have a polygonal shape such as, for example, a square, rectangle, or trapezoid. The fingers 136 can generally be rectangular and have a length extending away from the base 134 that is greater than the width. The elements 133 are disposed between the fingers 136 of the element 131 and are electrically insulated from each other and from the element 131. In one example, the elements 133 are intermeshed with the fingers 136 of the element 131. The elements 135 can be round or square and are each electrically connected to corresponding contacts 121 in the integrated circuit 120 via vias (not shown). The elements 135 are electrically insulated from each other and from the elements 131, 133.

[0017] Referring to FIG. 2, a layer 140 of material extends over the layer 130 and covers the entire side portion 108 of each integrated circuit 120. The layer 140 is formed from an electrically insulating material such as polyimide. One or more slots or openings 142 extend through the insulating layer 140 to expose a portion of the layer 130, that is, to expose portions of the elements 135 and the elements 131, 133. However, it will be understood that the layer 140 can be omitted (not shown).

[0018] The openings 142 can be sized and shaped to expose different portions of the same element 131 or 133, or portions of different elements 131, 133. For this purpose, the openings 142 can be aligned with the bases 134 and / or the fingers 136 of the elements 131, 133. Each opening 142 can have a cross-sectional area that varies along its depth or has a constant cross-sectional area (not shown). As shown, each opening 142 has a cross-sectional area that increases in the direction extending away from the layer 130.

[0019] Referring to FIG. 3B, the conductive interconnect 150 extends in contact with the exposed portions of element 135 and elements 131, 133 through each opening 142 (if present). Each interconnect 150 includes a first portion or bump 152 and a second portion or post 154 disposed between the first portion and respective elements 131, 133, 135. Alternatively, the first portion 152 may be omitted (not shown). Each second portion 154 engages an element 135 or a portion of elements 131, 133 exposed by the associated opening 142. Although the interconnects 150 are shown only on a single integrated circuit 120 in FIG. 1, it should be understood that any number of integrated circuits on the substrate 110 may include any number of interconnects.

[0020] The first portion 152 may be formed of a conductive material, such as a tin solder, e.g., SnAg or NiSnAg, that undergoes a solder reflow to secure the die 94 to the lead frame 147. With this in mind, the lead frame 147 may be secured to the die 94 prior to singulation of the die from the wafer 90. As a result, a portion of the lead frame 147 is separated during singulation, and the remainder of the lead frame remains within the electronic device after singulation. Thus, the lead frame 147 may not have a frame shape within the electronic device.

[0021] In any case, the second portion 154 can be formed of a conductive material such as copper. The first portion 152 can have a thickness t1 of about 5 to 30 μm. The second portion 154 can have a thickness t2 of about 25 to 55 μm. The interconnect 150 can have an overall thickness T of about 60 μm. The thickness T of the interconnect 150 may be different from the width extending perpendicular to the thickness (left to right in the illustration), that is, the thickness may be greater than or less than the width. The interconnect 150 can be formed by electroplating the first portion 152 and the second portion 154 directly onto the insulating layer 140 and bringing them into contact with the exposed portions of the element 135 and the elements 131, 133 through the opening 142. The interconnect 150 can have an overhang or lip 160 that engages with the insulating layer 140 outside the opening 142. In other words, the interconnect 150 can have a footprint larger than the opening 142 and can extend around or surround the opening entirely (as shown in the illustration) from above. The lip 160 can have a width w of about 25 μm with respect to the minimum cross-sectional area of the opening 142 in the layer 130.

[0022] The interconnects 150 can have a wide range of shapes and dimensions on each integrated circuit 120. In particular, the interconnects 150 can have any shape or cross-section, for example, square or rectangular (see FIG. 3), circular, polygonal, and / or elongated, with any number of straight and / or curved sides. The interconnects 150 associated with a single integrated circuit 120 can have different dimensions and / or different shapes from each other. In one example, the interconnects 150 can have a width of about 150 to 500 μm and a length of about 150 to 500 μm. The interconnects 150 can have an aspect ratio of at least 1:1 to about 5:1. Nevertheless, the interconnects 150 completely fill each opening 142, and the shape of the interconnect is defined by the shape of the opening. That is, by configuring the opening 142 to expose specific portions of the elements 131, 133, the interconnect 150 extending into the opening can easily contact these exposed portions.

[0023] Keeping this in mind, depending on the shape of the openings 142 in the insulating layer 140, the interconnect 150 can contact any number of elements 131, 133, 135. In the example shown in FIG. 3A, five openings 142 in the insulating layer 140 enable five interconnects 150 to contact the exposed individual elements 135 formed as contacts. The interconnect 150 contacting the element 135 can be circular, round, or square (not shown).

[0024] Another elongated opening 142 exposes the finger 136 on the element 131 and the base 134 of the plurality of elements 133. Thus, the interconnect 150 electroplated through this opening 142 contacts the finger 136 on the element 131 as well as the base 134 of the element 133. As a result, the elements 131, 133, which would otherwise be electrically insulated from each other, are electrically connected to each other by the interconnect 150. Accordingly, a plurality of contacts 121 within the same integrated circuit 120 that are electrically connected to the exposed elements 131, 133 are electrically connected to each other. This is desirable, for example, when a plurality of integrated circuits 120 are intended for the same integrated circuit when the electronic device 100 is diced, or when it is desirable to increase the power delivery to one or more integrated circuits.

[0025] It will be appreciated that a single interconnect 150 can extend within a plurality of discrete openings 142 to electrically connect spaced-apart portions of the elements 131, 133 (not shown). In any case, the openings 142 throughout the insulating layer 140 are sized and shaped to expose a portion of the layer 130 so as to electrically connect the contacts 121 within a single integrated circuit 120 by providing the interconnect 150 within the openings. This is repeated across all the integrated circuits 120 on the electronic device 100 in the desired manner.

[0026] For this purpose, in another exemplary die 94 shown in FIG. 4, pairs of interconnects 150 are provided on surface 108 for three contacts 121 within the die. A first generally square interconnect 150 extends through a similarly shaped opening 142 in the insulating layer 140 so that the interconnect can contact an exposed element 135 aligned with an opening (not shown). A second generally rectangular interconnect 150 extends through a similarly shaped opening 142 in the insulating layer 140 to enable the interconnect to contact portions of a plurality of elements 131, 133 aligned with an opening (not shown).

[0027] In another exemplary electronic device configuration shown in FIG. 5, the electronic device is a die 200 formed by dividing a wafer 90 by dicing, such as by stealth dicing. Nine interconnects 150 are provided on surface 108 for the 13 contacts 121 within die 94. Five interconnects 150 are square and contact element 135. The remaining interconnects 150 are elongated and contact portions of a plurality of elements 131, 133.

[0028] In another example shown in FIG. 6, the electronic device is a WLCSP 300 for high current applications. As a result, conductive materials are formed in a plurality of layers 230 within substrate 110. Layers 230 can be formed from damascene copper and can define one or more field effect transistors including gates (not shown), drains (D), and sources (S). Layers 230 are disposed through the thickness of integrated circuit 120 and cooperate with vias (not shown) to electrically connect contacts 121 within integrated circuit 120 to each other and to electrically connect the structure to interconnect 250.

[0029] Forming the interconnects 150, 250 in multiple dimensions and / or shapes advantageously enables the interconnects to transfer power to the integrated circuit 120 at an increased level. More specifically, a single interconnect 150 can contact the conductive layer 130 over a surface area larger than that of a conventional spherical solder ball, thereby allowing more power to flow through a single interconnect to a contact 121 within the integrated circuit 120 that is electrically connected thereto. Accordingly, the frequency of the encoded message that can pass through the layer 130 / interconnect 150, 250 interface increases.

[0030] In one example, the interconnects 150, 250 can increase the Vss area by at least 80%, the I / O area by at least 30%, the Vin area by at least 100%, and the Vsw area by at least 120% compared to the area provided by a spherical solder ball. As a result, the interconnects 150, 250 can be designed to maximize the dimensions of the power and logic interconnects within the electronic device without increasing the dimensions of the associated integrated circuit 120 or infringing on surface mount technology capabilities. Accordingly, the interconnect 150 described herein can be used for power devices.

[0031] The non-circular interconnects 150, 250 described herein can also advantageously relieve or substantially reduce the conductive layer wiring in the substrate typically required by conventional spherical solder connections. In particular, some existing electronic devices require multi-level conductive metal wiring in the substrate to electrically connect multiple integrated circuits on opposite sides of the substrate. In contrast, the conductive interconnects described herein can contact multiple electrically isolated contacts or structures within a single integrated circuit in an efficient and cost-effective manner.

[0032] Also, the interconnects 150, 250 can have a reduced thickness compared to spherical interconnects, resulting in greater heat transfer through thinner non-circular interconnects, thereby improving thermal performance. More specifically, shorter interconnects provide less resistance and generate less heat loss. As a result, the interconnects 150, 250 described herein can increase the flexibility in electrical wiring to improve the electromigration resistance and thermal efficiency of the electronic device while increasing the important interconnect area between the interconnect and the electrical element. Also, the interconnects enable more efficient use of substrate space for functional devices.

[0033] Within the scope of the claims of the present invention, modifications may be made to the illustrated examples described, and other embodiments are possible.

Claims

1. A semiconductor die, comprising: a substrate; an integrated circuit provided on the substrate, the integrated circuit having contacts; a conductive layer provided on the integrated circuit and defining a conductive element electrically connected to the contacts, the conductive element including: a first base portion connected to a first contact, a second base portion connected to a second contact, and first and second finger portions extending between the first and second bases and connecting the first and second base portions to each other; a second element disposed between the first and second finger portions of the first element, the second element including a base portion connected to a third contact, a first finger portion extending from the base portion toward the first base portion of the first element, and a second finger portion extending from the base portion toward the second base portion of the first element; a third element disposed along the first finger portion of the first element, the third element including a base portion connected to a fourth contact, a first finger portion extending from the base portion toward the first base portion of the first element, and a second finger portion extending from the base portion toward the second base portion of the first element; the conductive layer including the above; a conductive interconnect coupled to a selected conductive element, the conductive interconnect including: a first interconnect disposed on and connected to the base portion of the second element and the base portion of the third element; a second interconnect disposed on and connected to the first base portion of the first element, the second interconnect having a dimension or shape different from that of the first interconnect; the conductive interconnect including the above; the semiconductor die including the above.

2. The semiconductor die according to claim 1, wherein at least one of the conductive interconnects has a thickness extending away from the conductive element that is greater than a width extending perpendicular to the thickness.

3. The semiconductor die according to claim 1, wherein at least one of the conductive interconnects has a polygonal shape.

4. The semiconductor die according to claim 1, wherein at least one of the conductive interconnects has an aspect ratio greater than 1:

1.

5. The semiconductor die according to claim 1, wherein at least one of the conductive interconnects has a thickness extending away from the conductive element that is greater than a width extending perpendicular to the thickness.

6. The semiconductor die according to claim 1, wherein at least one of the conductive interconnects has a polygonal shape.

7. The semiconductor die according to claim 1, wherein at least one of the conductive interconnects has an aspect ratio greater than 1:

1.

8. The semiconductor die according to claim 1, wherein an insulating layer provided on the conductive layer, the semiconductor die further including the insulating layer and including an opening for exposing the conductive element.

6. The semiconductor die according to claim 5, wherein the conductive interconnect extends to contact the conductive element through the opening.

7. The semiconductor die according to claim 1, wherein each conductive interconnect includes a first portion containing tin and a second portion containing copper and disposed between the first portion and the conductive layer.

8. The semiconductor die according to claim 7, wherein the second portion has a thickness of 25 to 55 μm.

9. The semiconductor die according to claim 7, wherein at least one of the conductive interconnects has a thickness of 60 μm.

10. An electronic device package, comprising a die, a substrate, an integrated circuit provided on the substrate and having contacts, a conductive layer provided on the integrated circuit and defining a conductive element electrically connected to the contacts, the conductive element including a first base portion connected to a first contact, a second base portion connected to a second contact, and first and second finger portions extending between the first and second bases and connecting the first and second base portions to each other; a second element disposed between the first and second finger portions of the first element, the second element including a base portion connected to a third contact, a first finger portion extending from the base portion toward the first base portion of the first element, and a second finger portion extending from the base portion toward the second base portion of the first element; a third element disposed along the first finger portion of the first element, the third element including a base portion connected to a fourth contact, a first finger portion extending from the base portion toward the first base portion of the first element, and a second finger portion extending from the base portion toward the second base portion of the first element; the conductive layer including; a conductive interconnect coupled to a selected conductive element, A first interconnect disposed over and connected to the base portion of the second element and the base portion of the third element; A second interconnect disposed over and connected to the first base portion of the first element, the second interconnect having a dimension or shape different from that of the first interconnect; The conductive interconnect including the above; The die including the above; A lead frame including a portion attached to the conductive interconnect; An electronic device package including the above.

11. The electronic device package according to claim 10, wherein at least one of the conductive interconnects has a thickness extending away from the conductive element that is greater than a width extending perpendicular to the thickness.

12. The electronic device package according to claim 10, wherein at least one of the conductive interconnects has a polygonal shape.

13. The electronic device package according to claim 10, wherein at least one of the conductive interconnects has an aspect ratio greater than 1:

1.

14. The electronic device package according to claim 10, wherein the die further includes an insulating layer provided over the conductive layer and including an opening exposing the conductive element.

15. The electronic device package according to claim 14, wherein the conductive interconnect extends to contact the conductive element through the opening.

16. The electronic device package according to claim 10, wherein each conductive interconnect includes a first portion containing tin and a second portion containing copper and disposed between the first portion and the conductive layer.

17. The electronic device package according to claim 16, wherein the second portion has a thickness of 25 to 55 μm.

18. The electronic device package according to claim 16, wherein at least one of the conductive interconnects has a thickness of 60 μm.

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