Wiring Substrate and Method for Manufacturing Wiring Substrate

Abstract

To improve bonding strength with electronic components.SOLUTION: A wiring board has a first wiring layer having a wiring pattern and pads, a first insulating layer covering the first wiring layer and exposing the surface of the wiring pattern and pads of the first wiring layer from the top surface, a second insulating layer formed on the top surface of the first insulating layer, an aperture penetrating the second insulating layer to the pad of the first wiring layer, and a connection terminal formed in the aperture in the second insulating layer and connected to the pads of the first wiring layer and having one end protruding from the aperture of the second insulating layer and having a top that is wider than the pad of the first wiring layer at one end.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] Generally, connection terminals with electronic components such as semiconductor chips are formed on a wiring board on which electronic components such as semiconductor chips are mounted. From the viewpoint of avoiding a short circuit defect with a wiring layer, the connection terminals may be provided in another insulating layer different from the insulating layer covering the wiring layer.

[0003] A wiring board having such connection terminals is manufactured using, for example, a support. Specifically, a wiring layer including a wiring pattern and pads is formed on the support, an insulating layer covering the wiring layer is formed, and then the support is removed, and another insulating layer is laminated on the exposed surface of the exposed insulating layer. Then, the connection terminals are formed in another insulating layer different from the insulating layer covering the wiring layer by, for example, a semi-additive method. That is, the connection terminals are formed by forming openings penetrating to the pads of the wiring layer on the exposed surface of the insulating layer in the other insulating layer, and performing, for example, electrolytic copper plating in the openings of the other insulating layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in a wiring board having connection terminals in another insulating layer different from the insulating layer covering the wiring layer, there is a problem that the bonding strength between the connection terminals and the electronic components is not sufficient.

[0006] That is, in the wiring board described above, generally, the width of the top portion protruding from the opening of the other insulating layer of the connection terminal is substantially equal to the width of the pad of the wiring layer exposed at the bottom of the opening. The pads of the wiring layer are arranged adjacent to the wiring pattern. Therefore, as the arrangement of the wiring pattern is miniaturized and the width of the pad of the wiring layer becomes smaller, the width of the top portion of the connection terminal equal to the width of the pad of this wiring layer also becomes smaller. As a result, the connection area between the top portion of the connection terminal and the electrode of the electronic component becomes smaller, and there is a possibility that the bonding strength between the connection terminal and the electronic component decreases.

[0007] The disclosed technology has been made in view of the above, and an object thereof is to provide a wiring board and a method for manufacturing the wiring board capable of improving the bonding strength with an electronic component.

Means for Solving the Problems

[0008] In one aspect, the wiring board disclosed in the present application includes a first wiring layer including a wiring pattern and a pad, a first insulating layer that covers the first wiring layer and exposes the surfaces of the wiring pattern and the pad of the first wiring layer from the upper surface, a second insulating layer formed on the upper surface of the first insulating layer, an opening that penetrates the second insulating layer to the pad of the first wiring layer, and a connection terminal formed in the opening of the second insulating layer and connected to the pad of the first wiring layer, one end of which protrudes from the opening of the second insulating layer and has a top portion having a width larger than that of the pad of the first wiring layer.

Effects of the Invention

[0009] According to one aspect of the wiring board disclosed in the present application, there is an effect that the bonding strength with an electronic component can be improved.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the wiring board and the method for manufacturing the wiring board disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited by this embodiment.

[0012] (Embodiment) FIG. 1 is a diagram showing the configuration of a wiring board 10 according to an embodiment. In FIG. 1, a cross-section of the wiring board 10 is schematically shown. The wiring board 10 shown in FIG. 1 can be used, for example, as a substrate of a semiconductor device on which a semiconductor chip is mounted.

[0013] The wiring board 10 has a laminated structure and includes a build-up layer 100 and solder resist layers 200 and 300. The build-up layer 100 is further divided into a first layer 110, a second layer 120, and a third layer 130. Hereinafter, as shown in FIG. 1, it will be described assuming that the solder resist layer 300 is the lowermost layer and the solder resist layer 200 is the uppermost layer. However, the wiring board 10 may be used, for example, upside down, and may be used in any orientation.

[0014] The first layer 110 is a layer formed from a conductive first wiring layer 111, an insulating first insulating layer 112, and a conductive second wiring layer 113. The first wiring layer 111 is formed using a metal such as copper or a copper alloy, for example. The first wiring layer 111 includes a wiring pattern 111a and pads 111b. The first insulating layer 112 covers the back surface (lower surface) and side surfaces of the first wiring layer 111, and the surfaces of the wiring pattern 111a and pads 111b of the first wiring layer 111 are exposed from the upper surface 112a of the first insulating layer 112. The first insulating layer 112 has heat resistance such as an epoxy resin, a polyimide resin, and a cyanate resin, for example, and is formed using a non-photosensitive and thermosetting insulating resin. The second wiring layer 113 is formed on the lower surface 112b of the first insulating layer 112. The second wiring layer 113 is formed using a metal such as copper or a copper alloy, for example. The second wiring layer 113 and the pads 111b of the first wiring layer 111 are connected by vias 114 that penetrate the first insulating layer 112.

[0015] The second layer 120 is laminated adjacent to the upper side of the first layer 110 and is a layer formed from an insulating second insulating layer 121. The second insulating layer 121 is formed on the upper surface 112a of the first insulating layer 112 so as to cover the exposed surfaces of the wiring pattern 111a and pads 111b of the first wiring layer 111. The second insulating layer 121 is the outermost insulating layer on the upper surface side of the build-up layer 100. The material of the second insulating layer 121 can be the same as that of the first insulating layer 112, for example.

[0016] The side of the second layer 120 (that is, the second insulating layer 121) of the build-up layer 100 is a surface on which an electronic component such as a semiconductor chip is mounted, for example. At the position where the semiconductor chip is mounted, an opening 121a is formed in the second insulating layer 121. Since the second insulating layer 121 is formed using a non-photosensitive thermosetting resin, it is possible to form the opening 121a by laser processing.

[0017] [[ID=eleven]] In the opening 121a, a connection terminal 410 for connecting the pad 111b of the first wiring layer 111 and the electrode of the semiconductor chip is formed. The top 411 of the connection terminal 410 protruding from the opening 121a is wider than the pad 111b of the first wiring layer 111 and extends to a predetermined range around the opening 121a on the upper surface of the second insulating layer 121.

[0018] Since the width of the top 411 of the connection terminal 410 is larger than the width of the pad 111b of the first wiring layer 111, even if the arrangement of the wiring pattern 111a is miniaturized and the width of the pad 111b becomes smaller, a decrease in the surface area of the top 411 of the connection terminal 410 can be suppressed. And, for example, when a semiconductor chip is mounted above the connection terminal 410, the connection area between the top 411 of the connection terminal 410 and the electrode of the semiconductor chip becomes larger, and the bonding strength between the semiconductor chip and the connection terminal 410 can be improved. Note that the range in which the top 411 of the connection terminal 410 extends on the upper surface of the second insulating layer 121 will be described later.

[0019] The third layer 130 is a layer formed by laminating adjacent to the lower side of the first layer 110 and is composed of an insulating third insulating layer 131 and a conductive third wiring layer 132. The third insulating layer 131 is formed on the lower surface 112b of the first insulating layer 112 so as to cover the second wiring layer 113. The third insulating layer 131 is the outermost insulating layer on the lower surface side of the build-up layer 100. The material of the third insulating layer 131 can be the same as that of the first insulating layer 112, for example. The third wiring layer 132 is formed on the lower surface of the third insulating layer 131. The material of the third wiring layer 132 can be the same as that of the first wiring layer 111, for example. The third wiring layer 132 and the second wiring layer 113 adjacent via the third insulating layer 131 are connected by a via 133 penetrating the third insulating layer 131 as necessary.

[0020] The solder resist layer 200 is a layer that covers the second layer 120 which is the outermost layer on the upper surface side of the build-up layer 100. The solder resist layer 200 is a layer made of an insulating photosensitive resin such as an acrylic resin and a polyimide resin, and is one of the insulating layers. Note that the solder resist layer 200 may be formed using an insulating non-photosensitive resin such as an epoxy resin.

[0021] The side of the wiring board 10 on the solder resist layer 200 side is, for example, a region corresponding to the mounting surface of an electronic component such as a semiconductor chip. An opening 201 is formed in the solder resist layer 200 at a position corresponding to the mounting surface of the semiconductor chip, and the top 411 of the connection terminal 410 is exposed at the bottom surface of the opening 201. When the solder resist layer 200 is formed using a photosensitive resin, the opening 201 can be formed by exposure and development. Also, when the solder resist layer 200 is formed using a non-photosensitive resin, the opening 201 can be formed by laser processing.

[0022] The solder resist layer 300 is a layer that covers the third wiring layer 132 of the third layer 130 which is the outermost layer on the lower surface side of the build-up layer 100 and protects the wiring. The solder resist layer 300 is a layer made of an insulating photosensitive resin such as an acrylic resin and a polyimide resin, and is one of the insulating layers. Note that the solder resist layer 300 may be formed using an insulating non-photosensitive resin such as an epoxy resin.

[0023] The side of the solder resist layer 300 of the wiring board 10 is the surface that is connected to external components, devices, etc. At the position where external connection terminals for electrically connecting to external components and devices are formed, an opening 301 is formed in the solder resist layer 300, and the third wiring layer 132 of the third layer 130 of the build-up layer 100 is exposed from the opening 301. External connection terminals such as solder balls may be formed in the opening 301. Also, instead of providing solder balls, the portion of the third wiring layer 132 exposed from the opening 301 may be used as an external connection terminal. When the solder resist layer 300 is formed using a photosensitive resin, the opening 301 can be formed by exposure and development. Also, when the solder resist layer 300 is formed using a non-photosensitive resin, the opening 301 can be formed by laser processing.

[0024] Here, the range where the top 411 of the connection terminal 410 spreads on the upper surface of the second insulating layer 121 will be described with reference to FIG. 2. FIG. 2 is a plan perspective view showing an enlargement of the periphery of the top 411 of the connection terminal 410 on the upper surface of the second insulating layer 121. The second insulating layer 121 is formed on the upper surface 112a of the first insulating layer 112 and covers the exposed surfaces of the wiring pattern 111a and the pad 111b of the first wiring layer 111 exposed on the upper surface 112a of the first insulating layer 112. In the plan perspective view of FIG. 2, the exposed surfaces of the wiring pattern 111a and the pad 111b of the first wiring layer 111 covered by the second insulating layer 121 are shown. And, for example, as shown in FIG. 2, when a plurality of wiring patterns 111a are located around the pad 111b, the top 411 of the connection terminal 410 spreads to a position overlapping at least one of the plurality of wiring patterns 111a in plan view on the upper surface of the second insulating layer 121. The diameter of the pad 111b of the first wiring layer 111 is, for example, in the range of 60 μm or more and 120 μm or less, and the diameter of the top 411 of the connection terminal 410 is, for example, 80 μm or more. Also, the pitch of the plurality of wiring patterns 111a located around the pad 111b is, for example, in the range of 10 μm or more and 40 μm or less, and the pitch between the wiring pattern 111a and the pad 111b is, for example, in the range of 8 μm or more and 12 μm or less. For example, when the diameter of the pad 111b is 60 μm, the pitch of the plurality of wiring patterns 111a is 10 μm, and the diameter of the top 411 of the connection terminal 410 is 80 μm, the top 411 of the connection terminal 410 overlaps with two wiring patterns 111a sandwiching the pad 111b in plan view. Also, for example, when the diameter of the pad 111b is 60 μm, the pitch of the plurality of wiring patterns 111a is 10 μm, and the diameter of the top 411 of the connection terminal 410 is 100 μm, the top 411 of the connection terminal 410 overlaps with four wiring patterns 111a sandwiching the pad 111b in plan view. FIG. 2 shows a state where the top 411 of the connection terminal 410 overlaps with four wiring patterns 111a sandwiching the pad 111b in plan view.

[0025] In this way, by expanding the top portion 411 of the connection terminal 410 to a position overlapping at least one of the plurality of wiring patterns 111a in a plan view, the surface area of the top portion 411 of the connection terminal 410 can be increased. As a result, the connection area between the top portion 411 of the connection terminal 410 and the electrode of the semiconductor chip becomes larger, and the bonding strength between the connection terminal 410 and the semiconductor chip can be further improved.

[0026] Next, a method for manufacturing a semiconductor device having the wiring substrate 10 configured as described above will be described with reference to FIG. 3 while specifically giving examples. FIG. 3 is a flowchart showing an example of the flow of the method for manufacturing a semiconductor device according to an embodiment.

[0027] First, a support 500 serving as a base for manufacturing the wiring substrate 10 is prepared (step S101). Specifically, for example, as shown in FIG. 4, the support 500 is provided by sequentially forming a first metal layer 502 and a second metal layer 503 on the flat upper surface of a substrate 501. FIG. 4 is a diagram showing a specific example of the support 500. The substrate 501 is a prepreg in which a reinforcing material such as a woven fabric or a non-woven fabric of glass fiber, aramid fiber, etc. is impregnated with an epoxy-based insulating resin or the like. The first metal layer 502 is a metal foil made of, for example, copper and has a release layer (not shown) on its upper surface. The second metal layer 503 is a metal foil made of, for example, copper and is laminated on the first metal layer 502 via a release layer (not shown).

[0028] Note that a plurality of wiring substrate formation regions 500A are provided on the support 500, for example, in a grid pattern, and the wiring substrate 10 is formed in a region corresponding to each wiring substrate formation region 500A. That is, a plurality of wiring substrates 10 are formed using one support 500.

[0029] When the support 500 is prepared, the first wiring layer 111 is formed on the second metal layer 503 (step S102). Specifically, a plating resist layer having openings in the wiring pattern forming portion and the pad forming portion is formed on the second metal layer 503. For example, electrolytic copper plating is performed on the second metal layer 503 exposed from the openings of the plating resist layer to form an electrolytic plating layer. The plating resist layer is formed using, for example, a dry film resist, and the openings of the plating resist layer can be formed by, for example, photolithography or laser processing. Thereafter, the plating resist layer is removed with a stripping solution as shown in FIG. 5, for example, to form the first wiring layer 111 having the wiring pattern 111a and the pad 111b. FIG. 5 is a diagram showing a specific example of the first wiring layer forming process.

[0030] When the first wiring layer 111 is formed, a first insulating layer 112 covering the first wiring layer 111 is formed on the second metal layer 503 (step S103). That is, as shown in FIG. 6, for example, a first insulating layer 112 made of a heat-resistant, non-photosensitive, and thermosetting resin such as an epoxy resin, a polyimide resin, and a cyanate resin is laminated on the second metal layer 503 so as to cover the first wiring layer 111. FIG. 6 is a diagram showing a specific example of the first insulating layer forming process. The first insulating layer 112 is formed on the second metal layer 503 in an upside-down state. That is, the surface of the first insulating layer 112 in contact with the second metal layer 503 becomes the upper surface 112a, and the surface of the first insulating layer 112 located on the side opposite to the second metal layer 503 becomes the lower surface 112b.

[0031] An opening is formed at the position where the via 114 of the first insulating layer 112 is to be formed (step S104). That is, as shown in FIG. 7, for example, an opening 112c that penetrates the first insulating layer 112 and reaches the pad 111b of the first wiring layer 111 is formed by, for example, laser processing. FIG. 7 is a diagram showing a specific example of the opening forming process. The pad 111b of the first wiring layer 111 is exposed on the bottom surface of the opening 112c. The opening 112c has a tapered shape in which the width (diameter) decreases as it goes from the lower surface 112b of the first insulating layer 112 toward the pad 111b of the first wiring layer 111.

[0032] Then, a second wiring layer 113 is formed on the first insulating layer 112 in which the opening 112c is formed (step S105). The second wiring layer 113 is formed, for example, by a semi-additive method. In this case, a seed layer is formed on the inner wall surface of the opening 112c and the lower surface 112b of the first insulating layer 112, for example, by electroless copper plating. Next, a plating resist layer having an opening in the wiring pattern forming portion is formed on the seed layer. Next, electrolytic copper plating is applied, for example, on the seed layer exposed from the opening of the plating resist layer to form an electrolytic plating layer. Next, the plating resist layer is removed. After that, the seed layer exposed from the electrolytic plating layer is removed by etching, whereby the second wiring layer 113 having a desired wiring pattern is formed on the lower surface 112b of the first insulating layer 112.

[0033] At this time, for example, as shown in FIG. 8, the opening 112c of the first insulating layer 112 is filled with electrolytic copper plating to form a via 114 penetrating the first insulating layer 112, and the second wiring layer 113 and the pad 111b of the first wiring layer 111 are connected by the via 114. FIG. 8 is a diagram showing a specific example of the second wiring layer forming process. Since the opening 112c has a tapered shape in which the width (diameter) decreases as it goes from the lower surface 112b of the first insulating layer 112 toward the pad 111b of the first wiring layer 111, the via 114 has a tapered shape corresponding to the opening 112c. That is, the via 114 has a tapered shape in which the width (diameter) decreases as it goes from the second wiring layer 113 on the lower surface 112b of the first insulating layer 112 toward the pad 111b of the first wiring layer 111.

[0034] When the second wiring layer 113 is formed, the first layer 110 of the build-up layer 100 is obtained. That is, on the support 500, the first layer 110 in which the first wiring layer 111, the first insulating layer 112, and the second wiring layer 113 are formed is formed.

[0035] When the first layer 110 is formed, the support 500 is removed from the first layer 110 (step S106). Specifically, first, the upper layer above the second metal layer 503 is peeled off from the peeling layer (not shown) of the first metal layer 502, and then the second metal layer 503 in contact with the upper surface 112a of the first insulating layer 112 is removed by etching. As a result, as shown in FIG. 9, for example, the upper surface 112a of the first insulating layer 112 is exposed, and the wiring pattern 111a and the pad 111b of the first wiring layer 111 are exposed on the upper surface 112a of the first insulating layer 112. FIG. 9 is a diagram showing a specific example of the support removal process.

[0036] When the support 500 is removed, a second insulating layer 121 is formed on the upper surface 112a of the first insulating layer 112, and a third insulating layer 131 is formed on the lower surface 112b of the first insulating layer 112 (step S107). That is, as shown in FIG. 10, for example, a second insulating layer 121 made of a resin having heat resistance such as an epoxy resin, a polyimide resin, and a cyanate resin, and being non-photosensitive and thermosetting, is laminated on the upper surface 112a of the first insulating layer 112. Also, a third insulating layer 131 made of a resin having heat resistance such as an epoxy resin, a polyimide resin, and a cyanate resin, and being non-photosensitive and thermosetting, is laminated on the lower surface 112b of the first insulating layer 112. FIG. 10 is a diagram showing a specific example of the second insulating layer and third insulating layer formation process. In FIG. 10, the structure shown in FIG. 9 is shown upside down. Note that the formation of the second insulating layer 121 and the formation of the third insulating layer 131 do not necessarily have to be performed in parallel, and may be performed in any order.

[0037] Then, as shown in, for example, FIG. 11, an opening 121a is formed, for example, by laser processing at a position on the second insulating layer 121 on the side where the semiconductor chip is mounted, at a position where the connection terminal 410 with the semiconductor chip is provided (step S108). FIG. 11 is a diagram showing a specific example of the opening forming process. On the bottom surface of the opening 121a, the pad 111b of the first wiring layer 111 is exposed. The opening 121a has a tapered shape whose width (diameter) decreases as it goes from the upper surface of the second insulating layer 121 toward the pad 111b of the first wiring layer 111. On the other hand, an opening 131a is formed, for example, by laser processing at a position where the via 133 of the third insulating layer 131 is formed. On the bottom surface of the opening 131a, the second wiring layer 113 is exposed. The opening 131a has a tapered shape whose width (diameter) decreases as it goes from the lower surface of the third insulating layer 131 toward the second wiring layer 113. Note that the formation of the opening 121a and the formation of the opening 131a do not necessarily have to be performed in parallel and may be performed in any order.

[0038] Then, the connection terminal 410 is formed in the opening 121a of the second insulating layer 121, and the third wiring layer 132 is formed on the lower surface of the third insulating layer 131 (step S109). The connection terminal 410 is formed, for example, by a semi-additive method. That is, a seed layer is formed on the inner wall surface of the opening 121a and the upper surface of the second insulating layer 121, for example, by electroless copper plating. Next, a plating resist layer having an opening in the connection terminal forming portion is formed on the seed layer. Next, electrolytic copper plating is applied, for example, on the seed layer exposed from the opening of the plating resist layer to form an electrolytic plating layer. Next, the plating resist layer is removed. After that, the connection terminal 410 is formed by etching away the seed layer exposed from the electrolytic plating layer. The connection terminal 410 is connected to the pad 111b of the first wiring layer 111 at the position of the opening 121a of the second insulating layer 121, as shown in, for example, FIG. 12. FIG. 12 is a diagram showing a specific example of the connection terminal and third wiring layer forming process.

[0039] When forming the connection terminal 410, a top portion 411 having a width (diameter) larger than that of the pad 111b of the first wiring layer 111 is formed on the upper surface of the second insulating layer 121. That is, on the upper surface of the second insulating layer 121, the electrolytic copper plating is deposited in a state of spreading to a predetermined range around the opening 121a, whereby the top portion 411 having a width (diameter) larger than that of the pad 111b of the first wiring layer 111 is formed. For example, when a plurality of wiring patterns 111a are located around the pad 111b of the first wiring layer 111, the top portion 411 of the connection terminal 410 spreads to a position overlapping at least one of the plurality of wiring patterns 111a in a plan view on the upper surface of the second insulating layer 121. Thereby, the surface area of the top portion 411 of the connection terminal 410 becomes larger than the surface area of the pad 111b of the first wiring layer 111. As a result, for example, when a semiconductor chip is mounted above the connection terminal 410, the connection area between the top portion 411 of the connection terminal 410 and the electrode of the semiconductor chip becomes larger, and the bonding strength between the semiconductor chip and the connection terminal 410 can be improved.

[0040] Further, since the opening 121a has a tapered shape in which the width (diameter) decreases as it goes from the upper surface of the second insulating layer 121 toward the pad 111b of the first wiring layer 111, the portion located within the opening 121a of the connection terminal 410 has a tapered shape corresponding to the opening 121a. That is, the portion located within the opening 121a of the connection terminal 410 has a tapered shape in which the width (diameter) decreases as it goes from the top portion 411 toward the pad 111b of the first wiring layer 111. The tapered shape of the portion located within the opening 121a of the connection terminal 410 is a tapered shape opposite to the tapered shape of the via 114 connecting the second wiring layer 113 and the pad 111b of the first wiring layer 111. Thereby, even when the width (diameter) of the pad 111b of the first wiring layer 111 is relatively small, the connection terminal 410 and the via 114 can be surely connected to the pad 111b, and the miniaturization of the arrangement of the wiring patterns 111a around the pad 111b can be promoted.

[0041] On the other hand, the third wiring layer 132 is formed by a semi-additive method in the same manner as the connection terminal 410. At this time, for example, as shown in FIG. 12, the opening 131a of the third insulating layer 131 is filled with electrolytic copper plating to form a via 133 that penetrates the third insulating layer 131, and the third wiring layer 132 and the second wiring layer 113 are connected by the via 133. Note that the formation of the connection terminal 410 and the formation of the third wiring layer 132 do not necessarily have to be performed in parallel, and may be performed in any order.

[0042] By forming the connection terminal 410 and the third wiring layer 132, the build-up layer 100 composed of the first layer 110 to the third layer 130 is completed. Then, the second layer 120, which is the outermost layer on the upper surface side of the build-up layer 100, is covered by the solder resist layer 200, and the third wiring layer 132 of the third layer 130, which is the outermost layer on the lower surface side of the build-up layer 100, is covered by the solder resist layer 300 (step S110).

[0043] Then, for example, as shown in FIG. 13, an opening 201 is formed at a position corresponding to the mounting surface of the semiconductor chip in the solder resist layer 200 on the side corresponding to the mounting surface of the semiconductor chip. The top 411 of the connection terminal 410 is exposed at the bottom surface of the opening 201. On the other hand, an opening 301 is formed at a position where an external connection terminal is provided in the solder resist layer 300 on the side connected to external components, devices, etc. The third wiring layer 132 is exposed at the bottom surface of the opening 301. FIG. 13 is a diagram showing a specific example of the solder resist layer forming process.

[0044] When photosensitive resin is used as the solder resist layers 200 and 300, it is possible to form the openings 201 and 301 by exposure and development. Also, when non-photosensitive resin is used as the solder resist layers 200 and 300, it is possible to form the openings 201 and 301 by laser processing.

[0045] By the steps up to this point, an intermediate structure having the same structure as the wiring board 10 is obtained, for example, as shown in FIG. 14. Since this intermediate structure is composed of an aggregate including a plurality of wiring boards 10, cutting for cutting out the individual wiring boards 10 is performed (step S111). Specifically, at the cutting line A where the intermediate structure shown in FIG. 14 is located inside the region corresponding to each wiring board formation region 500A, the wiring board 10 is obtained by being cut by, for example, a dicing saw or a slicer. FIG. 14 is a diagram showing a specific example of the cutting process.

[0046] Then, a semiconductor chip is mounted on the second layer 120 (that is, the second insulating layer 121) side of the build-up layer 100 (step S112), and the connection terminal 410 and the electrode of the semiconductor chip are connected. FIG. 15 is a diagram showing a specific example of the semiconductor chip mounting process.

[0047] Specifically, as shown in FIG. 15, the semiconductor chip 610 is mounted above the connection terminal 410, and the electrode 611 of the semiconductor chip 610 is joined to the top 411 of the connection terminal 410 by, for example, solder 612 or the like. At this time, since the width of the top 411 of the connection terminal 410 is larger than the width of the pad 111b of the first wiring layer 111, the connection area between the top 411 of the connection terminal 410 and the electrode 611 of the semiconductor chip 610 becomes larger. As a result, the bonding strength between the connection terminal 410 and the semiconductor chip 610 can be improved. Also, at this time, since the top 411 of the connection terminal 410 protrudes above the upper surface of the second insulating layer 121, the upper surface and the side surface of the top 411 are covered by the solder 612.

[0048] Then, the joint between the electrode 611 and the top 411 of the connection terminal 410 is sealed with the underfill resin 613, and a semiconductor device in which the semiconductor chip 610 is mounted on the wiring board 10 is completed. At the joint between the electrode 611 and the top 411 of the connection terminal 410, the upper surface and the side surface of the top 411 are covered with the solder 612. Therefore, the semiconductor device can improve the bonding strength between the electrode 611 and the top 411 of the connection terminal 410 as compared with the structure in which the top 411 is embedded in the second insulating layer 121 and only the upper surface of the top 411 is covered with solder. Note that external connection terminals such as solder balls may be formed in the opening 301 of the solder resist layer 300. Also, instead of providing the solder balls, the portion of the third wiring layer 132 exposed from the opening 301 of the solder resist layer 300 may be used as an external connection terminal.

[0049] As described above, the wiring board (for example, the wiring board 10) according to the embodiment includes a first wiring layer (for example, the first wiring layer 111), a first insulating layer (for example, the first insulating layer 112), a second insulating layer (for example, the second insulating layer 121), an opening (for example, the opening 121a), and a connection terminal (for example, the connection terminal 410). The first wiring layer includes a wiring pattern (for example, the wiring pattern 111a) and pads (for example, the pads 111b). The first insulating layer covers the first wiring layer and exposes the surfaces of the wiring pattern and the pads of the first wiring layer from the upper surface (for example, the upper surface 112a). The second insulating layer is formed on the upper surface of the first insulating layer. The opening penetrates the second insulating layer to the pads of the first wiring layer. The connection terminal is formed in the opening of the second insulating layer and is connected to the pads of the first wiring layer, and one end protrudes from the opening of the second insulating layer and has a top (for example, the top 411) that is wider than the pads of the first wiring layer at one end. Thereby, according to the wiring board according to the embodiment, the bonding strength with an electronic component (for example, the semiconductor chip 610) can be improved.

[0050] Also, in the wiring board according to the embodiment, the first wiring layer may include a plurality of wiring patterns located around the pad. And the top of the connection terminal may extend to a position overlapping at least one of the plurality of wiring patterns in a plan view on the upper surface of the second insulating layer. Thereby, according to the wiring board according to the embodiment, the bonding strength with the electronic component can be further improved.

[0051] Further, the wiring board according to the embodiment may further include a second wiring layer (for example, the second wiring layer 113) and a via (for example, the via 114). The second wiring layer may be formed on the lower surface (for example, the lower surface 112b) of the first insulating layer. The via may penetrate the first insulating layer to connect the second wiring layer and the pad of the first wiring layer. Thereby, according to the wiring board according to the embodiment, the pads of the second wiring layer and the first wiring layer adjacent via the first insulating layer can be electrically connected.

[0052] Also, in the wiring board according to the embodiment, the portion of the connection terminal located within the opening of the second insulating layer may have a tapered shape in which the width decreases as it goes from the top toward the pad of the first wiring layer. The via may have a tapered shape in which the width decreases as it goes from the second wiring layer toward the pad of the first wiring layer. Thereby, according to the wiring board according to the embodiment, the miniaturization of the arrangement of the wiring patterns around the pad can be promoted.

[0053] Further, the wiring board according to the embodiment may further include a third insulating layer (for example, the third insulating layer 131), a third wiring layer (for example, the third wiring layer 132), and a via (for example, the via 133). The third insulating layer is formed on the lower surface of the first insulating layer and may cover the second wiring layer. The third wiring layer may be formed on the lower surface of the third insulating layer. The via may penetrate the third insulating layer to connect the third wiring layer and the second wiring layer. Thereby, according to the wiring board according to the embodiment, the number of layers of the build-up layer (for example, the build-up layer 100) formed by laminating the layers formed of the insulating layer and the wiring layer can be appropriately adjusted.

[0054] (Modification example) FIG. 16 is a diagram showing the configuration of the wiring board 10 according to the modified example. In FIG. 16, the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 16, a cross section of the wiring board 10 is schematically shown. The wiring board 10 shown in FIG. 16 has a laminated structure and includes build-up layers 100A and solder resist layers 200 and 300. The build-up layer 100A is further divided into a first layer 110 and a second layer 120.

[0055] In the above embodiment, the build-up layer 100A is configured such that the second layer 120 is laminated above the first layer 110 and the third layer 130 is laminated below the first layer 110. On the other hand, in the wiring board 10 according to the modified example, the build-up layer 100A does not have the third layer 130, and the number of layers of the build-up layer 100A is two. Therefore, the first insulating layer 112 of the first layer 110 is the outermost insulating layer on the lower surface side of the build-up layer 100A.

[0056] The solder resist layer 300 is a layer that covers the second wiring layer 113 of the first layer 110, which is the outermost layer on the lower surface side of the build-up layer 100A, and protects the wiring.

[0057] The side of the wiring board 10 on the solder resist layer 300 side is a surface that is connected to external components, devices, etc. At the position where an external connection terminal for electrically connecting to an external component or device is formed, an opening 301 is formed in the solder resist layer 300, and the second wiring layer 113 of the first layer 110 of the build-up layer 100A is exposed from the opening 301. External connection terminals such as solder balls may be formed in the opening 301. Alternatively, without providing solder balls, the portion of the second wiring layer 113 exposed from the opening 301 may be used as an external connection terminal.

[0058] Next, a method for manufacturing a semiconductor device having the wiring board 10 configured as described above will be described with reference to FIG. 17 while specifically giving examples. FIG. 17 is a flowchart showing an example of the flow of a method for manufacturing a semiconductor device according to a modified example. In FIG. 17, since the steps of steps S201 to S206 are the same as the steps of steps S101 to S106 in FIG. 3, detailed description thereof will be omitted.

[0059] When the first layer 110 is formed, the support 500 is removed from the first layer 110 (step S206). As a result, for example, as shown in FIG. 18, the upper surface 112a of the first insulating layer 112 is exposed, and the wiring pattern 111a and the pad 111b of the first wiring layer 111 are exposed on the upper surface 112a of the first insulating layer 112. FIG. 18 is a diagram showing a specific example of the support removal step.

[0060] When the support 500 is removed, a second insulating layer 121 is formed on the upper surface 112a of the first insulating layer 112 (step S207). That is, for example, as shown in FIG. 19, a second insulating layer 121 made of a resin having heat resistance such as an epoxy resin, a polyimide resin, and a cyanate resin, which is non-photosensitive and thermosetting, is laminated on the upper surface 112a of the first insulating layer 112. FIG. 19 is a diagram showing a specific example of the second insulating layer formation step. In FIG. 19, the structure shown in FIG. 18 is shown upside down.

[0061] Then, for example, as shown in FIG. 20, an opening 121a is formed, for example, by laser processing at a position on the second insulating layer 121 on the side where the semiconductor chip is mounted, at a position where a connection terminal 410 with the semiconductor chip is provided (step S208). FIG. 20 is a diagram showing a specific example of the opening formation step. The pad 111b of the first wiring layer 111 is exposed on the bottom surface of the opening 121a. The opening 121a has a tapered shape in which the width (diameter) decreases as it goes from the upper surface of the second insulating layer 121 toward the pad 111b of the first wiring layer 111.

[0062] Then, a connection terminal 410 is formed in the opening 121a of the second insulating layer 121 (step S209). The connection terminal 410 is formed, for example, by a semi-additive method. That is, a seed layer is formed on the inner wall surface of the opening 121a and the upper surface of the second insulating layer 121, for example, by electroless copper plating. Next, a plating resist layer having an opening in the connection terminal forming portion is formed on the seed layer. Next, electrolytic copper plating is applied, for example, on the seed layer exposed from the opening of the plating resist layer to form an electrolytic plating layer. Next, the plating resist layer is removed. After that, the connection terminal 410 is formed by etching away the seed layer exposed from the electrolytic plating layer. The connection terminal 410 is connected to the pad 111b of the first wiring layer 111 at the position of the opening 121a of the second insulating layer 121, for example, as shown in FIG. 21. FIG. 21 is a diagram showing a specific example of the connection terminal forming process.

[0063] When forming the connection terminal 410, a top portion 411 having a width (diameter) larger than that of the pad 111b of the first wiring layer 111 is formed on the upper surface of the second insulating layer 121. That is, on the upper surface of the second insulating layer 121, the electrolytic copper plating is deposited in a state of spreading to a predetermined range around the opening 121a, whereby the top portion 411 having a width (diameter) larger than that of the pad 111b of the first wiring layer 111 is formed. For example, when a plurality of wiring patterns 111a are located around the pad 111b of the first wiring layer 111, the top portion 411 of the connection terminal 410 spreads to a position overlapping at least one of the plurality of wiring patterns 111a in a plan view on the upper surface of the second insulating layer 121. As a result, the surface area of the top portion 411 of the connection terminal 410 becomes larger than the surface area of the pad 111b of the first wiring layer 111. As a result, for example, when a semiconductor chip is mounted above the connection terminal 410, the connection area between the top portion 411 of the connection terminal 410 and the electrode of the semiconductor chip becomes larger, and the bonding strength between the connection terminal 410 and the semiconductor chip can be improved.

[0064] In addition, since the opening 121a has a tapered shape in which the width (diameter) decreases as it extends from the upper surface of the second insulating layer 121 toward the pad 111b of the first wiring layer 111, the portion of the connection terminal 410 located within the opening 121a has a tapered shape corresponding to the opening 121a. That is, the portion of the connection terminal 410 located within the opening 121a has a tapered shape in which the width (diameter) decreases as it extends from the top portion 411 toward the pad 111b of the first wiring layer 111. The tapered shape of the portion of the connection terminal 410 located within the opening 121a is opposite to the tapered shape of the via 114 that connects the second wiring layer 113 and the pad 111b of the first wiring layer 111. Thereby, even when the width (diameter) of the pad 111b of the first wiring layer 111 is relatively small, the connection terminal 410 and the via 114 can be surely connected to the pad 111b, and the miniaturization of the arrangement of the wiring pattern 111a around the pad 111b can be promoted.

[0065] By forming the connection terminal 410, the build-up layer 100A composed of the first layer 110 and the second layer 120 is completed. Then, the second layer 120, which is the outermost layer on the upper surface side of the build-up layer 100A, is covered with the solder resist layer 200, and the second wiring layer 113 of the first layer 110, which is the outermost layer on the lower surface side of the build-up layer 100, is covered with the solder resist layer 300 (step S210).

[0066] Then, as shown in, for example, FIG. 22, an opening 201 is formed in the solder resist layer 200 on the side corresponding to the mounting surface of the semiconductor chip at a position corresponding to the mounting surface of the semiconductor chip. The top portion 411 of the connection terminal 410 is exposed on the bottom surface of the opening 201. On the other hand, an opening 301 is formed in the solder resist layer 300 on the side connected to an external component, device, or the like at a position where an external connection terminal is provided. The second wiring layer 113 is exposed on the bottom surface of the opening 301. FIG. 22 is a diagram showing a specific example of the solder resist layer forming process.

[0067] When a photosensitive resin is used as the solder resist layers 200 and 300, it is possible to form the openings 201 and 301 by exposure and development. Also, when a non-photosensitive resin is used as the solder resist layers 200 and 300, it is possible to form the openings 201 and 301 by laser processing.

[0068] Through the steps up to this point, an intermediate structure having the same structure as the wiring substrate 10 is obtained, for example, as shown in FIG. 23. Since this intermediate structure is composed of an aggregate including a plurality of wiring substrates 10, cutting for cutting out the individual wiring substrates 10 is performed (step S211). Specifically, at the cutting line A where the intermediate structure shown in FIG. 23 is located inside the region corresponding to each wiring substrate forming region 500A, the wiring substrate 10 is obtained by being cut, for example, by a dicing saw or a slicer. FIG. 23 is a diagram showing a specific example of the cutting process.

[0069] Then, a semiconductor chip is mounted on the second layer 120 (that is, the second insulating layer 121) side of the build-up layer 100 (step S212), and the connection terminal 410 and the electrode of the semiconductor chip are connected. FIG. 24 is a diagram showing a specific example of the semiconductor chip mounting process.

[0070] Specifically, as shown in FIG. 24, the semiconductor chip 610 is mounted above the connection terminal 410, and the electrode 611 of the semiconductor chip 610 is joined to the top 411 of the connection terminal 410 by, for example, solder 612 or the like. At this time, since the width of the top 411 of the connection terminal 410 is larger than the width of the pad 111b of the first wiring layer 111, the connection area between the top 411 of the connection terminal 410 and the electrode 611 of the semiconductor chip 610 becomes large. As a result, the bonding strength between the connection terminal 410 and the semiconductor chip 610 can be improved. Also, at this time, since the top 411 of the connection terminal 410 protrudes above the upper surface of the second insulating layer 121, the upper surface and the side surface of the top 411 are covered by the solder 612.

[0071] Then, the joint portion between the electrode 611 and the top 411 of the connection terminal 410 is sealed with an underfill resin 613, and a semiconductor device in which the semiconductor chip 610 is mounted on the wiring board 10 is completed. At the joint portion between the electrode 611 and the top 411 of the connection terminal 410, the upper surface and the side surface of the top 411 are covered with solder 612. Therefore, the semiconductor device can improve the bonding strength between the electrode 611 and the top 411 of the connection terminal 410 as compared with the structure in which the top 411 is embedded in the second insulating layer 121 and only the upper surface of the top 411 is covered with solder. Note that external connection terminals such as solder balls may be formed in the opening 301 of the solder resist layer 300. Alternatively, the portion of the third wiring layer 132 exposed from the opening 301 of the solder resist layer 300 may be used as an external connection terminal without providing solder balls.

[0072] As described above, in the wiring board according to the modification, the connection terminal is formed in the opening of the second insulating layer and connected to the pad of the first wiring layer, and one end protrudes from the opening of the second insulating layer and has a top (for example, the top 411) that is wider than the pad of the first wiring layer at one end. Thus, according to the wiring board according to the modification, the bonding strength with an electronic component (for example, the semiconductor chip 610) can be improved. Further, according to the wiring board according to the modification, since the number of layers of the build-up layer (for example, the build-up layer 100A) can be reduced as compared with the wiring board according to the embodiment, the size in the thickness direction can be reduced.

[0073] (Other Modifications) In the above embodiment and the above modification, the number of layers of the build-up layers 100 and 100A is assumed to be 2 or 3, but a build-up layer may be configured by laminating 4 or more layers. In this case, a layer having the same structure as the third layer 130 may be sequentially laminated below the first layer 110 of the build-up layers 100 and 100A.

Description of Reference Numerals

[0074] 10 Wiring board 100, 100A Build-up layer 111 First wiring layer 111a Wiring pattern 111b Pad 112 First insulating layer 112a Upper surface 112b Lower surface 112c Opening 113 Second wiring layer 114 Via 121 Second insulating layer 121a Opening 131 Third insulating layer 131a Opening 132 Third wiring layer 133 Via 200, 300 Solder resist layer 201, 301 Opening 410 Connection terminal 411 Top 500 Support 500A Wiring board formation region 501 Substrate 502 First metal layer 503 Second metal layer 610 Semiconductor chip 611 Electrode 612 Solder 613 Underfill resin

Claims

1. a first wiring layer including a wiring pattern and pads; a first insulating layer covering the first wiring layer and exposing the surfaces of the wiring pattern and pads of the first wiring layer from above; a second insulating layer formed on the upper surface of the first insulating layer; an opening penetrating the second insulating layer to the pads of the first wiring layer; a connection terminal formed in the opening of the second insulating layer and connected to the pads of the first wiring layer, having one end protruding from the opening of the second insulating layer and having a top portion wider than the pads of the first wiring layer at the one end; a solder resist layer formed on the upper surface of the second insulating layer and having; the solder resist layer has an opening formed at a position corresponding to the mounting surface of an electronic component on the second insulating layer, exposing the mounting surface; a plurality of the connection terminals are located in the opening of the solder resist layer; each of the tops of the plurality of connection terminals; has an upper surface and a side surface exposed in the opening of the solder resist layer; the first wiring layer; includes a plurality of wiring patterns located around the pads; the plurality of wiring patterns; include two or more wiring patterns sandwiching the pads; each of the tops of the plurality of connection terminals; extends to a position overlapping with two or more wiring patterns sandwiching the pads in a plan view on the upper surface of the second insulating layer A wiring board characterized by that.

2. a second wiring layer formed on the lower surface of the first insulating layer; a via penetrating the first insulating layer and connecting the second wiring layer and the pads of the first wiring layer The wiring board according to claim 1, further comprising.

3. The portion of the connection terminal located within the opening of the second insulating layer; has a tapered shape in which the width becomes smaller as it goes from the top portion toward the pads of the first wiring layer; the via; has a tapered shape in which the width becomes smaller as it goes from the second wiring layer toward the pads of the first wiring layer The wiring board according to claim 2, characterized by that.

4. a third insulating layer formed on the lower surface of the first insulating layer and covering the second wiring layer; a third wiring layer formed on the lower surface of the third insulating layer; a via penetrating the third insulating layer and connecting the third wiring layer and the second wiring layer The wiring board according to claim 2, further comprising.

5. a step of forming a first wiring layer including a wiring pattern and pads on a support; A step of forming a first insulating layer covering the first wiring layer on the support; A step of removing the support to expose the wiring pattern of the first wiring layer and the pad from the upper surface of the first insulating layer; A step of forming a second insulating layer on the upper surface of the first insulating layer; A step of forming an opening penetrating to the pad of the first wiring layer in the second insulating layer; A step of forming a connection terminal that is connected to the pad of the first wiring layer and has one end protruding from the opening of the second insulating layer in the opening of the second insulating layer; A step of forming a solder resist layer on the upper surface of the second insulating layer and having, The step of forming the connection terminal is forming the connection terminal having a top portion wider than the pad of the first wiring layer at one end protruding from the opening of the second insulating layer, The step of forming the solder resist layer is forming an opening in the solder resist layer, the opening being formed at a position corresponding to the mounting surface of the electronic component on the second insulating layer to expose the mounting surface, a plurality of the connection terminals are located in the opening of the solder resist layer, each of the tops of the plurality of connection terminals has an upper surface and a side surface exposed in the opening of the solder resist layer, The first wiring layer includes a plurality of wiring patterns located around the pad, The plurality of wiring patterns include two or more wiring patterns sandwiching the pad, each of the tops of the plurality of connection terminals extends to a position overlapping with two or more wiring patterns sandwiching the pad in a plan view on the upper surface of the second insulating layer A method for manufacturing a wiring board, characterized in that.

6. Before the step of removing the support, a step of forming an opening penetrating to the pad in the first insulating layer; A step of forming a second wiring layer on the lower surface of the first insulating layer in which the opening is formed further having, In the step of forming the second wiring layer, a via penetrating the first insulating layer is formed in the opening of the first insulating layer, and the second wiring layer and the pad are connected by the via The method for manufacturing a wiring board according to claim 5, characterized in that.

7. A step of forming a third insulating layer covering the second wiring layer on the lower surface of the first insulating layer; A step of forming an opening penetrating to the second wiring layer in the third insulating layer; A step of forming a third wiring layer on the lower surface of the third insulating layer further having, The step of forming the second insulating layer is performed in parallel with the step of forming the third insulating layer, The step of forming an opening in the second insulating layer is performed in parallel with the step of forming an opening in the third insulating layer, The step of forming the connection terminal is performed in parallel with the step of forming the third wiring layer, In the step of forming the third wiring layer, a via penetrating the third insulating layer is formed in the opening of the third insulating layer, and the third wiring layer and the second wiring layer are connected by the via A method for manufacturing a wiring board according to claim 6, characterized in that.

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