Display device

Abstract

To provide a display device suitable for enlargement.SOLUTION: A display device includes first to third wires, a first transistor, first to third conductive layers, and a first pixel electrode. The first wire extends in a first direction and intersects with the second and third wires. The second and third wires extend in a second direction intersecting with the first direction. A gate of the first transistor is electrically connected to the first wire. One of a source and a drain of the first transistor is electrically connected to the second wire through the first to third conductive layers. The second conductive layer includes a region overlapping with the third wire. The first conductive layer, the third conductive layer, and the first pixel electrode include the same material. The first wire and the second conductive layer include the same material. A selection signal is supplied to the first wire. Different signals are supplied to the second and third wires.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] One aspect of the present invention relates to a display device and a method for manufacturing the same.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the present invention disclosed in this specification etc. includes semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, or manufacturing methods thereof, as an example.

[0003] Note that in this specification etc., the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Transistors, semiconductor circuits, arithmetic units, storage devices, etc. are one aspect of semiconductor devices. In addition, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices may have semiconductor devices.

Background Art

[0004] In recent years, high-resolution display devices have been demanded. For example, in a household television device (also referred to as a TV or a television receiver), those with a resolution of full high vision (1920×1080 pixels) are mainstream, but the development of high-resolution display devices such as 4K (3840×2160 pixels) and 8K (7680×4320 pixels) is underway.

[0005] Also, among display devices, a liquid crystal display device is known. A transmissive liquid crystal display device controls the amount of light transmitted from a backlight by utilizing the optical modulation action of liquid crystal to express contrast and perform image display.

[0006] Also, as a type of field effect transistor, a thin film transistor in which a channel formation region is formed using a semiconductor film formed on a substrate having an insulating surface is known. Patent Document 1 discloses a technique of using amorphous silicon for a semiconductor film used in a channel formation region of a thin film transistor. For example, in the case of a liquid crystal display device, the thin film transistor is used as a switching transistor for each pixel.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] In the case of a display device such as a television device or a monitor device, the higher the resolution or the larger the screen size, the more remarkable the increase in the load of transistors and the like included in the display device becomes. Due to this, especially when the field effect mobility of the transistor is low, it may be difficult to operate at a high driving frequency.

[0009] One aspect of the present invention is to provide a high-resolution display device and a method for manufacturing the same as one of the problems. Or, to provide a display device suitable for enlargement and a method for manufacturing the same as one of the problems. Or, to provide a low-cost display device and a method for manufacturing the same as one of the problems. Or, to provide a display device with high productivity and a method for manufacturing the same as one of the problems. Or, to provide a highly reliable display device and a method for manufacturing the same as one of the problems. ​​​​​​​​​One of the problems is to provide a display device using amorphous silicon or the like and a method for manufacturing the same. Or, one of the problems is to provide a display device using a metal oxide or the like and a method for manufacturing the same. Or, one of the problems is to provide a novel display device and a method for manufacturing the same. Note that the description of these problems does not prevent the existence of other problems. Note that one

[0010] aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is a display device including a first wiring, a second wiring, and a third wiring, a first transistor, a first conductive layer, a second conductive layer, and a third conductive layer, and a first pixel electrode, wherein the first wiring extends in a first direction and intersects the second wiring and the third wiring, the second wiring and the third wiring extend in a second direction intersecting the first direction, the gate of the first transistor is electrically connected to the first wiring, one of the source or drain of the first transistor is electrically connected to the second wiring via the first conductive layer, the second conductive layer, and the third conductive layer, the second conductive layer has a region overlapping the third wiring, the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material, the first wiring and the second conductive layer contain the same material, and the first wiring is supplied with a selection signal, and the second wiring and the third wiring are supplied with different signals.

[0012] ​​​​​​​​​​Alternatively, in the above aspect, the second wiring and the third wiring may be electrically connected to the first source driver and the second source driver.

[0013] Alternatively, in the above aspect, the fourth wiring, the fifth wiring, and the sixth wiring, the second transistor and the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer, and the second pixel electrode, wherein the fourth wiring extends in a first direction and intersects the second wiring, the third wiring, the fifth wiring and the sixth wiring, the fifth wiring and the sixth wiring each extend in a second direction intersecting the first direction, the gate of the second transistor is electrically connected to the fourth wiring, one of the source or drain of the second transistor is electrically connected to the fifth wiring via the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer, the fifth conductive layer has a region overlapping the sixth wiring, the fourth conductive layer, the sixth conductive layer, and the second pixel electrode contain the same material, the fourth wiring and the fifth conductive layer contain the same material, the fourth wiring is supplied with the same selection signal as the first wiring, and the second wiring, the third wiring, the fifth wiring, and the sixth wiring may each be supplied with different signals.

[0014]

[0015] Alternatively, in the above aspect, the fifth wiring and the sixth wiring may be electrically connected to the first source driver and the second source driver.

[0015] Alternatively, in the above aspect, the first transistor has a first semiconductor layer, the second transistor has a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer may each have a portion located between the third wiring and the sixth wiring.

[0016] ​ Alternatively, in the above aspect, the first semiconductor layer and the second semiconductor layer may each contain amorphous silicon.

[0017] Alternatively, in the above aspect, the first semiconductor layer and the second semiconductor layer may each contain microcrystalline silicon or polycrystalline silicon.

[0018] Alternatively, in the above aspect, the first semiconductor layer and the second semiconductor layer may each contain a metal oxide.

[0019] Alternatively, in the above aspect, the metal oxide may contain indium, zinc, and M (where M is aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium).

[0020] Alternatively, one aspect of the present invention is a method for manufacturing a display device, the manufacturing method including: a step of forming a gate line and a first conductive layer; a step of forming a first insulating layer; a step of forming a semiconductor layer; a step of forming a second conductive layer and a third conductive layer having regions in contact with the semiconductor layer, the second conductive layer including a first source line and a second source line; a step of forming a second insulating layer; a step of forming a first opening reaching the second conductive layer, a second opening reaching the third conductive layer, and a third opening reaching the second source line in the second insulating layer, and forming a fourth opening and a fifth opening reaching the first conductive layer in the first insulating layer and the second insulating layer so as to sandwich the first source line; a step of forming a pixel electrode so as to be electrically connected to the second conductive layer through the first opening, electrically connected to the third conductive layer through the second opening, and Form a fourth conductive layer so as to be electrically connected to the first conductive layer through, and form a third opening To be electrically connected to the second source line through, and electrically connected to the first conductive layer through a fifth opening Forming a fifth conductive layer so as to be connected thereto, and a method of manufacturing a display device having the step of 。

Advantages of the Invention

[0021] According to one aspect of the present invention, a high-resolution display device and a method of manufacturing the same can be provided 。Or, a display device suitable for increasing the size and a method of manufacturing the same can be provided. Or A low-cost display device and a method of manufacturing the same can be provided. Or, a highly productive Display device and a method of manufacturing the same can be provided. Or, a highly reliable display device and A method of manufacturing the same can be provided. Or, a display device using amorphous silicon or the like And a method of manufacturing the same can be provided. Or, a display device using a metal oxide or the like and A method of manufacturing the same can be provided. Or, a novel display device and a method of manufacturing the same Can be provided.

[0022] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention Does not necessarily have to have all of these effects. Note that other effects can be Extracted from the description of the specification, drawings, claims, etc.

Brief Description of the Drawings

[0023]

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Mode for Carrying Out the Invention

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof is omitted. Also, similarly ​When referring to the function, the hatching pattern may be the same and may not be particularly labeled.

[0026] In addition, in each figure described in this specification, the size of each component, the thickness of the layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0027] In addition, ordinal numbers such as "first" and "second" in this specification are attached to avoid confusion of components and are not numerically limiting.

[0028] A transistor is a type of semiconductor device and can realize operations such as amplification of current or voltage and switching operations for controlling conduction or non-conduction. The transistors in this specification include IGFET (Insulated Gate Field Effect Transistor) and thin film transistors (TFT: Thin Film Transistor). GFET(Insulated Gate Field Effect Transis tor) and thin film transistors (TFT: Thin Film Transistor)

[0029] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are adopted or when the direction of current changes in circuit operation. For this reason, in this specification, the terms "source" and "drain" can be used interchangeably.

[0030] In addition, in this specification and the like, the terms "source", "drain", and "gate" can sometimes be rephrased as "source electrode", "drain electrode", and "gate electrode" respectively.

[0031] In addition, in this specification and the like, "electrically connected" includes "having some electrical effect". includes the case where it is connected via "". Here, "something having some electrical effect" is not particularly limited as long as it enables the exchange of electrical signals between connection targets. For example, "something having some electrical effect" includes electrodes, wiring, transistors and other switching elements such as, resistor elements, coils, capacitor elements, and elements having various other functions. is included.

[0032] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting ) an image or the like on a display surface. Therefore, the display panel is one aspect of an output device.

[0033] Also, in this specification and the like, a substrate of a display panel having, for example, an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package e) or the like attached thereto, or a substrate having an IC mounted thereon by a COG (Chip On Glass ) method or the like may be referred to as a display panel module, a display module , or simply a display panel or the like.

[0034] Also, in this specification and the like, a touch sensor has a function of detecting that a detection object such as a finger or a stylus touches, presses on, or approaches. It may also have a function of detecting the position information thereof. Therefore, the touch sensor is one aspect of an input device. For example the touch sensor can be configured to have one or more sensor elements. For example, the touch sensor can be configured to have one or more sensor elements.

[0035] Also, in this specification and the like, a substrate having a touch sensor may be referred to as a touch sensor panel, or simply a touch sensor or the like. Also, in this specification and the like, on the substrate of the touch sensor panel For example, those with FPC or TCP connectors attached, or those with CO The IC mounted by the G method is called a touch sensor panel module or touch sensor It may be called a module, a sensor module, or simply a touch sensor.

[0036] In this specification, a touch panel, which is one aspect of a display device, is a device that displays an image or the like on a display surface. The function of the display is to display (output) the information when a finger, stylus, or other object touches, presses, or The touch panel has a function as a touch sensor that detects approaching objects. A panel is one aspect of an input / output device.

[0037] The touch panel is, for example, a display panel (or display device) with a touch sensor, a touch sensor It can also be called a functional display panel (or display device).

[0038] The touch panel may also have a configuration including a display panel and a touch sensor panel. Alternatively, the display panel may be configured to have a touch sensor function inside or on its surface. It can also be done as follows.

[0039] In this specification, a connector such as an FPC or TCP is attached to the substrate of the touch panel. or a board with an IC mounted on it using the COG method, It may be called a touch panel module, display module, or simply a touch panel. .

[0040] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0041] One embodiment of the present invention is a display device having a display portion in which a plurality of pixels are arranged in a matrix. . The display section is provided with a plurality of wirings (also referred to as gate lines or scanning lines) to which selection signals are supplied, and wirings (also referred to as source lines, signal lines, data lines, etc.) to which signals (also referred to as video signals, etc.) to be written into the pixels are supplied. Here, the gate lines are provided parallel to each other, and the source lines are provided parallel to each other, and the gate lines and the source lines intersect each other. . . .

[0042] One pixel has at least one transistor and one display element. The display element has a conductive layer that functions as a pixel electrode, and the conductive layer is electrically connected to one of the source or drain of the transistor. Also, for the transistor, the gate is electrically connected to the gate line, and the other of the source or drain is electrically connected to the source line. . . .

[0043] Here, the extending direction of the gate line is referred to as the row direction or the first direction, and the extending direction of the source line is referred to as the column direction or the second direction. .

[0044] Here, it is preferable that the same selection signal is supplied to three or more adjacent gate lines. That is, it is preferable that the selection periods of these gate lines are the same. In particular, it is preferable to group four gate lines because the configuration of the drive circuit can be simplified. . .

[0045] When the same selection signal is supplied to four gate lines, four adjacent pixels in the column direction are selected simultaneously. Therefore, these four pixels are configured to be connected to different source lines. That is, a configuration is adopted in which four source lines are arranged for each column. . .

[0046] By adopting a configuration in which four source lines are arranged for each column, one horizontal period can be made longer than before. It is possible. For example, when the same selection signal is supplied to four gate lines, the length of one horizontal period can be quadrupled. Furthermore, since the parasitic capacitance between source lines can be reduced, the load on the source lines can be reduced. As a result, even in a display device with an extremely high resolution such as 4K or 8K, it is possible to operate using a transistor with low field-effect mobility. Of course, even in a display device with a resolution exceeding 8K (e.g., 10K, 12K, or 1 6K, etc.), by adopting the configuration of one aspect of the present invention, it becomes possible to operate. In addition, the above-described configuration can also be applied to a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal.

[0047] When adopting a configuration in which four source lines are arranged for each column, two source lines can be arranged on the left side of the pixel and two source lines can be arranged on the right side of the pixel. That is, source lines can be arranged on the left outer side, left inner side, right inner side, and right outer side of the pixel, respectively. In this configuration, the source of the transistor electrically connected to the left outer source line of the pixel intersects the left inner source line of the pixel. Also, in this configuration, the source of the transistor electrically connected to the right outer source line of the pixel intersects the right inner source line of the pixel. In one aspect of the present invention, using a conductive layer that can be formed in the same process as the pixel electrode and a conductive layer that can be formed in the same process as the gate of the transistor, short-circuiting between the source of the transistor electrically connected to the left outer source line of the pixel and the left inner source line of the pixel is suppressed. Moreover, in one aspect of the present invention, using a conductive layer that can be formed in the same process as the pixel electrode and a transistor... A conductive layer that can be formed in the same process as the gate of the transistor is used to connect the source of the transistor electrically connected to the source line on the right outer side of the pixel and the source line on the right inner side of the pixel. Short-circuiting is suppressed. Thus, even when four source lines are arranged for each column, the number of processes, specifically the number of photolithography processes, can be suppressed from increasing compared to the case where one or two source lines are arranged for each column. That is, the increase in the number of photomasks can be suppressed. As a result, the increase in the manufacturing cost of the display device can be suppressed. Specifically, the increase in the number of processes, specifically the number of photolithography processes, can be suppressed. That is, the increase in the number of photomasks can be suppressed. As a result, the increase in the manufacturing cost of the display device can be suppressed. That is, the increase in the number of photomasks can be suppressed. As a result, the increase in the manufacturing cost of the display device can be suppressed.

[0048] Hereinafter, a more specific example of the display device will be described with reference to the drawings.

[0049] [Configuration Example of Display Device] FIG. 1 shows a block diagram of a display device 10 according to an aspect of the present invention. The display device 10 includes a display unit 17, a gate driver 12a, a gate driver 12b, a source driver 13a, and a source driver 13b. Pixels 11 are arranged in a matrix in the display unit 17. In this specification, etc., the pixel 11 at the i-th row and j-th column is described as pixel 11(i,j). In FIG. 1, an example is shown in which the gate driver 12a and the gate driver 12b are provided at positions facing each other with the display unit 17 interposed therebetween. A plurality of wirings GL0 are connected to the gate driver 12a and the gate driver 12b. In FIG. 1, the wiring GL0(i) is shown. The wiring GL0(i) is electrically connected to four wirings (wiring GL(i), wiring GL(i + 1), wiring GL(i + 2), wiring GL(i + 3)). Therefore, these four wirings In this specification, etc., the pixel 11 at the i-th row and j-th column is described as pixel 11(i,j). is described.

[0050] In FIG. 1, an example is shown in which the gate driver 12a and the gate driver 12b are provided at positions facing each other with the display unit 17 interposed therebetween. The gate driver 12a and the gate driver 12b are provided with a plurality of wirings GL0 connected thereto. In FIG. 1, the wiring GL0(i) is shown. The wiring GL0(i) is electrically connected to four wirings (wiring GL(i), wiring GL(i + 1), wiring GL(i + 2), wiring GL(i + 3)). The wiring GL0(i) is electrically connected to four wirings (wiring GL(i), wiring GL(i + 1), wiring GL(i + 2), wiring GL(i + 3)). Therefore, these four wirings The same selection signal is applied to the lines. Note that the wiring GL0 and the wiring GL function as gate lines. have the function of

[0051] The gate drivers 12a and 12b have the function of supplying the same selection signal to the same wiring GL0. As a result, the charging and discharging time of the wiring GL0 can be shortened compared to the case where the display device 10 has only one gate driver. Thereby, even in a display device with an extremely high resolution such as 4K or 8K, it becomes possible to operate using a transistor with low field-effect mobility. Also, it is possible to apply the display device according to one aspect of the present invention to a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal. have the function of can be made shorter than when a transistor with low field-effect mobility can be used even in a display device with an extremely high resolution such as 4K or 8K. Also, it is possible to apply the display device according to one aspect of the present invention to a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal. a transistor with low field-effect mobility can be used even in a display device with an extremely high resolution such as 4K or 8K. Also, it is possible to apply the display device according to one aspect of the present invention to a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal. [[ID=]15] a transistor with low field-effect mobility can be used even in a display device with an extremely high resolution such as 4K or 8K. Also, it is possible to apply the display device according to one aspect of the present invention to a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal. a transistor with low field-effect mobility can be used even in a display device with an extremely high resolution such as 4K or 8K. Also, it is possible to apply the display device according to one aspect of the present invention to a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal.

[0052] In FIG. 1, an example is shown in which the source driver 13a and the source driver 13b are provided with the display unit 17 therebetween. A plurality of wirings are connected to the source driver 13a and the source driver 13b. Four wirings are provided for one pixel column. In FIG. 1, four wirings (wiring SL1(j), wiring SL2(j), wiring SL3(j), wiring SL4(j)) corresponding to the j-th pixel column and four wirings (wiring SL1(j + 1), wiring SL2(j + 1), wiring SL3(j + 1), wiring SL4(j + 1)) corresponding to the (j + 1)-th pixel column are shown. Different signals can be supplied to different wirings. For example, different signals can be supplied to the wiring SL1(j), wiring SL2(j), wiring SL3(j), and wiring SL4(j), respectively. Note that the wiring SL (wiring SL1, wiring SL2, wiring SL3, wiring SL4) functions as a source line. 1), wiring SL2(j + 1), wiring SL3(j + 1), wiring SL4(j + 1)) corresponding to the (j + 1)-th pixel column are shown. Different signals can be supplied to different wirings. For example, different signals can be supplied to the wiring SL1(j), wiring SL2(j), wiring SL3(j), and wiring SL4(j), respectively. Note that the wiring SL (wiring SL1, wiring SL2, wiring SL3, wiring SL4) functions as a source line. SL (wiring SL1, wiring SL2, wiring SL3, wiring SL4) functions as a source line. SL3, wiring SL4) functions as a source line. SL3, wiring SL4) functions as a source line.

[0053] The source drivers 13a and 13b have a function of supplying the same signal to the same wiring SL. Thereby, when the display device 10 has only one source driver, the charging and discharging time of the wiring SL can be shortened. Thereby, even in a display device with extremely high resolution such as 4K or 8K resolution, it is possible to operate using a transistor with low field-effect mobility. Also, in a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal, the display device according to one aspect of the present invention can be applied.

[0054] One pixel 11 is a pixel corresponding to one color. Therefore, when performing color display using the mixed color of light presented by a plurality of pixels, the pixel 11 can also be called a sub-pixel.

[0055] Also, it is preferable that a plurality of pixels arranged in a row in the column direction are pixels that exhibit the same color. When using a liquid crystal element as the display element, the pixels arranged in a row in the column direction are provided with a coloring layer that transmits light of the same color when overlapped with the liquid crystal element.

[0056] Here, when applying a transistor with low field-effect mobility, the display unit of the display device can be divided into a plurality of display areas and driven. However, in the case of the above method, due to variations in the characteristics of the drive circuit or the like, the boundary portion of the divided display area may be visually recognized, resulting in a decrease in visibility. Also, image processing or the like for pre-dividing the input image data is required, and a high-speed and large-scale image processing device is required.

[0057] On the one hand, the display device according to one aspect of the present invention can be driven without dividing the display unit into a plurality of display areas even when using transistors with relatively low field-effect mobility. Even in such a case, it is possible to drive without dividing the display unit into a plurality of display areas. .

[0058] A protection circuit may be provided in the display device 10. FIG. 2 shows the display device 10 having the configuration shown in FIG. 1, in which protection circuits 18a, 18b, 19a, and 19b are provided. FIG. 2 shows a block diagram of the display device 10 in this case. The protection circuits 18a and 18b are electrically connected to the wiring GL0. The protection circuits 19a and 19b are electrically connected to the wirings SL1, SL2, SL3, and SL4.

[0059] The protection circuit 18a can be provided on the side of the gate driver 12a, and the protection circuit 18b can be provided on the side of the gate driver 12b. That is, the protection circuit 18a and the protection circuit 18b can be provided at positions facing each other with the display unit 17 interposed therebetween. Also, the protection circuit 19 a can be provided on the side of the source driver 13a, and the protection circuit 19b can be provided on the side of the source driver 13b. That is, the protection circuit 19a and the protection circuit 19b can be provided at positions facing each other with the display unit 17 interposed therebetween.

[0060] By providing a protection circuit in the display device 10, the pixels 11 can be protected from noise, surges, electrostatic discharges, etc. Thereby, the reliability of the display device 10 can be improved.

[0061] In FIG. 1, four source lines are provided per pixel column, but one aspect of the present invention is not limited to this. In FIG. 3, three source lines (wirings SL1, SL2, SL) are provided per pixel column. 3) shows the provided configuration. In the display device 10 of this configuration, the wiring GL0(i) is electrically connected to three wirings (wiring GL(i), wiring GL(i + 1), wiring GL(i + 2)), and the same selection signal is applied to these three wirings. In one aspect of the present invention, five or more source lines may be provided per pixel column.

[0062] In FIG. 1, an example is shown in which two gate drivers and two source drivers are arranged respectively, but it may be configured to arrange only one or both of the gate driver and the source driver.

[0063] In FIG. 4, an example is shown in which the source driver 13a and the source driver 13b are arranged one by one per pixel column. That is, the same number of source drivers 13a as the pixel columns are provided along one side of the rectangular display portion 17, and the same number of source drivers 13b as the pixel columns are provided at positions facing each other with the source driver 13a and the display portion 17 interposed therebetween. Also, in FIG. 4, an example is shown in which the gate driver 12a and the gate driver 12b are arranged one by one per one wiring GL0. That is, the number of gate drivers 12a obtained by dividing the pixel rows by 4 is provided along one side of the rectangular display portion 17, and the number of gate drivers 12b obtained by dividing the pixel rows by 4 is provided at positions facing each other with the gate driver 12a and the display portion 17 interposed therebetween. By adopting such a configuration, display unevenness due to potential drop caused by wiring resistance can be reduced even in a large display device.

[0064] A reference voltage generation circuit can be provided in the display device 10. The reference voltage generation circuit is a source ​​​​​​​​​​​​​It has a function of generating a reference voltage of a signal supplied by a driver. As a reference voltage generation circuit , for example, it can be a gamma reference generation circuit. FIG. 5 shows the table of the configuration shown in FIG. 4 In the display device 10 shown, a reference voltage generation circuit 16a having a function of supplying a reference voltage to the source driver 13a and a reference voltage generation circuit 16b having a function of supplying a reference voltage to the source driver 13b are provided. By configuring the display device 10 as shown in FIG. 5 , the accuracy of the voltage of the signal generated from each source driver 13a and the accuracy of the voltage of the signal generated from each source driver 13b can be improved.

[0065] FIG. 6 shows a case where a reference voltage generation circuit 16 having a function of supplying a reference voltage to the source driver 13a and the source driver 13b is provided in the display device 10 having the configuration shown in FIG. 4. Even when the display device 10 is configured as shown in FIG. 6 , the accuracy of the voltage of the signal generated from each source driver 13a and the accuracy of the voltage of the signal generated from each source driver 13b can be improved.

[0066] [Configuration example of pixel] Hereinafter, a configuration example of a pixel arranged in the display unit 17 of the display device 10 will be described.

[0067] FIG. 7 shows a circuit diagram including four pixels pixel 11(i,j), pixel 11(i +1,j), pixel 11(i+2,j), and pixel 11(i+3,j) arranged in a column in the column direction.

[0068] One pixel 11 has a transistor 30, a liquid crystal element 20, and a capacitor element 60.

[0069] Wiring S1 to wiring S4 each correspond to a source line, and wiring G1 to wiring G4 each correspond to a gate line. For example, in the case shown in FIG. 7, wiring S1 corresponds to wiring SL1(j), wiring S2 corresponds to wiring SL2(j), wiring S3 corresponds to wiring SL3(j), and wiring S4 corresponds to wiring SL4(j). Also, in the case shown in FIG. 7, wiring G1 corresponds to wiring GL(i), wiring G2 corresponds to wiring GL(i + 1), wiring G3 corresponds to wiring GL(i + 2), and wiring G4 corresponds to wiring GL(i + 3).

[0070] One of the source or drain of the transistor 30 included in pixel 11(i, j) is electrically connected to wiring S1, and the gate of the transistor 30 included in pixel 11(i, j) is electrically connected to wiring G1. One of the source or drain of the transistor 30 included in pixel 11(i + 1, j) is electrically connected to wiring S2, and the gate of the transistor 30 included in pixel 11(i + 1, j) is electrically connected to wiring G2. One of the source or drain of the transistor 30 included in pixel 11(i + 2, j) is electrically connected to wiring S3, and the gate of the transistor 30 included in pixel 11(i + 2, j) is electrically connected to wiring G3. One of the source or drain of the transistor 30 included in pixel 11(i + 3, j) is electrically connected to wiring S4, and the gate of the transistor 30 included in pixel 11(i + 3, j) is electrically

[0071] connected to wiring G4. Also, the other of the source or drain of the transistor 30 is electrically connected to one electrode of the capacitor element 60 and one electrode A wiring CS is electrically connected to the square electrode, and a common potential is supplied to the wiring CS.

[0072] The transistor 30 has a function of controlling the writing of the signal supplied from the source line to the pixel 11 by switching between the on state and the off state. Specifically, by turning on the transistor 30, the charge corresponding to the signal supplied from the source line can be written into the capacitor element 60 electrically connected to the transistor 30. Also, by turning off the transistor 30, the charge written in the capacitor element 60 can be held. Here, the transistor 30 can be a transistor using amorphous silicon. Although it is difficult to increase the field-effect mobility of a transistor using amorphous silicon, the display device according to one aspect of the present invention can achieve an extremely high resolution such as 4K or 8K even when such a transistor is used. Also, it can be a large display device with a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal.

[0073] Alternatively, as the transistor 30, a transistor including a metal oxide in the channel formation region (hereinafter also referred to as an OS transistor) can be used. The metal oxide has a larger energy gap than semiconductors such as silicon, and the OS transistor can reduce the minority carrier density. Therefore, when the OS transistor is in the off state, the current flowing between the source and drain of the OS transistor (hereinafter referred to as the off-current) can be extremely low.

[0074] ​​​​​​​​​Therefore, the leakage current (hereinafter also referred to as leakage) is extremely small. Therefore, an OS transistor is used as the transistor 30. As a result, the charge can be held in the capacitive element 60 for a long time. Thereby, the frequency of writing the charge to the capacitive element 60, that is, the frequency of the refresh operation can be reduced, and the power consumption of the display device 10 can be reduced.

[0075] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor, abbreviated as OS. Further, an OS FET refers to a transistor having a metal oxide or an oxide semiconductor.

[0076]

[0077]

[0078] Also, in this specification and the like, CAC-OS or CAC-metal oxide refers to a material that has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxid e is used for the active layer of a transistor, the conductive function is the function of flowing electrons (or holes) that serve as carriers, and the insulating function is the function of not flowing electrons that serve as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxid e, by separating the respective functions, both functions can be maximally enhanced.

[0079] Also, in this specification and the like, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed as being blurred at the periphery and connected in a cloud -like shape.

[0080] Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulative region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.​

[0081] In addition, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to an insulating region and a component having a narrow band gap due to a conductive region. In this configuration, when carriers flow, in the component having a narrow band gap, the carriers mainly flow. Further, the component having a narrow band gap acts complementarily to the component having a wide band gap, and carriers also flow in the component having a wide band gap in conjunction with the component having a narrow band gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor. That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite. FIG. 8(A) shows an example of the layout of pixels 11(i + 2,j) and 11(i + 3,j). In FIG. 8(A) and the like, components provided in the same layer are given the same hatching. Note that in subsequent figures, components provided in the same layer may be given the same hatching.

[0082] [[ID=?]] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite (matrix composite), or a metal matrix composite (metal matrix composite).

[0083] FIG. 8(A) shows an example of the layout of pixels 11(i + 2,j) and 11(i + 3,j).

[0084] In FIG. 8(A) and the like, components provided in the same layer are given the same hatching. Note that in subsequent figures, components provided in the same layer may be given the same hatching.

[0085] As shown in FIG. 8(A), wiring G3, wiring G4, and wiring CS extend in the row direction (horizontal direction), and wiring S1 to wiring S4 extend in the column direction (vertical direction).

[0086] A configuration example of pixel 11(i + 2, j) will be described. In the transistor 30 included in pixel 11(i + 2, j), a semiconductor layer 32 is provided on wiring G3, and a part of wiring G3 functions as a gate. Also, a part of wiring S3 functions as one of a source or a drain. The semiconductor layer 32 has a region located between wiring S2 and wiring S3.

[0087] In addition, a conductive layer 33a that functions as the other of the source or drain of transistor 30 and one electrode of capacitor element 60 is provided so as to be electrically connected to the semiconductor layer 32. Also, a conductive layer 21 that functions as a pixel electrode is provided, and the conductive layer 33a and the conductive layer 21 are electrically connected via an opening 38.

[0088] A configuration example of pixel 11(i + 3, j) will be described. In the transistor 30 included in pixel 11(i + 3, j), a semiconductor layer 32 is provided on wiring G4, and a part of wiring G4 functions as a gate. The semiconductor layer 32 has a region located between wiring S2 and wiring S3.

[0089] In addition, a conductive layer 33a that functions as the other of the source or drain of transistor 30 and one electrode of capacitor element 60 is provided so as to be electrically connected to the semiconductor layer 32. Also, a conductive layer 21 that functions as a pixel electrode is provided, and the conductive layer 33a and the conductive layer 21 are electrically connected via an opening 38.

[0090] Also, a conductive layer 51 having a function as one of the source or drain of the transistor 30 is provided so as to be electrically connected to the semiconductor layer 32. The conductive layer 51 is electrically connected to a conductive layer 52 formed in the same layer as the conductive layer 21 via an opening 71 . The conductive layer 52 is electrically connected to a conductive layer 53 formed in the same layer as the wiring G4 via an opening 72 . The conductive layer 53 is electrically connected to a conductive layer 54 formed in the same layer as the conductive layer 21 via an opening 73 . The conductive layer 54 is electrically connected to the wiring S4 via an opening 74 . That is, in the pixel 11(i + 3,j), the conductive layer 51 having a function as one of the source or drain of the transistor 30 is electrically connected to the wiring S4 via the conductive layer 52, the conductive layer 53, and the conductive layer 54 . When the pixel 11(i + 3,j) has the configuration shown in FIG. 8(A), the conductive layer 51, the wiring S3, and the wiring S4 are provided in the same layer, and the conductive layer 53 has a region overlapping with the wiring S3, but it is possible to suppress one of the source or drain of the transistor 30 from being short-circuited with the wiring S3

[0091] . Also, the conductive layer 52 and the conductive layer 54 can be formed in the same process as the conductive layer 21 having a function as a pixel electrode, and the conductive layer 53 can be formed in the same process as the wiring G4 . Thereby, even when a configuration is adopted in which four source lines are arranged for each column, the number of processes, specifically the number of photolithography processes, can be suppressed from increasing as compared with the case where one or two source lines are arranged for each column . That is, it is possible to suppress an increase in the number of photomasks . . . . . . . . can be suppressed. As a result, an increase in the manufacturing cost of the display device can be suppressed.

[0092] FIG. 8(B) shows an example of the layout of pixel 11(i,j) and pixel 11(i+1,j). As shown in FIG. 8(B), wiring G1 and wiring G2 extend in the row direction. .

[0093] In pixel 11(i,j), the conductive layer 51 having the function of either the source or the drain of transistor 30 is electrically connected to wiring S1 via conductive layer 52, conductive layer 53, and conductive layer 54. Otherwise, the configuration of pixel 11(i,j) and the configuration of pixel 11( i+3,j) are the same. i+3,j) are the same. i+3,j) are the same.

[0094] In pixel 11(i+1,j), a part of wiring S2 has the function of either the source or the drain of transistor 30. Otherwise, the configuration of pixel 11(i+1,j) and the configuration of pixel 11(i+2,j) are the same. drain of transistor 30. Otherwise, the configuration of pixel 11(i+1,j) and the configuration of pixel 11(i+2,j) are the same.

[0095] The above is the description of the pixel configuration example.

[0096] [Cross-sectional configuration example] Hereinafter, an example of the cross-sectional configuration of the display device will be described.

[0097] [Cross-sectional configuration example 1] FIG. 9 shows an example of a cross-section corresponding to cutting line A1-A2 in FIG. 8(A). Here, an example in the case where a transmissive liquid crystal element 20 is applied as the display element is shown. In FIG. 9, the substrate 15 side is the display surface side. element is shown. In FIG. 9, the substrate 15 side is the display surface side.

[0098] The display device 10 has a configuration in which liquid crystal 22 is sandwiched between substrate 14 and substrate 15. The liquid crystal element 20 includes a conductive layer 21 provided on the substrate 14 side, and a conductive layer 23 provided on the substrate 15 side, and liquid crystal 22 sandwiched therebetween. Further, an alignment film 24a is provided between the liquid crystal 22 and the conductive layer 21, and an alignment film 24b is provided between the liquid crystal 22 and the conductive layer 23 .

[0099] The conductive layer 21 functions as a pixel electrode. The conductive layer 23 functions as a common electrode or the like. Further, both the conductive layer 21 and the conductive layer 23 have a function of transmitting visible light . Therefore, the liquid crystal element 20 is a transmissive liquid crystal element .

[0100] A coloring layer 41 and a light shielding layer 42 are provided on the surface of the substrate 15 on the substrate 14 side. An insulating layer 26 is provided to cover the coloring layer 41 and the light shielding layer 42, and a conductive layer 23 is provided to cover the insulating layer 26 . Further, the coloring layer 41 is provided in a region overlapping the conductive layer 21. The light shielding layer 42 is provided to cover the transistor 30, the opening 38, and the like .

[0101] A polarizing plate 39a is disposed outside the substrate 14, and a polarizing plate 39b is disposed outside the substrate 15 . Further, a backlight unit 90 is provided outside the polarizing plate 39a .

[0102] A transistor 30, a capacitor element 60, etc. are provided on the substrate 14. The transistor 30 functions as a selection transistor for the pixel 11. The transistor 30 is electrically connected to the liquid crystal element 20 through the opening 38 .

[0103] The transistor 30 shown in FIG. 9 is a transistor having a so-called bottom gate-channel etch structure ​​It is a transistor. The transistor 30 has a conductive layer 31 having a function as a gate, an insulating layer 34 having a function as a gate insulating layer, a semiconductor layer 32, a pair of impurity semiconductor layers 35 having a function as a source region and a drain region, and a pair of conductive layers 33a and 33b having a function as a source and a drain. The portion of the semiconductor layer 32 that overlaps with the conductive layer 31 has a function as a channel formation region. The impurity semiconductor layer 35 is provided in contact with the semiconductor layer 32, and the conductive layers 33a and 33b are provided in contact with the impurity semiconductor layer 35. The impurity semiconductor layer may sometimes be simply referred to as a semiconductor layer in this specification and the like. Note that the conductive layer 31 corresponds to a part of the wiring G3 in FIG. 8(A), and the conductive layer 33b corresponds to a part of the wiring S3. Also, the conductive layer 31a and the conductive layer 33c described later respectively correspond to a part of the wiring CS and a part of the wiring S4. It is preferable to use a semiconductor containing silicon for the semiconductor layer 32. For example, amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used. In particular, using amorphous silicon is preferable because it can be formed with good yield on a large substrate. The display device according to one aspect of the present invention can provide good display even when a transistor to which amorphous silicon with relatively low field-effect mobility is applied is used. The impurity semiconductor layer 35 is formed of a semiconductor to which an impurity element for imparting one conductivity type is added. When the transistor is of the n-type, the semiconductor to which an impurity element for imparting one conductivity type is added

[0104]

[0105]

[0106]

[0107] Examples include silicon to which P or As is added. Alternatively, for a transistor when it is p-type, for example, B may be added as an impurity element that imparts one conductivity type, but the transistor is preferably n-type. Note that the impurity semiconductor layer 35 may be formed of an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.

[0108] The capacitor element 60 is composed of a conductive layer 31a, an insulating layer 34, and a conductive layer 33a. Also, a conductive layer 33c is provided on the conductive layer 31 via the insulating layer 34.

[0109] Also, an insulating layer 82 and an insulating layer 81 are laminated and provided so as to cover the transistor 30 and the like. The conductive layer 21 having a function as a pixel electrode is provided on the insulating layer 81. Also, the conductive layer 21 and the conductive layer 33a are electrically connected via an opening 38 provided in the insulating layer 81 and the insulating layer 82. The insulating layer 81 preferably has a function as a planarization layer. Also, the insulating layer 82 preferably has a function as a protective film that suppresses the diffusion of impurities and the like into the transistor 30 and the like. For example, an inorganic insulating material can be used for the insulating layer 82, and an organic insulating material can be used for the insulating layer 81.

[0110] In this specification and the like, there are cases where the insulating layer 82 and the insulating layer 81 are collectively regarded as one insulating layer.

[0111] 〔Example of Cross-sectional Configuration 2〕 FIG. 10 shows an example of a cross-section corresponding to the cutting line B1 - B2 in FIG. 8(A). The transistor 30 shown in FIG. 10 has a conductive layer 31 having a function as a gate and, as a gate insulating layer, ​​​The insulating layer 34 has a function as a source region and a drain region. The semiconductor layer 32 has a function as a source region and a drain region. a pair of impurity semiconductor layers 35 having a function as a source and a drain; The semiconductor layer 32 has a pair of conductive layers 33a and 51. The impurity semiconductor layer 35 functions as a channel formation region. The conductive layer 33a and the conductive layer 51 are provided in contact with the impurity semiconductor layer 35. can be.

[0112] The conductive layer 31 corresponds to a part of the wiring G4 in FIG. As in the case of the first embodiment, the conductive layer 31a, the conductive layer 33b, and the conductive layer 33c are each a part of the wiring CS. , a part of the wiring S3, and a part of the wiring S4. 4 and has an area overlapping with the conductive layer 53.

[0113] As described above, the conductive layer 81 and the conductive layer 82 are formed through the openings 71 formed in the insulating layers 81 and 82. The conductive layer 51 and the conductive layer 52 are electrically connected. The conductive layer 52 and the conductive layer 53 are electrically connected through an opening 72 provided in the layer 34. The conductive layer 81 is electrically connected to the insulating layer 82 through an opening 73 formed in the insulating layer 34. The conductive layer 53 and the conductive layer 54 are electrically connected to each other. The conductive layer 54 and the conductive layer 33c are electrically connected through the opening 74. As described above, the transistor 3 is connected to the conductive layer 52, the conductive layer 53, and the conductive layer 54. A conductive layer 51 having a function as either the source or drain of the semiconductor device 10 and a part of the wiring S4 The openings 72 and 73 are electrically connected to the corresponding conductive layers 33c. and are formed with the conductive layer 33b interposed therebetween. Thus, the conductive layer 51 which functions as one of the source or drain of the transistor 30 is prevented from being short-circuited with the conductive layer 3 3b corresponding to a part of the wiring S3. As shown in FIG. 10, the conductive layer 52 and the conductive layer 54 are formed in the same layer as the conductive layer 21, and the conductive layer 53 is formed in the same layer as the conductive layer 31 and the conductive layer 31a.

[0114] Components formed in the same layer can have the same material. That is, for example, the conductive layer 21, the conductive layer 52, and the conductive layer 54 can each have the same material. Also, for example, the conductive layer 31, the conductive layer 31a, and the conductive layer 53 can each have the same material.

[0115] 〔Cross-sectional configuration example 3〕 FIG. 11 shows a modified example of the configuration shown in FIG. 10. FIG. 11 shows an example in the case where the coloring layer 41 is provided on the substrate 14 side. Thereby, the configuration on the substrate 15 side can be simplified.

[0116] When the coloring layer 41 is used as a planarization film, the insulating layer 81 may not be provided. Thereby, the number of manufacturing steps of the display device 10 can be reduced, and the manufacturing cost of the display device 10 can be reduced.

[0117] 〔Cross-sectional configuration example 4〕 FIG. 12 shows a modified example of the configuration shown in FIG. 10. FIG. 12 shows an example in the case where the conductive layer 52, the conductive layer 53, the conductive layer 54, the opening 72, and the opening 73 are omitted. In this case, the conductive layer 51 and the conductive layer 33c are connected via the conductive layer 55 formed in the same layer as the conductive layer 21. ​​and are electrically connected. Specifically, the conductive layer 51 and the conductive layer 55 are electrically connected via the opening 71 and the conductive layer 33c and the conductive layer 55 are electrically connected via the opening 74 Even when the configuration shown in FIG. 12 is used, the short circuit between the conductive layer 51 and the conductive layer 33b can be suppressed .

[0118] [Cross-sectional configuration example 5] FIG. 13 shows a modified example of the configuration shown in FIG. 9, FIG. 14 shows a modified example of the configuration shown in FIG. 10, FIG. 15 shows a modified example of the configuration shown in FIG. 11, and FIG. 16 shows a modified example of the configuration shown in FIG. 12 . The configurations shown in FIGS. 13 to 16 are different from the configurations shown in FIGS. 9 to 12 in that they do not have the impurity semiconductor layer 35 .

[0119] In the configurations shown in FIGS. 13 to 16, it is preferable to use a semiconductor containing a metal oxide for the semiconductor layer 32 . By using a semiconductor containing a metal oxide for the semiconductor layer 32, that is, making the transistor 30 an OS transistor, as described above, the charge corresponding to the signal supplied from the source line can be held in the capacitor element 60 for a long time . As a result, the frequency of writing charges to the capacitor element 60, that is, the frequency of the refresh operation, can be reduced, and the power consumption of the display device 10 can be reduced .

[0120] The above is the description of the cross-sectional configuration example

[0121] [Regarding each component] Hereinafter, each component shown above will be described

[0122] [Substrate] For the substrate of the display panel, a material having a flat surface can be used. From the display element For the substrate that extracts the light, a material that transmits the light is used. For example, materials such as glass, quartz, ceramic chuck, sapphire, and organic resin can be used.

[0123] By using a thin substrate, the display panel can be made lighter and thinner. Further more, by using a substrate with a thickness that has flexibility, a flexible display panel can be realized . Alternatively, glass or the like that is thin enough to have flexibility can also be used as the substrate. Also , a composite material in which a glass and a resin material are bonded together by an adhesive layer may be used.

[0124] 〔Transistor〕 The transistor has a conductive layer having a function as a gate, a semiconductor layer, a conductive layer having a function as a source , a conductive layer having a function as a drain, and an insulating layer having a function as a gate insulating layer.

[0125] Note that the structure of the transistor included in the display device according to one aspect of the present invention is not particularly limited. For example , it may be a planar transistor, a staggered transistor, or an inverse staggered transistor. Also, it may have any transistor structure of a top gate type or a bottom gate type. Alternatively, gates may be provided above and below the channel .

[0126] 〔Semiconductor layer〕 The crystallinity of the semiconductor layer used for the transistor is not particularly limited, and any of an amorphous semiconductor, a semiconductor having crystallinity (microcrystalline semiconductor, polycrystalline semiconductor, single crystal semiconductor, or a semiconductor having a crystal region in part) can be used. Using a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0127] For the semiconductor layer of the transistor, for example, elements of Group 14 (such as silicon, germanium, etc.) can be used. When silicon is used for the semiconductor layer of the transistor, it is particularly preferable to use amorphous silicon. By using amorphous silicon, transistors can be formed with good yield on a large substrate, so the mass productivity of the display device according to one aspect of the present invention can be improved.

[0128] In addition, crystalline silicon such as microcrystalline silicon, polycrystalline silicon, and single-crystalline silicon can also be used. In particular, polycrystalline silicon can be formed at a lower temperature than single-crystalline silicon and has a higher field-effect mobility and higher reliability than amorphous silicon.

[0129] The bottom-gate structure transistor exemplified in this embodiment is preferable because the manufacturing process can be reduced. At this time, by using amorphous silicon, it can be formed at a lower temperature than polycrystalline silicon so that as materials for wirings and electrodes in a layer below the semiconductor layer and for the substrate, materials with low heat resistance can be used, thus widening the range of material selection. For example, a glass substrate with an extremely large area can be suitably used. On the other hand, the top-gate type transistor is preferable because impurity regions can be formed self-alignedly, so variations in characteristics and the like can be reduced. At this time, in particular, it may be suitable when using polycrystalline silicon, single-crystalline silicon, or the like. For example, a glass substrate with an extremely large area can be suitably used. On the other hand, the top-gate type transistor is preferable because impurity regions can be formed self-alignedly, so variations in characteristics and the like can be reduced. At this time, in particular, it may be suitable when using polycrystalline silicon, single-crystalline silicon, or the like.

[0130] For the semiconductor layer of the transistor, metal oxides can be used. Typically, semiconductors containing silicon, semiconductors containing gallium arsenide, or metal oxides containing indium, etc. can be applied. ​ to cut

[0131] In particular, it is preferable to apply a metal oxide having a larger band gap than silicon. Using a semiconductor material having a wider band gap and a lower carrier density than silicon is preferable because it can reduce the current in the off state of the transistor. than silicon, and is preferable because it can reduce the current in the off state of the transistor.

[0132] A transistor using a metal oxide having a larger band gap than silicon can maintain the charge accumulated in a capacitor connected in series with the transistor for a long time due to its low off current. By applying such a transistor to a pixel, it is possible to stop the drive circuit while maintaining the gradation of the image displayed on each display unit. As a result, a display device with extremely low power consumption can be realized. while maintaining the charge accumulated in the capacitor connected in series with the transistor for a long time. By applying such a transistor to a pixel, it is also possible to stop the drive circuit while maintaining the gradation of the image displayed on each display unit. As a result, a display device with extremely low power consumption can be realized. while maintaining the gradation of the image displayed on each display unit. As a result, a display device with extremely low power consumption can be realized.

[0133] The semiconductor layer preferably includes, for example, a film represented by an In-M-Zn-based oxide containing at least indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). Further, in order to reduce the variation in the electrical characteristics of the transistor using the semiconductor layer, it is preferable to include a stabilizer together with them. ium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium, etc.). Further, in order to reduce the variation in the electrical characteristics of the transistor using the semiconductor layer, it is preferable to include a stabilizer together with them.

[0134] Examples of the stabilizer include gallium, tin, hafnium, aluminum, or zirconium, including the metal described as M above. Further, examples of other stabilizers include lanthanoids such as lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, holmium, erbium, thulium, ​​​There are lithium, ytterbium, lutetium, etc.

[0135] As the metal oxide constituting the semiconductor layer, for example, In-Ga-Zn-based oxide, In-Al -Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La- Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Z n-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn -based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based ac id, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga -Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide can be used for this.

[0136] Here, for example, the In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the atomic ratio of In, Ga, and Zn is not limited. For example, the atomic ratio may be In:Ga:Zn = 1:1:1, or In:Ga:Zn = 2:2:1 or In:Ga:Zn = 3:1:2, or In:Ga:Zn = 4: or In:Ga:Zn = 4:2:3, or In:Ga:Zn = 5:1:6, or near these values. Also, metal elements other than In, Ga, and Zn may be included.

[0137] In addition, the semiconductor layer and the conductive layer may have the same metal element among the above oxides. Semi-con By using the same metal element for the layer and the conductive layer, the manufacturing cost can be reduced. For example by using a metal oxide target with the same metal composition, the manufacturing cost can be reduced In addition, the etching gas or etching solution used when processing the semiconductor layer and the conductive layer can be used in common. However, even if the semiconductor layer and the conductive layer have the same metal element their compositions may be different. For example, during the manufacturing process of transistors and capacitor elements the metal element in the film may desorb, resulting in different metal compositions

[0138] The metal oxide constituting the semiconductor layer preferably has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using such a metal oxide with a wide energy gap the off-current of the transistor can be reduced

[0139] When the metal oxide constituting the semiconductor layer is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≧M For the atomic ratio of the metal elements of such a sputtering target preferred are In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3 :1:2, 4:2:4.1, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2 In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1 :8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, etc. Note that the atomic ratio of the metal elements contained in the formed semiconductor layer each includes a fluctuation of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target as an error ​​​ .

[0140] The metal oxide constituting the semiconductor layer is preferably CAC-OS or CAC-metal o xide described later. This can increase the field-effect mobility of the transistor. .

[0141] It is preferable to use a metal oxide with a low carrier density for the semiconductor layer. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less , more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, even more preferably 1×10 / cm 10 / cm 3 less than, and a metal oxide of 1×10 -9 / cm 3 or more can be used. Such a semiconductor layer has stable characteristics because of its low impurity concentration and low defect level density. When the semiconductor layer is a metal oxide, examples of impurities include water or hydrogen.

[0142] In this specification and the like, a metal oxide with a low impurity concentration and a low defect level density may be referred to as a high-purity intrinsic metal oxide or a substantially high-purity intrinsic metal oxide.

[0143] A high-purity intrinsic or substantially high-purity intrinsic metal oxide has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor having such a metal oxide is less likely to have electrical characteristics (also referred to as normally on) in which the threshold voltage becomes negative. Yes. In addition, a metal oxide that is highly pure and truly or substantially highly pure and truly has a low density of defect energy levels Therefore, the trap energy level density may also be low. In addition, a transistor having a metal oxide that is highly pure and truly or substantially highly pure and truly has an extremely small off-current, and even for an element with a channel width W of 1 × 10 6 μm and a channel length L of 10 μm, the off-current is below the measurement limit of a semiconductor parameter analyzer in the range where the voltage (drain voltage) between the source and the drain is from 1 V to 10 V, that is, it is possible to obtain a characteristic of 1 × 10 -13 A or less. That is.

[0144] Note that the semiconductor layer applicable to one aspect of the present invention is not limited to the above, and a material with an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor. Also, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to set the carrier density, impurity concentration, defect density, atomic number ratio of metal elements and oxygen, interatomic distance, density, etc. of the semiconductor layer to appropriate values. Note that the semiconductor layer applicable to one aspect of the present invention is not limited to the above, and a material with an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor. Also, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to set the carrier density, impurity concentration, defect density, atomic number ratio of metal elements and oxygen, interatomic distance, density, etc. of the semiconductor layer to appropriate values. In the metal oxide constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is included in the semiconductor layer, oxygen deficiency may increase and the layer may become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is preferably 2 × 10

[0145] In the metal oxide constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is included in the semiconductor layer, oxygen deficiency may increase and the layer may become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is preferably 2 × 10 atoms / cm 18 or less, preferably 2 × 10 3 atoms / cm 17 or less, preferably 3 2 × 10

[0146] In addition, when an alkali metal and an alkaline earth metal combine with a metal oxide, carriers are generated There are cases where the off-current of the transistor may increase. Therefore, for the semiconductor layer, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is preferably 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / c m 3 or less.

[0147] Also, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, a polycrystalline structure , a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels.

[0148] The metal oxide with an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film with an amorphous structure has, for example, a completely amorphous structure and no crystal part.

[0149] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-mentioned regions.

[0150] s 〔Conductive layer〕 As materials that can be used for the conductive layers such as the gates, sources, and drains of the transistors, as well as various wirings and electrodes constituting the display device, there are metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys mainly composed of these. Also, materials containing these The film can be used as a single layer or in a laminated structure. For example, aluminum containing silicon, a single layer structure of an aluminum film, a two-layer structure in which an aluminum film is laminated on a titanium film, tungsten a two-layer structure in which an aluminum film is laminated on a film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated thereon, and a titanium film or a titanium nitride film is further formed thereon, a three-layer structure, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated thereon, and a molybdenum film or a molybdenum nitride film is further formed thereon, etc. There is. In addition, oxides such as indium oxide, tin oxide, or zinc oxide may be used. Also, copper containing manganese is preferably used because the controllability of the shape by etching is enhanced. In addition, in addition to the gate, source, and drain of the transistor, as a conductive material having translucency that can be used for various conductive layers such as wiring and electrodes constituting the display device, acid Conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide added with gallium, or graphene can be used. Or gold, silver Platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt,

[0151] Copper, palladium, or metal materials such as titanium, or alloy materials containing the metal materials can be used. Or nitrides of the metal materials (for example, titanium nitride) may be used. Note When a metal material or an alloy material (or their nitrides) is used, it has translucency Indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide added with gallium, etc. conductive oxides or graphene can be used. Or gold, silver Platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, Copper, palladium, or metal materials such as titanium, or alloy materials containing the metal materials can be used. Or nitrides of the metal materials (for example, titanium nitride) may be used. Note When a metal material or an alloy material (or their nitrides) is used, it has translucency can be. Or nitrides of the metal materials (for example, titanium nitride) may be used. Note When using a metal material or an alloy material (or their nitrides), having translucency It may be made thinner. Further, the laminated film of the above material can be used as a conductive layer. For example When using a laminated film of an alloy of silver and magnesium and indium tin oxide, etc., it is preferable because the conductivity can be enhanced. These can be used for the conductive layers of various wirings and electrodes constituting the display device, etc and the conductive layers of the display element (conductive layers having functions as pixel electrodes and common electrodes ).

[0152] 〔Insulating layer〕 As the insulating material that can be used for each insulating layer, for example, resins such as acrylic and epoxy , resins having a siloxane bond, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide , silicon nitride, and aluminum oxide can also be used.

[0153] Further, when the semiconductor layer contains a metal oxide, the insulating layer having a region in contact with the semiconductor layer preferably has a region containing oxygen in excess of the stoichiometric composition (excess oxygen region). For example, the insulating layers 34 and 82 having a region in contact with the semiconductor layer 32 preferably have an excess oxygen region. Thereby, oxygen can be supplied from the insulating layers 34 and 82 to the semiconductor layer 32. When the semiconductor layer 32 contains a metal oxide, if oxygen vacancies are formed in the metal oxide, impurities such as hydrogen may enter the oxygen vacancies, and electrons, which are carriers, may be generated. As a result, the electrical characteristics of the transistor may deteriorate . When the insulating layer having a region in contact with the semiconductor layer has an excess oxygen region, oxygen can be supplied from the insulating layer to the semiconductor layer, and the oxygen vacancies can be filled. This can suppress the deterioration of the electrical characteristics of the transistor. Note that the insulating layer has an excess oxygen region . When the insulating layer having a region in contact with the semiconductor layer has an excess oxygen region, oxygen can be supplied from the insulating layer to the semiconductor layer, and the oxygen vacancies can be filled. This can suppress the deterioration of the electrical characteristics of the transistor. By this, deterioration of the electrical characteristics of the transistor can be suppressed. In addition, when the insulating layer has an excess oxygen region To provide a pixel region, for example, an insulating layer may be formed in an oxygen atmosphere. Or, the insulating layer formed after film formation may be heat-treated in an oxygen atmosphere.

[0154] 〔Liquid crystal element〕 As the liquid crystal element, for example, a liquid crystal element to which a vertical alignment (VA: Vertical Alignment) mode is applied can be used. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, etc. can be used. atterned Vertical Alignment) mode, an ASV (Adva nced Super View) mode, etc. can be used.

[0155] In addition, as the liquid crystal element, a liquid crystal element to which various modes are applied can be used. For example, in addition to the VA mode, a TN (Twisted Nematic) mode, an IPS (In- Plane-Switching) mode, an FFS (Fringe Field Swi tching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensate d Birefringence) mode, an FLC (Ferroelectric Li quid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an ECB (Electrically Cont rolled Birefringence) mode, a guest-host mode, etc. can be used as the liquid crystal element to which these modes are applied.

[0156] Note that the liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. It is. Note that the optical modulation effect of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Note that as the liquid crystal used in the liquid crystal element, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network type liquid crystal (PNLC: Polymer Network Liquid Cryst al), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0157] In addition, as the liquid crystal material, either a positive-type liquid crystal or a negative-type liquid crystal may be used, and an optimal liquid crystal material may be used according to the mode and design to be applied.

[0158] In addition, in order to control the alignment of the liquid crystal, an alignment film can be provided. Note that when adopting the horizontal electric field method, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the cholesteric liquid crystal is heated, it is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral agent of several weight% or more is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and optical isotropy. In addition, the liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required ​​​​​Therefore, electrostatic breakdown caused by the rubbing treatment can be prevented. This reduces defects and damage to the liquid crystal display device during the manufacturing process.

[0159] The liquid crystal element may be a transmissive liquid crystal element, a reflective liquid crystal element, or a semi-transmissive liquid crystal element. There are children.

[0160] In one embodiment of the present invention, a transmissive liquid crystal element can be particularly suitably used.

[0161] When using a transmissive or semi-transmissive liquid crystal element, two polarizing plates are placed between a pair of substrates. A backlight is provided outside the polarizing plate. The backlight may be a bottom-type backlight or an edge-light type backlight. Direct backlight with LED (Light Emitting Diode) This is preferred because it makes local dimming easier and increases contrast. In addition, when an edge-light type backlight is used, the module including the backlight can be This is preferable because it allows the thickness of the foil to be reduced.

[0162] In addition, by turning off the edge-lit backlight, a see-through display can be achieved. This can be done.

[0163] [Colored layer] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. Examples of such materials include resin materials.

[0164] [Light blocking layer] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. It may be a film containing a resin material, or a thin film of an inorganic material such as metal. Also, A laminated film of a film containing the material of the coloring layer can also be used for the light-shielding layer. For example, a film containing the material used for the coloring layer that transmits light of a certain color and a film containing the material used for the coloring layer that transmits light of another color can be used in a laminated structure. By forming the coloring layer and the light-shielding layer with the same material, it is preferable because the same apparatus can be used and the process can be simplified.

[0165] The above is the explanation of each component.

[0166] [An example of a method for manufacturing pixels and the like] Hereinafter, an example of a method for manufacturing the display device 10 will be described.

[0167] The thin films (insulating films, semiconductor films, conductive films, etc.) constituting the display device can each be formed by sputtering method, chemical vapor deposition (CVD: Chemical Vapor Deposition) method , vacuum evaporation method, pulsed laser deposition (PLD: Pulsed Laser Deposit ion) method, atomic layer deposition (ALD: Atomic Layer Deposition) method, etc. Examples of the CVD method include plasma enhanced chemical vapor deposition (PECVD) method and thermal CVD method. Examples of the thermal CVD method include metal organic chemical vapor deposition (MOCVD: Metal Organic CVD) method.

[0168] The thin films (insulating films, semiconductor films, conductive films, etc.) constituting the display device can each be formed by spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, etc., or methods such as doctor knife, slit coating, roll coating, curtain coating It can be formed by spin coating or knife coating.

[0169] The thin film constituting the display device can be processed using a lithography method or the like. Or, An island-shaped thin film may be formed by a film formation method using a masking mask. Or, nanoimp The thin film may be processed by a lint method, a sandblasting method, a lift-off method, or the like.

[0170] When processing using a photolithography method, the light used for exposure is, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), and light mixed with these. In addition, ultraviolet light, KrF laser light, or ArF laser light, etc. can also be used. Further, exposure may be performed by a liquid immersion exposure technique. The light used for exposure includes extreme ultraviolet light (EUV: Extreme Ultra-Violet) and X rays, etc. In addition, an electron beam instead of light can also be used for exposure. Extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. When performing exposure by scanning a beam such as an electron beam, a photomask is unnecessary.

[0171] For the etching of the thin film, a dry etching method, a wet etching method, a sandblasting method etc. can be used. <X

[0172] 〔An example of the manufacturing method 1〕 An example of the manufacturing method of the pixel 11(i+3,j) etc. having the configuration shown in FIG. 10 is shown in FIGS. 17 to 19. When manufacturing the display device 10, first, a conductive layer is formed on the substrate 14. Next, patterning is performed by a photolithography method or the like, and the conductive layer is processed by an etching method or the like. By doing so, the conductive layer 31, the conductive layer 31a, and the conductive layer 53 are formed (FIG. 17(A)) . As described above, the conductive layer 31 corresponds to a part of the wiring G3, and the conductive layer 31a corresponds to a part of the wiring CS .

[0173] Next, the insulating layer 34 is formed. As described above, the insulating layer 34 functions as a gate insulating layer of the transistor provided in the display device 10 .

[0174] Thereafter, a semiconductor layer is formed on the insulating layer 34. When, for example, amorphous silicon is used as the semiconductor layer, monosilane or the like can be used as a raw material and formed by a CVD method or the like. By this, the unbonded hands (dangling bonds) of silicon contained in the semiconductor layer can be terminated by hydrogen and thermodynamically stabilized. Thus, amorphous silicon containing hydrogen is called hydrogenated amorphous silicon . . . .

[0175] Next, an impurity semiconductor layer, which is a semiconductor layer containing impurities, is formed on the semiconductor layer. When, for example, hydrogenated amorphous silicon is used as the impurity semiconductor layer, when making the transistor n-type, phosphine or arsine or the like is added to the raw material such as monosilane, and it can be formed by a CVD method or the like. Also, when making the transistor p-type, diborane or the like is added to the raw material such as monosilane, and the impurity semiconductor layer can be formed by a CVD method or the like . . . . .

[0176] Thereafter, patterning is performed by a photolithography method or the like, and the formed semiconductor layer is processed by an etching method or the like to form the semiconductor layer 32 and the impurity semiconductor layer 35 (FIG. 17(B)) . (FIG. 17(B)).

[0177] Next, a conductive layer is formed on the insulating layer 34 and the impurity semiconductor layer 35. Thereafter, patterning is performed by a photolithography method or the like, and the conductive layer is processed by an etching method or the like to form a conductive layer 51, a conductive layer 33a, a conductive layer 33b, and a conductive layer 33c (FIG. 17(C)). As described above, the conductive layer 51 functions as one of the source or drain of the transistor 30, and the conductive layer 33a functions as the other of the source or drain of the transistor 30 and as one electrode of the capacitor element 60. Further, the conductive layer 33b corresponds to a part of the wiring S3, and the conductive layer 33c corresponds to a part of the wiring S4. Also, the conductive layer 33b is formed so as to have a region overlapping with the conductive layer 53

[0178]

[0179] Next, an insulating layer 82 is formed, and thereafter, an insulating layer 81 is formed. After the formation of the insulating layer 81, chemical mechanical polishing (CMP) is performed on the insulating layer 81 by a method or the like to perform a planarization process.

[0179] Next, patterning is performed by a photolithography method or the like. Thereafter, by processing the insulating layer 81 and the insulating layer 82 by an etching method or the like, an opening 71 reaching the conductive layer 51, an opening 38 reaching the conductive layer 33a, and an opening 74 reaching the conductive layer 33c are formed (FIG. 18(A)). Also, by processing the insulating layer 81, the insulating layer 82, and the insulating layer 34 by an etching method or the like, openings 72 and 73 reaching the conductive layer 53 are formed so as to sandwich the conductive layer 33b

[0180] Thus, the opening 38 and the openings 71 to 74 are formed.

[0180] Next, a conductive layer is formed on the insulating layer 81, in the opening 38, and in the openings 71 to 74. . Then, patterning is performed by a photolithography method or the like, and the conductive layer is processed by an etching method or the like to form the conductive layer 21, the conductive layer 52, and the conductive layer 54 (FIG. 18(B)). The conductive layer 21 is electrically connected to the conductive layer 33a through the opening 38 . The conductive layer 52 is electrically connected to the conductive layer 51 through the opening 71 and is electrically connected to the conductive layer 53 through the opening 72 . The conductive layer 54 is electrically connected to the conductive layer 53 through the opening 73 and is electrically connected to the conductive layer 33c through the opening 74. As described above , the conductive layer 21 functions as a pixel electrode of a liquid crystal element provided in the display device 10 . Also, the conductive layer 51, which functions as one of the source or drain of the transistor 30, is electrically connected to the conductive layer 33c corresponding to a part of the wiring S4 through the conductive layer 52, the conductive layer 53, and the conductive layer 54.

[0181] Next, an alignment film 24a is formed (FIG. 19(A)). Then, a light-shielding layer 42, a coloring layer 41, an insulating layer 26, a conductive layer 23, and an alignment film 24b are formed on the substrate 15 (FIG. 19(B)) . The coloring layer 41 can be formed using a photolithography method, a printing method, or an inkjet method . For example, by using the inkjet method, the coloring layer 41 can be formed at room temperature, formed under a low vacuum, or formed on a large substrate. Thereby, the coloring layer 41 can be formed even in a display device with extremely high resolution such as 4K or 8K . Also, the coloring layer 41 can be formed in a large display device having a screen size of 50 inches or more, 60 inches or more, or 70 inches or more in diagonal . Also, a resist mask​​​​​​ Since the colored layer 41 can be formed without using , the number of manufacturing steps of the display device 10 can be reduced, and the manufacturing cost can be reduced.

[0182] Next, the liquid crystal 22 is sealed between the substrate 14 shown in FIG. 19(A) and the substrate 15 shown in FIG. 19(B) using an adhesive layer (not shown). Then, the polarizing plate 39a, the polarizing plate 39b, and the backlight unit 90 are formed. Thus, the display device 10 having the configuration shown in FIG. 10 can be manufactured.

[0183] Here, when manufacturing the display device, the fewer the photolithography steps in the manufacturing process, that is, the fewer the number of photomasks, the lower the manufacturing cost can be.

[0184] For example, among the steps shown in FIGS. 17 and 18 (steps on the substrate 14 side), through a total of five photolithography steps including the formation step of the conductive layer 31 etc. (FIG. 17(A)), the formation step of the semiconductor layer 32 etc. (FIG. 17(B)), the formation step of the conductive layer 33a etc. (FIG. 17(C)), the formation step of the opening 38 etc. (FIG. 18(A)), and the formation step of the conductive layer 21 etc. (FIG. 18(B)), the display device 10 can be manufactured. That is, the backplane substrate can be manufactured using five photomasks.

[0185] When the display device is configured to have one or two source lines per pixel column, it is not necessary to provide the pixel 11 having the configuration shown in FIG. 10. For example, the configuration of all the pixels 11 can be the configuration shown in FIG. 9. Even in this case, when manufacturing the backplane substrate, it is necessary to go through a total of five photolithography steps. That is, five photomasks are required. ​​​​​​​​​​​​​​ This is the case where four source lines are provided per pixel column. Even in this case, the display device can be manufactured using the same number of photomasks as in the case where one or two source lines are provided per pixel column. This makes it possible to manufacture a display device. As a result, it is possible to suppress an increase in the manufacturing cost of a display device having a configuration in which four source lines are provided per pixel column as compared with the manufacturing cost of a display device having a configuration in which one or two source lines are provided per pixel column.

[0186] 〔Example 2 of manufacturing method〕 An example of a manufacturing method for pixels 11(i + 3, j) etc. having the configuration shown in FIG. 14 is shown in FIGS. 20 to 22. FIGS. 20(A), (B), (C), FIGS. 21(A), (B), and FIGS. 22(A), ( B) respectively correspond to FIGS. 17(A), (B), (C), FIGS. 18(A), (B), and FIGS. 19 (A), (B). The manufacturing method shown in FIGS. 20 to 22 is different from the above-described manufacturing method in that the impurity semiconductor layer 35 is not formed in the process shown in FIG. 20(B).

[0187] In the manufacturing method shown in FIGS. 20 to 22, for example, a metal oxide can be used as the semiconductor layer formed on the insulating layer 34. In this case, the semiconductor layer can be formed by a sputtering method. When, for example, an In-Ga-Zn-based oxide is used as the semiconductor layer, the semiconductor layer can be formed by a sputtering method using an In-Ga-Zn-based oxide as a target. The other steps can be performed in the same manner as the manufacturing method shown in FIGS. 17 to 19.

[0188] The above is the description of an example of the manufacturing method for pixels and the like.

[0189] 〔Regarding the shape of the conductive layer〕 A conductive layer that can be used for wirings such as gate lines and source lines is preferably made of a low-resistance material such as metal or alloy, because the wiring resistance can be reduced. Also, when manufacturing a large-screen display device, it is also effective to increase the width of the wiring. However, since such a conductive layer does not transmit visible light, in a transmissive liquid crystal display device, an increase in the width of the wiring itself or an increase in the number of wirings may lead to a decrease in the aperture ratio. Therefore, by devising the shape of the end portion of the conductive layer, light from the backlight unit can be efficiently extracted. FIG. 23(A) shows a cross-sectional view of a conductive layer 33 that constitutes a source line or the like and its vicinity. The conductive layer 33 has an inverted taper shape at its end. The conductive layer 33 can be regarded as, for example, conductive layer 33a, conductive layer 33b, and conductive layer 33c. Alternatively, the conductive layer 33 can be regarded as, for example, conductive layer 51. Here, the taper angle refers to the angle between the bottom surface (the surface in contact with the surface to be formed) and the side surface at the end of the thin film. The taper angle is greater than 0 degrees and less than 180 degrees. Also, the case where the taper angle is less than 90 degrees is called a forward taper, and the case where the taper angle is greater than 90 degrees is called an inverted taper.

[0190] As shown in FIG. 23(A), since the conductive layer 33 has an inverted taper shape, a part of the light 50 incident from the backlight unit is reflected by the side surface of the conductive layer 33 and reaches the liquid crystal 22. As a result, the light extraction efficiency can be increased compared to the case where the side surface of the conductive layer 33 is vertical and the case where it has a forward taper shape.

[0191]

[0192]

[0193]

[0194] ​​​​​​​​​​​​ Here, the taper angle of the conductive layer 33 is greater than 90 degrees and less than 135 degrees, preferably 91 degrees or less. It is preferable that the angle is 120 degrees or less, and more preferably 95 degrees or more and 110 degrees or less.

[0195] In addition, in FIG. 23(B), when the conductive layer 31 constituting the gate line etc. has an inverse tapered shape, By forming the conductive layer 31 in an inverse tapered shape in addition to the conductive layer 33, the The light extraction efficiency can be effectively increased.

[0196] The above is the description of the shape of the conductive layer.

[0197] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0198] (Embodiment 2) In this embodiment mode, a transistor which can be used for a display device or the like shown in the above embodiment mode will be described. An example of the data will be described with reference to the drawings.

[0199] [Transistor configuration example 1] Modified examples of the transistors shown in FIGS. 9 to 12 will be described below.

[0200] The transistor shown in FIG. 24A has a semiconductor layer 32 and an impurity semiconductor layer 35 between them. It has a layer 37.

[0201] The semiconductor layer 37 may be formed of a semiconductor film similar to the semiconductor layer 32. 37 indicates that the semiconductor layer 32 is etched away during etching of the impurity semiconductor layer 35. It has a function as an etching stopper to prevent the In the example shown, the semiconductor layer 37 is separated into left and right halves. It may cover the channel forming region of the conductor layer 32 .

[0202] The semiconductor layer 37 may contain impurities at a lower concentration than the impurity semiconductor layer 35. This allows the semiconductor layer 37 to be an LDD (Lightly Doped Drain) region. This can function as a gate driver, suppressing the hot channel effect when the transistor is driven. It can be controlled.

[0203] The transistor shown in FIG. 24B has an insulating layer 84 on the channel forming region of the semiconductor layer 32. The insulating layer 84 is provided to prevent etching when the impurity semiconductor layer 35 is etched. It functions as a topper.

[0204] The transistor shown in FIG. 24C includes a semiconductor layer 32p instead of the semiconductor layer 32. The semiconductor layer 32p includes a semiconductor film with high crystallinity. For example, the semiconductor layer 32p is a polycrystalline semiconductor. This allows the transistor to have high field-effect mobility. This can be done.

[0205] The transistor shown in FIG. 24(D) has a semiconductor layer 32p in the channel forming region of the semiconductor layer 32. For example, the transistor shown in FIG. 24D has a semiconductor film that becomes the semiconductor layer 32. It can be formed by irradiating the area with laser light or the like to crystallize it locally. This makes it possible to realize a transistor with high field-effect mobility.

[0206] The transistor shown in FIG. 24(E) is the same as the transistor shown in FIG. 24(A) except for the semiconductor layer 32 The channel formation region of the semiconductor device includes a crystalline semiconductor layer 32p.

[0207] The transistor shown in FIG. 24(F) has a crystalline semiconductor layer 32p in the channel formation region of the semiconductor layer 32 of the transistor shown in FIG. 24(B).

[0208] 〔Example of transistor configuration 2〕 Hereinafter, a modified example of the transistor shown in FIGS. 13 to 16 and the like will be described.

[0209] As an example of the structure of the transistor, the transistor 200a will be described with reference to FIGS. 25(A), (B ), (C). FIG. 25(A) is a top view of the transistor 200a. FIG 25(B) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line X1-X2 shown in FIG. 25(A), and FIG. 25(C) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line Y1-Y2 shown in FIG. 25(A). In FIG. 25(A), in order to avoid complexity, some of the components of the transistor (such as the insulating layer having the function of the gate insulating layer) are omitted in the figure shown. Hereinafter, in some cases, the direction of the dashed-dotted line X1-X2 will be referred to as the channel length direction, and the direction of the dashed-dotted line Y1-Y2 will be referred to as the channel width direction. In the top view of the transistor and also in the subsequent drawings, as in FIG. 25(A), some of the components may be omitted in the illustration .

[0210] The transistor 200a includes a conductive layer 221 on the insulating layer 224, an insulating layer 211 on the insulating layer 224 and on the conductive layer 221, a semiconductor layer 231 on the insulating layer 211, a conductive layer 222a on the semiconductor layer 231 and on the insulating layer 211, a conductive layer 222b on the semiconductor layer 231 and on the insulating layer 211, and an insulating layer on the semiconductor layer 231, on the conductive layer 222a, and on the conductive layer 222b ​It has 212 and a conductive layer 223 on the insulating layer 212.

[0211] Note that the insulating layer 224 can be a substrate instead of an insulating layer. When the insulating layer 224 is used as the substrate, the substrate can be a substrate containing the same material as the substrate 14 shown in Embodiment 1. It can be done.

[0212] Also, the conductive layer 221 and the conductive layer 223 can contain, for example, the same material as the conductive layer 31 shown in Embodiment 1. The insulating layer 211 can contain, for example, the same material as the insulating layer 34 shown in Embodiment 1. The conductive layers 222a and 222b can contain, for example, the same materials as the conductive layers 33 and 51 shown in Embodiment 1. The insulating layer 212 can contain the same material as the insulating layer 82 shown in Embodiment 1. It can be done.

[0213] Also, as the semiconductor layer 231, a semiconductor layer containing a metal oxide can be used in the same manner as the semiconductor layer 32 shown in Embodiment 1. In this embodiment, the description will be made assuming that the semiconductor layer 231 is a semiconductor layer containing a metal oxide. It can be done. It will be described.

[0214] The insulating layers 211 and 212 have an opening 235. The conductive layer 223 is electrically connected to the conductive layer 221 through the opening 2 35.

[0215] Here, the insulating layer 211 functions as the first gate insulating layer of the transistor 200a, and the insulating layer 212 functions as the second gate insulating layer of the transistor 200a. In the transistor 200a, the conductive layer 221 functions as the first gate, the conductive layer 222a functions as one of the source or drain, and the conductive layer 22 2b functions as the other of the source or the drain. Also, the transistor 200 In a, the conductive layer 223 functions as a second gate.

[0216] Note that the transistor 200a is a so-called channel etch type transistor and has a dual gate structure.

[0217] Also, the transistor 200a can be configured without the conductive layer 223. In this case, the transistor 200a is a so-called channel etch type transistor and has a bottom gate structure.

[0218] As shown in FIGS. 25(B) and (C), the semiconductor layer 231 is positioned to face the conductive layer 221 and the conductive layer 2 23, and is sandwiched between conductive layers having the functions of two gates. The length of the conductive layer 223 in the channel length direction and the length of the conductive layer 223 in the channel width direction are each longer than the length of the semiconductor layer 231 in the channel length direction and the length of the semiconductor layer 231 in the channel width direction, and the entire semiconductor layer 231 is covered by the conductive layer 223 via the insulating layer 212 thereby. That is to say, the conductive layer 221 and the conductive layer 223 are connected at the opening 235 provided in the insulating layer 211 and the insulating layer 212, and have a region located outside the side end portion of the semiconductor layer 231

[0219] By having such a configuration, the semiconductor layer 231 included in the transistor 200a can be electrically surrounded by the electric fields of the conductive layer 221 and the conductive layer 223. As in the transistor 200a, the channel formation region is formed by the electric fields of the first gate and the second gate.

[0220] By having such a configuration, the semiconductor layer 231 included in the transistor 200a can be electrically surrounded by the electric fields of the conductive layer 221 and the conductive layer 223. As in the transistor 200a, the channel formation region can be formed by the electric fields of the first gate and the second gate. surround the semiconductor layer to be formed with a device structure of a transistor that electrically encloses it It can be called an enclosed channel (s-channel) structure.

[0221] Since the transistor 200a has an s-channel structure, an electric field for inducing a channel by a conductive layer 221 having the function of the first gate can be effectively applied to the semiconductor layer 231 Therefore, the current driving ability of the transistor 200a is improved, and high on-current characteristics can be obtained. Also, since it is possible to increase the on-current, the transistor 200a can be miniaturized. Further, since the transistor 200a has a structure in which the semiconductor layer 231 is surrounded by the conductive layer 221 having the function of the first gate and the conductive layer 223 having the function of the second gate, the mechanical strength of the transistor 200a can be increased.

[0222] The transistor 200a having an s-channel structure has a high field-effect mobility and a high driving ability. Therefore, by using the transistor 200a in a driving circuit, typically a gate driver, a display device with a narrow border width (also referred to as a narrow border) can be provided.

[0223] Next, as an example of the structure of a transistor, the transistor 200b will be described with reference to FIGS. 26(A), (B), and (C). FIG. 26(A) is a top view of the transistor 200b. FIG. 26(B) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line X1 - X2 shown in FIG. 26(A), and FIG. 26(C) corresponds to a cross-sectional view of the cut surface between the dashed-dotted line Y1 - Y2 shown in FIG. 26(A).

[0224] ​​​​​​​​​​​Transistor 200b differs from transistor 200a in that the semiconductor layer 231, the conductive layer 222a, the conductive layer 222b, and the insulating layer 212 have a stacked structure.

[0225] The insulating layer 212 has an insulating layer 212a on the semiconductor layer 231, on the conductive layer 222a, and on the conductive layer 222b, and an insulating layer 212b on the insulating layer 212a. The insulating layer 212 has a function of supplying oxygen to the semiconductor layer 231. That is, the insulating layer 212 contains oxygen. Also, the insulating layer 212a is an insulating layer that can permeate oxygen. Note that the insulating layer 212a also functions as a damage relaxation film for the semiconductor layer 231 when forming the insulating layer 212b to be formed later.

[0226] As the insulating layer 212a, a silicon oxide film, a silicon oxynitride film, etc. with a thickness of 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less can be used.

[0227] Also, the insulating layer 212a preferably has a small amount of defects. Typically, by ESR measurement, the spin density of the signal appearing at g = 2.001 derived from silicon dangling bonds is preferably 3×10 17 spins / cm 3 or less. This is because if the density of defects contained in the insulating layer 212a is high, oxygen will bind to the defects, and the oxygen permeability in the insulating layer 212a will decrease.

[0228] Note that in the insulating layer 212a, all the oxygen that enters the insulating layer 212a from the outside may not move outside the insulating layer 212a and may remain in the insulating layer 212a. Also, the insulating layer As oxygen enters the insulating layer 212a, the oxygen contained in the insulating layer 212a flows out of the insulating layer 212a. The migration may cause oxygen migration in the insulating layer 212a. When an oxide insulating layer that can transmit oxygen is formed as insulating layer 212a, the insulating layer 212b is provided on the insulating layer 212a. The oxygen desorbed from the insulating layer 212b is transported to the semiconductor layer 231 via the insulating layer 212a. can be moved to

[0229] In addition, an oxide insulating layer with a low density of states due to nitrogen oxides is used as the insulating layer 212a. The density of levels due to the nitrogen oxides can be calculated by the valence band of the metal oxide. can be formed between the energy of the upper edge of the conduction band of the metal oxide and the energy of the lower edge of the conduction band of the metal oxide. The oxide insulating layer may be a silicon oxynitride film which emits less nitrogen oxides, or For example, an aluminum oxynitride film which releases less nitrogen oxides can be used.

[0230] The silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectroscopy (TDS). In Thermal Desorption Spectroscopy (TDS), nitrogen This is a film that releases more ammonia than oxide, and typically releases ammonia is 1×10 18 / cm 3 5x10 or more 19 / cm 3 The following is a list of ammonia release rates. The amount is set so that the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by heat treatment.

[0231] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO2 or NO forms levels in the insulating layer 212a or the like. These levels are located within the energy gap of the semiconductor layer 23 1. Therefore, when nitrogen oxides diffuse to the interface between the insulating layer 212a and the semiconductor layer 231, these levels may trap electrons on the insulating layer 212a side. As a result, since the trapped electrons remain near the interface between the insulating layer 212a and the semiconductor layer 231, the threshold voltage of the transistor is shifted in the positive direction.

[0232] Also, nitrogen oxides react with ammonia and oxygen during heat treatment. The nitrogen oxides contained in the insulating layer 212a react with the ammonia contained in the insulating layer 212b during heat treatment, so the nitrogen oxides contained in the insulating layer 212a are reduced. For this reason, it is difficult for electrons to be trapped at the interface between the insulating layer 212a and the semiconductor layer 231.

[0233] By using the oxide insulating layer as the insulating layer 212a, it is possible to reduce the shift of the threshold voltage of the transistor and reduce the variation in the electrical characteristics of the transistor.

[0234] Also, the oxide insulating layer has a nitrogen concentration of 6×10 20 atoms / cm 3 or less as measured by SIMS.

[0235] When the substrate temperature is 220°C or higher and 350°C or lower, and the above oxide insulating layer is formed using PECVD with silane and dinitrogen monoxide, a dense and high-hardness film can be formed.

[0236] ​​​​​​​​​​The insulating layer 212b is an oxide insulating layer containing more oxygen than the oxygen required for the stoichiometric composition. In the oxide insulating layer, part of the oxygen is released by heating. , the oxide insulating layer has an oxygen release rate of 1.0 × 10 19 atoms / cm 3 That's all good Preferably 3.0 x 10 20 atoms / cm 3 The above region is also The amount of release is determined when the temperature of the heat treatment in TDS is between 50°C and 650°C, or between 50°C and 650°C. The total amount of oxygen released is in the range of 550℃ or less. This is the total amount converted into atoms.

[0237] The insulating layer 212b has a thickness of 30 nm to 500 nm, preferably 50 nm or more. A silicon oxide film, a silicon oxynitride film, or the like having a thickness of 400 nm or less can be used.

[0238] Furthermore, it is preferable that the insulating layer 212b has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating layer 212b is a semiconductor compared to the insulating layer 212a. Since it is farther away from layer 231, it can have a higher defect density than insulating layer 212a.

[0239] In addition, the insulating layers 212a and 212b can be made of the same material. Therefore, the interface between the insulating layer 212a and the insulating layer 212b may not be clearly visible. In this embodiment, the interface between the insulating layer 212a and the insulating layer 212b is illustrated by a dashed line. In this embodiment, a two-layer structure of the insulating layer 212a and the insulating layer 212b has been described, but the present invention is not limited thereto. For example, a single-layer structure of the insulating layer 212a or a stacked structure of three or more layers may be used.

[0240] In the transistor 200b, the semiconductor layer 231 has a semiconductor layer 231_1 on the insulating layer 211 and a semiconductor layer 231_2 on the semiconductor layer 231_1. Note that the semiconductor layer 231_1 and the semiconductor layer 231_2 each have the same element. For example, it is preferable that the semiconductor layer 231_1 and the semiconductor layer 231_2 have the elements that the semiconductor layer 231 described above has.

[0241] Further, it is preferable that the semiconductor layer​​​​​​​​​​​​​​​Since the conductive layer 231_2 can be formed, it is possible to suppress the incorporation of impurities at the interface between the semiconductor layer 231_1 and the semiconductor layer 231_ 2.

[0242] Here, the semiconductor layer 231_1 may have a region with lower crystallinity than the semiconductor layer 231_2. The crystallinity of the semiconductor layer 231_1 and the semiconductor layer 231_2 can be analyzed, for example, using X-ray diffraction (XRD) or by analyzing using a transmission electron microscope (TEM).

[0243] The region with low crystallinity of the semiconductor layer 231_1 serves as a diffusion path for excess oxygen, and excess oxygen can also be diffused to the semiconductor layer 231_2 having higher crystallinity than the semiconductor layer 231_1. In this way, by forming a stacked structure of semiconductor layers with different crystal structures and using the region with low crystallinity as the diffusion path for excess oxygen, a highly reliable transistor can be provided.

[0244] In addition, since the semiconductor layer 231_2 has a region with higher crystallinity than the semiconductor layer 231_1, impurities that can be mixed into the semiconductor layer 231 can be suppressed. In particular, by increasing the crystallinity of the semiconductor layer 231_2, the damage during the formation of the conductive layer 222a and the conductive layer 222b can be suppressed. The surface of the semiconductor layer 231, that is, the surface of the semiconductor layer 231_2, is exposed to an etchant or an etching gas during the formation of the conductive layer 222a and the conductive layer 222b. However, when the semiconductor layer 231_2 has a region with high crystallinity, it has better etching resistance compared to the semiconductor layer 231_1 with low crystallinity. Therefore ​​​​​​​​​​​​The semiconductor layer 231_2 functions as an etching stopper.

[0245] The semiconductor layer 231_1 has a region with lower crystallinity than the semiconductor layer 231_2. This can result in a high carrier density.

[0246] Furthermore, when the carrier density of the semiconductor layer 231_1 increases, the conduction band of the semiconductor layer 231_1 The Fermi level may become relatively high in the semiconductor layer 231_1. The lower end of the conduction band is lowered, and the lower end of the conduction band of the semiconductor layer 231_1 and the gate insulating layer (here In this case, the energy difference between the trap level that may be formed in the insulating layer 211 may become large. The larger the energy difference, the less charge is trapped in the gate insulating layer. This may reduce the fluctuation in the threshold voltage of the transistor. When the carrier density of the layer 231_1 is increased, the field effect mobility of the semiconductor layer 231 is increased. This can be done.

[0247] In the transistor 200b, an example in which the semiconductor layer 231 has a stacked structure of two layers is shown. However, the present invention is not limited to this, and a configuration in which three or more layers are laminated may also be used.

[0248] The conductive layer 222a included in the transistor 200b includes a conductive layer 222a_1 and a conductive layer 222 a_1 and a conductive layer 222a_3 on the conductive layer 222a_2. The conductive layer 222b included in the transistor 200b includes a conductive layer 222b_1 and The conductive layer 222b_2 on the conductive layer 222b_1 and the conductive layer 222b_2 on the conductive layer 222b_2 _3 and,.

[0249] For example, as the conductive layer 222a_1, the conductive layer 222b_1, the conductive layer 222a_3, and the conductive layer 222b_3, it is preferable to have any one or more selected from titanium, tungsten, tantalum, molybdenum, indium, gallium, lithium, tin, and zinc. Further, as the conductive layer 222a_2 and the conductive layer 222b_2, it is preferable to have any one or more selected from copper, aluminum, and silver.

[0250] More specifically, indium-tin oxide or indium-zinc oxide can be used for the conductive layer 222a_1, the conductive layer 222b_1, the conductive layer 222a_3, and the conductive layer 222b_3, and copper can be used for the conductive layer 222a_2 and the conductive layer 222b_2.

[0251] Also, the end of the conductive layer 222a_1 has a region located outside the end of the conductive layer 222a_2, the conductive layer 222a_3 covers the upper surface and the side surface of the conductive layer 222a_2, and has a region in contact with the conductive layer 222a_1. Further, the end of the conductive layer 222b_1 has a region located outside the end of the conductive layer 222b_2, the conductive layer 222b_3 covers the upper surface and the side surface of the conductive layer 222b_2, and has a region in contact with the conductive layer 222b_1.

[0252] With the above configuration, it is preferable because the wiring resistance of the conductive layer 222a and the conductive layer 222b can be reduced, and the diffusion of copper into the semiconductor layer 231 can be suppressed.

[0253] Next, as an example of the structure of the transistor, the transistor 200c will be described with reference to FIGS. 27(A), (B), and (C). FIG. 27(A) is a top view of the transistor 200c. This is the case. FIG. 27(B) is a cross-sectional view of the cross-section between the dashed-dotted line X1-X2 shown in FIG. 27(A). This corresponds to the cross-sectional view of the cross-section between the dashed-dotted line Y1-Y2 shown in FIG. 27(A). This corresponds to the cross-sectional view of the cross-section between the dashed-dotted line Y1-Y2 shown in FIG. 27(A).

[0254] The transistor 200c includes a conductive layer 221 on the insulating layer 224, an insulating layer 211 on the conductive layer 221 and on the insulating layer 224, a semiconductor layer 231 on the insulating layer 211, an insulating layer 216 on the semiconductor layer 231 and on the insulating layer 211, a conductive layer 222a on the semiconductor layer 231 and on the insulating layer 216, a conductive layer 222b on the semiconductor layer 231 and on the insulating layer 216, an insulating layer 212 on the insulating layer 216, the conductive layer 222a, and the conductive layer 222b, and a conductive layer 223 on the insulating layer 212. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layer 216 has the function of a channel protection layer of the transistor 200c. If the insulating layer 216 is not present, the conductive layer 222a and the conductive layer 222b are formed by an etching method or the like. The insulating layer 216 has the function of a channel protection layer of the transistor 200c. If the insulating layer 216 is not present, the conductive layer 222a and the conductive layer 222b are formed by an etching method or the like. The insulating layer 216 has the function of a channel protection layer of the transistor 200c. If the insulating layer 216 is not present, the conductive layer 222a and the conductive layer 222b are formed by an etching method or the like. The insulating layer 216 has the function of a channel protection layer of the transistor 200c. If the insulating layer 216 is not present, the conductive layer 222a and the conductive layer 222b are formed by an etching method or the like.

[0255] The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b. The insulating layers 211, 216, and 212 have openings 235. The conductive layer 221 having the function of the first gate of the transistor 200c is electrically connected to the conductive layer 223 having the function of the second gate of the transistor 200c through the opening 235. Further, the insulating layer 216 has openings 238a and 238b. The conductive layer 222a having the function of one of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238a. The conductive layer 222b having the function of the other of the source or drain of the transistor 200c is electrically connected to the semiconductor layer 231 through the opening 238b.

[0256] The insulating layer 216 has the function of a channel protection layer of the transistor 200c. In the case where the insulating layer 216 is not present, the conductive layer 222a and the conductive layer 222b are formed by an etching method or the like. In the case where the insulating layer 216 is not present, the conductive layer 222a and the conductive layer 222b are formed by an etching method or the like. When forming, damage may be caused to the channel formation region of the semiconductor layer 231. This may cause the electrical characteristics of the transistor to become unstable. After forming the insulating layer 216 and providing the openings 238a and 238b, a conductive layer is formed, and the conductive layer is processed by an etching method or the like to form the conductive layer 222a and the conductive layer 222b, thereby suppressing damage to the channel formation region of the semiconductor layer 231. As a result, the electrical characteristics of the transistor can be stabilized, and a highly reliable transistor can be realized.

[0257] The insulating layer 216 can include, for example, the same material as the insulating layer 212.

[0258] The insulating layer 216 preferably has an excess oxygen region. By having the excess oxygen region in the insulating layer 216, oxygen can be supplied to the channel formation region of the semiconductor layer 231. Thus, the oxygen defects formed in the channel formation region can be compensated for by the excess oxygen, and a highly reliable display device can be provided.

[0259] Also, after forming the openings 238a and 238b, it is preferable to add an impurity element to the semiconductor layer 231. Specifically, it is preferable to add an element that forms an oxygen defect or an element that combines with the oxygen defect. As a result, although details will be described later, the conductivity of the region of the semiconductor layer 231 that overlaps with the conductive layer 222a (one of the source region or the drain region), and the region that overlaps with the conductive layer 222b (the other of the source region or the drain region) can be increased. Thereby, the current driving ability of the transistor 200c is improved, and high on-current characteristics can be obtained.

[0260] The transistor 200c is a so-called channel protection type transistor, and It has a rugate structure.

[0261] The transistor 200c is s By having such a configuration, the transistor 200c has a -channel structure. The semiconductor layer 231 included therein is electrically connected by the electric field of the conductive layer 221 and the conductive layer 223. It can be surrounded.

[0262] The transistor 200c has an s-channel structure, and therefore the conductive layer 221 The electric field for inducing a channel is effectively applied to the semiconductor layer 231 by the electric layer 223. This improves the current driving capability of the transistor 200c, resulting in a high on-state current. It is also possible to increase the on-current, which allows The transistor 200c can be miniaturized. The conductor layer 231 has a structure surrounded by the conductive layer 221 and the conductive layer 223. Therefore, the mechanical strength of the transistor 200c can be increased.

[0263] Note that the transistor 200c may not include the conductive layer 223. In this case, the transistor 200c is a so-called channel protection type transistor, and It has a gate structure.

[0264] Next, an example of the structure of a transistor will be described using FIGS. 28(A), (B), (C), and (D). and explain.

[0265] 28(A) and (B) are cross-sectional views of the transistor 200d, and FIGS. 28(C) and (D) are cross-sectional views of the transistor 200d. 1 is a cross-sectional view of a transistor 200e. Transistor 200e is a variation of transistor 200b shown above. Therefore, in Fig. 28(A), (B), (C), and (D), The parts having the same functions as the transistors 200b and 200c are the same. The same reference numerals are used and detailed explanations are omitted.

[0266] 28(A) is a cross-sectional view of the transistor 200d in the channel length direction, and FIG. FIG. 28B is a cross-sectional view of the transistor 200d in the channel width direction. 28(D) is a cross-sectional view of the transistor 200e in the channel length direction. FIG. 10 is a cross-sectional view of 0e in the channel width direction.

[0267] The transistor 200d shown in FIGS. 28A and 28B has the following characteristics compared to the transistor 200b: The conductive layer 223 and the opening 235 are not provided. Compared to transistor 200b, the insulating layer 212, the conductive layer 222a, and the conductive layer 222b The configuration is different.

[0268] In the transistor 200d, the insulating layer 212 is formed by an insulating layer 212c and a thin film transistor 212b. The insulating layer 212c is made of a material that supplies oxygen to the semiconductor layer 231. and a function of preventing the intrusion of impurities (typically, water, hydrogen, etc.). The insulating layer 212c may be an aluminum oxide film, an aluminum oxynitride film, or an aluminum nitride film. In particular, the insulating layer 212c may be a reactive sputtering film. It is preferably an aluminum oxide film formed by the Talin method. Note that the reactivity As an example of a method for forming an aluminum oxide film by a reactive sputtering method, the following method

[0269] First, a gas mixture of an inert gas (typically Ar gas) and oxygen gas is introduced into the sputtering chamber. Subsequently, a voltage is applied to the aluminum target placed in the sputtering chamber, whereby an aluminum oxide film can be formed . Note that as the power source for applying a voltage to the aluminum target, a DC power source, an AC power source, or an RF power source can be mentioned. In particular, it is preferable to use a DC power source because productivity is improved .

[0270] The insulating layer 212d has a function of suppressing the entry of impurities (typically water, hydrogen, etc.) . As the insulating layer 212d, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film can be used. In particular, as the insulating layer 212d, a silicon nitride film formed by the PECVD method is preferably used. A silicon nitride film formed by the PECVD method is preferable because a high film density can be easily obtained. Note that a silicon nitride film formed by the PECVD method may have a high hydrogen concentration in the film.

[0271] In the transistor 200d, since the insulating layer 212c is disposed below the insulating layer 212d , the hydrogen contained in the insulating layer 212d does not diffuse or is difficult to diffuse to the semiconductor layer 231 side.

[0272] Note that the transistor 200d has a single gate structure, unlike the transistor 200b By using a transistor having a single gate structure, The number of masks can be reduced, thereby increasing productivity.

[0273] The transistor 200e shown in FIGS. 28(C) and 28(D) has the following characteristics compared to the transistor 200c: The configurations of the insulating layer 216 and the insulating layer 212 are different. has insulating layer 216a instead of insulating layer 216, and insulating layer 212 instead of insulating layer 213. 2d. In the transistor 200e, the semiconductor layer 231 has a semiconductor layer 23 1_1 and a semiconductor layer 231_2.

[0274] The insulating layer 216a has the same function as the insulating layer 212c.

[0275] The structure of the transistor 200d and the transistor 200e reduces the need for large capital investment. It can be produced using existing production lines without the need for additional capital investment. Fast silicon production lines can be easily replaced with oxide semiconductor production lines. It becomes possible.

[0276] Next, as an example of the structure of a transistor, a transistor 200f will be described with reference to FIG. 29A is a top view of a transistor 200f. FIG. 29(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 29(A). 29(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 29(A). This corresponds to a cross-sectional view.

[0277] The transistor 200f shown in FIGS. 29A, 29B, and 29C has a conductive layer 224 on an insulating layer 224. 221, an insulating layer 211 on the conductive layer 221 and on the insulating layer 224, and a half conductor layer 231, an insulating layer 212 on the semiconductor layer 231, and a conductive layer 223 on the insulating layer 212 , and has an insulating layer 215 on the insulating layer 211, on the semiconductor layer 231, and on the conductive layer 223. Note that the semiconductor layer 231 has a channel formation region 231i that overlaps with the conductive layer 223, a source region 231s that contacts the insulating layer 2 15, and a drain region 231d that contacts the insulating layer 215. has.

[0278] Also, the insulating layer 215 contains nitrogen or hydrogen. When the insulating layer 215 contacts the source region 231s and the drain region 231d, nitrogen or hydrogen in the insulating layer 215 is added to the source region 231s and the drain region 231d. The source region 231s and the drain region 231d have an increased carrier density by the addition of nitrogen or hydrogen. become.

[0279] Also, the transistor 200f may have a conductive layer 222a that is electrically connected to the source region 231s through an opening 236a provided in the insulating layer 215. Also, the transistor 200f may have a conductive layer 222b that is electrically connected to the drain region 231d through an opening 236b provided in the insulating layer 215.

[0280] The insulating layer 211 functions as a first gate insulating layer, and the insulating layer 212 functions as a second gate insulating layer. Also, the insulating layer 215 functions as a protective insulating layer .

[0281] Also, the insulating layer 212 has an excess oxygen region. Since the insulating layer 212 has an excess oxygen region Thus, it is possible to supply excess oxygen into the channel formation region 231i of the semiconductor layer 231. Therefore, since oxygen vacancies that can be formed in the channel formation region 231i can be filled with excess oxygen, a highly reliable display device can be provided. In addition, in order to supply excess oxygen into the semiconductor layer 231, excess oxygen may be supplied to the insulating layer 211 formed below the semiconductor layer 231. In this case, the excess oxygen contained in the insulating layer 211 can also be supplied to the source region 231s and the drain region 231d of the semiconductor layer 231. When excess oxygen is supplied to the source region 231s and the drain region 231d, the resistance of the source region 231s and the drain region 231d may increase. On the other hand, by configuring the insulating layer 212 formed above the semiconductor layer 231 to have excess oxygen, it becomes possible to selectively supply excess oxygen only to the channel formation region 231i. Alternatively, after supplying excess oxygen to the channel formation region 231i, the source region 231s, and the drain region 231d, by selectively increasing the carrier density of the source region 231s and the drain region 231d, it is possible to suppress an increase in the resistance of the source region 231s and the drain region 231d.

[0282] In addition, the source region 231s and the drain region 231d of the semiconductor layer 231 preferably each have an element that forms an oxygen vacancy or an element that binds to an oxygen vacancy. Representative examples of the element that forms an oxygen vacancy or the element that binds to an oxygen vacancy include hydrogen. Moreover, by supplying excess oxygen to the insulating layer 211 formed below the semiconductor layer 231, the excess oxygen can be supplied to the source region 231s and the drain region 231d of the semiconductor layer 231 as well. When excess oxygen is supplied to the source region 231s and the drain region 231d, the resistance of the source region 231s and the drain region 231d may increase. Furthermore, by making the insulating layer 212 formed above the semiconductor layer 231 have a structure containing excess oxygen, it becomes possible to selectively supply excess oxygen only to the channel formation region 231i. Or, after supplying excess oxygen to the channel formation region 231i, the source region 231s, and the drain region 231d, by selectively increasing the carrier density of the source region 231s and the drain region 231d, it is possible to suppress an increase in the resistance of the source region 231s and the drain region 231d. Also, the source region 231s and the drain region 231d of the semiconductor layer 231 preferably each have an element that forms an oxygen vacancy or an element that binds to an oxygen vacancy. Representative examples of the element that forms an oxygen vacancy or the element that binds to an oxygen vacancy include hydrogen. Furthermore, by supplying excess oxygen to the insulating layer 211 formed below the semiconductor layer 231, the excess oxygen can be supplied to the source region 231s and the drain region 231d of the semiconductor layer 231 as well. When excess oxygen is supplied to the source region 231s and the drain region 231d, the resistance of the source region 231s and the drain region 231d may increase. In addition, by making the insulating layer 212 formed above the semiconductor layer 231 have a structure containing excess oxygen, it becomes possible to selectively supply excess oxygen only to the channel formation region 231i. Or, after supplying excess oxygen to the channel formation region 231i, the source region 231s, and the drain region 231d, by selectively increasing the carrier density of the source region 231s and the drain region 231d, it is possible to suppress an increase in the resistance of the source region 231s and the drain region 231d.

[0283] Moreover, by making the insulating layer 212 formed above the semiconductor layer 231 have a structure containing excess oxygen, it becomes possible to selectively supply excess oxygen only to the channel formation region 231i. Or, after supplying excess oxygen to the channel formation region 231i, the source region 231s, and the drain region 231d, by selectively increasing the carrier density of the source region 231s and the drain region 231d, it is possible to suppress an increase in the resistance of the source region 231s and the drain region 231d. In addition, the source region 231s and the drain region 231d of the semiconductor layer 231 preferably each have an element that forms an oxygen vacancy or an element that binds to an oxygen vacancy. Representative examples of the element that forms an oxygen vacancy or the element that binds to an oxygen vacancy include hydrogen. Furthermore, by supplying excess oxygen to the insulating layer 211 formed below the semiconductor layer 231, the excess oxygen can be supplied to the source region 231s and the drain region 231d of the semiconductor layer 231 as well. When excess oxygen is supplied to the source region 231s and the drain region 231d, the resistance of the source region 231s and the drain region 231d may increase. Also, by making the insulating layer 212 formed above the semiconductor layer 231 have a structure containing excess oxygen, it becomes possible to selectively supply excess oxygen only to the channel formation region 231i. Or, after supplying excess oxygen to the channel formation region 231i, the source region 231s, and the drain region 231d, by selectively increasing the carrier density of the source region 231s and the drain region 231d, it is possible to suppress an increase in the resistance of the source region 231s and the drain region 231d. Moreover, the source region 231s and the drain region 231d of the semiconductor layer 231 preferably each have an element that forms an oxygen vacancy or an element that binds to an oxygen vacancy. Representative examples of the element that forms an oxygen vacancy or the element that binds to an oxygen vacancy include hydrogen. In addition, by supplying excess oxygen to the insulating layer 211 formed below the semiconductor layer 231, the excess oxygen can be supplied to the source region 231s and the drain region 231d of the semiconductor layer 231 as well. When excess oxygen is supplied to the source region 231s and the drain region 231d, the resistance of the source region 231s and the drain region 231d may increase.

[0284] In addition, the source region 231s and the drain region 231d of the semiconductor layer 231 preferably each have an element that forms an oxygen vacancy or an element that binds to an oxygen vacancy. Representative examples of the element that forms an oxygen vacancy or the element that binds to an oxygen vacancy include hydrogen. Also, the source region 231s and the drain region 231d of the semiconductor layer 231 preferably each have an element that forms an oxygen vacancy or an element that binds to an oxygen vacancy. Representative examples of the element that forms an oxygen vacancy or the element that binds to an oxygen vacancy include hydrogen. Moreover, the source region 231s and the drain region 231d of the semiconductor layer 231 preferably each have an element that forms an oxygen vacancy or an element that binds to an oxygen vacancy. Representative examples of the element that forms an oxygen vacancy or the element that binds to an oxygen vacancy include hydrogen. Examples include boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, noble gas elements, etc. In addition, representative examples of noble gas elements include helium, neon, argon, krypton, and xenon, etc. When one or more of the elements that form the oxygen deficiency or the elements that bind to the oxygen deficiency are included in the insulating layer 215, they diffuse from the insulating layer 215 into the source region 231s and the drain region 231d, and / or are added to the source region 231s and the drain region 231d by an impurity addition process.

[0285] When an impurity element is added to a metal oxide, the bond between the metal element and oxygen in the metal oxide is broken, and an oxygen deficiency is formed. Or, when an impurity element is added to a metal oxide, the oxygen that was bonded to the metal element in the metal oxide binds to the impurity element, and oxygen is desorbed from the metal element, forming an oxygen deficiency. As a result, the carrier density increases in the metal oxide, and the conductivity becomes higher.

[0286] Also, the conductive layer 221 has a function as a first gate, the conductive layer 223 has a function as a second gate, the conductive layer 222a has a function as a source, and the conductive layer 222b has a function as a drain.

[0287] Also, as shown in FIG. 29(C), openings 237 are provided in the insulating layer 211 and the insulating layer 212. Further, the conductive layer 221 is electrically connected to the conductive layer 223 through the openings 237. Therefore, the same potential is applied to the conductive layer 221 and the conductive layer 223. Note that different potentials may be applied to the conductive layer 221 and the conductive layer 223 without providing the openings 237. Alternatively, without providing the opening 237, the conductive layer 221 may be used as a light-shielding film. For example , by forming the conductive layer 221 from a light-shielding material, it is possible to suppress the light from below that irradiates the channel formation region 231i .

[0288] Also, as shown in FIGS. 29(B) and (C), the semiconductor layer 231 is positioned so as to face each of the conductive layer 221 having a function as a first gate and the conductive layer 223 having a function as a second gate, and is sandwiched between the conductive layers having functions as two gates . Also, the transistor 200f also has an s-channel structure similar to the transistors 200a, 200b, and 200c. With such a configuration, the semiconductor layer 231 included in the transistor 200f can be electrically surrounded by the electric fields of the conductive layer 221 having a function as a first gate and the conductive layer 223 having a function as a second gate

[0289] . Since the transistor 200f has an s-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 231 by the conductive layer 221 or the conductive layer 223. As a result, the current driving ability of the transistor 200f is improved, and high on-current characteristics can be obtained. Also, since it is possible to increase the on-current, it becomes possible to miniaturize the transistor 200f. Also, since the transistor 200f has a structure in which the semiconductor layer 231 is surrounded by the conductive layer 221 and the conductive layer 223, the mechanical strength of the transistor 200f can be increased . .

[0290] Since the transistor 200f has an s-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 231 by the conductive layer 221 or the conductive layer 223. As a result, the current driving ability of the transistor 200f is improved, and high on-current characteristics can be obtained. Also, since it is possible to increase the on-current, it becomes possible to miniaturize the transistor 200f. Also, since the transistor 200f has a structure in which the semiconductor layer 231 is surrounded by the conductive layer 221 and the conductive layer 223, the mechanical strength of the transistor 200f can be increased . . Also, since it is possible to increase the on-current, it becomes possible to miniaturize the transistor 200f. Also, since the transistor 200f has a structure in which the semiconductor layer 231 is surrounded by the conductive layer 221 and the conductive layer 223, the mechanical strength of the transistor 200f can be increased . . .

[0291] ​​ Note that the transistor 200f may be referred to as a TGSA (Top Gate Self Aligned) type FET based on the position of the conductive layer 223 with respect to the semiconductor layer 231 or the method of forming the conductive layer 223. Note that the transistor 200f may be referred to as a TGSA (Top Gate Self Aligned) type FET based on the position of the conductive layer 223 with respect to the semiconductor layer 231 or the method of forming the conductive layer 223. type FET.

[0292] In the transistor 200f as well, the semiconductor layer 231 may be stacked in two or more layers, similar to the transistor 200b. In the transistor 200f as well, the semiconductor layer 231 may be stacked in two or more layers, similar to the transistor 200b.

[0293] Also, in the transistor 200f, although the insulating layer 212 is provided only at the portion overlapping the conductive layer 223, it is not limited to this, and the insulating layer 212 may be configured to cover the semiconductor layer 231. Also, a configuration without providing the conductive layer 221 is also possible. Also, in the transistor 200f, although the insulating layer 212 is provided only at the portion overlapping the conductive layer 223, it is not limited to this, and the insulating layer 212 may be configured to cover the semiconductor layer 231. Also, a configuration without providing the conductive layer 221 is also possible. Also, in the transistor 200f, although the insulating layer 212 is provided only at the portion overlapping the conductive layer 223, it is not limited to this, and the insulating layer 212 may be configured to cover the semiconductor layer 231. Also, a configuration without providing the conductive layer 221 is also possible.

[0294] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0295] (Embodiment 3) In this embodiment, an example of a method for crystallizing polycrystalline silicon that can be used for the semiconductor layer of a transistor and a laser crystallization apparatus will be described. In this embodiment, an example of a method for crystallizing polycrystalline silicon that can be used for the semiconductor layer of a transistor and a laser crystallization apparatus will be described.

[0296] To form a polycrystalline silicon layer with good crystallinity, it is preferable to provide an amorphous silicon layer on a substrate and irradiate the amorphous silicon layer with laser light to crystallize it. For example, by using a linear beam as the laser light and moving the substrate while irradiating the linear beam onto the amorphous silicon layer, a polycrystalline silicon layer can be formed in a desired region on the substrate. To form a polycrystalline silicon layer with good crystallinity, it is preferable to provide an amorphous silicon layer on a substrate and irradiate the amorphous silicon layer with laser light to crystallize it. For example, by using a linear beam as the laser light and moving the substrate while irradiating the linear beam onto the amorphous silicon layer, a polycrystalline silicon layer can be formed in a desired region on the substrate. To form a polycrystalline silicon layer with good crystallinity, it is preferable to provide an amorphous silicon layer on a substrate and irradiate the amorphous silicon layer with laser light to crystallize it. For example, by using a linear beam as the laser light and moving the substrate while irradiating the linear beam onto the amorphous silicon layer, a polycrystalline silicon layer can be formed in a desired region on the substrate. To form a polycrystalline silicon layer with good crystallinity, it is preferable to provide an amorphous silicon layer on a substrate and irradiate the amorphous silicon layer with laser light to crystallize it. For example, by using a linear beam as the laser light and moving the substrate while irradiating the linear beam onto the amorphous silicon layer, a polycrystalline silicon layer can be formed in a desired region on the substrate.

[0297] The method using a linear beam has a relatively good throughput. On the other hand, for a certain region Since the method involves irradiating the laser beam multiple times while it moves relatively, variations in the output of the laser beam and resulting changes in the beam profile are likely to cause variations in crystallinity. For example, if a semiconductor layer crystallized by this method is used in a transistor of a pixel of a display device, random stripe patterns due to variations in crystallinity may be visible when displaying an image. There is.

[0298] Also, although it is ideal for the length of the linear beam to be equal to or greater than the length of one side of the substrate, the length of the linear beam is limited by the output of the laser oscillator and the configuration of the optical system. Therefore, in the processing of a large substrate, it is practical to fold back the inside of the substrate surface and perform laser irradiation. Therefore, a region where the laser light is overlapped and irradiated is generated. The crystallinity of the region is likely to be different from that of other regions, so display unevenness may occur in the region.

[0299] In order to suppress the above problems, local laser irradiation may be performed on the amorphous silicon layer formed on the substrate to crystallize it. In local laser irradiation, it is easy to form a polycrystalline silicon layer with less variation in crystallinity.

[0300] FIG. 30(A) is a diagram for explaining a method of locally irradiating a laser on an amorphous silicon layer formed on a substrate.

[0301] The laser beam 826 emitted from the optical system unit 821 is reflected by the mirror 822 and enters the micro lens array 823. The micro lens array 823 condenses the laser beam 826 to form a plurality of laser beams 827.

[0302] On the stage 815, a substrate 830 formed with an amorphous silicon layer 840 is fixed. Amorph By irradiating the amorphous silicon layer 840 with a plurality of laser beams 827, a plurality of polycrystalline silicon layers 841 can be formed simultaneously.

[0303] Each micro lens of the microlens array 823 is preferably provided in accordance with the pixel pitch of the display device. Or, it may be provided at intervals that are an integer multiple of the pixel pitch. In any case, by repeating the laser irradiation and the movement of the stage 815 in the X direction or the Y direction, a polycrystalline silicon layer can be formed in the region corresponding to all the pixels. For example, when the microlens array 823 has M rows and N columns (M and N are natural numbers) of micro lenses at the pixel pitch, first, laser light is irradiated at a predetermined starting position, and M rows and N columns of polycrystalline silicon layers 841 can be formed. Then, it is moved by a distance corresponding to N columns in the row direction and laser light is irradiated, and further, by forming M rows and N columns of polycrystalline silicon layers 841, M rows and 2 N columns of polycrystalline silicon layers 841 can be formed. By repeating this process, a plurality of polycrystalline silicon layers 841 can be formed in the desired region. Also, when performing the laser irradiation process in a folded manner, it is only necessary to move by a distance corresponding to N columns in the row direction and perform laser irradiation,

[0304] and further repeat the movement by a distance corresponding to M rows in the column direction and the irradiation of laser light. When the microlens array 823 has M rows and N columns (M and N are natural numbers) of micro lenses at the pixel pitch, first, laser light is irradiated at a predetermined starting position, and M rows and N columns of polycrystalline silicon layers 841 can be formed. Then, it is moved by a distance corresponding to N columns in the row direction and laser light is irradiated, and further, by forming M rows and N columns of polycrystalline silicon layers 841, M rows and 2 N columns of polycrystalline silicon layers 841 can be formed. By repeating this process, a plurality of polycrystalline silicon layers 841 can be formed in the desired region. Also, when performing the laser irradiation process in a folded manner, it is only necessary to move by a distance corresponding to N columns in the row direction and perform laser irradiation, and further repeat the movement by a distance corresponding to M rows in the column direction and the irradiation of laser light. By repeating this process, a plurality of polycrystalline silicon layers 841 can be formed in the desired region. Also, when performing the laser irradiation process in a folded manner, it is only necessary to move by a distance corresponding to N columns in the row direction and perform laser irradiation, and further repeat the movement by a distance corresponding to M rows in the column direction and the irradiation of laser light. If the oscillation frequency of the laser light and the moving speed of the stage 815 are appropriately adjusted, even by the method of performing laser irradiation while moving the stage

[0305] 8 at a distance corresponding to the pixel pitch. 15 in one direction, a polycrystalline silicon layer can be formed at the pixel pitch. layers 841 can be formed.

[0306] The size of the laser beam 827 can be, for example, an area that includes the entire semiconductor layer of one transistor. Or, it can be an area that includes the entire channel formation region of one transistor. Or, it can be an area that includes a part of the channel formation region of one transistor. These can be used appropriately according to the electrical characteristics of the required transistors.

[0307] In addition, when targeting a display device having a plurality of transistors in one pixel, the size of the laser beam 827 can be an area that includes the entire semiconductor layer of each transistor within one pixel. Also, the size of the laser beam 827 may be an area that includes the entire semiconductor layer of the transistors included in a plurality of pixels.

[0308] Also, as shown in FIG. 31(A), a mask 824 may be provided between the mirror 822 and the microlens array 823. The mask 824 is provided with a plurality of openings corresponding to each microlens. The shape of the opening can be reflected in the shape of the laser beam 827. When the mask 824 has a circular opening as shown in FIG. 31(A), a circular laser beam 827 can be obtained. Also, when the mask 824 has a rectangular opening, a rectangular laser beam 827 can be obtained. The mask 824 is effective, for example, when it is desired to crystallize only the channel formation region of the transistor. Note that the mask 824 may be provided between the optical system unit 821 and the mirror 822 as shown in FIG. 31(B).

[0309] FIG. 30(B) is a laser crystal It is a perspective view for explaining the main configuration of the crystallization apparatus. The laser crystallization apparatus has a moving mechanism 812, a moving mechanism 813, and a stage 815 which are components of the X-Y stage. Also, it has a laser oscillator 820, an optical system unit 821, a mirror 822, and a microlens array 823 for shaping the laser beam 827.

[0310] The moving mechanism 812 and the moving mechanism 813 are provided with the function of reciprocating linearly in the horizontal direction. As a mechanism for applying power to the moving mechanism 812 and the moving mechanism 813, for example, a ball screw mechanism 816 driven by a motor can be used. Since the moving directions of the moving mechanism 812 and the moving mechanism 813 intersect perpendicularly, the stage 815 fixed to the moving mechanism 813 can be freely moved in the X direction and the Y direction.

[0311] The stage 815 has a fixing mechanism such as a vacuum suction mechanism and can fix a substrate 830 or the like. Also, the stage 815 may have a heating mechanism as needed. Although not shown in the figure, the stage 815 has a pusher pin and its upper and lower mechanisms, and when loading and unloading a substrate 830 or the like, the substrate 830 or the like can be moved up and down.

[0312] The laser oscillator 820 only needs to be able to output light with a wavelength and intensity suitable for the purpose of the process. A pulsed laser is preferred, but a CW laser may also be used. Typically, an excimer laser capable of irradiating ultraviolet light such as a wavelength of 351 nm - 353 nm (XeF), 308 nm (XeCl), etc. can be used. Alternatively, the second harmonic (515 nm, 532 nm, etc.) or the third harmonic (343 nm, 355 nm, etc.) of a solid-state laser (YAG laser, fiber laser, etc.) can be used. ​ This is also acceptable. Additionally, there may be a plurality of laser oscillators 820.

[0313] The optical system unit 821 includes, for example, a mirror, a beam expander, a beam homogenizer, etc. and can stretch while making the in-plane distribution of the energy of the laser beam 825 output from the laser oscillator 820 uniform.

[0314] For the mirror 822, for example, a dielectric multilayer mirror can be used and installed so that the incident angle of the laser beam is approximately 45°. The microlens array 823 can have, for example, a shape in which a plurality of convex lenses are provided on the upper surface or the upper and lower surfaces of a quartz plate.

[0315] By using the above laser crystallization apparatus, a polycrystalline silicon layer with little variation in crystallinity can be formed.

[0316] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0317] (Embodiment 4) Hereinafter, the configuration of the CAC-OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0318] CAC-OS is, for example, a structure of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Note that hereinafter, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more ​​​​​​​​​A state of being mixed in a size of 2 nm or less, or in the vicinity thereof, is also referred to as a mosaic state or a patch state. It is called.

[0319] In addition, the metal oxide preferably contains at least indium. In particular, it preferably contains indium and zinc. Further, in addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained. It is called. Lithium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. It may be contained. One or more selected from the group consisting of It may be contained.

[0320] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO.) refers to indium oxide (hereinafter, InO (X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In (X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In X1 (X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In (X2, Y2, and Z2 are real numbers greater than 0) X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) And gallium oxide (hereinafter, GaO X3 (X3 is a real number greater than 0) Or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) When the materials are separated from each other, it becomes a mosaic state, and the mosaic-like InO Or In X1 Or In X2 Zn Y2 O Z2 Is uniformly distributed in the film Structure (hereinafter, also referred to as a cloud state).

[0321] That is, CAC-OS is a composite metal oxide having a structure in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 , or InO X1 are mixed. In this specification, for example, when the atomic ratio of In to the element M in the first region is greater than the atomic ratio of In to the element M in the second region, it is considered that the concentration of In in the first region is higher than that in the second region.

[0322] Note that IGZO is a general term and refers to a compound composed of In, Ga, Zn, and O in some cases. Representative examples include InGaO3(ZnO) (m1 is a natural number), or In m1 ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number). Crystalline compounds represented by are included.

[0323] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

[0324] On the other hand, CAC-OS relates to the material composition of metal oxides. CAC-OS refers to a structure in which, in a material composition containing In, Ga , Zn, and O, a region observed as nanoparticle-like with Ga as the main component in part and a region observed as nanoparticle-like with In as the main component in part are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is Manufacture is a secondary element.

[0325] Note that CAC-OS does not include a laminated structure of two or more types of films with different compositions. For example, a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga is not included. Not included.

[0326] Note that GaO X3 In the region where is the main component, and In X2 Zn Y2 O Z2 Or InO X1 Is In the region where is the main component, there may be cases where a clear boundary cannot be observed.

[0327] Note that instead of gallium, one or more selected from aluminum, yttrium, copper, vanadium, beryllium Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium When one or more selected from cesium, etc. are included, in part of CAC-OS, A region observed as nanoparticles mainly composed of the metal element and a region observed as nanoparticles mainly composed of In in part Are randomly dispersed in a mosaic pattern, respectively. This is what is meant.

[0328] CAC-OS can be formed by, for example, a sputtering method under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by a sputtering method, as the film-forming gas One or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used. Also, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable. For example, the flow rate ratio of oxygen gas is 0% or more and less than 30%, preferably ​​It is preferably 0% or more and 10% or less.

[0329] CAC-OS was measured using the θ / 2θ scan by the Out-of-plane method, which is a particular type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the Out-of-plane method, it has the characteristic that no distinct peak is observed. That is, it can be seen from the X-ray diffraction that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region. That is, it can be seen from the X-ray diffraction that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region. That is, it can be seen from the X-ray diffraction that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0330] Also, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness is observed in a ring shape, and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction. Also, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness is observed in a ring shape, and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction. Also, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness is observed in a ring shape, and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction. Also, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness is observed in a ring shape, and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction. Also, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam having a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness is observed in a ring shape, and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0331] Also, for example, in CAC-OS in In-Ga-Zn oxide, by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions where GaO is the main component and regions where In X3 is the main component, or regions where In is the main component, or regions where In X2 Zn Y2 O Z2 is the main component, or regions where InO X1 is the main component are unevenly distributed and mixed. It can be confirmed that it has a structure where they are unevenly distributed and mixed.

[0332] CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IG ZO compound. That is, CAC-OS has regions where GaO X3 and the like are the main components The region where In X2 Zn Y2 O Z2 or InO X1 is the main component, and the region where GaO is the main component are phase-separated from each other, and the regions with each element as the main component have a mosaic-like structure.

[0333] Here, the region where In X2 Zn Y2 O Z2 or InO X1 is the main component is a region with higher conductivity compared to the region where GaO X3 etc. are the main components. That is, when carriers flow through the region where In X2 Zn Y2 O Z2 or InO X1 is the main component, the conductivity as a metal oxide is exhibited. Therefore, when the regions where In Zn X2 O Y2 or InO Z2 is the main component are distributed in the metal oxide in a cloud-like manner, high field-effect mobility X1 (μ) can be realized. On the other hand, the region where GaO (μ) is a region with higher insulation compared to the region where In

[0334] [[ID=5,2]]Zn X3 etc. are the main components. That is, when the regions where GaO X2 Zn Y2 O Z2 or InO X1 is the main component are distributed in the metal oxide, the leakage current is suppressed, and a good switching X3 operation can be realized. Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO etc. and the conductivity caused by In

[0335] Zn X3 etc. In X2 Zn Y2 OZ2 or InO X1 The conductivity caused by the above and the like act complementarily By this, a high on-current (I on ), and a high field-effect mobility (μ) can be realized .

[0336] In addition, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is optimal for various semiconductor devices including displays.

[0337] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification .

[0338] (Embodiment 5) In this embodiment, another configuration example of the display device described in the above embodiment will be described

[0339] FIG. 32 shows a configuration example of the display device 10. The display device 10 has a display unit 17 provided on the substrate 14. The display unit 17 has a plurality of pixels 11 connected to the wiring GL and the wiring SL .

[0340] In addition, the display device 10 is provided with a plurality of TAB (Tape Automated Bondin g) tapes 121a and a plurality of TAB tapes 121b. The TAB tape 121a and the TAB tape 121b are provided at positions facing each other with the display unit 17 interposed therebetween . An integrated circuit in which a gate driver 12a or the like is formed is mounted on the TAB tape 121a, and an integrated circuit in which a gate driver 12b or the like is formed is mounted on the TAB tape 121b. The gate driver 12a and the gate driver 12b are connected to a plurality of wirings GL and have a function of supplying a selection signal to the wiring GL.

[0341] In addition, the display device 10 is provided with a plurality of printed circuit boards 131a and a plurality of TAB tapes 132 a, and a plurality of printed circuit boards 131b and a plurality of TAB tapes 132b are provided. The printed circuit board 131a and the TAB tape 132a, and the printed circuit board 1 31b and the TAB tape 132b are provided at positions facing each other with the display unit 17 interposed therebetween.

[0342] Each of the printed circuit boards 131a is connected to a plurality of TAB tapes 132a and has a function of distributing signals input from the outside to the TAB tapes 132a. Each of the printed circuit boards 131b is connected to a plurality of TAB tapes 132b and has a function of distributing signals input from the outside to the TAB tapes 132b. In addition, an integrated circuit in which a source driver 1 3a or the like is formed is mounted on the TAB tape 132a, and an integrated circuit in which a source driver 13b or the like is formed is mounted on the TAB tape 132b. The source driver 13a and the source driver 13b are connected to a plurality of wirings SL and have a function of supplying signals to the wirings SL.

[0343] When manufacturing a large-screen display panel capable of supporting 2K, 4K, 8K broadcasting, etc., as shown in FIG. 32, it is preferable to provide a plurality of printed circuit boards 131a and a plurality of printed circuit boards 131b. Thereby, the input of image data to the display device 10 can be easily performed.

[0344] Note that the gate driver 12a, the gate driver 12b, the source driver 13a, and the so urce driver 13b are of the COG (Chip On Glass) method, COF (Chip ​​​​It can also be provided on the substrate 14 by means such as (On Film).

[0345] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification. and implemented in combination.

[0346] (Embodiment 6) In this embodiment, an electronic device according to an aspect of the present invention will be described with reference to the drawings.

[0347] The electronic device exemplified below has a display device according to an aspect of the present invention in the display unit. Therefore, it is an electronic device with high resolution realized. Also, it is possible to achieve an electronic device in which high resolution and a large screen are compatible. and. can be achieved.

[0348] In the display unit of the electronic device according to an aspect of the present invention, for example, images having a resolution of full high vision, 4K2K, 8K4K, 16K8K, or higher can be displayed. Also, as the screen size of the display unit, it can be 20 inches or more in diagonal, or 30 inches or more in diagonal, or 50 inches or more in diagonal, 60 inches or more in diagonal, or 70 inches or more in diagonal.

[0349] Examples of the electronic device include relatively large-screen electronic devices such as television sets, desktop or notebook personal computers, monitors for computers, digital signage (electronic signboards), large game machines such as pachinko machines, and other electronic devices such as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, and audio playback devices.

[0350] ​​​​​​​An electronic device or a lighting device according to one aspect of the present invention can be incorporated along the inner wall or outer wall of a house or a building, or along the curved surface of the interior or exterior of an automobile.

[0351] The electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, images, information, etc. can be displayed on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

[0352] The electronic device according to one aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).

[0353] The electronic device according to one aspect of the present invention can have various functions. For example, functions of displaying various information ( still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying a date or time, etc., functions of executing various software (programs), a wireless communication function, a function of reading a program or data recorded on a recording medium, etc. can be provided.

[0354] An example of a television device is shown in Fig. 33(A). In the television device 7100, a display unit 7000 is incorporated in a housing 71 01. Here, a configuration in which the housing 71 01 is supported by a stand 7103 is shown.

[0355] The display device according to one aspect of the present invention can be applied to the display unit 7000. Thereby, the television The revision device 7100 can display high-resolution images. Also, the television device 7100 can display high-resolution images on a large screen.

[0356] The operation of the television device 7100 shown in Fig. 33(A) can be performed by the operation switches provided on the housing 7101 or by a separate remote control operation unit 7111. Alternatively, the display unit 700 0 may be provided with a touch sensor, and the operation may be performed by touching the display unit 7000 with a finger or the like. The remote control operation unit 7111 may have a display unit for displaying information output from the remote control operation unit 7111. The operation keys or touch panel provided on the remote control operation unit 7111 can be used to operate the channel and volume, and the video displayed on the display unit 7000 can be operated. displayed

[0357] Note that the television device 7100 has a configuration including a receiver and a modem, etc. The receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via a modem, one-way (from sender to receiver) or two-way communication (between sender and receiver, or between receivers, etc.) of information is also possible.

[0358] Fig. 33(B) shows a notebook personal computer 7200. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. The display unit 7000 is incorporated in the housing 7211.

[0359] The display device according to one aspect of the present invention can be applied to the display unit 7000. Thereby, the notebook​​ The laptop personal computer 7200 can display high-resolution images. Also, the laptop personal computer 7200 can display high-resolution images on a large screen.

[0360] Figures 33(C) and (D) show an example of digital signage.

[0361] The digital signage 7300 shown in Figure 33(C) includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it can have an LED lamp, operation keys (including a power switch or operation switches), connection terminals, various sensors, a microphone, etc.

[0362] Also, Figure 33(D) shows digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0363] In Figures 33(C) and (D), the display device according to an aspect of the present invention can be applied to the display unit 7000. As a result, the digital signage 7300 and the digital signage 7400 can display high-resolution images. Also, the digital signage 7300 and the digital signage 7400 can display high-resolution images on a large screen.

[0364] The larger the display unit 7000, the more information can be provided at once. Also, the larger the display unit 7000, the more easily it catches people's eyes, and for example, it can enhance the advertising effect. ​​​​​​​

[0365] By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but also it is preferable that the user can operate it intuitively. Further, when used for applications such as providing route information or traffic information, etc., the usability can be improved by intuitive operation. Moreover, as shown in FIGS. 33(C) and (D), the digital signage 7300 or the digital signage 7400 is preferably capable of being linked by wireless communication with an information terminal 7311 such as a smartphone possessed by the user or the information terminal 7411. For example, the advertisement information displayed on the display unit

[0366] 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Further, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7000 can be switched. Moreover, a game can also be executed on the digital signage 7300 or the digital signage 7400 using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). As a result, an unspecified number of users can participate in the game and enjoy it simultaneously. This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0367] EXAMPLE In this example, an 8K4K liquid crystal having a pixel area of diagonal 65 inches

[0368] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

Example

[0369] In this example, an 8K4K liquid crystal having a pixel area of diagonal 65 inches ​​​Regarding the data writing time of the crystal display module, the results of the approximate calculation will be described. Do.

[0370] In particular, in this embodiment, a large and high-resolution display using hydrogenated amorphous silicon (a-Si :H) in the semiconductor layer of the transistor was confirmed to be operable by applying one aspect of the present invention. Whether it can be operated was confirmed.

[0371] Note that the resolution of an 8K4K display is 7680 for the horizontal resolution and 4320 for the vertical resolution, which is extremely high resolution. Also, as an international standard for 8K4K displays, Rec ommendation ITU-R BT.2020-2 exists. In this standard, the driving method is the progressive method, and the frame frequency is a maximum of 120 Hz.

[0372] When using a transistor with low field-effect mobility in a large and high-resolution display module, the image rewriting operation may not be completed within the frame period, and it may not be possible to drive. At this time, the pixel region can be divided into a plurality (for example, four), and a scanning line driving circuit (also called a gate driver) and a signal line driving circuit (also called a source driver) can be arranged in each. Such a configuration can be applied. Such a configuration enables image rewriting during the frame period even when applying a transistor with low field-effect mobility by rewriting the image simultaneously in a plurality of pixel regions. This realizes the image rewriting during the frame period.

[0373] However, in a configuration that divides the pixel region, the cost increases due to the increase in ICs such as source drivers and gate drivers and the accompanying components, and the aperture ratio decreases due to the increase in the number of wirings. Increasing the frame area by implementing an IC, a circuit for synchronizing between divided pixel regions is separately required, and there are concerns such as a decrease in visibility due to the boundaries of the divided pixel regions being visible . Also, image processing for dividing the input image data is required, and there are concerns that a high-speed and large-scale image processing circuit is needed .

[0374] Therefore, in this embodiment, in addition to a configuration in which a selection signal is supplied to each gate line and pixels are selected one by one , a configuration in which a selection signal is simultaneously supplied to two or four gate lines and two or four adjacent pixels in the column direction are simultaneously selected was considered . The two or four pixels selected simultaneously are each connected to a different source line . That is, two or four source lines are arranged for each column . In this embodiment, the pixel layout in these configurations was used to estimate the data writing time .

[0375] In addition, in this embodiment, the case of using hydrogenated amorphous silicon and the case of using metal oxide for the semiconductor layer of the transistor were considered .

[0376] Regarding the case of using hydrogenated amorphous silicon for the semiconductor layer, the data writing time was estimated using pseudo-parameters obtained by changing the field-effect mobility, which is a design parameter, from the measured values of transistors fabricated using microcrystalline silicon [[ID=3!]]

[0377] Regarding the semiconductor layer using metal oxide, the following two types of configurations were considered. As the metal oxide , In-Ga-Zn oxide was used. The first type is a single-layer semiconductor layer made of a metal oxide in which the atomic number ratio of In, Ga, and Zn is In:Ga:Zn = 1:1:1 or in the vicinity thereof . This is the case of use. The second type is when a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Z n = 4:2:3 or in the vicinity thereof is used in the semiconductor layer in a stacked manner. Specifically, a CAC-OS (Cloud-Aligned Co mposite oxide semiconductor) film is used for the first metal oxide layer, and the second metal oxidation for the second metal oxide layer, a CAAC-OS (c-axis-aligned crystalline o xide semiconductor) film is assumed to be used.

[0378] The parameters of each layer used in this example are shown in Table 1. These are parameters assumed for a transistor using a metal oxide in the semiconductor layer, but in this example, the same parameters were used even when hydrogenated amorphous silicon con was used in the semiconductor layer.

[0379]

Table 1

[0380] <When one pixel is selected at a time> FIG. 34(A) is a block diagram showing the configuration of the display module used in this example. In this configuration, a selection signal is supplied to each gate line, and one pixel is selected at a time. Both the gate driver and the source driver are external. The same signal is supplied to the gate line from two gate driver ICs (Gate Driver IC (External)). A signal is supplied to the source line from one source driver IC (Source Driver IC (External)). The pixel region is not divided. The size of the pixel region is 65 inches diagonally, and the number of effective pixels is 7680×RGB(H)×432 ​ It is 0 (V).

[0381] Fig. 34 (B) shows the circuit diagram of pixel PIX (i, j). Pixel PIX (i, j) has a thin film transistor M1, a capacitive element C1, and a liquid crystal element LC. The gate of thin film transistor M1 is connected to gate line GL (i). One of the source and drain of thin film transistor M1 is connected to source line SL (j), and the other is connected to one electrode of capacitive element C1 and one electrode of liquid crystal element LC. The other electrode of capacitive element C1 is connected to wiring CS COM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0382] Figs. 35 (A) and (B) show the pixel layout of the display module when one pixel is selected at a time. Fig. 35 (A) is a top view of the stacked structure from gate line GL (i) to the pixel electrode, seen from the pixel electrode side. Fig. 35 (B) is a top view of Fig. 35 (A) excluding the pixel electrode (Pixel electrode).

[0383] The pixel size is 62.5 μm × 187.5 μm. Thin film transistor M1 is a channel-etch type transistor with a bottom gate top contact structure. The channel length L of thin film transistor M1 is 4 μm, the channel width W is 8 μm, and the LDD region overlapping with the gate (hereinafter, overlap LDD region L ov ) is 2 μm. The width of gate line GL (i) is 10 μm, and the width of wiring CSCOM is 3.5 μm. The width of source line SL (j) is 10 μm, but at the cross section with other wirings (gate line GL (i) and wiring CSCOM), it is 4 μm. The aperture ratio is 45.6%.

[0384] First, with reference to FIG. 36, an estimate of the data writing time when a metal oxide is used for the semiconductor layer will be described. This will be described.

[0385] The parasitic resistance and parasitic capacitance were extracted from the pixel layout of FIG. 35(A), and the charging time of the gate line of the pixel, the source line, and the charging time of the pixel were estimated by changing only the parameter of the field effect mobility of the transistor. In this embodiment, the data writing time corresponds to the charging time of the gate line and the sum of the charging times of the source line and the pixel. Further, in this embodiment, the charging time of the gate line is the time until the potential of the gate line reaches 75% of the maximum value of the input voltage, and the charging times of the source line and the pixel are the times until the potential of the source line reaches 99% of the maximum value of the input voltage. by changing only the parameter of the field effect mobility of the transistor, the charging time of the gate line of the pixel, the source line, and the charging time of the pixel were estimated. In this embodiment, the data writing time corresponds to the charging time of the gate line and the sum of the charging times of the source line and the pixel. Further, in this embodiment, the charging time of the gate line is the time until the potential of the gate line reaches 75% of the maximum value of the input voltage, and the charging times of the source line and the pixel are the times until the potential of the source line reaches 99% of the maximum value of the input voltage. In this embodiment, the data writing time corresponds to the charging time of the gate line and the sum of the charging times of the source line and the pixel. Further, in this embodiment, the charging time of the gate line is the time until the potential of the gate line reaches 75% of the maximum value of the input voltage, and the charging times of the source line and the pixel are the times until the potential of the source line reaches 99% of the maximum value of the input voltage. In this embodiment, the data writing time corresponds to the charging time of the gate line and the sum of the charging times of the source line and the pixel. Further, in this embodiment, the charging time of the gate line is the time until the potential of the gate line reaches 75% of the maximum value of the input voltage, and the charging times of the source line and the pixel are the times until the potential of the source line reaches 99% of the maximum value of the input voltage. In this embodiment, the charging time of the gate line is the time until the potential of the gate line reaches 75% of the maximum value of the input voltage, and the charging times of the source line and the pixel are the times until the potential of the source line reaches 99% of the maximum value of the input voltage. In this embodiment, the charging time of the gate line is the time until the potential of the gate line reaches 75% of the maximum value of the input voltage, and the charging times of the source line and the pixel are the times until the potential of the source line reaches 99% of the maximum value of the input voltage. In this embodiment, the charging time of the gate line is the time until the potential of the gate line reaches 75% of the maximum value of the input voltage, and the charging times of the source line and the pixel are the times until the potential of the source line reaches 99% of the maximum value of the input voltage.

[0386] Also, here, the field effect mobility when a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner is set to 1, and a normalized value (normalized mobility) is used. The size of the transistor has not been changed. The load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, the parasitic capacitance Csl of the source line is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF. In this embodiment, the parasitic capacitance Cpix of the pixel includes the holding capacitance of the capacitive element, the capacitance of the liquid crystal element, and the parasitic capacitance of node A. In this embodiment, node A is the node to which the source or drain of the transistor, one electrode of the capacitive element, and one electrode of the liquid crystal element are connected in each pixel. Also, here, the field effect mobility when a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner is set to 1, and a normalized value (normalized mobility) is used. The size of the transistor has not been changed. The load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, the parasitic capacitance Csl of the source line is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF. In this embodiment, the parasitic capacitance Cpix of the pixel includes the holding capacitance of the capacitive element, the capacitance of the liquid crystal element, and the parasitic capacitance of node A. In this embodiment, node A is the node to which the source or drain of the transistor, one electrode of the capacitive element, and one electrode of the liquid crystal element are connected in each pixel. Also, here, the field effect mobility when a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner is set to 1, and a normalized value (normalized mobility) is used. The size of the transistor has not been changed. The load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, the parasitic capacitance Csl of the source line is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF. In this embodiment, the parasitic capacitance Cpix of the pixel includes the holding capacitance of the capacitive element, the capacitance of the liquid crystal element, and the parasitic capacitance of node A. In this embodiment, node A is the node to which the source or drain of the transistor, one electrode of the capacitive element, and one electrode of the liquid crystal element are connected in each pixel. Also, here, the field effect mobility when a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner is set to 1, and a normalized value (normalized mobility) is used. The size of the transistor has not been changed. The load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, the parasitic capacitance Csl of the source line is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF. In this embodiment, the parasitic capacitance Cpix of the pixel includes the holding capacitance of the capacitive element, the capacitance of the liquid crystal element, and the parasitic capacitance of node A. In this embodiment, node A is the node to which the source or drain of the transistor, one electrode of the capacitive element, and one electrode of the liquid crystal element are connected in each pixel. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, the parasitic capacitance Csl of the source line is 147 pF, the parasitic capacitance Cpix of the pixel is 216.6 fF. In this embodiment, the parasitic capacitance Cpix of the pixel includes the holding capacitance of the capacitive element, the capacitance of the liquid crystal element, and the parasitic capacitance of node A. In this embodiment, node A is the node to which the source or drain of the transistor, one electrode of the capacitive element, and one electrode of the liquid crystal element are connected in each pixel. In this embodiment, node A is the node to which the source or drain of the transistor, one electrode of the capacitive element, and one electrode of the liquid crystal element are connected in each pixel.

[0387] In FIG. 36, the result with a normalized mobility of 1 corresponds to the case where a metal oxide with an atomic ratio of In, Ga, and Zn of In :Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner (denoted as "CAC\CAAC" in FIG. 36). At this time, the data writing time is 3.55 μs, which is shorter than the 3.85 μs of one horizontal period during 60 Hz driving, and it is estimated that it can operate with 60 Hz driving. Also, the data writing time is longer than the 1.93 μs of one horizontal period during 120 Hz driving, and it is estimated that it is difficult to operate with 120 Hz driving.

[0388] In FIG. 36, the result with a normalized mobility of 0.5 corresponds to the case where a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 1:1:1 or in the vicinity thereof is used for the semiconductor layer as a single layer (denoted as "IGZO(111)" in FIG. 36). At this time, the data writing time is 4.17 μs, which is longer than the 3.85 μs of one horizontal period during 60 Hz driving, and it is estimated that it is difficult to operate not only with 120 Hz driving but also with 60 Hz driving.

[0389] Next, with reference to FIG. 37, an estimation of the data writing time when hydrogenated amorphous silicon is used for the semiconductor layer will be described.

[0390] Parasitic resistance and parasitic capacitance are extracted from the pixel layout of FIG. 35(A), and by changing the field-effect mobility, which is a design parameter, from the measured values of transistors fabricated using microcrystalline silicon, the charging time of the gate line of the pixel and the charging time of the source line and the pixel are estimated. The size of the transistor and the magnitude of the holding capacitance are not changed. Actually, hydrogenated amorphous silicon ​​​​​​​​​​ When using re-con in the semiconductor layer, a larger transistor size and holding capacitance are necessary, so the data write time needs to be longer than the results of this example. The load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 255 pF, the parasitic resistance Rsl of the source line is 5.80 kΩ, the parasitic capacitance Csl of the source line is 147 pF, and the parasitic capacitance Cpix of the pixel is 216.6 fF. .

[0391] In FIG. 37, the results of the field-effect mobility being 0.6, 0.7, 0.8 [cm 2 / Vs] correspond to the case where hydrogenated amorphous silicon is used for the semiconductor layer. At this time, the data write times are 19.66 μs, 16.19 μs, and 13.81 μs respectively, which are longer than the 1.93 μs of one horizontal period during 120 Hz driving and the 3.85 μs of one horizontal period during 60 Hz driving. It is estimated that it is difficult to operate not only at 120 Hz driving but also at 60 Hz driving. .

[0392] <When two pixels are selected simultaneously> FIG. 38(A) is a block diagram showing the configuration of the display module used in this example. In this configuration, selection signals are simultaneously supplied to two gate lines, and two pixels adjacent in the column direction are selected simultaneously. Both the gate driver and the source driver are external. The same signal is supplied to the gate line from two gate driver ICs. The gate line GL0( i) is electrically connected to the gate line GL(i) and the gate line GL(i + 1), and the pixels in two rows, the i-th row and the (i + 1)-th row, are driven simultaneously. The source line is connected to one source ​​​​A signal is supplied from the driver IC. The pixel region is not divided. The size of the pixel region is 65 inches on the diagonal, and the number of effective pixels is 7680×RGB(H)×4320(V).

[0393] Fig. 38(B) shows the circuit diagrams of pixel PIX(i,j) and pixel PIX(i+1,j). .

[0394] First, the configuration of pixel PIX(i,j) will be described. Pixel PIX(i,j) has transistor M1, capacitor element C1, and liquid crystal element LC. The gate of transistor M1 is connected to gate line GL(i). One of the source and drain of transistor M1 is connected to source line SL1(j), and the other is connected to one electrode of capacitor element C1 and one electrode of liquid crystal element LC. The other electrode of capacitor element C1 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM. .

[0395] Next, the configuration of pixel PIX(i+1,j) will be described. Pixel PIX(i+1,j) has transistor M2, capacitor element C2, and liquid crystal element LC. The gate of transistor M2 is connected to gate line GL(i+1). One of the source and drain of transistor M2 is connected to source line SL2(j), and the other is connected to one electrode of capacitor element C2 and one electrode of liquid crystal element LC. The other electrode of capacitor element C2 is connected to wiring CSCOM. The other electrode of liquid crystal element LC is connected to wiring TCOM.

[0396] Figs. 39(A) and (B) show the display module when two pixels are selected simultaneously. ​​​​​​​​​​​​The pixel layout is shown. FIG. 39(A) is a top view of the stacked structure from the gate line GL(i) to the pixel electrode, as seen from the pixel electrode side. FIG. 39(B) is a top view of FIG. 39(A) with the pixel electrode removed. The pixel size is 62.5 μm × 187.5 μm. Transistor M1 is a channel etch type transistor with a bottom gate top contact structure. The channel length L of transistor M1 is 4 μm, the channel width W is 8 μm, and the overlap LDD region L is 2 μm

[0397] is. The width of the gate line GL(i) is 10 μm, and the width of the wiring CSCOM is 3.5 μm. The widths of the source line SL1(j) and the source line SL2(j) are both 10 μm, but at the cross section with the gate line, both are 4 μm. The aperture ratio is 37.3%. ov

[0398] First, with reference to FIG. 40, an estimate of the data write time when a metal oxide is used for the semiconductor layer will be described.

[0399] Parasitic resistance and parasitic capacitance were extracted from the pixel layout of FIG. 39(A), and by changing only the parameter of the field effect mobility of the transistor, the charging time of the gate line of the pixel and the charging time of the source line and the pixel were estimated. Here, a normalized value (normalized mobility) with the field effect mobility when a metal oxide with an atomic ratio of In, Ga, and Zn of In: Ga:Zn = 4:2:3 or in the vicinity thereof was used as the semiconductor layer by stacking was used. The size of the transistor was not changed. The load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 364 pF, and the parasitic resistance of the source line is 3.60 kΩ, the parasitic capacitance Cgl of the gate line is 364 pF, and the parasitic resistance of the source line ​​​​​​​​The anti-Rsl is 4.83 kΩ, the parasitic capacitance Csl of the source line is 182 pF, and the parasitic capacitance Cp of the pixel ix is 191 fF.

[0400] In FIG. 40, the result with a normalized mobility of 1 corresponds to the case where a metal oxide with an atomic ratio of In :Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner (denoted as "CAC\CAAC" in FIG. 40). At this time, the data writing time is 3.49 μs, which is shorter than 3.83 μs of one horizontal period during 120 Hz driving, and it is estimated that it can operate at 12 0 Hz driving.

[0401] In FIG. 40, the result with a normalized mobility of 0.5 corresponds to the case where a metal oxide with an atomic ratio of In :Ga:Zn = 1:1:1 or in the vicinity thereof is used for the semiconductor layer in a single layer (denoted as "IGZO(111)" in FIG. 40). At this time, the data writing time is 4.02 μs, which is shorter than 7.66 μs of one horizontal period during 60 Hz driving, and it is estimated that it can operate at 60 Hz driving. Also, this data writing time is longer than 3.83 μs of one horizontal period during 120 Hz driving, and it is estimated that it is difficult to operate at 120 Hz driving.

[0402] In FIG. 40, since the same selection signal is supplied to two gate lines, the length of one horizontal period can be doubled compared to FIG 36. Therefore, it becomes easy to operate a high-resolution display device using a transistor with a low field-effect mobility.

[0403] From the results of FIGS. 36 and 40, when CAC\CAAC is used for the semiconductor layer, for each pixel The operation at 120 Hz driving, which was difficult to achieve with a configuration that writes one by one, was shown to be achievable by adopting a configuration that writes to two pixels simultaneously. It was also shown that the operation at 60 Hz driving, which was difficult to achieve with a configuration that writes to each pixel one by one, was achievable by adopting a configuration that writes to two pixels simultaneously when using IGZO(111) as the semiconductor layer, based on the results of FIGS. 36 and 40.

[0404] Next, with reference to FIG. 41, an estimation of the data writing time will be described when using hydrogenated amorphous silicon as the semiconductor layer. The parasitic resistance and parasitic capacitance were extracted from the pixel layout of FIG. 39(A), and by changing the field-effect mobility, which is a design parameter, from the measured values of transistors fabricated using microcrystalline silicon, the charging time of the gate line of the pixel and the charging time of the source line and the pixel were estimated. The size of the transistor and the magnitude of the holding capacitance were not changed. The load of the entire pixel region is as follows. The parasitic resistance of the gate line Rgl is 3.60 kΩ, the parasitic capacitance of the gate line Cgl is 364 pF, the parasitic resistance of the source line Rsl is 4.83 kΩ, the parasitic capacitance of the source line Csl is 182 pF, and the parasitic capacitance of the pixel Cpix is 191 fF. The results in FIG. 41 with field-effect mobilities of 0.6, 0.7, 0.8 [cm

[0405] / Vs] correspond to the case of using hydrogenated amorphous silicon as the semiconductor layer. At this time, the data writing times are 17.98 μs, 14.89 μs, and 12.78 μs respectively, which are longer than the 1 horizontal period of 3.83 μs at 120 Hz driving and the 1 horizontal period of 7.66 μs at 60 Hz driving.

[0406] The parasitic resistance and parasitic capacitance were extracted from the pixel layout of FIG. 39(A), and by changing the field-effect mobility, which is a design parameter, from the measured values of transistors fabricated using microcrystalline silicon, the charging time of the gate line of the pixel and the charging time of the source line and the pixel were estimated. The size of the transistor and the magnitude of the holding capacitance were not changed. The load of the entire pixel region is as follows. The parasitic resistance of the gate line Rgl is 3.60 kΩ, the parasitic capacitance of the gate line Cgl is 364 pF, the parasitic resistance of the source line Rsl is 4.83 kΩ, the parasitic capacitance of the source line Csl is 182 pF, and the parasitic capacitance of the pixel Cpix is 191 fF. In FIG. 41, the results with field-effect mobilities of 0.6, 0.7, 0.8 [cm / Vs] correspond to the case of using hydrogenated amorphous silicon as the semiconductor layer. At this time, the data writing times are 17.98 μs, 14.89 μs, and 12.78 μs respectively, which are longer than the 1 horizontal period of 3.83 μs at 120 Hz driving and the 1 horizontal period of 7.66 μs at 60 Hz driving. The parasitic resistance of the gate line Rgl is 3.60 kΩ, the parasitic capacitance of the gate line Cgl is 364 pF, the parasitic resistance of the source line Rsl is 4.83 kΩ, the parasitic capacitance of the source line Csl is 182 pF, and the parasitic capacitance of the pixel Cpix is 191 fF.

[0407] In FIG. 41, the results with field-effect mobilities of 0.6, 0.7, 0.8 [cm 2 / Vs] correspond to the case of using hydrogenated amorphous silicon as the semiconductor layer. At this time, the data writing times are 17.98 μs, 14.89 μs, and 12.78 μs respectively, which are longer than the 1 horizontal period of 3.83 μs at 120 Hz driving and the 1 horizontal period of 7.66 μs at 60 Hz driving. ​​​​ It is estimated that it is long and difficult to operate not only at 120 Hz driving but also at 60 Hz driving. .

[0408] From the results of Fig. 41, when hydrogenated amorphous silicon is used for the semiconductor layer, unlike the case where metal oxide is used for the semiconductor layer (see the results of Fig. 40), even with a configuration in which two pixels are written simultaneously, it is estimated that it is difficult to operate at 60 Hz driving.

[0409] <When four pixels are selected simultaneously> The block diagram showing the configuration of the display module used in this embodiment is the same as Fig. 1 except that only one of the source drivers 1 to 3 is provided. The size of the pixel region is 65 diagonal inches, and the number of effective pixels is 7680×RGB(H)×4320(V). Also, the circuit diagram of the pixel provided in the pixel region is the same as Fig. 7, and the pixel layout is the same as Fig. 8(A), ( B). The pixel size is 62.5 μm × 187.5 μm. The transistors provided in the pixel are

[0410] each a channel etch type transistor with a bottom gate top contact structure and have the same size. Specifically, the channel length L of each transistor provided in the pixel is all 4 μm, the channel width W is 8 μm, and the overlap LDD region L is 3 μm ov . The width of each gate line is 10 μm, and the width of each wiring CS is 5 μm. The width of each source line is 4 μ m. The aperture ratio is 29%.

[0411] First, using Fig. 42, the estimation of the data writing time when metal oxide is used for the semiconductor layer will be described. .

[0412] The parasitic resistance and parasitic capacitance were extracted from the pixel layout of FIG. 8, and only the mobility parameter was changed to estimate the charging time of the gate line of the pixel and the charging time of the source line and the pixel. Here, the field-effect mobility when a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner was standardized using the value (normalized mobility) with a value of 1. The size of the transistor was not changed. The total load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.53 kΩ, the parasitic capacitance Cgl of the gate line is 518 pF, the parasitic resistance Rsl of the source line is 10.28 kΩ, the parasitic capacitance Csl of the source line is 170 pF, and the parasitic capacitance Cpix of the pixel is 99.7 fF.

[0413] In FIG. 42, the result with a normalized mobility of 1 corresponds to the case where a metal oxide with an atomic ratio of In, Ga, and Zn of In :Ga:Zn = 4:2:3 or in the vicinity thereof is used for the semiconductor layer in a stacked manner (denoted as "CAC\CAAC" in FIG. 42). At this time, the data writing time is 5.05 μs, which is shorter than the 7.61 μs of one horizontal period during 120 Hz driving, and it is estimated that it can operate at 12 0 Hz driving.

[0414] In FIG. 42, the result with a normalized mobility of 0.5 corresponds to the case where a metal oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = 1:1:1 or in the vicinity thereof is used for the semiconductor layer in a single layer (denoted as "IGZO(111)" in FIG. 42). At this time, the data writing time is 5.22 μs, which is shorter than the 7.61 μs of one horizontal period during 120 Hz driving and it is estimated that it can operate at 120 Hz driving.

[0415] ​​​​In FIG. 42, since the same selection signal is supplied to the four gate lines, the length of one horizontal period can be made four times that in FIG. 36. Therefore, it becomes easy to operate a high-resolution display device using a transistor with low field-effect mobility.

[0416] From the results of FIG. 42, by adopting a configuration in which four pixels are written simultaneously, even when IGZO(111) with lower mobility than CAC\CAAC is used for the semiconductor layer, operation at 120 Hz driving was shown to be achievable.

[0417] Next, with reference to FIG. 43, an estimation of the data writing time when hydrogenated amorphous silicon is used for the semiconductor layer will be described.

[0418] Parasitic resistance and parasitic capacitance were extracted from the pixel layout of FIG. 8, and by changing the field-effect mobility, which is a design parameter, from the measured values of transistors fabricated using microcrystalline silicon, the charging time of the gate line of the pixel and the charging time of the source line and the pixel were estimated. The size of the transistor and the size of the holding capacitance were not changed. The load of the entire pixel region is as follows. The parasitic resistance Rgl of the gate line is 3.53 kΩ, the parasitic capacitance Cgl of the gate line is 5 18 pF, the parasitic resistance Rsl of the source line is 10.28 kΩ, the parasitic capacitance Csl of the source line is 1 70 pF, and the parasitic capacitance Cpix of the pixel is 99.7 fF.

[0419] In FIG. 43, the results with field-effect mobilities of 0.6, 0.7, 0.8 [cm 2 / Vs] correspond to the case where hydrogenated amorphous silicon is used for the semiconductor layer. At this time, the data writing times are 11.66 μs, 10.06 μs, and 9.01 μs, respectively, for 60 Hz driving. ​​​​​​It is estimated that it can operate at 60 Hz, with a horizontal period shorter than 15.3 μs during driving. Also, it is estimated that the data writing time is longer than 7.61 μs of one horizontal period during 120 Hz driving, making it difficult to operate at 120 Hz.

[0420] From the results of FIGS. 37, 41, and 43, when hydrogenated amorphous silicon is used for the semiconductor layer, it is shown that by applying a configuration for simultaneously writing four pixels, operation at 60 Hz can be achieved.

[0421] As described above, by applying one aspect of the present invention, even when hydrogenated amorphous silicon is used for the semiconductor layer of the transistor, it is estimated that a large-sized and high-resolution display such as a 65-inch diagonal and 8K4K resolution can be operated.

Explanation of Reference Numerals

[0422] 10 Display device 11 Pixel 12a Gate driver 12b Gate driver 13 Source driver 13a Source driver 13b Source driver 14 Substrate 15 Substrate 16 Reference voltage generation circuit 16a Reference voltage generation circuit 16b Reference voltage generation circuit 17 Display unit 18a Protection circuit 18b Protection circuit 19a Protection circuit 19b Protection circuit 20 Liquid crystal element 21 Conductive layer 22 Liquid crystal 23 Conductive layer 24a Alignment film​​​​​ 24b Alignment film 26 Insulating layer 30 Transistor 31 Conductive layer 31a Conductive layer 32 Semiconductor layer 32p Semiconductor layer 33 Conductive layer 33a Conductive layer 33b Conductive layer 33c Conductive layer 34 Insulating layer 35 Impurity semiconductor layer 37 Semiconductor layer 38 Opening 39a Polarizing plate 39b Polarizing plate 41 Coloring layer 42 Light-shielding layer 50 Light 51 Conductive layer 52 Conductive layer 53 Conductive layer 54 Conductive layer 55 Conductive layer 60 Capacitor element 71 Opening 72 Opening 73 Opening 74 Opening 81 Insulating layer 82 Insulating layer 84 Insulating layer 90 Backlight unit 121a TAB tape 121b TAB tape 131a Printed circuit board 131b Printed circuit board 132a TAB tape 132b TAB tape 200a Transistor 200b Transistor 200c Transistor 200d Transistor 200e Transistor 200f Transistor 211 Insulating layer 212 Insulating layer Insulating layer 212a Insulating layer 212b Insulating layer 212c Insulating layer 212d Insulating layer 215 Insulating layer 216 Insulating layer 216a Conductive layer 221 Conductive layer 222a Conductive layer 222a_1 Conductive layer 222a_2 Conductive layer 222a_3 Conductive layer 222b Conductive layer 222b_1 Conductive layer 222b_2 Conductive layer 222b_3 Conductive layer 223 Insulating layer 224 Semiconductor layer 231 Semiconductor layer 231_1 Semiconductor layer 231_2 Drain region 231d Channel formation region 231i Source region 231s Opening 235 Opening 236a Opening 236b Opening 237 Opening 238a Opening 238b Moving mechanism 812 Moving mechanism 813 Stage 815 Ball screw mechanism 816 Laser oscillator 820 Optical system unit 821 Mirror 822 Micro lens array 823 Mask 824 Laser light 825 Laser light 826 Laser beam 827 Substrate 830 Amorphous silicon layer 840 Polycrystalline silicon layer 841 7000 Display Unit 7100 Television Device 7101 Housing 7103 Stand 7111 Remote Control Unit 7200 Notebook Personal Computer 7211 Housing 7212 Keyboard 7213 Pointing Device 7214 External Connection Port 7300 Digital Signage 7301 Housing 7303 Speaker 7311 Information Terminal 7400 Digital Signage 7401 Column 7411 Information Terminal

Claims

1. A display device in which a plurality of pixels are arranged in a matrix, a first source line having a region extending in a first direction, a second source line having a region extending in the first direction, a first gate line having a region extending in a second direction intersecting the first direction, a second gate line having a region extending in the second direction, a first wiring and a second wiring having a region extending in the second direction in a plan view and having a region functioning as a capacitive electrode, a first pixel having a first transistor electrically connected to the first source line and the first gate line, a first capacitive element electrically connected to the first wiring, and a first pixel electrode, a second pixel provided in the same column as the first pixel and having a second transistor electrically connected to the second source line and the second gate line, a second capacitive element electrically connected to the second wiring, and a second pixel electrode, wherein the first pixel and the second pixel are provided adjacent to each other in the first direction, in a plan view, the second source line has a region located between the first source line and the first pixel electrode and a region located between the first source line and the second pixel electrode, a semiconductor layer having a channel formation region of the first transistor is electrically connected to the first source line via a first conductive layer, in a plan view, the first conductive layer has a shape extending in the first direction, the first source line has a first region that is partially widened, the first region has an overlap with the first conductive layer, in a plan view, the first gate line is provided at a position closer to the first wiring than the second wiring between the first wiring and the second wiring, in a plan view, the second wiring is provided at a position closer to the second gate line than the first gate line between the first gate line and the second gate line, in a plan view, each of the first wiring and the second wiring has a second region that is partially widened, the second region of the first wiring has a region overlapping with a second conductive layer, the second conductive layer is electrically connected to the semiconductor layer and the first pixel electrode, a display device.

2. A display device in which a plurality of pixels are arranged in a matrix, a first source line having a region extending in a first direction, A second source line having a region extending in the first direction, A first gate line having a region extending in a second direction intersecting the first direction, A second gate line having a region extending in the second direction, A first wiring and a second wiring having a region extending in the second direction in a plan view and having a region functioning as a capacitive electrode, A first pixel having a first transistor electrically connected to the first source line and the first gate line, a first capacitive element electrically connected to the first wiring, and a first pixel electrode, A second pixel provided in the same column as the first pixel and having a second transistor electrically connected to the second source line and the second gate line, a second capacitive element electrically connected to the second wiring, and a second pixel electrode, The first pixel and the second pixel are provided adjacent to each other in the first direction, In a plan view, the second source line has a region located between the first source line and the first pixel electrode and a region located between the first source line and the second pixel electrode, A semiconductor layer having a channel formation region of the first transistor is electrically connected to the first source line via a first conductive layer, In a plan view, the first conductive layer has a shape extending in the first direction, In a plan view, the first conductive layer has a region located between the first source line and the second source line, The first source line has a first region with a partially widened width, The first region has an overlap with the first conductive layer, In a plan view, the first gate line is provided between the first wiring and the second wiring at a position closer to the first wiring than the second wiring, In a plan view, the second wiring is provided between the first gate line and the second gate line at a position closer to the second gate line than the first gate line, In a plan view, each of the first wiring and the second wiring has a second region with a partially widened width, The second region of the first wiring has a region overlapping with a second conductive layer, The second conductive layer is electrically connected to the semiconductor layer and the first pixel electrode, a display device.

3. In Claim 1 or 2, The second conductive layer has the same material as the first source line, a display device.

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