Semiconductor device

Abstract

To provide a liquid crystal display device capable of low power consumption.SOLUTION: A liquid crystal display device has a plurality of pixels on a display unit and displays in a plurality of frame periods. A frame period includes a write period and a hold period. After inputting image signals on each of the plurality of pixels during a write period, transistors of the plurality of pixels are turned off, and an image signal is held for at least 30 seconds during a hold period. The pixels include a semiconductor layer including an oxide semiconductor layer. The oxide semiconductor layer has a carrier concentration of less than 1×1014 / cm3.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a liquid crystal display device. Or, it relates to an electronic apparatus including the liquid crystal display device.

Background Art

[0002] Thin film transistors formed on a flat plate such as a glass substrate, as typified by liquid crystal display devices, are fabricated using amorphous silicon or polycrystalline silicon. Although thin film transistors using amorphous silicon have a low field-effect mobility, they can respond to the enlargement of the area of the glass substrate. On the other hand, thin film transistors using crystalline silicon have a high field-effect mobility, but require a crystallization process such as laser annealing and do not necessarily adapt to the enlargement of the area of the glass substrate. have the characteristics described above.

[0003]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] ​​​Thin film transistors using an oxide semiconductor in the channel region have higher field-effect mobility than thin film transistors using amorphous silicon in the channel region. Pixels equipped with thin film transistors formed using such an oxide semiconductor are expected to be applied to display devices such as liquid crystal display devices.

[0006] Each pixel of a liquid crystal display device is provided with a holding capacitor for holding a voltage for controlling the alignment of liquid crystal elements. The off-current of the thin film transistor is a factor that determines the size of the holding capacitor. By reducing the off-current, the period during which the voltage can be held by the holding capacitor can be lengthened, which is important for achieving low power consumption when displaying still images and the like.

[0007] The off-current described in this specification refers to the current flowing between the source and the drain when the thin film transistor is in the off state (also referred to as the non-conducting state). In an n-channel thin film transistor (for example, with a threshold voltage of about 0 to 2 V), it refers to the current flowing between the source and the drain when the voltage applied between the gate and the source is a negative voltage.

[0008] In addition, in liquid crystal display devices with further added value such as 3D displays and 4K2K displays, the area per pixel is expected to be reduced, while a liquid crystal display device having pixels with an improved aperture ratio is desired. In order to improve the aperture ratio, it is important to reduce the area of the holding capacitor. As a result, reduction of the off-current of the thin film transistor is desired.

[0009] Therefore, one aspect of the present invention is in a pixel including a thin film transistor using an oxide semiconductor. One of the problems is to provide a liquid crystal display device capable of reducing the off-current of thin film transistors. Let it be so.

Means for Solving the Problem

[0010] One aspect of the present invention is a liquid crystal display device having a plurality of pixels in a display unit and performing display in a plurality of frame periods. The frame period has a writing period and a holding period. In the writing period, after an image signal is input to each of the plurality of pixels, in the holding period, the transistors included in the plurality of pixels are turned off, and the image signal is held for at least 30 seconds. That is, it is a liquid crystal display device. In the writing period, after an image signal is input to each of the plurality of pixels, in the holding period, the transistors included in the plurality of pixels are turned off, and the image signal is held for at least 30 seconds. That is, it is a liquid crystal display device. That is, it is a liquid crystal display device.

[0011] One aspect of the present invention is a liquid crystal display device having a plurality of pixels in a display unit and performing display in a plurality of frame periods. The frame period has a writing period and a holding period. In the writing period, after an image signal of a voltage with a plurality of polarity inversions is input to the pixels, in the holding period, the transistors of the plurality of pixels are turned off, and the image signal is held for at least 30 seconds. That is, it is a liquid crystal display device. In the writing period, after an image signal of a voltage with a plurality of polarity inversions is input to the pixels, in the holding period, the transistors of the plurality of pixels are turned off, and the image signal is held for at least 30 seconds. That is, it is a liquid crystal display device. That is, it is a liquid crystal display device.

[0012] In one aspect of the present invention, the polarity of the voltage supplied to the plurality of pixels in the holding period may be the polarity of the image signal of the voltage with a plurality of polarity inversions supplied in the writing period, which is the polarity of the image signal supplied last. That is, it may be a liquid crystal display device. That is, it may be a liquid crystal display device.

[0013] In one aspect of the present invention, the transistor has a semiconductor layer made of an oxide semiconductor, and the oxide semiconductor may be a liquid crystal display device having a carrier concentration of less than 1×10 / cm 14 / cm 3 That is, it may be a liquid crystal display device.

[0014] In one aspect of the present invention, the off-current per 1 μm channel width of the transistor may be a liquid crystal display device that is 1×1 0 -17 A or less.

Advantages of the Invention

[0015] In a pixel including a thin film transistor using an oxide semiconductor, it is possible to reduce the off-current. Therefore, it is possible to extend the period during which the voltage can be held by the holding capacitor, and a liquid crystal display device capable of achieving low power consumption when displaying a still image or the like can be obtained. Further, by improving the aperture ratio, a liquid crystal display device having a high-definition display section can be obtained. and so on. etc. can be made. Further, by improving the aperture ratio, a liquid crystal display device having a high-definition display section can be made. etc.

Brief Description of the Drawings

[0016]

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Modes for Carrying Out the Invention

[0017] Embodiments and examples of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention It should not be construed as being limited to the descriptions of the embodiments and examples shown below. In the following In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and the repeated description thereof is omitted.

[0018] In addition, in each drawing described in this specification, the size of each component, the thickness of each layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0019] The terms "first", "second", "third", etc. used in this specification are attached to avoid confusion of components and are not numerically limiting. Therefore, for example, " the first" can be appropriately replaced with "

[0020] the second" or " "the third" and so on for explanation. An example of configuring a pixel of a liquid crystal display device using a thin film transistor will be described below. In this embodiment, as an example, a thin film transistor (hereinafter also referred to as TFT) that a pixel in a liquid crystal display device has and an electrode (simply referred to as a pixel electrode) that functions as the pixel electrode connected to the TFT are shown and described. Note that a pixel refers to each element provided for each pixel of the display device, for example, a thin film transistor, an electrode that functions as a pixel electrode, and an element group composed of elements for controlling display by electrical signals such as wiring. Note that a pixel may include a color filter or the like, and one pixel may be regarded as one color element capable of controlling brightness. Therefore, as an example, in the case of a color display device composed of RGB color elements, the minimum unit of an image is composed of three pixels: an R pixel, a G pixel, and a B pixel.Next, an image can be obtained by a plurality of pixels. However, one aspect of the present invention is not limited to a display device for color display, and may be a display device for monochrome display instead.

[0021] In addition, when it is described that A and B are connected, it shall include the case where A and B are electrically connected and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0022] First, a top view of the pixel is shown in FIG. 1(A). Note that the structure of the TFT shown in FIG. 1(A) shows a bottom gate type structure as an example. In FIG. 1(A), on the side opposite to the oxide semiconductor layer that becomes the channel region when viewed from the wiring that becomes the gate, a wiring layer that becomes the source electrode and the drain electrode of the TFT is shown, which is a so-called reverse staggered type configuration.

[0023] The pixel 100 shown in FIG. 1(A) has a first wiring 101 that functions as a scanning line, a second wiring 102A that functions as a signal line, an oxide semiconductor layer 103, a capacitance line 104, and a pixel electrode 105. In addition, it has a third wiring 102B for electrically connecting the oxide semiconductor layer 103 and the pixel electrode 105, and a thin film transistor 106 is formed. The first wiring 101 is also a wiring that functions as the gate of the thin film transistor 106. The second wiring 102A is also a wiring that functions as one of the source electrode or the drain electrode and one of the electrodes of the holding capacitor. The third wiring 102B is also a wiring that functions as the other of the source electrode or the drain electrode. The capacitance line 104 is a wiring that functions as the other electrode of the holding capacitor. ​

[0024] For the sake of simplicity of the process, it is preferable that the first wiring 101 and the capacitor wiring 104 are provided on the same layer, and the second wiring 102A and the third wiring 102B are provided on the same layer. Also, the third wiring 102B and the capacitor wiring 104 are provided so as to partially overlap, and form the holding capacitor of the liquid crystal element. The oxide semiconductor layer 103 of the thin film transistor 106 is provided via a gate insulating film (not shown) on a wiring branched from the first wiring 101. and form the holding capacitor of the liquid crystal element. The oxide semiconductor layer 103 of the thin film transistor 106 is provided via a gate insulating film (not shown) on a wiring branched from the first wiring 101. and form the holding capacitor of the liquid crystal element. The oxide semiconductor layer 103 of the thin film transistor 106 is provided via a gate insulating film (not shown) on a wiring branched from the first wiring 101. and form the holding capacitor of the liquid crystal element. The oxide semiconductor layer 103 of the thin film transistor 106 is provided via a gate insulating film (not shown) on a wiring branched from the first wiring 101. and form the holding capacitor of the liquid crystal element. The oxide semiconductor layer 103 of the thin film transistor 106 is provided via a gate insulating film (not shown) on a wiring branched from the first wiring 101.

[0025] Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 1 Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode 105 is connected to the third wiring 102B at the opening. Also, the third wiring 102B and the capacitor wiring 104 form a capacitor element with the gate insulating film 113 as a dielectric. Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode 105 is connected to the third wiring 102B at the opening. Also, the third wiring 102B and the capacitor wiring 104 form a capacitor element with the gate insulating film 113 as a dielectric. Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode 105 is connected to the third wiring 102B at the opening. Also, the third wiring 102B and the capacitor wiring 104 form a capacitor element with the gate insulating film 113 as a dielectric. Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode 105 is connected to the third wiring 102B at the opening. Also, the third wiring 102B and the capacitor wiring 104 form a capacitor element with the gate insulating film 113 as a dielectric. Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 10 Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode 105 is connected to the third wiring 102B at the opening. Also, the third wiring 102B and the capacitor wiring 104 form a capacitor element with the gate insulating film 113 as a dielectric. Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode 105 is connected to the third wiring 102B at the opening. Also, the third wiring 102B and the capacitor wiring 104 form a capacitor element with the gate insulating film 113 as a dielectric. Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 11 Also, FIG. 1(B) shows the cross-sectional structure between the dashed-dotted line A1 - A2 in FIG. 1(A). In the cross-sectional structure shown in FIG. 1(B), on the substrate 111, the first wiring 101 serving as a gate and the capacitor wiring 104 are provided via the underlayer film 112. The gate insulating film 113 is provided so as to cover the first wiring 101 and the capacitor wiring 104. On the gate insulating film 113, the oxide semiconductor layer 103 is provided. On the oxide semiconductor layer 103, the second wiring 102A and the third wiring 102B are provided. Also, an oxide insulating layer 114 functioning as a passivation film is provided on the oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B. An opening is formed in the oxide insulating layer 114, and the pixel electrode 105 is connected to the third wiring 102B at the opening. Also, the third wiring 102B and the capacitor wiring 104 form a capacitor element with the gate insulating film 113 as a dielectric.

[0026] Also, FIG. 1(C) shows the cross-sectional view of the dashed-dotted line B1 - B2 in FIG. 1(A), and shows the capacitance It shows a configuration having an insulating layer 121 between the measurement line 104 and the second wiring 102A. 。

[0027] When the second wiring 102A is provided on the first wiring 101 and the capacitance line 104, depending on the film thickness of the gate insulating film 113, a parasitic capacitance will occur between the first wiring 101 and the second wiring 102A, and between the capacitance line 104 and the second wiring 102A. Therefore, as shown in FIG. 1(C), by providing the insulating layer 121, the parasitic capacitance can be reduced, and defects such as malfunction can be reduced. This can be achieved.

[0028] Note that the pixels shown in FIGS. 1(A) to (C) are such that, as shown in FIG. 2, a plurality of pixels 201 are arranged in a matrix on the substrate 200. In FIG. 2, a configuration having a pixel portion 202, a scanning line driving circuit 203, and a signal line driving circuit 204 is shown. The pixel 201 is determined to be in a selected state or a non - selected state for each row by a scanning signal supplied by the first wiring 101 connected to the scanning line driving circuit 203. Also, the pixel 201 selected by the scanning signal is supplied with a video voltage (also referred to as an image signal, a video signal, or video data) from the wiring 102 A connected to the signal line driving circuit 204. A.

[0029] In FIG. 2, a configuration in which the scanning line driving circuit 203 and the signal line driving circuit 204 are provided on the substrate 200 is shown. However, either one of the scanning line driving circuit 203 or the signal line driving circuit 203 is provided on the substrate 200, and the other is formed on another substrate (for example, single - crystal silicon), and can be connected to the pixel portion 202 by mounting techniques such as the TAB method or the COG method. Yes. Further, only the pixel section 202 is provided on the substrate 200, and the scanning line drive circuit 203 and the signal line drive circuit 204 formed on a separate substrate may be connected to the pixel section 202 by mounting techniques such as the TAB method or the COG method.

[0030] In FIG. 2, an example is shown in which a plurality of pixels 201 are arranged (in a stripe arrangement) on a matrix in the pixel section 202. Note that the pixels 201 do not necessarily have to be arranged on a matrix. For example, the pixels 201 may be arranged in a delta arrangement or a Bayer arrangement. Further, either a progressive method or an interlace method may be used as the display method in the pixel section 202. When performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R is red, G is green, and B is blue), and more colors may be used. For example, RGBW (W is white), or RGB with one or more additional colors such as yellow, cyan, and magenta may be used. Note that the size of the display area may be different for each dot of the color elements.

[0031] In FIG. 2, the first wiring 101 and the second wiring 102A are shown according to the number of rows and columns of the pixels. Note that the first wiring 101 and the second wiring 102A may be configured to increase the number according to the number of sub-pixels (also referred to as sub-pixels or sub-pixels) that make up the pixels or the number of transistors in the pixels. Further, the first wiring 101 and the second wiring 102A may be shared between the pixels to drive the pixels 201.

[0032] Note that in FIG. 1(A), the shape of the second wiring 102A of the TFT is shown as a rectangle, but the shape surrounding the third wiring 102B (specifically, a U-shape or a C-shape) is used, and the key ​​​​​​​​​​​​​Increase the area of the region where carriers move, and the configuration may be such that the amount of current (also referred to as on-current) flowing when the thin-film transistor is conducting is increased. The on-current described in this specification refers to the current flowing between the source and the drain when the thin-film transistor is in the on state (also referred to as the conducting state).

[0033] For an n-channel thin-film transistor, it refers to the current flowing between the source and the drain when the voltage applied between the gate and the source is greater than the threshold voltage (Vth). ). When the voltage applied between the gate and the source is greater than the threshold voltage (Vth), it refers to the current flowing between the source and the drain.

[0034] The aperture ratio represents the ratio of the area of the region through which light passes to the unit area. When the area occupied by the member that does not transmit light becomes larger, the aperture ratio decreases, and when the area occupied by the member that transmits light becomes larger, the aperture ratio improves. In a liquid crystal display device, the aperture ratio improves by reducing the area occupied by the wiring and capacitance lines superimposed on the pixel electrode, and the size of the thin-film transistor.

[0035] The thin-film transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region, and can conduct current through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which is the source or the drain. Therefore, the regions functioning as the source and the drain may not be called the source or the drain. In that case, as an example, they may be denoted as the first terminal and the second terminal respectively. Alternatively, each of them may be denoted as the first terminal and the second terminal respectively. They may be referred to as the first electrode and the second electrode. Alternatively, there are cases where they are referred to as the first region and the second region. There are cases.

[0036] Next, the oxide semiconductor layer 103 will be described.

[0037] The oxide semiconductor used in this embodiment is such that the hydrogen concentration contained in the oxide semiconductor is 5×10 19 / cm 3 Hereinafter, preferably 5×10 18 / cm 3 Hereinafter, more preferably 5×10 17 / c m 3 The hydrogen (including OH bonds) contained in the oxide semiconductor is removed so as to be as follows. And the carrier concentration is 1×10 14 / cm 3 Less than, preferably 1×10 12 / cm 3 Hereinafter A thin-film transistor is configured in which a channel region is formed with an oxide semiconductor film having the above characteristics. Note that the hydrogen concentration in the oxide semiconductor layer is obtained by analysis using secondary ion mass spectroscopy (SIMS). Secondary Ion Mass Spectroscopy). That is the case.

[0038] If the energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, carriers generated by thermal excitation can be ignored, and by reducing impurities such as hydrogen that form donors as much as possible, the carrier concentration can be made 1× 10 10 10 14 / cm 3 Less than, preferably 1×10 12 / cm 3 Hereinafter. That is, The carrier concentration of the oxide semiconductor layer is made as close to zero as possible.

[0039] By thoroughly removing the hydrogen contained in the oxide semiconductor in this way, a highly purified oxide semiconductor is obtained. When this highly purified oxide semiconductor is used in the channel formation region of a thin film transistor, even when the channel width is 10 mm, in the range where the drain voltage is from 1 V to 10 V and the gate voltage is from -5 V to - 20 V, the drain current is 1×10 -13 A or less.

[0040] When a circuit of a display device or the like is fabricated using such a thin film transistor with an extremely small off-current value, since there is almost no leakage, the time for holding an electrical signal such as a video signal can be extended. When a circuit of a display device or the like is fabricated using such a thin film transistor with an extremely small off-current value, since there is almost no leakage, the time for holding an electrical signal such as a video signal can be extended. can be extended.

[0041] Specifically, for the transistor having the above-described oxide semiconductor layer, when the channel width is 10 μm m, the off-current per 1 μm of the channel width can be made 10 aA / μm (1×10 -1 7 A / μm) or less, and further 1 aA / μm (1×10 -18 A / μm) or less. By using a transistor with an extremely small current value (off-current value) in the off state as the selection transistor of a pixel, the holding time of an electrical signal such as a video signal can be extended. By using a transistor with an extremely small current value (off-current value) in the off state as the selection transistor of a pixel, the holding time of an electrical signal such as a video signal can be extended. Since the holding time can be extended, for example, the holding period after writing of a video signal is 10 seconds or more, preferably 30 seconds or more, more preferably 1 minute or more and less than 10 minutes. By extending the holding period, the writing interval can be lengthened, and the effect of suppressing power consumption can be enhanced. and the effect of suppressing power consumption can be enhanced.

[0042] On the other hand, for example, in a transistor having low-temperature polysilicon, the off-current is 1×10 -12 The design is based on the estimation that it is equivalent to A / μm. In a transistor having When the capacitance is the same (about 0.1 pF), the voltage retention period is 10 4 Stretch it out to about twice its size. In addition, in the case of a transistor having amorphous silicon, the channel width is 1 The off-state current per μm is 1×10 -13 A / μm or more. Therefore, the retention capacity is When the capacitance is the same (about 0.1 pF), the transistor using a high-purity oxide semiconductor has a higher capacitance. Compared to transistors using amorphous silicon, the voltage retention period is 10 4 More than double It can be stretched out.

[0043] As an example, an active matrix using thin film transistors with low temperature polysilicon is used. In a display device, the leakage current of a thin film transistor causes the voltage held in the pixel to Because the charge is lost, the video signal is rewritten every 16 milliseconds (60 frames per second). However, the active layer using the thin film transistor having the oxide semiconductor layer is In the sub-matrix display device, the thin film transistors having the oxide semiconductor layer as described above are used. The off-state current is much smaller than that of thin film transistors with low-temperature polysilicon, The retention period due to signal writing can be increased by 10,000 times to approximately 160 seconds.

[0044] Since the retention period can be extended, the frequency of signal writing can be reduced, especially when displaying still images. Therefore, the number of times signals are written to the pixels can be reduced, and Power consumption can be reduced.

[0045] The storage capacitance shown in FIG. 1 is configured by sandwiching an insulating layer as a dielectric between a pair of electrodes. And the size of the storage capacitance is set so that electric charges can be stored for a predetermined period in consideration of the leakage current of the thin film transistor disposed in the pixel portion. The size of the storage capacitance may be set in consideration of the off-current of the transistor. In the present embodiment, since a transistor having a high-purity oxide semiconductor layer is used as the transistor 106, a storage capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel is sufficient. The storage capacitance shown in FIG. 1 is configured by sandwiching an insulating layer as a dielectric between a pair of electrodes. And the size of the storage capacitance is set so that electric charges can be stored for a predetermined period in consideration of the leakage current of the thin film transistor disposed in the pixel portion. The size of the storage capacitance may be set in consideration of the off-current of the transistor. In the present embodiment, since a transistor having a high-purity oxide semiconductor layer is used as the transistor 106, a storage capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel is sufficient. And the size of the storage capacitance is set so that electric charges can be stored for a predetermined period in consideration of the leakage current of the thin film transistor disposed in the pixel portion. The size of the storage capacitance may be set in consideration of the off-current of the transistor. In the present embodiment, since a transistor having a high-purity oxide semiconductor layer is used as the transistor 106, a storage capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel is sufficient. And the size of the storage capacitance is set so that electric charges can be stored for a predetermined period in consideration of the leakage current of the thin film transistor disposed in the pixel portion. The size of the storage capacitance may be set in consideration of the off-current of the transistor. In the present embodiment, since a transistor having a high-purity oxide semiconductor layer is used as the transistor 106, a storage capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel is sufficient. And the size of the storage capacitance is set so that electric charges can be stored for a predetermined period in consideration of the leakage current of the thin film transistor disposed in the pixel portion. The size of the storage capacitance may be set in consideration of the off-current of the transistor. In the present embodiment, since a transistor having a high-purity oxide semiconductor layer is used as the transistor 106, a storage capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel is sufficient.

[0046] Since the transistor including the high-purity oxide semiconductor layer can have a long holding period, particularly when displaying a still image, the frequency of writing signals can be significantly reduced. Since the transistor including the high-purity oxide semiconductor layer can have a long holding period, particularly when displaying a still image, the frequency of writing signals can be significantly reduced. Therefore, in the display of a still image with few display switches, the number of times of writing signals to the pixels can be reduced, and thus power consumption can be reduced. Therefore, in the display of a still image with few display switches, the number of times of writing signals to the pixels can be reduced, and thus power consumption can be reduced.

[0047] In addition, in the still image display, a refresh operation may be appropriately performed in consideration of the holding ratio of the voltage applied to the liquid crystal element during the holding period. For example, the refresh operation may be performed at the timing when the voltage has dropped to a predetermined level with respect to the value (initial value) of the voltage immediately after writing a signal to the pixel electrode of the liquid crystal element. The voltage set as the predetermined level is preferably set so that no flicker is felt with respect to the initial value. Specifically, when the display target is a video, the refresh operation (rewriting) is preferably performed every time the voltage is 1.0% lower, preferably 0.3% lower, than the initial value. When the display target is a character, In addition, in the still image display, a refresh operation may be appropriately performed in consideration of the holding ratio of the voltage applied to the liquid crystal element during the holding period. For example, the refresh operation may be performed at the timing when the voltage has dropped to a predetermined level with respect to the value (initial value) of the voltage immediately after writing a signal to the pixel electrode of the liquid crystal element. The voltage set as the predetermined level is preferably set so that no flicker is felt with respect to the initial value. Specifically, when the display target is a video, the refresh operation (rewriting) is preferably performed every time the voltage is 1.0% lower, preferably 0.3% lower, than the initial value. When the display target is a character, In addition, in the still image display, a refresh operation may be appropriately performed in consideration of the holding ratio of the voltage applied to the liquid crystal element during the holding period. For example, the refresh operation may be performed at the timing when the voltage has dropped to a predetermined level with respect to the value (initial value) of the voltage immediately after writing a signal to the pixel electrode of the liquid crystal element. The voltage set as the predetermined level is preferably set so that no flicker is felt with respect to the initial value. Specifically, when the display target is a video, the refresh operation (rewriting) is preferably performed every time the voltage is 1.0% lower, preferably 0.3% lower, than the initial value. When the display target is a character, In addition, in the still image display, a refresh operation may be appropriately performed in consideration of the holding ratio of the voltage applied to the liquid crystal element during the holding period. For example, the refresh operation may be performed at the timing when the voltage has dropped to a predetermined level with respect to the value (initial value) of the voltage immediately after writing a signal to the pixel electrode of the liquid crystal element. The voltage set as the predetermined level is preferably set so that no flicker is felt with respect to the initial value. Specifically, when the display target is a video, the refresh operation (rewriting) is preferably performed every time the voltage is 1.0% lower, preferably 0.3% lower, than the initial value. When the display target is a character, In addition, in the still image display, a refresh operation may be appropriately performed in consideration of the holding ratio of the voltage applied to the liquid crystal element during the holding period. For example, the refresh operation may be performed at the timing when the voltage has dropped to a predetermined level with respect to the value (initial value) of the voltage immediately after writing a signal to the pixel electrode of the liquid crystal element. The voltage set as the predetermined level is preferably set so that no flicker is felt with respect to the initial value. Specifically, when the display target is a video, the refresh operation (rewriting) is preferably performed every time the voltage is 1.0% lower, preferably 0.3% lower, than the initial value. When the display target is a character, In addition, in the still image display, a refresh operation may be appropriately performed in consideration of the holding ratio of the voltage applied to the liquid crystal element during the holding period. For example, the refresh operation may be performed at the timing when the voltage has dropped to a predetermined level with respect to the value (initial value) of the voltage immediately after writing a signal to the pixel electrode of the liquid crystal element. The voltage set as the predetermined level is preferably set so that no flicker is felt with respect to the initial value. Specifically, when the display target is a video, the refresh operation (rewriting) is preferably performed every time the voltage is 1.0% lower, preferably 0.3% lower, than the initial value. When the display target is a character, (rewriting) is preferably performed every time the voltage is 1.0% lower, preferably 0.3% lower, than the initial value. When the display target is a character, Every time it reaches a state 10% lower, preferably 3% lower, a refresh operation (rewriting) is preferably performed. Preferably, a refresh operation (rewriting) is performed.

[0048] Also, during the holding period in still image display, the counter electrode (also referred to as the common electrode, common electrode) can be set in a floating state. Specifically, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. For this switch as well, it is preferable to use a transistor having the above-described high-purity oxide semiconductor layer. By using a TFT using an oxide semiconductor with an extremely low off-current as described above, the potential between the pixel electrode and the counter electrode of the liquid crystal display panel hardly fluctuates, and within a range where so-called image sticking of the liquid crystal does not occur, a still image can be continuously displayed while the driving circuit is stopped. Also, during the holding period in still image display, the counter electrode (also referred to as the common electrode, common electrode) can be set in a floating state. Specifically, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. For this switch as well, it is preferable to use a transistor having the above-described high-purity oxide semiconductor layer. By using a TFT using an oxide semiconductor with an extremely low off-current as described above, the potential between the pixel electrode and the counter electrode of the liquid crystal display panel hardly fluctuates, and within a range where so-called image sticking of the liquid crystal does not occur, a still image can be continuously displayed while the driving circuit is stopped. Preferably, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. Preferably, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. Preferably, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. Preferably, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. Preferably, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. Preferably, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state. Preferably, a switch is provided between the power supply that applies the common potential to the counter electrode and the counter electrode. During the writing period, the switch is turned on to apply the common potential from the power supply to the counter electrode, and then during the remaining holding period, the switch is turned off to make it in a floating state.

[0049] Also, the intrinsic resistance of the liquid crystal material is 1×10 12 Ω·cm or more, preferably 1×10 1 3 Ω·cm or more, more preferably 1×10 14 Ω·cm or more. Note that the value of the intrinsic resistance in this specification is the value measured at 20°C. Also, when a liquid crystal display device is configured using this liquid crystal material, the resistance of the portion that becomes the liquid crystal element may be, for example, 1×10 Ω·cm or more, and may even be in the range of 1×10 Ω·cm or more because impurities may be mixed into the liquid crystal layer due to the alignment film or the sealing material or the like. Ω·cm or more, and may even be in the range of 1×10 11 Ω·cm or more. Ω·cm or more, and may even be in the range of 1×10 12 Ω·cm or more.

[0050] The greater the resistivity of the liquid crystal material, the more the charge leaking through the liquid crystal material can be reduced, and the liquid crystal phenomenon in which the voltage for maintaining the operating state of the element decreases over time can be alleviated. As a result, since the holding period can be lengthened, the frequency of writing signals can be reduced, and low power consumption of the display device can be achieved.

[0051] Fig. 3(A) shows the relationship between the writing period and the holding period in the frame period. In Fig. 3(A), periods 251 and 252 correspond to the holding period, and periods 261 and 262 correspond to the writing period.

[0052] In Fig. 3(A), by inverting the polarity of the voltage applied to the liquid crystal element, which is the display element, for each frame period (illustrated by plus and minus signs in the figure), the electric field applied to the liquid crystal element is not biased, and the degree of deterioration of the liquid crystal element can be reduced. The thin film transistor having the aforementioned oxide semiconductor layer can have a long holding period, so the number of write operations to the pixel can be extremely reduced. Therefore, in the display of still images with few display switches, low power consumption can be achieved. Moreover, in Fig. 3(B), the relationship of writing voltages with inverted polarities multiple times during the writing periods 261 and 262 in Fig. 3(A) is shown. As shown in Fig. 3(B), by writing voltages with inverted polarities multiple times during the writing periods 261 and 262, the degree of deterioration of the liquid crystal element can be further reduced. Note that the writing of the voltage applied at the end of the writing periods 261 and 262 has the polarity for holding within the holding period.

[0053] Also, in Fig. 3(B), the relationship of writing voltages with inverted polarities multiple times during the writing periods 261 and 262 in Fig. 3(A) is shown. As shown in Fig. 3(B), by writing voltages with inverted polarities multiple times during the writing periods 261 and 262, the degree of deterioration of the liquid crystal element can be further reduced. Note that the writing of the voltage applied at the end of the writing periods 261 and 262 has the polarity for holding within the holding period. That is, it is the polarity for holding within the holding period.

[0054] In FIGS. 3(A) and (B), the voltage applied to the liquid crystal element is input so as to be driven using dot inversion driving, source line inversion driving, gate line inversion driving, frame inversion driving, or the like. It may be configured as such.

[0055] When a still image is not displayed, when forming a pixel using a thin film transistor including an oxide semiconductor layer, it is also possible to display a moving image without forming a holding capacitor. Regarding the configuration of the top view and the cross-sectional view of the pixel when the holding capacitor is not formed, FIGS. 4(A) and (B) are shown. The configurations shown in FIGS. 4(A) and (B) correspond to the figures in which the capacitor lines in FIGS. 1(A) and (B) are omitted. As can be seen from the top view shown in FIG. 4(A) and the cross-sectional view shown in FIG. 4(B), by using a thin film transistor having an oxide semiconductor layer, the area occupied by the pixel electrode 105, that is, the aperture ratio can be improved. Also, as can be seen from the cross-sectional view shown in FIG. 4(B), by using a thin film transistor having an oxide semiconductor layer, the capacitor lines can be reduced, and the area occupied by the pixel electrode 105 can be expanded, that is, the aperture ratio can be improved.

[0056] As described above, by adopting the configuration shown in this embodiment, in a pixel including a thin film transistor using an oxide semiconductor, the off-current can be reduced. Therefore, the period during which the voltage can be held by the holding capacitor can be lengthened, and a liquid crystal display device capable of achieving low power consumption when displaying a still image or the like can be obtained. Also, by aiming to improve the aperture ratio, a liquid crystal display device having a high-definition display section can be obtained.

[0057] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is.

[0058] (Embodiment 2) This embodiment shows an example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification. The thin film transistor 410 shown in this embodiment can be used as the thin film transistor 106 of Embodiment 1.

[0059] An embodiment of the thin film transistor and a method of manufacturing the thin film transistor according to this embodiment will be described with reference to FIGS. 5 and FIG. 6.

[0060] FIGS. 5(A) and (B) show an example of the planar and cross-sectional structures of the thin film transistor. FIGS. 5(A) and (B ) show that the thin film transistor 410 is one of the thin film transistors with a top gate structure. .

[0061] FIG. 5(A) is a plan view of the thin film transistor 410 with a top gate structure, and FIG. 5(B) is a cross-sectional view taken along line C1-C2 of FIG. 5(A).

[0062] The thin film transistor 410 includes an insulating layer 407, an oxide semiconductor layer 412, a source electrode layer or a drain electrode layer 415a, and a source electrode layer or a drain electrode layer 415b, a gate insulating layer 402, and a gate electrode layer 411 on a substrate 400 having an insulating surface, and a wiring layer 4 14a and a wiring layer 414b are respectively provided in contact with the source electrode layer or the drain electrode layer 415a and the source electrode layer or the drain electrode layer 415b and are electrically connected. Moreover, the thin film transistor 410 is described using a thin film transistor with a single gate structure.

[0063] ​However, if necessary, a thin film transistor with a multi-gate structure having a plurality of channel formation regions can also be formed.

[0064] Hereinafter, the process of fabricating the thin film transistor 410 on the substrate 400 will be described with reference to FIGS. 6(A) to (E).

[0065] There are no major restrictions on the substrate that can be used for the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance to withstand subsequent heat treatment.

[0066] For example, when using a glass substrate as the substrate 400, if the temperature of the subsequent heat treatment is high it is advisable to use one with a strain point of 730 °C or higher. For the glass substrate, for example, alumino silicate glass, aluminoborosilicate glass, barium borosilicate glass, etc. are used as the glass material. Note that by containing more barium oxide (BaO) compared to boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3

[0067] In addition to the above glass substrate, as the substrate 400, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may also be used. Alternatively, crystallized glass or the like can be used. In addition, a plastic substrate or the like can also be used as appropriate.

[0068] First, an insulating layer 407 serving as an underlying film is formed on the substrate 400 having an insulating surface. The insulating layer 407 in contact with the oxide semiconductor layer is preferably an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer. The insulating layer 4 The method for forming the film 07 can be a plasma CVD method, a sputtering method, or the like. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, the sputtering method is used. It is preferable to deposit the insulating layer 407 by using a silicon dioxide film.

[0069] In this embodiment, a silicon oxide layer is formed as the insulating layer 407 by a sputtering method. The substrate 400 is transferred to a processing chamber and subjected to a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A silicon oxide layer was formed on the substrate 400 as an insulating layer 407 using a target. The substrate 400 may be at room temperature or may be heated.

[0070] For example, quartz (preferably synthetic quartz) is used as the target, the substrate temperature is 108° C., and the substrate The distance between the plate and the target (TS distance) was 60 mm, the pressure was 0.4 Pa, and the high frequency power 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1 1) A silicon oxide film is formed by RF sputtering in a 100 MPa atmosphere. nm. Note that the silicon target is replaced with silicon oxide instead of quartz (preferably synthetic quartz). It can be used as a target for forming a silicon film. This is carried out using oxygen or a mixed gas of oxygen and argon.

[0071] In this case, it is preferable to form the insulating layer 407 while removing the remaining moisture in the processing chamber. This is to prevent the insulating layer 407 from containing hydrogen, a hydroxyl group, or moisture.

[0072] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. This is preferable. Further, as the exhaust means, a cold trap may be added to the turbo pump. The film formation chamber evacuated using a cryopump can, for example, exhaust hydrogen molecules, compounds containing hydrogen atoms such as water (H2O), etc., so that the concentration of impurities contained in the insulating layer 407 formed in the film formation chamber can be reduced.

[0073] For forming the insulating layer 407, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides used as the sputtering gas during film formation have been removed to 1 ppm or less, preferably 10 ppb or less.

[0074] Sputtering methods include the RF sputtering method using a high-frequency power source for the sputtering power supply and the DC sputtering method. There is also the pulsed DC sputtering method in which a bias is applied pulsedly. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0075] There is also a multi-source sputtering apparatus capable of installing a plurality of targets made of different materials. The multi-source sputtering apparatus can laminate and deposit different material films in the same chamber, or can simultaneously discharge a plurality of types of materials in the same chamber to form a film.

[0076] There are also sputtering apparatuses using the magnetron sputtering method equipped with a magnet mechanism inside the chamber, and sputtering apparatuses using the ECR sputtering method in which plasma generated using microwaves without using glow discharge is used.

[0077] As a film formation method using sputtering, during film formation, the target substance and the sputtering gas Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0078] The insulating layer 407 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and so on from the substrate 400 side. nitride insulation such as silicon oxide, aluminum nitride, or aluminum oxide nitride layers; The insulating layer may have a stacked structure of the insulating layer and the oxide insulating layer.

[0079] For example, a high-purity nitrogen gas containing hydrogen and moisture removed is used between the silicon oxide layer and the substrate 400. A sputtering gas containing silicon nitride is introduced and a silicon target is used to form a silicon nitride layer. In this case, similar to the silicon oxide layer, the silicon nitride layer is formed while removing the remaining moisture in the processing chamber. It is preferable to deposit a layer.

[0080] When forming a silicon nitride layer, the substrate may also be heated during film formation.

[0081] When a silicon nitride layer and a silicon oxide layer are stacked as the insulating layer 407, the silicon nitride layer The silicon oxide layer and the silicon nitride layer are formed in the same processing chamber using a common silicon target. First, a sputtering gas containing nitrogen is introduced to the silicon substrate installed in the processing chamber. A silicon nitride layer is formed using a target, and then the sputtering gas is changed to a sputtering gas containing oxygen. The silicon nitride layer is then deposited using the same silicon target. The silicon nitride layer and the silicon oxide layer can be formed successively without exposure to the atmosphere. It is possible to prevent impurities such as hydrogen and moisture from being adsorbed onto the surface of the cement layer.

[0082] Next, an oxide semiconductor film is formed over the insulating layer 407.

[0083] Also, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor film, as a pretreatment for film formation, the substrate 400 on which the insulating layer 407 is formed is preheated in the preheating chamber of the sputtering apparatus, and impurities such as hydrogen and moisture adsorbed on the substrate 400 are desorbed and exhausted. This is preferable. The exhaust means provided in the preheating chamber is preferably a cryopump. Note that this preheating treatment can also be omitted.

[0084] Note that before forming the oxide semiconductor film by sputtering, reverse sputtering is performed by introducing argon gas to generate plasma, and dust adhering to the surface of the insulating layer 407 is removed. Reverse sputtering is a method in which a voltage is applied to the substrate side using a high-frequency power supply in an argon atmosphere without applying a voltage to the target side to form plasma near the substrate and modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

[0085] The oxide semiconductor film is formed by sputtering. The oxide semiconductor film is an In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, ZnO system oxide semiconductor film. In this embodiment, the oxide semiconductor film is formed by sputtering using an In-Ga-Zn-O system oxide semiconductor target. Specifically, as a composition ratio, In2O3: Ga2O3:ZnO = 1:1:1 [mol%] (that is, In:Ga:Zn = 1:1: 1). 1). ​​​0.5 [atom%]). In addition, In:Ga:Zn=1:1:1 [atom% ], or a target having a composition ratio of In:Ga:Zn=1:1:2 [atom %] is used. The filling rate of the oxide semiconductor target is 90% or more and 100% or less. Preferably, the filling rate is 95% or more and 99.9% or less. By using the sputtering atmosphere, the oxide semiconductor film formed becomes a dense film. The atmosphere may be a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. The target may contain 2% to 10% by weight of SiO2.

[0086] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which all impurities have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable that

[0087] The oxide semiconductor film is formed by holding the substrate in a treatment chamber maintained in a reduced pressure state and removing residual moisture in the treatment chamber. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. A film is formed on the substrate 400. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, or a titanium sublimator may be used. It is preferable to use a pump for exhausting the gas. The deposition chamber evacuated using a cryopump may be, for example, For example, hydrogen molecules, water (H2O) and other compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) Since impurities (including compounds containing impurities) are exhausted, the impurities contained in the oxide semiconductor film formed in the film formation chamber The concentration of the substance can be reduced. Further, the substrate may be heated during the formation of the oxide semiconductor film.

[0088] As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 kW, and the conditions in an atmosphere of oxygen and argon (oxygen flow rate 15 scc m: argon flow rate 30 sccm) are applicable. Note that when a pulsed DC (DC ) power supply is used, dust can be reduced and the film thickness distribution becomes uniform, which is preferable. The thickness of the oxide semiconductor film is set to be 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material.

[0089] Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 4 12 by the first photolithography process (see Fig. 6(A)). Also, a resist mask for forming the island-shaped oxide semiconductor layer 412 may be formed by the inkjet method. Forming the resist mask by the inkjet method does not use a photomask, so the manufacturing cost can be reduced.

[0090] Note that the etching of the oxide semiconductor film here may be dry etching, wet etching, or both may be used.

[0091] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CC l4), etc.) is preferable.

[0092] Also, a gas containing fluorine (fluorine-based gas, for example carbon tetrafluoride (CF4), sulfur hexafluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and noble gases such as helium (He) and argon (Ar) can be added to these gases. The added gas, etc. can be used.

[0093] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. Adjust the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the temperature of the substrate-side electrode, etc.) as appropriate so that the desired processing shape can be etched.

[0094] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0095] Also, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0096] Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate according to the material so that the desired processing shape can be etched.

[0097] ​​​​​​​​In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 412 by etching.

[0098] In this embodiment, the oxide semiconductor layer 412 is subjected to first heat treatment. The temperature is set to 400° C. or higher and 750° C. or lower. If the strain point of the substrate 400 is 750° C. or lower, The temperature is set to 400°C or higher and lower than the distortion point of the substrate. The substrate is introduced, and the oxide semiconductor layer is subjected to heat treatment at 450° C. for 1 hour in a nitrogen atmosphere. After this, the temperature was lowered to room temperature without exposure to the air, and the water and hydrogen were removed from the oxide semiconductor layer. The oxide semiconductor layer 41 is obtained by the first heat treatment. Dehydration or dehydrogenation of 2 can be carried out.

[0099] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0100] For example, as the first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C and moved, heated for several minutes, and then GRTA is performed to move the substrate out of the inert gas heated to a high temperature. Using GRTA enables high-temperature heat treatment in a short time. The substrate is moved and placed in the inert gas heated to a high temperature, and after heating for several minutes, the substrate is moved and taken out of the inert gas heated to a high temperature. GRTA may be performed. Using GRTA enables high-temperature heat treatment in a short time. For example, as the first heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C and moved, heated for several minutes, and then GRTA is performed to move the substrate out of the inert gas heated to a high temperature. Using GRTA enables high-temperature heat treatment in a short time. becomes possible.

[0101] In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0102] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may crystallize and become a microcrystalline film or a polycrystalline film. For example, it may become a microcrystalline oxide semiconductor film with a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may become an amorphous oxide semiconductor film that does not contain crystalline components. Also, there may be an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are present in the amorphous oxide semiconductor. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may crystallize and become a microcrystalline film or a polycrystalline film. For example, it may become a microcrystalline oxide semiconductor film with a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may become an amorphous oxide semiconductor film that does not contain crystalline components. Also, there may be an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are present in the amorphous oxide semiconductor. % or more, or an oxide semiconductor film of microcrystals with 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may become an amorphous oxide semiconductor film that does not contain crystalline components. Also, there may be an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are present in the amorphous oxide semiconductor. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may crystallize and become a microcrystalline film or a polycrystalline film. For example, it may become a microcrystalline oxide semiconductor film with a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may become an amorphous oxide semiconductor film that does not contain crystalline components. Also, there may be an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are present in the amorphous oxide semiconductor. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may crystallize and become a microcrystalline film or a polycrystalline film. For example, it may become a microcrystalline oxide semiconductor film with a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may become an amorphous oxide semiconductor film that does not contain crystalline components. Also, there may be an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are present in the amorphous oxide semiconductor. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may crystallize and become a microcrystalline film or a polycrystalline film. For example, it may become a microcrystalline oxide semiconductor film with a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may become an amorphous oxide semiconductor film that does not contain crystalline components. Also, there may be an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are present in the amorphous oxide semiconductor. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may crystallize and become a microcrystalline film or a polycrystalline film. For example, it may become a microcrystalline oxide semiconductor film with a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may become an amorphous oxide semiconductor film that does not contain crystalline components. Also, there may be an oxide semiconductor film in which microcrystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are present in the amorphous oxide semiconductor.

[0103] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before processing it into the island-shaped oxide semiconductor layer 412. In that case, after the first heat treatment, from the heating apparatus Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before processing it into the island-shaped oxide semiconductor layer 412. In that case, after the first heat treatment, from the heating apparatus Take out the substrate and perform a photolithography process.

[0104] In the above, the heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer was shown as an example performed immediately after the formation of the oxide semiconductor layer 412. However, as long as it is after the formation of the oxide semiconductor layer it may be performed at any time after laminating the source electrode and the drain electrode on the oxide semiconductor layer and then forming a gate insulating layer on the source electrode and the drain electrode.

[0105] Next, a conductive film is formed on the insulating layer 407 and the oxide semiconductor layer 412. The conductive film may be formed by a sputtering method or a vacuum evaporation method. As the material of the conductive film, elements selected from Al, Cr, Cu , Ta, Ti, Mo, W, or alloys containing the above-mentioned elements as components, or alloy films formed by combining the above-mentioned elements, etc. may be mentioned. Further, materials selected from any one or more of manganese, magnesium, zirconium, beryllium, and yttrium may be used. Also, the conductive film may have a single-layer structure or a laminated structure of two or more layers. For example , a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film , a three-layer structure in which a Ti film is laminated with an aluminum film on top of the Ti film and then a Ti film is formed on top of that, etc. may be mentioned. Also, a film, alloy film, or nitride film in which elements selected from titanium (Ti), tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) are combined singly or in plural may be used. In this embodiment, a titanium film with a thickness of 150 nm is formed by a sputtering method.

[0106] Then, a resist mask is formed on the conductive film by a second photolithography process. The re sist mask may be formed by an inkjet method. Since the photomask is not used when the resist mask is formed by the inkjet method, the manufacturing cost can be reduced. Then, selective etching is performed to form the source electrode layer or the drain electrode layer 415a, and the source electrode layer or the drain electrode layer 415b. After that, the resist mask is removed (see FIG. 6(B)). In addition, if the ends of the formed source electrode layer and drain electrode layer are tapered, it is preferable because the coverage of the gate insulating layer laminated thereon is improved. Furthermore, when etching the conductive film, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 412 is not removed and the insulating layer 407 thereunder is not exposed.

[0107] In this embodiment, since a Ti film is used as the conductive film and an In-Ga -Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 412, aqua ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide water) is used as the etchant.

[0108] In the second photolithography process, only a part of the oxide semiconductor layer 412 may be etched to form an oxide semiconductor layer having groove portions (recesses). In the exposure during the formation of the resist mask in the second photolithography process, ultraviolet light, KrF laser light, or ArF laser light may be used. The channel length L of the thin film transistor formed later is determined by the interval width between the lower ends of the adjacent source electrode layer and the lower end of the drain electrode layer on the oxide semiconductor layer 412. When performing exposure with a channel length L of less than 25 nm,

[0109]

[0110] ​​ uses extreme ultraviolet rays with an extremely short wavelength of several nm to several tens of nm (Extreme Ultravi olet) for exposure during the formation of a resist mask in the second photolithography process. Exposure with extreme ultraviolet rays has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin film transistor to be formed later to be 10 nm or more and 1000 nm or less. This can increase the operating speed of the circuit, and furthermore, since the off-current value is extremely small, low power consumption can also be achieved.

[0111] Next, a gate insulating layer 402 is formed on the insulating layer 407, the oxide semiconductor layer 412, the source electrode layer or drain electrode layer 415a, and the source electrode layer or drain electrode layer 415b (see Fig. 6 (C)). (Refer to Fig. 6 (C).)

[0112] The gate insulating layer 402 can be formed as a single layer or by laminating a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer using a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 402, it is preferable to form the gate insulating layer 402 by a sputtering method. When forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. In this embodiment, a silicon oxide layer with a thickness of 100 nm is formed by an RF sputtering method in an atmosphere of a pressure of 0.4 Pa, a high-frequency power supply of 1.5 kW, and oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1).

[0113] ​​​​​​​​​The gate insulating layer 402 can also have a multilayer structure formed by laminating a silicon oxide layer and a silicon nitride layer from the side of the SO substrate. For example, as the first gate insulating layer, a silicon oxide layer (SiO (x>0)) with a film thickness of 5 nm or more and 300 nm or less is formed, and on the first gate insulating layer, as the second gate insulating layer, a silicon nitride layer (SiN x (y>0)) with a film thickness of 50 nm or more and 200 nm or less is laminated by sputtering, and it may be used as a gate insulating layer with a film thickness of 70 nm or more and 400 nm or less, for example, 1 00 nm. Then, a resist mask is formed by the third photolithography process, and selective etching is performed to remove a part of the gate insulating layer 402 to form openings 421a and 421b that reach the source electrode layer or drain electrode layer 4 y 15a, the source electrode layer or drain electrode layer 415b (see Fig. 6(D)). Next, a conductive film is formed on the gate insulating layer 402 and the openings 421a and 421b. In this embodiment

[0114] form, a titanium film with a film thickness of 150 nm is formed by sputtering. Then, by the fourth photolithography process, a resist mask is formed on the conductive film, and using this, the conductive film is selectively etched to form the gate electrode layer 411, the wiring layers 414a and 414b. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. The materials of the gate electrode layer 411, the wiring layers 414a and 414b are molybdenum, titanium, chromium (Fig. 6(D) reference).

[0115] Next, a conductive film is formed on the gate insulating layer 402 and the openings 421a and 421b. In this embodiment form, a titanium film with a film thickness of 150 nm is formed by sputtering. Then, by the fourth photolithography process, a resist mask is formed on the conductive film, and using this, the conductive film is selectively etched to form the gate electrode layer 411, the wiring layers 414a and 414b. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. The materials of the gate electrode layer 411, the wiring layers 414a and 414b are molybdenum, titanium, chromium (Fig. 6(D) reference). When the resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. (Fig. 6(D) reference).

[0116] The materials of the gate electrode layer 411, the wiring layers 414a and 414b are molybdenum, titanium, chromium , metal materials such as tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or alloy materials mainly composed of these can be used to form them in a single layer or by lamination.

[0117] For example, as a two-layer laminated structure of the gate electrode layer 411 and the wiring layers 414a and 414b, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or tantalum nitride is laminated on a copper layer, a two-layer structure formed by laminating a titanium nitride layer and a molybdenum layer is preferable. As a three-layer laminated structure, it is preferable to laminate a tungsten layer or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride or titanium layer. In addition, the gate electrode layer can also be formed using a conductive film having translucency. Examples of the conductive film having translucency include translucent conductive oxides.

[0118] Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Also, the second heat treatment may be performed after forming a protective insulating layer or a planarizing insulating layer on the thin film transistor 410.

[0119] Further, a heat treatment may be performed in the air at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or may be a multi-step heating from room temperature to a heating temperature of 100°C or higher and 200°C or lower, and then cooling from the heating temperature to room temperature. It may be carried out reversely. Further, this heat treatment may be carried out under reduced pressure before the formation of the oxide insulating layer. When the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0120] In the above process, a thin film transistor 410 having an oxide semiconductor layer 412 with reduced concentrations of hydrogen, moisture, hydride, and hydroxide can be formed (see FIG. 6(E)). The thin film transistor 410 can be applied as the thin film transistor 106 in Embodiment 1.

[0121] Further, a protective insulating layer or a planarizing insulating layer for planarization may be provided on the thin film transistor 410. For example, as the protective insulating layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed as a single layer or in a stacked manner.

[0122] As the planarizing insulating layer, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide , or epoxy can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BP SG (borophosphosilicate glass), etc. can be used. Note that a planarizing insulating layer may be formed by laminating a plurality of insulating films formed of these materials.

[0123] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.

[0124] ​​​​​​ The method for forming the planarized insulating layer is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used.

[0125] When forming the oxide semiconductor film as described above, by removing residual moisture in the reaction atmosphere the concentration of hydrogen and hydrides in the oxide semiconductor film can be reduced. Thereby the oxide semiconductor film can be stabilized.

[0126] By using the thin film transistor having the oxide semiconductor layer manufactured as described above for a plurality of pixels constituting a display portion of a liquid crystal display device, the leakage current from the pixels can be reduced Thereby, the period during which the voltage can be held by the holding capacitance can be extended and a liquid crystal display device capable of achieving low power consumption when displaying a still image or the like can be obtained.

[0127] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0128] (Embodiment 3) This embodiment shows another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification. Note that the same portions or portions having similar functions and processes as those in Embodiment 2 may be the same as those in Embodiment 2, and the repeated description thereof will be omitted. Also, the detailed description of the same portions will be omitted. The thin film transistor 460 shown in this embodiment can be used as the thin film transistor 106 in Embodiment 1. ​​​​​​​

[0129] One form of the thin-film transistor and the method of manufacturing the thin-film transistor according to the present embodiment will be described with reference to FIGS. 7 and FIG. 8.

[0130] FIGS. 7(A) and (B) show an example of the planar and cross-sectional structures of the thin-film transistor. FIGS. 7(A) and (B ) The thin-film transistor 460 shown is one of the thin-film transistors with a top-gate structure .

[0131] FIG. 7(A) is a plan view of the thin-film transistor 460 with a top-gate structure, and FIG. 7(B) is a cross-sectional view taken along line D1-D2 of FIG. 7(A).

[0132] The thin-film transistor 460 includes an insulating layer 457, a source electrode layer or drain electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462, a source electrode layer or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, and a gate electrode layer 461 (461a, 461b) on a substrate 450 having an insulating surface. The source electrode layer or drain electrode layer 465a (465a1, 465a2) is electrically connected to the wiring layer 464 via the wiring layer 468 . Also, although not shown, the source electrode layer or drain electrode layer 465b is also electrically connected to the wiring layer at an opening provided in the gate insulating layer 452.

[0133] Hereinafter, the process of manufacturing the thin-film transistor 460 on the substrate 450 will be described with reference to FIGS. 8(A) to (E). process.

[0134] First, an insulating layer 457 serving as an underlayer film is formed on a substrate 450 having an insulating surface.

[0135] In the present embodiment, as the insulating layer 457, a silicon oxide layer is formed by a sputtering method The substrate 450 is transported into the processing chamber, and sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. Using a silicon target or quartz (preferably synthetic quartz), a silicon oxide layer is formed on the substrate 45 0 as the insulating layer 457. Note that the sputtering gas is oxygen or a mixed gas of oxygen and argon is used.

[0136] For example, with a purity of 6N, using quartz (preferably synthetic quartz) as the target, the substrate temperature is 108 °C, the distance between the substrate and the target (T-S distance) is 60 mm, the pressure is 0.4 Pa, the high-frequency power supply is 1.5 kW, and in an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1), a silicon oxide film is formed by the RF sputtering method. The film thickness is 100 nm. Note that instead of quartz (preferably synthetic quartz), a silicon target can be used as the target for forming the silicon oxide film.

[0137] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the insulating layer 457. The film-forming chamber evacuated using a cryo pump is exhausted of, for example, hydrogen molecules, compounds containing hydrogen atoms such as water (H2O), etc., so that the concentration of impurities contained in the insulating layer 457 formed in the film-forming chamber can be reduced.

[0138] For forming the insulating layer 457, it is preferable to use high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to 1 ppm or less, preferably 10 ppb or less.

[0139] Further, the insulating layer 457 may have a laminated structure. For example, nitride insulating layers such as a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, and an aluminum oxynitride layer from the substrate 450 side, and a laminated structure with the above oxide insulating layer may be used.

[0140] For example, a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced between the silicon oxide layer and the substrate, and a silicon nitride layer is formed using a silicon target. Also in this case, similar to the silicon oxide layer, it is preferable to form the silicon nitride layer while removing residual moisture in the processing chamber.

[0141] Next, a conductive film is formed on the insulating layer 457. As materials for the conductive film, elements selected from Al, Cr, Cu, Ta, Ti, Mo, W, or alloys containing the above-described elements, or alloy films formed by combining the above-described elements may be mentioned. Further, a material selected from any one or more of manganese, magnesium, zirconium, beryllium, and yttrium may be used. Also, the conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a Ti film is laminated with an aluminum film on top of the Ti film, and then a Ti film is formed on top of that may be mentioned. Also, a film, alloy film, or nitride film formed by combining a single or a plurality of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) with Al may be used. In the present embodiment, a titanium film with a film thickness of 150 nm is formed as the conductive film by sputtering. Then, through the first photolithography process, ​ A resist mask is formed on the electrofilm, and selective etching is performed to form the source electrode layer or the drain electrode layers 465a1 and 465a2. After that, the resist mask is removed (see Fig. 8(A)). The source electrode layer or the drain electrode layers 465a1 and 465a2 are shown separately in the cross-sectional view, but they are continuous films. Note that if the ends of the formed source electrode layer and drain electrode layers are tapered, the coverage of the gate insulating layer laminated thereon is improved, which is preferable.

[0142] Next, an oxide semiconductor film with a thickness of 2 nm or more and 200 nm or less is formed. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material. In this embodiment, an In-Ga-Zn-O-based oxide semiconductor target is used to form the film by sputtering.

[0143] For the oxide semiconductor film, the substrate is held in a processing chamber maintained in a reduced-pressure state, and a sputtering gas from which hydrogen and moisture have been removed is introduced while removing the residual moisture in the processing chamber. Then, an oxide semiconductor film is formed on the substrate 450 using the target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. When exhausting using a cryopump, the film formation chamber, for example, exhausts compounds containing hydrogen atoms such as hydrogen molecules and water (H2O) (more preferably compounds containing carbon atoms as well). Therefore, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. Also, the substrate may be heated during the formation of the oxide semiconductor film. 。

[0144] When forming the oxide semiconductor film, the sputtering gas used is preferably a high-purity gas in which any impurity has been removed to 1 ppm or less, preferably 10 ppb or less, such as hydrogen, water, hydroxyl groups, or hydrides. 。 。

[0145] As an example of the film formation conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, the pressure is 0.4 Pa, the DC power supply is 0.5 kW, and the conditions in an atmosphere of oxygen and argon (oxygen flow rate: 15 sccm; argon flow rate: 30 sccm) are applied. 。 。

[0146] Next, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 462 by a second photolithography process (see FIG. 8(B)). In the present embodiment, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 462 by a wet etching method using a solution in which phosphoric acid, acetic acid, and nitric acid are mixed as the etching solution. 。 。 。

[0147] In the present embodiment, a first heat treatment is performed on the oxide semiconductor layer 462. The temperature of the first heat treatment is 400°C or higher and 750°C or lower. When the distortion point of the substrate 450 is 750°C or lower, the temperature is 400°C or higher and lower than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. Then, without exposing it to the atmosphere, the temperature is lowered to room temperature to prevent re-mixing of water and hydrogen into the oxide semiconductor layer, thereby obtaining the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer 462 can be performed. 。 。 。 。 。 。

[0148] Note that the heat treatment apparatus is not limited to an electric furnace, and may be equipped with an apparatus that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, a GRTA (Gas Rapid Thermal Anneal) apparatus, an LRTA (Lamp Rapid Thermal Anneal) apparatus, or other RTA (Rapid Thermal An neal) apparatus can be used. For example, as the first heat treatment, the substrate is moved and placed in an inert gas heated to a high temperature of 650°C to 7 00°C, heated for several minutes, and then GRTA may be performed by moving the substrate and taking it out of the inert gas heated to a high temperature. Using GRTA enables high-temperature heat treatment in a short time.

[0149] In the first heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, the purity of nitrogen, or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more , preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0150] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 462 may crystallize and become a microcrystalline film or a polycrystalline film.

[0151] Also, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus and a photolithography process is performed.

[0152] ​Incidentally, in the above description, the heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer is illustrated as an example performed immediately after the formation of the oxide semiconductor layer 462. However, as long as it is after the formation of the oxide semiconductor layer it may be performed at any time after further laminating a source electrode layer or a drain electrode layer 465b on the oxide semiconductor layer and then forming a gate insulating layer 452 on the source electrode layer or the drain electrode layer 465b. It may be performed at any time.

[0153] Next, a conductive film is formed on the insulating layer 457 and the oxide semiconductor layer 462, and a resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed to form a source electrode layer or a drain electrode layer 465b and a wiring layer 468. Then, the resist mask is removed (see FIG. 8(C)). The source electrode layer or the drain electrode layer 465b and the wiring layer 4 68 may be formed of the same materials and by the same processes as the source electrode layers or the drain electrode layers 465a1 and 465a2. In the present embodiment, a titanium film with a thickness of 150 nm is formed on the source electrode layer or the drain electrode layer 465b and the wiring layer 468 by sputtering. In the present embodiment, since the same titanium film is used for the source electrode layers or the drain electrode layers 465a1 and 465a2 and the source electrode layer or the drain electrode layer 465 b, the source electrode layers or the drain electrode layers 465a1 and 465a2 and the source electrode layer or the drain electrode layer 465b do not have a selectivity ratio in etching. Therefore, in order to prevent the source electrode layers or the drain electrode layers 465a1 and 465a2 from being etched during the etching of the source electrode layer or the drain electrode layer 465b, a wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462

[0154] In the present embodiment, a titanium film with a thickness of 150 nm is formed on the source electrode layer or the drain electrode layer 465b and the wiring layer 468 by sputtering. In the present embodiment, since the same titanium film is used for the source electrode layers or the drain electrode layers 465a1 and 465a2 and the source electrode layer or the drain electrode layer 465 b, the source electrode layers or the drain electrode layers 465a1 and 465a2 and the source electrode layer or the drain electrode layer 465b do not have a selectivity ratio in etching. Therefore, in order to prevent the source electrode layers or the drain electrode layers 465a1 and 465a2 from being etched during the etching of the source electrode layer or the drain electrode layer 465b, a wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462 layers or the drain electrode layer 465 b, the source electrode layers or the drain electrode layers 465a1 and 46 5a2 and the source electrode layer or the drain electrode layer 465b do not have a selectivity ratio in etching. Therefore, in order to prevent the source electrode layers or the drain electrode layers 465a1 and 465a2 from being etched during the etching of the source electrode layer or the drain electrode layer 465b, a wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462 layers or the drain electrode layer 465 layers or the drain electrode layer 465b, a wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462 so that the source electrode layers or the drain electrode layers 465a1 and 465a2 are not etched during the etching of the source electrode layer or the drain electrode layer 465b. layers or the drain electrode layer 465b, a wiring layer 468 is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered by the oxide semiconductor layer 462 so that the source electrode layers or the drain electrode layers 465a1 and 465a2 are not etched during the etching of the source electrode layer or the drain electrode layer 465b. is provided. When different materials having a high selectivity in the etching process are used for the source electrode layer or drain electrode layers 465a1 and 465a2 and the source electrode layer or the drain electrode layer 465b, the wiring layer 468 for protecting the source electrode layer or drain electrode layer 465a2 during etching is not necessarily provided. Note that when etching the conductive film, part of the oxide semiconductor layer 462 may be etched. The respective materials and etching

[0155] conditions are appropriately adjusted so that the oxide semiconductor layer 462 is not removed more than necessary. In this embodiment, since a Ti film is used as the conductive film and an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 462, aqueous ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide water) is used as the etchant.

[0156]

[0157]

[0157] Note that in the second photolithography process, only part of the oxide semiconductor layer 462 may be etched to form an oxide semiconductor layer having a groove portion (recess). Also, a resist mask for forming the source electrode layer or the drain electrode layer 465b and the wiring layer 468 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0158]

[0159] Next, a gate insulating layer 452 is formed over the insulating layer 457, the oxide semiconductor layer 462, the source electrode layer or drain electrode layers 465a1, 465a2, and the source electrode layer or drain electrode layer 465b.

[0159] The gate insulating layer 452 can be formed by using a plasma CVD method, a sputtering method, or the like to form a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 452, it is preferable to form the gate insulating layer 452 by a sputtering method. When forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. The gate insulating layer 452 can also have a structure in which a silicon oxide layer and a silicon nitride layer are laminated from the source electrode layer or drain electrode layers 465a1 and 465a2, or the source electrode layer or drain electrode layer 465b side. In this embodiment, a silicon oxide layer with a thickness of 100 nm is formed by an RF sputtering method under an atmosphere of a pressure of 0.4 Pa, a high-frequency power source of 1.5 kW, and oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1). Next, a resist mask is formed by a fourth photolithography process, and selective etching is performed to remove a part of the gate insulating layer 452 to form an opening 423 reaching the wiring layer 468 (see Fig. 8(D)). Although not shown, an opening reaching the source electrode layer or drain electrode layer 465b may be formed when forming the opening 423. In this embodiment, an opening to the source electrode layer or drain electrode layer 465b is formed after further laminating an interlayer insulating layer, and an example is given in which a wiring layer for electrical connection is formed in the opening. To prevent a large amount of hydrogen from being contained in the gate insulating layer 452, it is preferable to form the gate insulating layer 452 by a sputtering method. When forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. When forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. When forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas. When forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

[0160] The gate insulating layer 452 can also have a structure in which a silicon oxide layer and a silicon nitride layer are laminated from the source electrode layer or drain electrode layers 465a1 and 465a2, or the source electrode layer or drain electrode layer 465b side. The gate insulating layer 452 can also have a structure in which a silicon oxide layer and a silicon nitride layer are laminated from the source electrode layer or drain electrode layers 465a1 and 465a2, or the source electrode layer or drain electrode layer 465b side. In this embodiment, a silicon oxide layer with a thickness of 100 nm is formed by an RF sputtering method under an atmosphere of a pressure of 0.4 Pa, a high-frequency power source of 1.5 kW, and oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1). In this embodiment, a silicon oxide layer with a thickness of 100 nm is formed by an RF sputtering method under an atmosphere of a pressure of 0.4 Pa, a high-frequency power source of 1.5 kW, and oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1). In this embodiment, a silicon oxide layer with a thickness of 100 nm is formed by an RF sputtering method under an atmosphere of a pressure of 0.4 Pa, a high-frequency power source of 1.5 kW, and oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1).

[0161] Next, a resist mask is formed by a fourth photolithography process, and selective etching is performed to remove a part of the gate insulating layer 452 to form an opening 423 reaching the wiring layer 468 (see Fig. 8(D)). Next, a resist mask is formed by a fourth photolithography process, and selective etching is performed to remove a part of the gate insulating layer 452 to form an opening 423 reaching the wiring layer 468 (see Fig. 8(D)). Next, a resist mask is formed by a fourth photolithography process, and selective etching is performed to remove a part of the gate insulating layer 452 to form an opening 423 reaching the wiring layer 468 (see Fig. 8(D)). Although not shown, an opening that reaches the source electrode layer or drain electrode layer 465b may be formed when forming the opening 423. In this embodiment, an opening to the source electrode layer or drain electrode layer 465b is formed after further laminating an interlayer insulating layer, and an example is given in which a wiring layer for electrical connection is formed in the opening. In this embodiment, an opening to the source electrode layer or drain electrode layer 465b is formed after further laminating an interlayer insulating layer, and an example is given in which a wiring layer for electrical connection is formed in the opening.

[0162] Next, after forming a conductive film on the gate insulating layer 452 and the opening 423, a fifth photolithography process is performed to form the gate electrode layer 461 (461a, 461b) and the wiring layer 464. Note that the resist mask may be formed by an inkjet method. Since the photomask is not used when the resist mask is formed by the inkjet method, the manufacturing cost can be reduced.

[0163] Also, the materials of the gate electrode layer 461 (461a, 461b) and the wiring layer 464 can be formed as a single layer or laminated using metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or alloy materials mainly composed of these.

[0164] In this embodiment, a titanium film with a thickness of 150 nm is formed by a sputtering method as the gate electrode layer 461 (461a, 461b) and the wiring layer 464. In FIG. 8(E), the gate electrode layer 461 (461a, 461b) is shown as being separated, but as shown in FIG. 7(A), it is formed so as to overlap the annular void portion generated between the source electrode layer or drain electrode layer 465a1, 465a2 and the source electrode layer or drain electrode layer 465b.

[0165] Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Also, the second heat treatment may be performed after forming a protective insulating layer or a planarizing insulating layer on the thin film transistor 460.

[0166] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat heating from 0℃ to 200℃ and cooling from the heating temperature to room temperature multiple times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Heating under reduced pressure can shorten the heating time.

[0167] Through the above steps, the oxide semiconductor layer 46 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2 can be formed (see FIG. 8E). The transistor 460 can be used as the thin film transistor 106 in Embodiment 1. can be done.

[0168] In addition, a protective insulating layer and a planarization insulating layer for planarization are provided over the thin film transistor 460. Although not shown, the source insulating layer 452, the protective insulating layer, and the planarizing insulating layer may be formed. An opening reaching the source or drain electrode layer 465b is formed in the opening. A wiring layer electrically connected to the drain electrode layer 465b is formed.

[0169] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0170] As described above, the display portion of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer Therefore, the off-state current can be reduced in the plurality of pixels constituting the storage capacitor. The period during which the voltage can be held can be lengthened, and low power consumption can be achieved when displaying still images or the like. It is possible to provide a liquid crystal display device that can achieve this. In the present embodiment, the channel is circular. In addition, by forming the source electrode layer and the drain electrode layer using different layers, the channel length can be shortened and the channel width can be made larger. In this way, a thin film transistor with a large channel width can be formed even on a relatively narrow area, so that a large current can be switched. Also, although the channel width is large, since a highly purified oxide semiconductor is used, it has the characteristic that the off-current is extremely small.

[0171] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0172] (Embodiment 4) This embodiment shows another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification. Note that the same parts or parts having the same functions and processes as those in Embodiment 2 may be the same as those in Embodiment 2, and the repeated description thereof will be omitted. Also, the detailed description of the same part will be omitted. The thin film transistors 425 and 426 shown in this embodiment can be used as the thin film transistor 106 in Embodiment 1. The thin film transistors shown in this embodiment will be described with reference to FIG. 9.

[0173] An example of the cross-sectional structure of the thin film transistor is shown in FIGS. 9(A) and 9(B). The thin film transistors 425 and 426 shown in FIGS. 9(A) and 9(B) are one of the thin film transistors having a structure in which an oxide semiconductor layer is sandwiched between a conductive layer and a gate electrode layer.

[0174]

[0175] In FIGS. 9(A) and 9(B), a silicon substrate is used as the substrate, and thin film transistors 425 and 426 are respectively provided on an insulating layer 422 provided on the silicon substrate 42 0. are provided.

[0176] In FIG. 9(A), a conductive layer 427 is provided so as to overlap at least the entire oxide semiconductor layer 412 between the insulating layer 422 provided on the silicon substrate 420 and the insulating layer 407 . .

[0177] Note that FIG. 9(B) is an example in which the conductive layer between the insulating layer 422 and the insulating layer 407 is processed by etching so as to overlap at least a part including the channel region of the oxide semiconductor layer 412 . .

[0178] The conductive layers 427 and 424 may be made of a metal material that can withstand the heat treatment temperature performed in a later process, such as titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), an element selected from Nd (neodymium), scandium (Sc), or an alloy containing the above-mentioned elements as components, an alloy film combining the above-mentioned elements, or a nitride containing the above-mentioned elements as components. Further, it may have a single-layer structure or a laminated structure. For example, a single tungsten layer or a laminated structure of a tungsten nitride layer and a tungsten layer can be used . . . . . .

[0179] Also, the potentials of the conductive layers 427 and 424 may be the same as or different from the gate electrode layer 411 of the thin film transistors 425 and 426, and can also function as a second gate electrode layer. Further, the potentials of the conductive layers 427 and 424 may be fixed potentials such as GND and 0V . . .

[0180] The electrical characteristics of the thin film transistors 425 and 426 can be controlled by the conductive layers 427 and 424. This can be achieved.

[0181] This embodiment can be implemented in appropriate combination with other embodiments.

[0182] (Embodiment 5) This embodiment shows an example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification. It is shown.

[0183] One form of the thin film transistor and the method of manufacturing the thin film transistor according to this embodiment will be described with reference to FIG. 10. It will be described using FIG. 10.

[0184] FIGS. 10(A) to (E) show an example of the cross-sectional structure of the thin film transistor. The thin film transistor 390 shown in FIGS. 10(A) to (E) is one of the bottom gate structures and is also called an inverted staggered type thin film transistor.

[0185] In addition, although the thin film transistor 390 is described using a single gate structure thin film transistor, if necessary, a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed. transistor. This can be achieved.

[0186] Hereinafter, the process of manufacturing the thin film transistor 390 on the substrate 394 will be described with reference to FIGS. 10(A) to (E). It will be described.

[0187] First, after forming a conductive film on the substrate 394 having an insulating surface, the gate electrode layer 391 is formed by the first photolithography process. It is preferable that the end of the formed gate electrode layer has a tapered shape because the covering property of the gate insulating layer laminated thereon is improved. Note that the resist The mask may be formed by an inkjet method. The resist mask is formed by an inkjet method Since a photomask is not used, the manufacturing cost can be reduced.

[0188] There is no major limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment..

[0189] For example, when using a glass substrate as the substrate 394, if the temperature of the subsequent heat treatment is high it is advisable to use one with a strain point of 730 °C or higher. For the glass substrate, for example, alumino silicate glass, aluminoborosilicate glass, barium borosilicate glass and other glasses materials are used. Note that by containing more barium oxide (BaO) compared with boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3

[0190] In addition to the above glass substrate, as the substrate 394, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may also be used. Alternatively, crystallized glass or the like can be used

[0191] An insulating film serving as an underlayer may be provided between the substrate 394 and the gate electrode layer 391. The underlayer has a function of preventing the diffusion of impurity elements from the substrate 394, and is formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film

[0192] ​​​In addition, the material of the gate electrode layer 391 can be formed as a single layer or by stacking using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material having these as main components. For example, as a two-layer stacked structure of the gate electrode layer 391, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable. As a three-layer stacked structure, it is preferable to stack tungsten or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride or a titanium layer. Note that the gate electrode layer can also be formed using a conductive film having translucency. Examples of the conductive film having translucency include translucent conductive oxides and the like. It can be formed in a single layer or by stacking.

[0193] For example, as a two-layer stacked structure of the gate electrode layer 391, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable. As a three-layer stacked structure, it is preferable to stack tungsten or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride or a titanium layer. Note that the gate electrode layer can also be formed using a conductive film having translucency. Examples of the conductive film having translucency include translucent conductive oxides and the like. For example, as a two-layer stacked structure of the gate electrode layer 391, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable. As a three-layer stacked structure, it is preferable to stack tungsten or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride or a titanium layer. Note that the gate electrode layer can also be formed using a conductive film having translucency. Examples of the conductive film having translucency include translucent conductive oxides and the like. As a three-layer stacked structure, it is preferable to stack tungsten or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride or a titanium layer. Note that the gate electrode layer can also be formed using a conductive film having translucency. Examples of the conductive film having translucency include translucent conductive oxides and the like. For example, as a two-layer stacked structure of the gate electrode layer 391, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked on a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable. As a three-layer stacked structure, it is preferable to stack tungsten or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride or a titanium layer. Note that the gate electrode layer can also be formed using a conductive film having translucency. Examples of the conductive film having translucency include translucent conductive oxides and the like. Next, a gate insulating layer 397 is formed on the gate electrode layer 391. The gate insulating layer 397 can be formed as a single layer or by stacking a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer using a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide film by a sputtering method, a target

[0194] Next, a gate insulating layer 397 is formed on the gate electrode layer 391.

[0195] The gate insulating layer 397 can be formed as a single layer or by stacking a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer using a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide film by a sputtering method, a target The gate insulating layer 397 can be formed as a single layer or by stacking a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer using a plasma CVD method, a sputtering method, or the like. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide film by a sputtering method, a target In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide film by a sputtering method, a target In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 397, it is preferable to form the gate insulating layer 397 by a sputtering method. When forming a silicon oxide film by a sputtering method, a target Using a silicon target or a quartz target as the target, and using oxygen or , or a mixed gas of oxygen and argon, it is carried out.

[0196] The gate insulating layer 397 can also have a structure in which a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 391 side. For example, as the first gate insulating layer, by sputtering , a silicon nitride layer (SiN with a film thickness of 50 nm or more and 200 nm or less (y>0)) is formed y , and on the first gate insulating layer, as the second gate insulating layer, a silicon oxide layer (SiO with a film thickness of 5 nm or more and 300 nm or less is stacked, and for example, a gate insulating layer with a film thickness of 100 nm is obtained. x (x>0)) is stacked to form, for example, a gate insulating layer with a film thickness of 100 nm .

[0197] In addition, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the gate insulating layer 397 and the oxide semiconductor film 393, as a pretreatment for film formation, in the preheating chamber of the sputtering apparatus, the gate electrode layer 391 formed on the substrate 394, or the substrate 394 on which the gate insulating layer 397 is formed up to is preheated to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 394. It is preferably done. The preheating temperature is preferably 100 °C or more and 400 °C or less, more preferably 150 °C or more and 300 °C or less. The exhaust means provided in the preheating chamber is preferably a cryopump . Note that this preheating process can also be omitted. Also, this preheating [[ID=3�]] can be carried out in the same manner on the substrate 394 on which the source electrode layer 395a and the drain electrode layer 395b shown in FIG. 10(C) are formed as long as it is before the formation of the oxide insulating layer 396.

[0198] Next, on the gate insulating layer 397, with a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more ​Form an oxide semiconductor film 393 with a thickness of 30 nm or less by sputtering (see Fig. 10(A ).). Note that the appropriate thickness varies depending on the oxide semiconductor material applied, and the thickness may be appropriately selected according to the material.

[0199] Before forming the oxide semiconductor film 393 by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove the dust adhering to the surface of the gate insulating layer 397. Reverse sputtering is a method of modifying the surface by applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma near the substrate. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere.

[0200] The oxide semiconductor film 393 uses an oxide semiconductor film of In-Ga-Zn-O system, In-Sn-Zn-O system, In-A l-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn -O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn- O system, Zn-O system. In this embodiment, the oxide semiconductor film 393 is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. Specifically, as the composition ratio, In2O3:Ga2O3:ZnO = 1:1:1 [mo l%] (that is, In:Ga:Zn = 1:1:0.5 [atom%]) is used. Alternatively, a target having a composition ratio of In:Ga:Zn = 1:1:1 [atom%] or In:Ga:Zn = 1:1:2 [atom%] can also be used. Note that the filling rate of the oxide semiconductor target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. Yes. By using an oxide semiconductor target with a high filling rate, the formed oxide semiconductor film becomes a dense film. Also, the oxide semiconductor film 393 can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen. Further, the film formation may be performed using a target containing 2 wt% or more and 10 wt% or less of SiO2.

[0201] A substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate is heated to room temperature or a temperature below 400°C. Then, while removing the residual moisture in the processing chamber, sputtering gas from which hydrogen and moisture have been removed is introduced, and an oxide semiconductor film 393 is formed on the substrate 394 using the above target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the evacuation means, a turbo pump with a cold trap added thereto may be used. The film formation chamber evacuated using a cryopump is evacuated of compounds containing hydrogen atoms such as hydrogen molecules and water (H2O), and more preferably compounds containing carbon atoms as well. Therefore, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. Also, by performing sputter film formation while removing the moisture remaining in the processing chamber by a cryopump, the substrate temperature at the time of forming the oxide semiconductor film 393 can be set to be from room temperature to below 400°C.

[0202] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, a DC power supply of 0.5 kW, and conditions in an oxygen (oxygen flow rate ratio 100%) atmosphere are applied.​​​​​​​​​​​ This is the case. When a pulsed direct current (DC) power source is used, dust can be reduced and the film thickness distribution can also be made uniform. This is preferable for this reason.

[0203] In the sputtering method, there are the RF sputtering method that uses a high-frequency power source for the sputtering power source, and the D C sputtering method. There is also the pulsed DC sputtering method that applies a bias pulse by pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0204] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can stack and form different material films in the same chamber, or can also discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0205] There is also a sputtering apparatus that uses the magnetron sputtering method equipped with a magnet mechanism inside the chamber, and an ECR sp uttering apparatus that uses plasma generated using microwaves without using glow discharge. There is also a sputtering apparatus that uses the ECR sputtering method.

[0206] As a film formation method using the sputtering method, there is the reactive sputtering method in which a chemical reaction is caused between the target substance and the sputtering gas component during film formation to form a compound thin film thereof, and the bias sputtering method in which a voltage is also applied to the substrate during film formation. There is also the bias sputtering method.

[0207] Next, the oxide semiconductor film is processed into island-shaped oxide semiconductor layers 3 99 by a second photolithography process (see FIG. 10(B)). Also, a resist mask for forming the island-shaped oxide semiconductor layer 399 may be formed by an inkjet method. The resist mask may be formed by inkjet When formed by the jet method, since a photomask is not used, the manufacturing cost can be reduced.

[0208] Also, when forming a contact hole in the gate insulating layer 397, the process can be performed during the formation of the oxide semiconductor layer 399.

[0209] Note that the etching of the oxide semiconductor film 393 here may be either dry etching or wet etching, or both may be used.

[0210] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CC l4), etc.) is preferable.

[0211] Also, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF 6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0212] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductive coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that etching can be performed into a desired processed shape.

[0213] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, A Ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2) can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0214] After wet etching, the etching solution is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0215] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired processing shape can be etched.

[0216]

[0217] Before forming the conductive film in the next process, reverse sputtering is preferably performed to remove resist residues and the like adhering to the surfaces of the oxide semiconductor layer 399 and the gate insulating layer 397. Next, a conductive film is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film may be formed by a sputtering method or a vacuum evaporation method. As the material of the conductive film, elements selected from Al, Cr, Cu, Ta, Ti, Mo, W, or alloys containing the above-described elements, or alloy films combining the above-described elements, etc. may be mentioned. Also, materials selected from any one or more of manganese, magnesium, zirconium, beryllium, and yttrium may be used. Further, the metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a titanium film on an aluminum film ​​​​​​​​​​​​A two-layer structure in which a Ti film is laminated and an aluminum film is laminated on top of the Ti film. A three-layer structure is also possible, where a titanium (Ti) film is formed on top of Al. , Tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Sc (Scandium) , an alloy film, or a nitride film may also be used.

[0218] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 395a and the drain electrode layer 395b by etching, a resist The mask is removed (see FIG. 10(C)).

[0219] The third photolithography process involves exposure to ultraviolet light or KrF laser light when forming a resist mask. The source electrode layer is formed on the oxide semiconductor layer 399. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the channel width of the thin film transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the film transistor to 10 nm or more and 1000 nm or less. This allows for faster circuit operation and, due to the extremely small off-state current, also reduces power consumption. This can be achieved.

[0220] Note that the conductive film was etched so that the oxide semiconductor layer 399 was not removed. Appropriately adjust the materials and etching conditions.

[0221] In this embodiment, a Ti film is used as the conductive film, and an In-Ga -Zn-O based oxide semiconductor is used for the oxide semiconductor layer 399, so that aqueous ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant.

[0222] Note that in the third photolithography process, only a part of the oxide semiconductor layer 399 may be etched to form an oxide semiconductor layer having a groove portion (concave portion). Further, a resist mask for forming the source electrode layer 395a and the drain electrode layer 395b may be formed by an inkjet method. Since no photomask is used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced.

[0223] Further, in order to reduce the number of photomasks and the number of processes used in the photolithography process, an etching process may be performed using a resist mask formed by a multi-tone mask, which is an exposure mask in which transmitted light has multiple intensities. The resist mask formed using the multi-tone mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching, so it can be used in a plurality of etching processes for processing into different patterns. Therefore, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

[0224] Further, after removing the resist mask, a process using a gas such as N2O, N2, or Ar is performed.​​​​​​​​​ Adsorbed water or the like adhering to the surface of the oxide semiconductor layer 399 exposed by the Rasma treatment may be removed. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0225] Next, an oxide insulating layer 396 is formed as an oxide insulating layer serving as a protective insulating film in contact with a part of the oxide semiconductor layer (see FIG. 10(D)). When the plasma treatment is performed, the oxide insulating layer 396 may be continuously formed without exposing the oxide semiconductor layer 399 to the atmosphere after the plasma treatment. In the present embodiment, the oxide insulating layer 396 and the oxide semiconductor layer 399 are formed so as to be in contact with each other in a region where the oxide semiconductor layer 399 does not overlap with the source electrode layer 395a and the drain electrode layer 395b.

[0226] In the present embodiment, the substrate 394 on which the island-shaped oxide semiconductor layer 399, the source electrode layer 395a, and the drain electrode layer 395b are formed is heated to room temperature or a temperature lower than 100° C., and a sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced, and a silicon semiconductor target is used to form a silicon oxide layer containing defects to form the oxide insulating layer 396.

[0227]

[0227] It can be used. Note that as the sputtering gas, oxygen or a mixed gas of oxygen and argon is used. It is performed using a sputtering target.

[0228] In this case, it is preferable to form the oxide insulating layer 396 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer 399 and the oxide insulating layer 396.

[0229] To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump is evacuated of compounds containing hydrogen atoms such as hydrogen molecules and water (H2O), etc. Therefore, the concentration of impurities contained in the oxide insulating layer 396 formed in the film formation chamber can be reduced.

[0230] Note that as the oxide insulating layer 396, instead of a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer, etc. can also be used.

[0231] Furthermore, after the formation of the oxide insulating layer 396, heat treatment may be performed at 100°C to 400°C with the oxide insulating layer 396 and the oxide semiconductor layer 399 in contact. Since the oxide insulating layer 396 in this embodiment contains many defects, impurities such as hydrogen, moisture, hydroxyl groups, or hydrides contained in the oxide semiconductor layer 399 are diffused into the oxide insulating layer 396 by this heat treatment, and the impurities contained in the oxide semiconductor layer 399 can be further reduced.

[0232] ​​​​​​​​ In the above process, an oxide semiconductor layer 39 with reduced concentrations of hydrogen, moisture, hydroxyl groups, or hydrides A thin film transistor 390 having 2 can be formed (see Fig. 10(E)).

[0233] When forming the oxide semiconductor film as described above, removing residual moisture in the reaction atmosphere can reduce the concentrations of hydrogen and hydrides in the oxide semiconductor film. Thereby The oxide semiconductor film can be stabilized.

[0234] A protective insulating layer may be provided on the oxide insulating layer. In this embodiment, a protective insulating layer 398 is formed on the oxide insulating layer 396. As the protective insulating layer 398, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film, etc. is used.

[0235] As the protective insulating layer 398, the substrate 394 formed up to the oxide insulating layer 396 is heated to a temperature of 100°C to 4 00°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced and a silicon nitride film is formed using a silicon semiconductor target. Also in this case , similar to the oxide insulating layer 396, it is preferable to form the protective insulating layer 398 while removing residual moisture in the processing chamber.

[0236] When forming the protective insulating layer 398, by heating the substrate 394 to 100°C to 400°C during the film formation of the protective insulating layer 398, hydrogen or moisture contained in the oxide semiconductor layer can be diffused into the oxide insulating layer. In this case, a heat treatment does not have to be performed after the formation of the above oxide insulating layer 396.

[0237] A silicon oxide layer is formed as the oxide insulating layer 396, and silicon nitride is used as the protective insulating layer 398​​​ When laminating layers, a silicon oxide layer and a silicon nitride layer can be formed in the same processing chamber using a common silicon target. First, a sputtering gas containing oxygen is introduced, and a silicon oxide layer is formed using the silicon target mounted in the processing chamber. Next, the sputtering gas is switched to a sputtering gas containing nitrogen, and a silicon nitride layer is formed using the same silicon target. Since the silicon oxide layer and the silicon nitride layer can be continuously formed without being exposed to the atmosphere, it is possible to prevent impurities such as hydrogen and moisture from adsorbing on the surface of the silicon oxide layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is laminated as the protective insulating layer 398. Then, a heat treatment (temperature: 100°C to 400 °C) may be performed to diffuse hydrogen or moisture contained in the oxide semiconductor layer into the oxide insulating layer. After the formation of the protective insulating layer, a heat treatment may be further performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or the temperature may be increased from room temperature to a heating temperature of 100°C or higher and 200°C, and the temperature may be decreased from the heating temperature to room temperature repeatedly a plurality of times. Further, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Performing the heat treatment under reduced pressure can shorten the heating time. By this heat treatment, a thin film transistor that becomes normally-off (in the case of an n-channel transistor, the threshold voltage becomes a positive value) can be obtained. Therefore, the reliability of the liquid crystal display device can be improved. When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction

[0238] After the formation of the protective insulating layer, a heat treatment may be further performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or the temperature may be increased from room temperature to a heating temperature of 100°C or higher and 200°C, and the temperature may be decreased from the heating temperature to room temperature repeatedly a plurality of times. Further, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. Performing the heat treatment under reduced pressure can shorten the heating time. By this heat treatment, a thin film transistor that becomes normally-off (in the case of an n-channel transistor, the threshold voltage becomes a positive value) can be obtained. Therefore, the reliability of the liquid crystal display device can be improved. When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction

[0239] When forming an oxide semiconductor layer as a channel formation region on the gate insulating layer, the reaction By removing residual moisture in the atmosphere, the concentrations of hydrogen and hydrides in the oxide semiconductor layer can be reduced.

[0240] The above process can be used in the manufacture of a backplane (a substrate on which thin film transistors are formed) such as a liquid crystal display panel, an electroluminescence display panel, or a display device using electronic ink. Since the above process is performed at a temperature of 400°C or lower, it can also be applied to a manufacturing process using a glass substrate with a thickness of 1 mm or less and one side exceeding 1 m. Also, since all processes can be performed at a processing temperature of 4 00°C or lower, it is not necessary to consume a large amount of energy for manufacturing the display panel. As described above, in a plurality of pixels constituting a display unit of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer, the off-current can be reduced. Therefore, the period during which the voltage can be held by the holding capacitance can be extended, and a liquid crystal display device capable of achieving low power consumption when displaying a still image or the like can be obtained.

[0241] As described above, in a plurality of pixels constituting a display unit of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer, the off-current can be reduced. Therefore, the period during which the voltage can be held by the holding capacitance can be extended, and a liquid crystal display device capable of achieving low power consumption when displaying a still image or the like can be obtained. can be extended, and low power consumption can be achieved when displaying a still image or the like. A liquid crystal display device can be obtained.

[0242] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0243] (Embodiment 6) This embodiment shows another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification. The thin film transistor 310 shown in this embodiment can be used as the thin film transistor 106 of Embodiment 1.

[0244] One form of the thin film transistor and the method of manufacturing the thin film transistor according to this embodiment will be described with reference to FIG. 11. ​​​​

[0245] Figs. 11(A) to (E) show an example of the cross-sectional structure of a thin film transistor. Figs. 11(A) to (E) show a thin film transistor 310, which is one of the bottom gate structures and is also called an inverted staggered thin film transistor.

[0246] Also, although the thin film transistor 310 is described using a single gate structure thin film transistor, if necessary, a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed.

[0247] Hereinafter, the process of fabricating the thin film transistor 310 on the substrate 300 will be described with reference to Figs. 11(A) to (E).

[0248] First, after forming a conductive film on the substrate 300 having an insulating surface, a gate electrode layer 311 is formed by a first photolithography process. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since no photomask is used, the manufacturing cost can be reduced.

[0249] There is no major limitation on the substrate that can be used for the substrate 300 having an insulating surface, but at least, it is necessary to have heat resistance to withstand subsequent heat treatment.

[0250] For example, when using a glass substrate as the substrate 300, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher. For the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Note that, compared with boron oxide, it contains more barium oxide (BaO). ​ By doing so, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0251] In addition to the above glass substrate, as the substrate 300, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, crystallized glass or the like can also be used.

[0252] An insulating film serving as an underlayer film may be provided between the substrate 300 and the gate electrode layer 311. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 300, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0253] Moreover, the material of the gate electrode layer 311 can be formed as a single layer or by lamination using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material mainly composed of these.

[0254] For example, as the two-layer laminated structure of the gate electrode layer 311, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, a two-layer laminated structure in which a molybdenum layer is laminated on a copper layer, a two-layer laminated structure in which a titanium nitride layer or tantalum nitride is laminated on a copper layer, a two-layer laminated structure in which a titanium nitride layer and a molybdenum layer are laminated, or a two-layer laminated structure of a tungsten nitride layer and a tungsten layer is preferable. As the three-layer laminated structure, a tungsten layer or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and nitrogen It is preferable to form a laminate in which titanium oxide or a titanium layer is laminated.

[0255] Next, a gate insulating layer 302 is formed on the gate electrode layer 311.

[0256] The gate insulating layer 302 can be formed as a single layer or laminated with a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer by using a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer can be formed by a plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the gate insulating layer 302 is set to 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. It is used to form a silicon oxynitride layer by the plasma CVD method. The film thickness of the gate insulating layer 302 is set to 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. It is set to 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. It is set to 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. It is set to 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer.

[0257] In this embodiment, a silicon oxynitride layer with a film thickness of 100 nm or less is formed as the gate insulating layer 302 by a plasma CVD method. It is formed by a plasma CVD method.

[0258] Next, an oxide semiconductor film 330 with a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less, is formed on the gate insulating layer 302. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness can be appropriately selected according to the material. The cross-sectional view at this stage corresponds to FIG. 11(A). It is formed on the gate insulating layer 302. The appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness can be appropriately selected according to the material. The cross-sectional view at this stage corresponds to FIG. 11(A).

[0259] Before forming the oxide semiconductor film 330 by sputtering, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas to remove dust adhering to the surface of the gate insulating layer 302. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. It is used to remove dust adhering to the surface of the gate insulating layer 302. It is used to remove dust adhering to the surface of the gate insulating layer 302. It may be used instead of the argon atmosphere.

[0260] The oxide semiconductor film 330 is made of an In-Ga-Zn-O-based, In-Sn-Zn-O-based, In-A l-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn -O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn- O-based, or Zn-O-based oxide semiconductor film. In this embodiment, the oxide semiconductor film 330 is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. Specifically, as the composition ratio, In2O3:Ga2O3:ZnO = 1:1:1 [mol %] (that is, In:Ga:Zn = 1:1:0.5 [atom%]) is used. Alternatively, targets having a composition ratio of In:Ga:Zn = 1:1:1 [atom%] or In:Ga:Zn = 1:1:2 atom%] can also be used. Note that the filling rate of the oxide semiconductor ta rget is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide semiconductor target with a high filling rate, the formed oxide semiconductor film becomes a dense film. Also, the target may contain 2 wt% or more and 10 wt% or less of SiO2.

[0261] As for the sputtering gas used when forming the oxide semiconductor film 330, high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrogen compounds are removed to 1 ppm or less, preferably 10 ppb or less, is preferably used.

[0262] In sputtering, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. Film formation is performed while heating the substrate. By doing so, the impurity concentration in the formed oxide semiconductor film can be reduced. . Further, the damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and an oxide semiconductor film 330 is formed on the substrate 30 using the above target. In order to remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as the exhaust means, a turbo pump with a cold trap added thereto may be used. When evacuating using a cryopump, the film formation chamber, for example, compounds containing hydrogen atoms such as hydrogen molecules and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0263] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa , a DC power supply of 0.5 kW, and conditions in an oxygen (oxygen flow rate ratio 100%) atmosphere are applied. Note that when using a pulsed DC power supply, dust can be reduced and the film thickness distribution becomes uniform, so it is preferable.

[0264] Next, the oxide semiconductor film 330 is processed into island-shaped oxide semiconductor layers 331 by a second photolithography process. Further, a resist mask for forming the island-shaped oxide semiconductor layer may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photo mask is not used, the manufacturing cost can be reduced.

[0265] Next, a first heat treatment is performed on the oxide semiconductor layer 331. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer 331 can be carried out. The temperature of the first heat treatment is 400°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer 331 (see Fig. 11(B)). The dehydration or dehydrogenation of the oxide semiconductor layer 331 can be carried out. The temperature of the first heat treatment is 400°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer 331 (see Fig. 11(B)). The temperature of the first heat treatment is 400°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer 331 (see Fig. 11(B)). Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer 331 (see Fig. 11(B)). Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer 331 (see Fig. 11(B)). Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without exposing it to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layer 331 (see Fig. 11(B)). )

[0266] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used. Note that the heat treatment apparatus is not limited to an electric furnace, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus for performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or an inert gas that does not react with the object to be treated by the heat treatment, such as nitrogen, is used.

[0267] For example, as the first heat treatment, the substrate is moved and placed into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then the substrate is moved and placed into an inert gas heated to a high temperature. For example, as the first heat treatment, the substrate is moved and placed into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then the substrate is moved and placed into an inert gas heated to a high temperature. GRTA may be performed to emit. When GRTA is used, high-temperature heat treatment can be performed in a short time. This becomes possible.

[0268] In the first heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Or, the purity of nitrogen, or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more , preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). This is preferable.

[0269] As a result of the first heat treatment, hydrogen and the like contained in the oxide semiconductor layer 331 are removed, but at the same time, oxygen deficiency also occurs, so it becomes an n-type semiconductor (a semiconductor with reduced resistance). Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 331 may crystallize and become a microcrystalline film or a polycrystalline film. For example, the crystallization rate may be 90% or more, or an oxide semiconductor film of microcrystals of 80% or more. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 331 may be an amorphous oxide semiconductor film that does not contain a crystal component. Also, in the amorphous oxide semiconductor, fine crystalline portions (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) may be mixed to form an oxide semiconductor film. This is also possible.

[0270] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 330 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus, and a photolithography process is performed. This is also possible.

[0271] The heat treatment that has the effect of dehydrating and dehydrogenating the oxide semiconductor layer can be carried out after forming the oxide semiconductor layer film. If it is after that, after laminating the source electrode and the drain electrode on the oxide semiconductor layer, the source It may be carried out either after forming the protective insulating film on the electrode and the drain electrode.

[0272] Also, when forming a contact hole in the gate insulating layer 302, the process can be carried out before or after performing the dehydration or dehydrogenation treatment on the oxide semiconductor film 330 or the oxide semiconductor layer 331.

[0273] Note that the etching of the oxide semiconductor film here is not limited to wet etching, and dry etching may be used.

[0274] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired processing shape can be etched.

[0275] Next, a conductive film is formed on the gate insulating layer 302 and the oxide semiconductor layer 331. The conductive film may be formed by sputtering or vacuum evaporation. As the material of the conductive film, Al, Cr, C u, Ta, Ti, Mo, W, an element selected therefrom, or an alloy containing the above-described elements, or an alloy film formed by combining the above-described elements, etc. may be mentioned. Also, manganese, magnesium , zirconium, beryllium, a material selected from any one or more of yttrium may be used. Also, the conductive film may have a single-layer structure or a laminated structure of two or more layers. For example , a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on the aluminum film , a Ti film, an aluminum film is laminated on the Ti film, and further on that Examples include a three-layer structure for forming a Ti film. Also, for Al, a film, alloy film, or nitride film using an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium ), Sc (scandium) alone or in combination of multiple elements may be used.

[0276] When performing a heat treatment after the conductive film, it is preferable that the conductive film has heat resistance to withstand this heat treatment. This is preferable.

[0277] A resist mask is formed on the conductive film by a third photolithography process, and after selectively etching to form the source electrode layer 315a and the drain electrode layer 315b, the resist mask is removed (see Fig. 11(C)).

[0278] For the exposure during the formation of the resist mask in the third photolithography process, ultraviolet light, KrF laser light, or ArF laser light is used. The channel length L of the thin-film transistor formed later is determined by the interval width between the lower end of the source electrode layer adjacent to the oxide semiconductor layer 331 and the lower end of the drain electrode layer. When performing exposure with a channel length L < 25 nm, exposure during the formation of the resist mask in the third photolithography process is performed using extreme ultraviolet (Extreme Ultraviolet t) with a very short wavelength of several nm to several 10 nm. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the thin-film transistor formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit, and further, since the off-current value is extremely small, low power consumption can be achieved.

[0279] ​​​​​​​​​Note that when etching the conductive film, the material and etching conditions of are appropriately adjusted so that the oxide semiconductor layer 331 is not removed.

[0280] In this embodiment, since a Ti film is used as the conductive film and an In-Ga -Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 331, aqueous ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the etchant.

[0281] Note that in the third photolithography process, only a part of the oxide semiconductor layer 331 may be etched to form an oxide semiconductor layer having a groove portion (recess). Further, a resist mask for forming the source electrode layer 3 15a and the drain electrode layer 315b may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0282] Further, an oxide conductive layer may be formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The metal layer for forming the oxide conductive layer and the source electrode layer and the drain electrode layer allows for continuous film formation. The oxide conductive layer can function as a source region and a drain region.

[0283] By providing the oxide conductive layer as the source region and the drain region between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, the resistance of the source region and the drain region can be reduced, and the transistor can operate at high speed.

[0284] Further, in order to reduce the number of photomasks and the number of processes used in the photolithography process, a resist mask formed by a multi-tone mask, which is an exposure mask in which transmitted light has a plurality of intensities, is used. Etching may be performed using a mask. A resist mask formed using a multi-tone mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching, so it can be used in multiple etching processes for processing different patterns. Therefore, a resist mask corresponding to at least two or more different patterns can be formed using a single multi-tone mask. Thus, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, enabling simplification of the process.

[0285] Next, plasma treatment using a gas such as N2O, N2, or Ar is performed. This plasma treatment removes adsorbed water and the like attached to the surface of the exposed oxide semiconductor layer. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0286] After the plasma treatment, an oxide insulating layer 316 serving as a protective insulating film in contact with a part of the oxide semiconductor layer is formed without exposing it to the atmosphere.

[0287] The oxide insulating layer 316 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the oxide insulating layer 316. If the oxide insulating layer 316 contains hydrogen, the hydrogen may penetrate into the oxide semiconductor layer, or the hydrogen may extract oxygen from the oxide semiconductor layer, causing oxygen deficiency and resulting in a low-resistance (N-type) back channel of the oxide semiconductor layer, which may form a parasitic channel. Therefore, it is important that the oxide insulating layer 316 is formed into a film that contains as little hydrogen as possible by not using hydrogen in the film formation method.

[0288] In this embodiment, a silicon oxide film with a thickness of 200 nm is formed as the oxide insulating layer 316 by sputtering method. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 100°C. Film formation of the silicon oxide film by sputtering can be performed in a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide can be formed by sputtering using a silicon target in an oxygen and nitrogen atmosphere. The oxide insulating layer 316 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH - and blocks the intrusion of these from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. In this case, it is preferable to form the oxide insulating layer 316 while removing residual moisture in the

[0289] processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer 331 and the oxide insulating layer 316.

[0290] To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as an exhaust means, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump exhausts, for example, compounds containing hydrogen atoms such as hydrogen molecules and water (H2O). Therefore, the oxide insulating layer formed in the The concentration of impurities contained in 316 can be reduced.

[0291] When forming the oxide insulating layer 316, the sputtering gas used is a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use such a gas.

[0292] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 316.

[0293] By going through the above steps, a heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film after film formation. As a result, a part of the low-resistance oxide semiconductor film is selectively made in an oxygen-excess state. As a result, the channel formation region 313 overlapping with the gate electrode layer 311 becomes of type I, and a high-resistance source region 314a made of a low-resistance oxide semiconductor overlapping with the source electrode layer 315a and a high-resistance drain region 314b made of a low-resistance oxide semiconductor overlapping with the drain electrode layer 315b are self-alignedly formed. The thin-film transistor 310 is formed by the above steps (see Fig. 11(D)).

[0294] Furthermore, a heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. In this embodiment, a heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or from room temperature to a heating temperature of 100°C or higher and 200°C. The temperature increase and the temperature decrease from the heating temperature to room temperature may be repeated a plurality of times. Also, this heating treatment may be performed under reduced pressure before forming the oxide insulating film. When performing the heat treatment under reduced pressure the heating time can be shortened. By this heat treatment, hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved. Also, when using a silicon oxide layer containing many defects in the oxide insulating layer, impurities such as hydrogen, moisture, hydroxyl groups or hydrides contained in the oxide semiconductor layer are diffused into the oxide insulating layer, and the impurities contained in the oxide semiconductor layer can be further reduced.

[0295] In addition, by forming a high-resistance drain region 314b (or high-resistance source region 314a) in the oxide semiconductor layer superimposed on the drain electrode layer 315b (and source electrode layer 315a), the reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region 314b, a structure can be formed such that the conductivity can be changed stepwise from the drain electrode layer 315b to the high-resistance drain region 314b and the channel formation region 313. Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer 315b, even if a high electric field is applied between the gate electrode layer 311 and the drain electrode layer 315b, the high-resistance drain region serves as a buffer and a local high electric field is not applied, and a configuration can be adopted in which the breakdown voltage of the transistor is improved.

[0296] Also, the high-resistance source region or high-resistance drain region in the oxide semiconductor layer is an oxide semiconductor When the thickness of the layer is as thin as 15 nm or less, it is formed throughout the thickness direction of the film. However, when the thickness of the oxide semiconductor layer is thicker, between 30 nm and 50 nm, a region in contact with a part of the oxide semiconductor layer, the source electrode layer, or the drain electrode layer and its vicinity becomes low resistance, and a high-resistance source region or a high-resistance drain region is formed. In the oxide semiconductor layer, the region close to the gate insulating film can also be of type I. When the thickness of the oxide semiconductor layer is thicker, between 30 nm and 50 nm, a region in contact with a part of the oxide semiconductor layer, the source electrode layer, or the drain electrode layer and its vicinity becomes low resistance, and a high-resistance source region or a high-resistance drain region is formed. In the oxide semiconductor layer, the region close to the gate insulating film can also be of type I. When the thickness of the oxide semiconductor layer is thicker, between 30 nm and 50 nm, a region in contact with a part of the oxide semiconductor layer, the source electrode layer, or the drain electrode layer and its vicinity becomes low resistance, and a high-resistance source region or a high-resistance drain region is formed. In the oxide semiconductor layer, the region close to the gate insulating film can also be of type I. It can also be of type I.

[0297] A protective insulating layer may be further formed on the oxide insulating layer 316. For example, a silicon nitride film is formed using the RF sputtering method. Since the RF sputtering method has good mass productivity, it is preferable as a method for forming the protective insulating layer. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used. A silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. are used. In this embodiment, the protective insulating layer 303 is formed using a silicon nitride film as the protective insulating layer (see Fig. 11(E)). Since the RF sputtering method has good mass productivity, it is preferable as a method for forming the protective insulating layer. The protective insulating layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used. - It does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used. A silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. are used. In this embodiment, the protective insulating layer 303 is formed using a silicon nitride film as the protective insulating layer (see Fig. 11(E)). In this embodiment, the protective insulating layer 303 is formed using a silicon nitride film as the protective insulating layer (see Fig. 11(E)). (See Fig. 11(E).)

[0298] In this embodiment, as the protective insulating layer 303, the substrate 300 formed up to the oxide insulating layer 316 is heated to a temperature of 100°C to 400°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced, and a silicon nitride film is formed using a silicon semiconductor target. In this embodiment, as the protective insulating layer 303, the substrate 300 formed up to the oxide insulating layer 316 is heated to a temperature of 100°C to 400°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced, and a silicon nitride film is formed using a silicon semiconductor target. In this case as well, similar to the oxide insulating layer 316, it is preferable to form the protective insulating layer 303 while removing residual moisture in the processing chamber. In this case as well, similar to the oxide insulating layer 316, it is preferable to form the protective insulating layer 303 while removing residual moisture in the processing chamber. It is preferable to form the protective insulating layer 303 while removing residual moisture in the processing chamber.

[0299] A planarizing insulating layer for planarization may be provided on the protective insulating layer 303.

[0300] As described above, in the display section of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer in a plurality of pixels constituting the same, the off-current can be reduced. Therefore, the holding capacitance can hold the voltage for a longer period, and it is possible to achieve low power consumption when displaying a still image or the like and obtain a liquid crystal display device that can achieve this.

[0301] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments as appropriate.

[0302] (Embodiment 7) This embodiment shows another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification. The thin film transistor 360 shown in this embodiment can be used as the thin film transistor 106 in Embodiment 1 as described above. and can be used as the thin film transistor 106 in Embodiment 1.

[0303] An example of a cross-sectional structure of the thin film transistor and a method for manufacturing the thin film transistor according to this embodiment will be described with reference to FIG. 12 .

[0304] FIGS. 12(A) to (D) show an example of a cross-sectional structure of the thin film transistor. The thin film transistor 360 shown in FIGS. 12(A) to (D) is one of the bottom gate structures called a channel protection type (also referred to as a channel stop type) and is also called an inverse staggered type thin film transistor. and is also called an inverse staggered type thin film transistor.

[0305] In addition, although the thin film transistor 360 is described using a single gate structure thin film transistor, if necessary, a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed. can also be formed.

[0306] Hereinafter, with reference to FIGS. 12(A) to (D), the thin film transistor 360 is manufactured on the substrate 320 The process will be described.

[0307] First, after forming a conductive film on a substrate 320 having an insulating surface, a resist mask is formed by a first photolithography process, and using this, the conductive film is selectively etched to form the gate electrode layer 361. Then, the resist mask is removed. Note that the resist mask may be formed by an inkjet method. Since forming the resist mask by the inkjet method does not use a photomask, the manufacturing cost can be reduced.

[0308] Also, the material of the gate electrode layer 361 can be formed as a single layer or laminated using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these.

[0309] Next, a gate insulating layer 322 is formed on the gate electrode layer 361.

[0310] In this embodiment, a silicon oxynitride layer with a film thickness of 100 nm or less is formed by plasma CVD as the gate insulating layer 322.

[0311] Next, an oxide semiconductor film with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 322 and processed into an island-shaped oxide semiconductor layer by a second photolithography process. In this embodiment, an In-Ga-Zn-O-based oxide semiconductor target is used as the oxide semiconductor film and formed by sputtering.

[0312] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the processing chamber. This is to prevent the oxide semiconductor film from containing hydrogen, hydroxyl groups, or moisture.

[0313] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added thereto may be used. The film formation chamber evacuated using a cryopump exhausts compounds containing hydrogen atoms such as hydrogen molecules and water (H2O), etc. Therefore, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0314] The sputtering gas used when forming the oxide semiconductor film is preferably a high-purity gas in which any impurity has been removed to 1 ppm or less, preferably 10 ppb or less, of hydrogen, water, hydroxyl groups, or hydrides.

[0315] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 400°C or higher and 750°C or lower, preferably lower than the strain point of the substrate and 400°C or higher. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 332 is obtained (see Fig. 12(A)).

[0316] Next, plasma treatment using a gas such as N2O, N2, or Ar is performed. This plasma treatment removes adsorbed water and the like adhering to the surface of the oxide semiconductor layer that is exposed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0317] Next, an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332. Subsequently, a resist mask is formed by a third photolithography process, and selective etching is performed to form the oxide insulating layer 366, and then the resist mask is removed.

[0318] In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the oxide insulating layer 366 by sputtering method. The substrate temperature during film formation may be set to be equal to or higher than room temperature and equal to or lower than 300 °C. In this embodiment, it is set to 100 °C. Film formation of the silicon oxide film by sputtering can be performed in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide can be formed by sputtering in an oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 366 formed in contact with the oxide semiconductor layer shall not contain impurities such as moisture, hydrogen ions, and OH and shall block the intrusion of these from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. - from the outside. In this case, it is preferable to form the oxide insulating layer 366 while removing residual moisture in the processing chamber. This is to prevent the oxide semiconductor layer 332 and the oxide insulating layer 366 from containing hydrogen, hydroxyl groups, or moisture.

[0319] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used.

[0320] For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. This is preferable. Further, as the exhaust means, a cold trap may be added to the turbo pump. The film formation chamber evacuated using a cryopump is evacuated of compounds containing hydrogen atoms such as hydrogen molecules and water (H2O), for example, and thus the concentration of impurities contained in the oxide insulating layer 366 formed in the film formation chamber can be reduced.

[0321] When forming the oxide insulating layer 366, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to 1 ppm or less, preferably 10 ppb or less.

[0322] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 366.

[0323] In this embodiment, the oxide semiconductor layer 332 provided with the oxide insulating layer 366 and having a part thereof exposed is heat-treated in a nitrogen or inert gas atmosphere or under reduced pressure. When the region of the exposed oxide semiconductor layer 332 not covered by the oxide insulating layer 366 is heat-treated in a nitrogen or inert gas atmosphere or under reduced pressure, the resistance can be reduced. For example, a heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere.

[0324] The heat treatment of the oxide semiconductor layer 332 provided with the oxide insulating layer 366 in a nitrogen atmosphere ​​​​​​​​​​As a result, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 12( In Fig. 1B, the oxide semiconductor layer 362 has a region indicated by hatched areas and white areas.

[0325] Next, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive film, a resist mask is formed by a fourth photolithography process. After selectively etching the silicon dioxide film to form the source electrode layer 365a and the drain electrode layer 365b, The resist mask is removed (see FIG. 12(C)).

[0326] The source electrode layer 365a and the drain electrode layer 365b may be made of Al, Cr, Cu, or T. An element selected from the group consisting of a, Ti, Mo, and W, or an alloy containing the above elements, or Examples include alloy films that combine the elements mentioned above. Conductive films can be either single-layer or double-layered. The above laminated structure may also be used.

[0327] By performing the above steps, a part of the oxide semiconductor film is selectively made into an oxygen-excess state. As a result, the channel forming region 363 overlapping the gate electrode layer 361 becomes I-shaped, and A high-resistance source region 364a overlaps the source electrode layer 365a, and a high-resistance source region 364b overlaps the drain electrode layer 365b. The high resistance drain region 364b is formed in a self-aligned manner. A star 360 is formed.

[0328] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The temperature increase and the temperature decrease from the heating temperature to room temperature may be repeated a plurality of times. Also, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. When the heat treatment is performed under reduced pressure the heating time can be shortened. By this heat treatment, hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved.

[0329] In addition, in the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a), a high-resistance drain region 364b (or a high-resistance source region 364a) made of a low-resistance oxide semiconductor is formed to improve the reliability of the thin film transistor. Specifically, by forming the high-resistance drain region 364b, a structure can be obtained in which the conductivity changes stepwise from the drain electrode layer to the high-resistance drain region 364b and the channel formation region 363. Therefore, when operating by connecting to a wiring for supplying a high source potential VDD to the drain electrode layer 365b, even if a high electric field is applied between the gate electrode layer 361 and the drain electrode layer 365b, the high-resistance drain region serves as a buffer and a local high electric field is not applied, and a configuration can be obtained that improves the breakdown voltage of the transistor.

[0330] A protective insulating layer 323 is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film (see FIG. 12(D)).

[0331] In addition, further An oxide insulating layer may be formed, and a protective insulating layer 323 may be laminated on the oxide insulating layer.

[0332] As described above, in a display portion of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer in a plurality of pixels constituting the same, an off-current can be reduced. Therefore, the period during which a voltage can be held by a holding capacitor can be lengthened, and low power consumption when displaying a still image or the like can be achieved, and a liquid crystal display device can be obtained.

[0333] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0334] (Embodiment 8) This embodiment shows another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification. The thin film transistor 350 shown in this embodiment can be used as the thin film transistor 106 of Embodiment 1.

[0335] One form of the thin film transistor and the method for manufacturing the thin film transistor according to this embodiment will be described with reference to FIG. 13. is used for the description.

[0336] Further, although the thin film transistor 350 is described using a single gate structure thin film transistor, if necessary, a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed. is possible.

[0337] Hereinafter, the process of manufacturing the thin film transistor 350 on the substrate 340 will be described with reference to FIGS. 13(A) to (D). is described.

[0338] First, after forming a conductive film on the substrate 340 having an insulating surface, a first photolithography Form the gate electrode layer 351 by a process. In this embodiment, as the gate electrode layer 351, form a tungsten film with a thickness of 150 nm using a sputtering method.

[0339] Next, form the gate insulating layer 342 on the gate electrode layer 351. In this embodiment, as the gate insulating layer 342, form a silicon oxynitride layer with a thickness of 100 nm or less by plasma CVD method. <x Form it.

[0340] Next, form a conductive film on the gate insulating layer 342, form a resist mask on the conductive film by a second photolithography process, perform selective etching to form the source electrode layer 355a and the drain electrode layer 355b, and then remove the resist mask (see Fig. 13(A)). ). ).

[0341] Next, form the oxide semiconductor film 345 (see Fig. 13(B)). In this embodiment, as the oxide semiconductor film 345, form a film by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. Process the oxide semiconductor film 345 into island-shaped oxide semiconductor layers by a third photolithography process. ).

[0342] In this case, it is preferable to form the oxide semiconductor film 345 while removing residual moisture in the processing chamber. This is to ensure that the oxide semiconductor film 345 does not contain hydrogen, hydroxyl groups or moisture. ).

[0343] To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added is used. This may be the case. The film formation chamber evacuated using a cryopump contains, for example, compounds containing hydrogen molecules, compounds containing hydrogen atoms such as water (H2 O), etc. Therefore, the concentration of impurities contained in the oxide semiconductor film 345 formed in the film formation chamber can be reduced.

[0344] When forming the oxide semiconductor film 345, the sputtering gas used is preferably high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrogen compounds have been removed to 1 ppm or less, preferably 10 ppb or less.

[0345] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and 750°C or lower, preferably 400°C or higher and less than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after performing a heat treatment on the oxide semiconductor layer at 450°C for 1 hour in a nitrogen atmosphere, without being exposed to the atmosphere, re-mixing of water or hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 346 is obtained ( see Fig. 13(C)).

[0346] Also, as the first heat treatment, the substrate may be moved and placed in an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then a GRTA may be performed to move the substrate out of the inert gas heated to a high temperature. Using GRTA enables high-temperature heat treatment in a short time.

[0347] An oxide insulating layer 356 serving as a protective insulating layer in contact with the oxide semiconductor layer 346 is formed.

[0348] The oxide insulating layer 356 has a film thickness of at least 1 nm or more, and is formed by a method such as sputtering, an oxide insulating ​​​​​​​It can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into layer 356. When the oxide insulating layer 356 contains hydrogen, the hydrogen may penetrate into the oxide semiconductor layer, or the hydrogen may extract oxygen in the oxide semiconductor layer, resulting in oxygen deficiency and causing the back channel of the oxide semiconductor layer to have a lower resistance (become N-type), and there is a possibility of forming a parasitic channel. Therefore, it is important that the oxide insulating layer 356 is formed into a film that contains as little hydrogen as possible by not using hydrogen in the film formation method.

[0349] In this embodiment, a silicon oxide film with a thickness of 200 nm is formed as the oxide insulating layer 356 by sputtering. The substrate temperature during film formation may be room temperature or higher and 300°C or lower, and in this embodiment, it is set to 100°C. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide can be formed by sputtering using a silicon target in an atmosphere of oxygen and nitrogen. The oxide insulating layer 356 formed in contact with the oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH - and blocks the intrusion of these from the outside, and typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used.

[0350] In this case, it is preferable to form the oxide insulating layer 356 while removing residual moisture in the processing chamber. This is to prevent the oxide semiconductor layer 346 and the oxide insulating layer 356 from containing hydrogen, hydroxyl groups, or moisture. ​

[0351] In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as the exhaust means, a turbo pump with a cold trap added thereto may be used. The film formation chamber evacuated using a cryopump is evacuated of compounds containing hydrogen atoms such as hydrogen molecules and water (H2O), and thus the concentration of impurities contained in the oxide insulating layer 356 formed in the film formation chamber can be reduced. When evacuating using a cryopump, the film formation chamber is evacuated of compounds containing hydrogen atoms such as hydrogen molecules and water (H2 O), etc. Therefore, the concentration of impurities contained in the oxide insulating layer 356 formed in the film formation chamber can be reduced. The oxide insulating layer 356 is formed using a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to 1 ppm or less, preferably 10 ppb or less.

[0352] When forming the oxide insulating layer 356, the sputtering gas used is a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to 1 ppm or less, preferably 10 ppb or less. The oxide insulating layer 356 is formed using a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use.

[0353] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 356. By going through the above steps, the oxide semiconductor film is brought into an oxygen-excess state. As a result, an n-type oxide semiconductor layer 352 is formed. The thin film transistor 350 is formed through the above steps. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 356. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 356.

[0354] By going through the above steps, the oxide semiconductor film is brought into an oxygen-excess state. As a result, an n-type oxide semiconductor layer 352 is formed. The thin film transistor 350 is formed through the above steps. As a result, an n-type oxide semiconductor layer 352 is formed. The thin film transistor 350 is formed through the above steps. is formed.

[0355] Furthermore, a heat treatment is performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide semiconductor layer can be converted into an oxide film. Hydrogen is taken into the insulating layer, and a normally-off thin film transistor can be obtained. This improves the reliability of the liquid crystal display device.

[0356] A protective insulating layer may be further formed on the oxide insulating layer 356. For example, a protective insulating layer may be formed by RF sputtering. In this embodiment, a protective insulating layer 343 is formed as a protective insulating layer. The insulating film is formed using a silicon nitride film (see FIG. 13(D)).

[0357] A planarization insulating layer for planarization may be provided over the protective insulating layer 343.

[0358] As described above, the display portion of a liquid crystal display device having a thin film transistor using an oxide semiconductor layer Therefore, the off-state current can be reduced in the plurality of pixels constituting the storage capacitor. This allows the voltage to be maintained for a longer period, which reduces power consumption when displaying still images, etc. The liquid crystal display device can achieve this.

[0359] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0360] (Embodiment 9) The present embodiment is directed to another thin film transistor that can be applied to the liquid crystal display device disclosed in this specification. An example will be shown. The thin film transistor 380 shown in this embodiment can be used as the thin film transistor 106 of Embodiment 1.

[0361] In this embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from that of Embodiment 6 is shown in FIG. 14. Since FIG. 14 is the same as FIG. 11 except for the part where the process is different, the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted.

[0362] According to Embodiment 6, a gate electrode layer 381 is formed on the substrate 370, and the first gate insulating layer 372a and the second gate insulating layer 372b are laminated. In this embodiment, the gate insulating layer has a two-layer structure, a nitride insulating layer is used for the first gate insulating layer 372a, and an oxide insulating layer is used for the second gate insulating layer 372b. As the oxide insulating layer, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer can be used. As the nitride insulating layer, a silicon nitride layer, a silicon oxynitride layer, an aluminum nitride layer, or an aluminum oxynitride layer can be used.

[0363]

[0364] In this embodiment, a structure in which a silicon nitride layer and a silicon oxide layer are laminated from the side of the gate electrode layer 381 is adopted. As the first gate insulating layer 372a, a silicon nitride layer (SiN (y>0)) with a film thickness of 50 nm or more and 200 nm or less (50 nm in this embodiment) is formed by sputtering, and on the first gate insulating layer 372a, a silicon oxide layer with a film thickness of 5 nm or more and 300 nm or less (100 nm in this embodiment) is formed as the second gate insulating layer 372b. y (y> 0)) x Stack (x>0)) to form, for example, a gate insulating layer with a film thickness of 150 nm.

[0365] Next, an oxide semiconductor film is formed and the oxide semiconductor film is processed into island-shaped oxide semiconductor layers by a photolithography process. In this embodiment, an In-Ga-Z n-O-based oxide semiconductor target is used to form a film by sputtering.

[0366] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the processing chamber This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor film.

[0367] To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump is, for example, exhausted of compounds containing hydrogen atoms such as hydrogen molecules and water (H2 O), etc., so that the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0368] The sputtering gas used when forming the oxide semiconductor film is a high-purity gas from which any impurity such as hydrogen, water, hydroxyl groups, or hydrides has been removed to 1 ppm or less, preferably 10 ppb or less. It is preferable to use such a gas.

[0369] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 400 °C or higher and 750 °C or lower of the substrate, preferably 425 °C or higher. ​​If the temperature is 425°C or higher, the heat treatment time may be 1 hour or less. If the temperature is lower than 425°C, the heat treatment time shall be longer than 1 hour. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere. After that, without exposing it to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented to obtain an oxide semiconductor layer. Then, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) is introduced into the same furnace for cooling. It is preferable that water, hydrogen, etc. are not contained in the oxygen gas or N2O gas. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e., the impurity concentration in the oxygen gas or N2O gas is 1 ppm or lower, preferably 0.1 ppm or lower). Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas.

[0370] Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. The LRTA apparatus is a device that heats the object to be processed by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Further, the LRTA apparatus may be provided with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA means heating using high-temperature gas. It is a method of performing a process. As the gas, an inert gas such as argon or a gas like nitrogen that does not react with the object to be processed by heat treatment is used. Using the RTA method, heat treatment may be performed at 600 °C ~750 °C for several minutes. ~750 °C for several minutes.

[0371] Also, after the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed in an oxygen gas or N2O gas atmosphere at a temperature of 200 °C or higher and 400 °C or lower, preferably 200 °C or higher and 300 °C or lower. Also, after the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed in an oxygen gas or N2O gas atmosphere at a temperature of 200 °C or higher and 400 °C or lower, preferably

[0372] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography process is performed. Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography process is performed. Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography process is performed.

[0373] By going through the above steps, the entire oxide semiconductor film is made in an oxygen-excess state, thereby achieving high resistance oxidation, that is, type I conversion. Thus, an oxide semiconductor layer 382 that is entirely type I converted is obtained. By going through the above steps, the entire oxide semiconductor film is made in an oxygen-excess state, thereby achieving high resistance oxidation, that is, type I conversion. Thus, an oxide semiconductor layer 382 that is entirely type I converted is obtained.

[0374] Next, a conductive film is formed on the oxide semiconductor layer 382, a resist mask is formed by a photolithography process, and selective etching is performed to form a source electrode layer 385a and a drain electrode layer 385b, and an oxide insulating layer 386 is formed by a sputtering method. Next, a conductive film is formed on the oxide semiconductor layer 382, a resist mask is formed by a photolithography process, and selective etching is performed to form a source electrode layer 385a and a drain electrode

[0375] In this case, it is preferable to form the oxide insulating layer 386 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer 382 and the oxide insulating layer 386. In this case, it is preferable to form the oxide insulating layer 386 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer 382 and the oxide insulating layer 386. In this case, it is preferable to form the oxide insulating layer 386 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer 382 and the oxide insulating layer 386.

[0376] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. As the exhaust means, a turbo pump with a cold trap added thereto may be used. The film formation chamber evacuated using a cryopump exhausts, for example, compounds containing hydrogen molecules, compounds containing hydrogen atoms such as water (H2O), etc., so that the concentration of impurities contained in the oxide insulating layer 386 formed in the film formation chamber can be reduced. When forming the oxide insulating layer 386, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to 1 ppm or less, preferably 10 ppb or less.

[0377]

[0378] In the above steps, the thin film transistor 380 can be formed.

[0379] Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, heat treatment (preferably at 150°C or higher and lower than 350°C) may be performed in an inert gas atmosphere or in a nitrogen gas atmosphere. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0380] Also, heat treatment may be performed in the atmosphere at 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. In this embodiment, heat treatment is performed at 150°C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be repeated a plurality of times with a temperature increase from room temperature to a heating temperature of 100°C or higher and 200°C and a temperature decrease from the heating temperature to room temperature. Further, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. Performing the heat treatment under reduced pressure can shorten the heating time. By this heat treatment, from the oxide semiconductor layer ​ Hydrogen can be trapped in the insulating layer, and a normally-off thin film transistor can be obtained. Therefore, the reliability of the liquid crystal display device can be improved.

[0381] A protective insulating layer 373 is formed on the oxide insulating layer 386. In this embodiment, as the protective insulating layer 3 73, a silicon nitride film with a thickness of 100 nm is formed using a sputtering method.

[0382] The protective insulating layer 373 made of a nitride insulating layer and the first gate insulating layer 372a do not contain impurities such as moisture, water element, hydride, and hydroxide, and have the effect of blocking these from entering from the outside.

[0383] Therefore, in the manufacturing process after the formation of the protective insulating layer 373, the intrusion of impurities such as moisture from the outside can be prevented. Also, even after the device is completed as a liquid crystal display device, in the long term the intrusion of impurities such as moisture from the outside can be prevented, and the long-term reliability of the device can be improved.

[0384] Also, the insulating layer provided between the protective insulating layer 373 made of a nitride insulating layer and the first gate insulating layer 372a may be removed so that the protective insulating layer 373 and the first gate insulating layer 372a are in contact with each other.

[0385] Therefore, the moisture, hydrogen, hydride, hydroxide, and other impurities in the oxide semiconductor layer can be ultimately reduced to the lowest level, and the re-mixing of these impurities can be prevented, and the impurity concentration in the oxide semiconductor layer can be maintained low.

[0386] A planarization insulating layer for planarization may be provided on the protective insulating layer 373.

[0387] ​​​​​​​As described above, in the display section of a liquid crystal display device having thin film transistors using an oxide semiconductor layer in a plurality of pixels constituting the same, the off-current can be reduced. Therefore, the period during which the voltage can be held by the holding capacitor can be extended, and a liquid crystal display device capable of achieving low power consumption when displaying a still image or the like can be obtained.

[0388] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments as appropriate.

[0389] (Embodiment 10) This embodiment shows another example of a thin film transistor applicable to the liquid crystal display device disclosed in this specification The thin film transistor shown in this embodiment can be applied to the thin film transistors of Embodiments 2 to 8 as appropriate.

[0390] In this embodiment, an example is shown in which a conductive material having translucency is used for the gate electrode layer, the source electrode layer, and the drain electrode layer. Therefore, the other operations can be performed in the same manner as in the above embodiments, and the description of the same parts or parts having similar functions and the repetition of the processes in the above embodiments are omitted as appropriate. Further, the detailed description of the same portion is omitted. For example, as the materials of the gate electrode layer, the source electrode layer, and the drain electrode layer, a conductive material having translucency to visible light, such as an In-Sn-O-based, In-Sn-Zn-O-based, In-Al -Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-

[0391] O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O -based, Zn-O-based metal oxide can be applied, and the film thickness is 50 nm or more and 300 nm or less -Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn- O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O -based, Zn-O-based metal oxide can be applied, and the film thickness is 50 nm or more and 300 nm or less Select appropriately within the range. The metal oxides used for the gate electrode layer, source electrode layer, and drain electrode layer are formed by sputtering, vacuum deposition (such as electron beam evaporation), arc discharge ion plating, or spraying. When using sputtering, a target containing 2 wt% or more and 10 wt% or less of SiO2 is used for film formation, and SiOx (X>0) that inhibits crystallization is included in the conductive film having transparency, and it is preferable to suppress crystallization during the heating treatment performed in a later step.

[0392] Note that the unit of the composition ratio of the conductive film having transparency is atomic%, and it is evaluated by analysis using an electron probe X-ray microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer ).

[0393] In addition, for the pixel in which the thin film transistor is disposed, a conductive film having transparency to visible light is used for the pixel electrode layer, or other electrode layers (such as a capacitive electrode layer) or other wiring layers (such as a capacitive wiring layer), and a display device having a high aperture ratio can be realized. Of course, it is preferable to use a film having transparency to visible light for the gate insulating layer, oxide insulating layer, protective insulating layer, and planarizing insulating layer existing in the pixel.

[0394] In this specification, a film having transparency to visible light refers to a film having a film thickness with a visible light transmittance of 75 to 100 %, and when the film has conductivity, it is also called a transparent conductive film. In addition, as the metal oxide applied to the gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrode layers and other wiring layers, a semi-transparent conductive film to visible light is used It may be. Being translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0395] Providing the thin film transistor with translucency can improve the aperture ratio. Especially in a small liquid crystal display panel of 10 inches or less, in order to increase the number of gate wirings and achieve higher definition of the displayed image, even if the pixel size is miniaturized, a high aperture ratio can be realized. Also, by using a film with translucency for the constituent members of the thin film transistor, in order to achieve a wide viewing angle, even if one pixel is divided into a plurality of sub-pixels, a high aperture ratio can be realized. That is, even if a high-density thin film transistor group is arranged, the aperture ratio can be increased, and the area of the display region can be sufficiently secured. For example, when one pixel has 2 to 4 sub-pixels, since the thin film transistor has translucency, the aperture ratio can be improved. Also, if the holding capacitor is formed using the same material in the same process as the constituent members of the thin film transistor, the holding capacitor can also be made translucent, so that the aperture ratio can be further improved. That is, even if a high-density thin film transistor group is arranged, the aperture ratio can be increased, and the area of the display region can be sufficiently secured. For example, when there are 2 to 4 sub-pixels in one pixel, since the thin film transistor has translucency, the aperture ratio can be improved. Also, if the holding capacitor is formed using the same material in the same process as the constituent members of the thin film transistor, the holding capacitor can also be made translucent, so that the aperture ratio can be further improved. When the holding capacitor is formed using the same material in the same process as the constituent members of the thin film transistor, the holding capacitor can also be made translucent, so that the aperture ratio can be further improved. .

[0396] This embodiment can be implemented in appropriate combination with other embodiments.

[0397] (Embodiment 11) Regarding the appearance and cross-section of a liquid crystal display panel corresponding to one form of the liquid crystal display device, it will be described with reference to FIG. 15. FIG. 15 is a plan view of the panel in which the thin film transistors 4010, 4011, and the liquid crystal element 4013 formed on the first substrate 4001 are sealed with a sealing material 4005 between the second substrate 4006. FIG. 15(B) corresponds to a cross-sectional view taken along M-N in FIG. 15(A) or FIG. 15(C). ​

[0398] Surrounding the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 In this way, the sealing material 4005 is provided. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006 . Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001 .

[0399] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 15(A) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 15(C) is an example of mounting the signal line driving circuit 4003 by the TA B method.

[0400] Also, the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 have a plurality of thin film transistors. In FIG. 15(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. Insulating layers 4041, 4 042, 4020, and 4021 are provided above and below the thin film transistors 4010 and 4011.

[0401] The thin film transistors 4010 and 4011 are the thin film transistors of any one of Embodiments 2 to 9 A dissta can be used as appropriate and can be formed by the same processes and materials. The oxide semiconductor layers of the thin film transistors 4010 and 4011 have reduced hydrogen and water. Therefore, the thin film transistors 4010 and 4011 are highly reliable thin film transistors. In this embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0402] On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. Also, the conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011 or may have a different potential, and can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0403] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided for the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0404] ​​​​​​​​​​ As the first substrate 4001 and the second substrate 4006, a light-transmissive substrate can be used, and glass, ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used.

[0405] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Using a common connection part, the counter electrode layer 40 31 and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 40 05.

[0406] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, and therefore, problems caused by the rubbing treatment can be eliminated. since rubbing treatment is not required, problems caused by the rubbing treatment can be eliminated. It is possible to prevent electrostatic breakdown from occurring, and reduce defects and damage in the liquid crystal display device during the manufacturing process Therefore, it is possible to improve the productivity of the liquid crystal display device. In particular, a thin film transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated by the influence of static electricity and deviate from the design range. Therefore, using a blue phase liquid crystal material in a liquid crystal display device having a thin film transistor using an oxide semiconductor layer is more effective. is more effective.\n is more effective.

[0407] Note that the liquid crystal display panel of this embodiment is an example of a transmissive liquid crystal display device, but one aspect of the present invention can also be applied to semi-transmissive or reflective liquid crystal display devices.

[0408] In addition, in a liquid crystal display device, a polarizing plate is provided on the outside (viewing side) of the substrate, and an example is shown in which a coloring layer and an electrode layer used for display elements are provided in this order on the inside. However, the polarizing plate may be provided inside the substrate. Also the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment, and may be appropriately set according to the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. Also, a light-shielding film that functions as a black matrix may be provided outside the display portion. and the manufacturing process conditions. Also, a light-shielding film that functions as a black matrix may be provided outside the display portion. and the manufacturing process conditions. Also, a light-shielding film that functions as a black matrix may be provided outside the display portion.

[0409] On the thin film transistors 4011 and 4010, an insulating layer 4041 is formed in contact with the oxide semiconductor layer. Here, as the insulating layer 4041, a silicon oxide layer is formed by a sputtering method On the thin film transistors 4011 and 4010, an insulating layer 4041 is formed in contact with the oxide semiconductor layer. Here, as the insulating layer 4041, a silicon oxide layer is formed by a sputtering method On the thin film transistors 4011 and 4010, an insulating layer 4041 is formed in contact with the oxide semiconductor layer. Here, as the insulating layer 4041, a silicon oxide layer is formed by a sputtering method. Also, a protective insulating layer 4042 is formed in contact with the insulating layer 4041. Also the protective insulating layer 4042 can use, for example, a silicon nitride film. Also, an insulating layer 4021 that functions as a planarizing insulating film to reduce the surface unevenness of the thin film transistor is provided to cover the protective insulating layer 4042. the protective insulating layer 4042 can use, for example, a silicon nitride film. Also, an insulating layer 4021 that functions as a planarizing insulating film to reduce the surface unevenness of the thin film transistor is provided to cover the protective insulating layer 4042. the protective insulating layer may use, for example, a silicon nitride film. Also, an insulating layer that functions as a planarizing insulating film to reduce the surface unevenness of the thin film transistor is provided to cover the protective insulating layer.

[0410] Also, an insulating layer 4021 is formed as a planarization insulating film. As the insulating layer 4021, organic materials having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials. polyimide, acrylic, benzocyclobutene, polyamide, epoxy, etc., organic materials with heat resistance can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) , siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used . Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials. 4021 may be formed.

[0411] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, an SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. By combining the baking process of the insulating layer 4021 with the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a liquid crystal display device. OG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater , knife coater, etc. can be used. By combining the baking process of the insulating layer 4021 with the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a liquid crystal display device. , knife coater, etc. can be used. By combining the baking process of the insulating layer 4021 with the annealing of the semiconductor layer, it becomes possible to efficiently manufacture a liquid crystal display device. It becomes possible to efficiently manufacture a liquid crystal display device by combining the baking process of the insulating layer 4021 with the annealing of the semiconductor layer.

[0412] The pixel electrode layer 4030 and the counter electrode layer 4031 can be formed of any light-transmissive conductive material such as indium tin oxide (ITO), IZO (indium zinc oxide) in which zinc oxide (ZnO) is mixed with indium oxide, a conductive material in which silicon dioxide (SiO2) is mixed with indium oxide, organic indium, organic tin, indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium. Or, in a reflective liquid crystal display device, when there is no need to have light transmittance or when it is necessary to have reflectivity, tungsten (W) IZO (indium zinc oxide) in which zinc oxide (ZnO) is mixed with indium oxide , a conductive material in which silicon dioxide (SiO2) is mixed with indium oxide, organic indium, organic tin, indium oxide containing tungsten, indium zinc oxide containing tungsten , indium oxide containing titanium, indium tin oxide containing titanium, etc. can be used. Or, in a reflective liquid crystal display device, when there is no need to have light transmittance or when it is necessary to have reflectivity, tungsten (W) , indium oxide containing titanium, indium tin oxide containing titanium, etc. can be used. Or, in a reflective liquid crystal display device, when there is no need to have light transmittance or when it is necessary to have reflectivity, tungsten (W) any light-transmissive conductive material can be used. Or, in a reflective liquid crystal display device, when there is no need to have light transmittance or when it is necessary to have reflectivity, tungsten (W) When there is no need to have light transmittance or when it is necessary to have reflectivity, tungsten (W) ) One or more of metals such as molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V ), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (A g), etc., or their alloys, or their metal nitrides can be used to form them. It can be formed.

[0413] In addition, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Also, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0414] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0415] In addition, various signals and potentials supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel portion 4 002 are supplied from the FPC 4018.

[0416] The connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010 and 4011.

[0417] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. and is electrically connected.

[0418] In addition, in FIG. 15, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. and mounted.

[0419] In addition, optical members (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a retardation member, and an antireflection member are appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. In addition, a backlight, a side light, or the like may be used as the light source. using circular polarization by a polarizing substrate and a retardation substrate may be used. In addition, a backlight, a side light, or the like may be used as the light source. using circular polarization by a polarizing substrate and a retardation substrate may be used. In addition, a backlight, a side light, or the like may be used as the light source.

[0420] In an active matrix liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, so that the optical modulation of the liquid crystal layer arranged between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by the observer as the display pattern. and this optical modulation is recognized by the observer as the display pattern. and this optical modulation is recognized by the observer as the display pattern. and this optical modulation is recognized by the observer as the display pattern. and this optical modulation is recognized by the observer as the display pattern.

[0421] In addition, since the thin film transistor is easily damaged by static electricity or the like, it is preferable to further provide a protection circuit on the same substrate as the pixel portion or the driving circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits and it is preferable to further provide a protection circuit on the same substrate as the pixel portion or the driving circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits and it is preferable to further provide a protection circuit on the same substrate as the pixel portion or the driving circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits and it is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits A path is provided such that a surge voltage is applied to the scanning line, signal line, and capacitance bus line due to static electricity or the like, and is configured so that pixel transistors and the like are not damaged. Therefore, when a surge voltage is applied to the protection circuit, it is configured to discharge the charge to the common wiring. Further, the protection circuit is composed of a non-linear element arranged in parallel between the scanning line, signal line, or capacitance bus line and the common wiring. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it can be formed in the same process as the thin film transistor in the pixel portion. For example, by connecting the gate terminal and the drain terminal, characteristics similar to those of a diode can be obtained.

[0422] In addition, the liquid crystal display module can use a TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetrically Aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal), etc. S(In-Plane-Switching) mode, FFS(Fringe Field d Switching) mode, ASM(Axially Symmetric al igned Micro-cell) mode, OCB(Optical Compens ated Birefringence) mode, FLC(Ferroelectric Liquid Crystal) mode, AFLC(AntiFerroelectr ic Liquid Crystal), etc. can be used.

[0423] Thus, in the liquid crystal display device disclosed in this specification, the type of liquid crystal element is not particularly limited, and TN liquid crystal, OCB liquid crystal, STN liquid crystal, VA liquid crystal, ECB type liquid crystal, GH liquid crystal, polymer dispersed type liquid crystal, discotic liquid crystal, etc. can be used. Among them, in particular, normally black Let it be a transmissive liquid crystal display device adopting a liquid crystal panel of a certain type, for example, a vertical alignment (VA) mode. This is preferable. Depending on conditions, these liquid crystal materials exhibit a cholesteric phase, a smectic phase , a cubic phase, a chiral nematic phase, an isotropic phase, etc. Also, as the vertical alignment mode , several examples can be mentioned. For example, the MVA (Multi-Domain Verti cal Alignment) mode, the PVA (Patterned Vertical Alignment) mode, the ASV mode, etc. can be used.

[0424] Moreover, it can also be applied to a VA type liquid crystal display device. The VA type liquid crystal display device is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is a method in which liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. Also, a method called multi-domainization or multi-domain design, in which pixels (picture elements) are divided into several regions (sub-pixels) and the molecules are devised to be tilted in different directions , can be used.

[0425] Note that one aspect of the present invention is not limited to a liquid crystal display device, and can also be applied to pixels of an EL display device using a light-emitting element such as an electroluminescence element (also referred to as an EL element) as a display element.

[0426] This embodiment can be implemented in appropriate combination with other embodiments.

[0427] (Embodiment 12) In this embodiment, an example of an electronic device including the liquid crystal display device described in the above embodiment will be described.

[0428] Figure 16(A) is a portable gaming machine, which can have a housing 9630, a display unit 9631, a speaker 9633 , operation keys 9635, connection terminals 9636, a recording medium reading unit 9672, etc. The portable gaming machine shown in Figure 16(A) can have a function of reading a program or data recorded on a recording medium and displaying it on the display unit, a function of performing wireless communication with other portable gaming machines to share information, etc. Note that the functions of the portable gaming machine shown in Figure 16(A) are not limited to this, and it can have various functions. Figure 16(B) is a digital camera, which can have a housing 9630, a display unit 9631, a speaker 963 3, operation keys 9635, connection terminals 9636, a shutter button 9676, an imaging unit 9677 , etc. The digital camera with a television reception function shown in Figure 16(B) can have a function of taking still images, a function of taking moving images, a function of automatically or manually correcting the taken images, a function of obtaining various information from an antenna, a function of saving the taken images or the information obtained from the antenna, a function of displaying the taken images or the information obtained from the antenna on the display unit, etc. Note that the functions of the digital camera with a television reception function shown in Figure 16(B) are not limited to this, and it can have various functions. Figure 16(C) is a television receiver, which can have a housing 9630, a display unit 9631, a speaker 9633

[0429] , operation keys 9635, connection terminals 9636, etc. The television receiver shown in Figure 16(C) can have a function of processing television radio waves and converting them into image signals, a function of processing the image signals and converting them into signals suitable for display, a function of converting the frame frequency of the image signals, etc. , operation keys 9635, connection terminals 9636, a shutter button 9676, an imaging unit 9677 , etc. The digital camera with a television reception function shown in Figure 16(B) can have a function of taking still images, a function of taking moving images, a function of automatically or manually correcting the taken images, a function of obtaining various information from an antenna, a function of saving the taken images or the information obtained from the antenna, a function of displaying the taken images or the information obtained from the antenna on the display unit, etc. Note that the functions of the digital camera with a television reception function shown in Figure 16(B) are not limited to this, and it can have various functions. , operation keys 9635, connection terminals 9636, a shutter button 9676, an imaging unit 9677 , etc. The digital camera with a television reception function shown in Figure 16(B) can have a function of taking still images, a function of taking moving images, a function of automatically or manually correcting the taken images, a function of obtaining various information from an antenna, a function of saving the taken images or the information obtained from the antenna, a function of displaying the taken images or the information obtained from the antenna on the display unit, etc. Note that the functions of the digital camera with a television reception function shown in Figure 16(B) are not limited to this, and it can have various functions. , operation keys 9635, connection terminals 9636, a shutter button 9676, an imaging unit 9677 , etc. The digital camera with a television reception function shown in Figure 16(B) can have a function of taking still images, a function of taking moving images, a function of automatically or manually correcting the taken images, a function of obtaining various information from an antenna, a function of saving the taken images or the information obtained from the antenna, a function of displaying the taken images or the information obtained from the antenna on the display unit, etc. Note that the functions of the digital camera with a television reception function shown in Figure 16(B) are not limited to this, and it can have various functions. , operation keys 9635, connection terminals 9636, a shutter button 9676, an imaging unit 9677

[0430] , operation keys 9635, connection terminals 9636, etc. The television receiver shown in Figure 16(C) can have a function of processing television radio waves and converting them into image signals, a function of processing the image signals and converting them into signals suitable for display, a function of converting the frame frequency of the image signals, etc. , operation keys 9635, connection terminals 9636, etc. The television receiver shown in Figure 16(C) can have a function of processing television radio waves and converting them into image signals, a function of processing the image signals and converting them into signals suitable for display, a function of converting the frame frequency of the image signals, etc. , operation keys 9635, connection terminals 9636, etc. The television receiver shown in Figure 16(C) can have a function of processing television radio waves and converting them into image signals, a function of processing the image signals and converting them into signals suitable for display, a function of converting the frame frequency of the image signals, etc. , operation keys 9635, connection terminals 9636, etc. The television receiver shown in Figure 16(C) can have a function of processing television radio waves and converting them into image signals, a function of processing the image signals and converting them into signals suitable for display, a function of converting the frame frequency of the image signals, etc. It is possible. Note that the functions of the television receiver shown in Fig. 16(C) are not limited to this, and it can have various functions. It is not limited to this, and it can have various functions.

[0431] Fig. 17(A) shows a computer, which can have a housing 9630, a display unit 9631, a speaker 9633 , operation keys 9635, connection terminals 9636, a pointing device 9681, an external connection port 9680, etc. The computer shown in Fig. 17(A) can have functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, controlling processing by various software (programs), a communication function such as wireless communication or wired communication, a function of connecting to various computer networks using the communication function, a function of transmitting or receiving various data using the communication function, etc. Note that the functions of the computer shown in Fig. 17(A) are not limited to this, and it can have various functions.

[0432] Next, Fig. 17(B) shows a mobile phone, which can have a housing 9630, a display unit 9631, a speaker 963 3, operation keys 9635, a microphone 9638, etc. The mobile phone shown in Fig. 17(B) can have functions such as displaying various information (still images, moving images, text images, etc.), a function of displaying a calendar, date, or time, etc. on the display unit, a function of operating or editing the information displayed on the display unit, a function of controlling processing by various software (programs), etc. Note that the functions of the mobile phone shown in Fig. 17(B) are not limited to this, and it can have various functions.

[0433] Next, Fig. 17(C) shows an electronic paper (also called an E-book), which has a housing 9630, a display It can have a display unit 9631, operation keys 9635, etc. The electronic paper shown in Fig. 17(C) has functions such as displaying various information (still images, moving images, text images, etc.), a calendar , a function of displaying the date or time on the display unit, a function of operating or editing the information displayed on the display unit , a function of controlling processing by various software (programs), etc. . Note that the functions of the electronic paper shown in Fig. 17(C) are not limited to this, and it can have various functions.

[0434] In the electronic device described in this embodiment, in a plurality of pixels constituting the display unit, the off-current can be reduced. Therefore, the period during which the voltage can be held by the holding capacitance can be lengthened, and an electronic device including a liquid crystal display device capable of achieving low power consumption when displaying a still image or the like can be provided. Also, by improving the aperture ratio, a liquid crystal display device having a high-definition display unit can be provided.

[0435] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0436] (Embodiment 13) In this embodiment, the operating principle of a bottom-gate type transistor using an oxide semiconductor will be described.

[0437] Fig. 18 is a cross-sectional view of an inverted staggered insulating gate type transistor usin...

Claims

1. a first conductive layer having a first opening; a second conductive layer having a region located inside the first opening in a plan view and functioning as one of a source and a drain of a transistor; an oxide semiconductor layer having a region in contact with a lower surface of the second conductive layer and having a channel formation region of the transistor; a third conductive layer having the same material as the second conductive layer and being electrically connected to the first conductive layer; a first insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer and containing oxygen; a second insulating layer having a region located above the first insulating layer and containing nitrogen; a fourth conductive layer having a region in contact with an upper surface of the second insulating layer, a region overlapping with the first conductive layer, a region overlapping with the second conductive layer, and a region overlapping with the channel formation region, and having a second opening; a fifth conductive layer having a region in contact with an upper surface of the second insulating layer and having the same material as the fourth conductive layer; in a plan view, the first opening and the second opening have an overlapping region; in a plan view, the oxide semiconductor layer has a region located inside the second opening; the fifth conductive layer is electrically connected to the third conductive layer, a semiconductor device.

2. A first conductive layer having a first opening; a second conductive layer having a region located inside the first opening in a plan view and functioning as one of a source and a drain of a transistor; an oxide semiconductor layer having a region in contact with a lower surface of the second conductive layer and having a channel formation region of the transistor; a third conductive layer having the same material as the second conductive layer and being electrically connected to the first conductive layer; a first insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a second insulating layer having a region located above the first insulating layer; a fourth conductive layer having a region in contact with an upper surface of the second insulating layer, a region overlapping with the first conductive layer, a region overlapping with the second conductive layer, and a region overlapping with the channel formation region, and having a second opening; a fifth conductive layer having a region in contact with an upper surface of the second insulating layer and having the same material as the fourth conductive layer; in a plan view, the first opening and the second opening have an overlapping region; In plan view, the oxide semiconductor layer has a region located inside the second opening. The fifth conductive layer is electrically connected to the third conductive layer, a semiconductor device.

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