Indicating device

Abstract

To provide a semiconductor device having a composition capable of sufficiently reducing parasitic capacitance between interconnections.SOLUTION: A bottom gate thin film transistor using an oxide semiconductor layer comprises: an oxide insulation layer to be a channel protection layer which is formed to partially contact a surface of an oxide semiconductor layer and overlap a gate electrode layer; and an oxide insulation layer which is formed at the time of forming the former oxide insulation layer to cover a periphery (including lateral faces) of lamination of the oxide semiconductor layer. The thin film transistor further comprises: a source electrode layer and a drain electrode layer which are formed not to overlap the channel protection layer; and an insulation layer formed on the source electrode layer and the drain electrode layer, which contacts the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology for constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. There are many types of metal oxides and they are used for various purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides with excellent semiconductor properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055

Summary of the Invention

Problems to be Solved by the Invention

[0006] When manufacturing a plurality of thin film transistors on an insulating surface, for example, there is a portion where a gate wiring and a source wiring intersect. An insulating layer is provided between the intersecting portion, between the gate wiring and the source wiring having a different potential from the gate wiring, and the insulating layer becomes a dielectric to form a capacitance. This capacitance is also called a parasitic capacitance between wirings, and there is a risk of signal waveform distortion. Also, if the parasitic capacitance is large, there is a risk that signal transmission will be slow.

[0007] In addition, an increase in parasitic capacitance leads to a crosstalk phenomenon in which an electrical signal leaks between wirings and an increase in power consumption.

[0008] Also, in an active matrix type display device, particularly when a large parasitic capacitance is formed between a signal wiring for supplying a video signal and another wiring or electrode, there is a risk of deterioration in display quality.

[0009] Also, even when attempting to miniaturize a circuit, the wiring interval becomes narrow, and there is a risk of an increase in the parasitic capacitance between wirings.

[0010] One aspect of the present invention is to provide a semiconductor device having a configuration capable of sufficiently reducing the parasitic capacitance between wirings. This is one of the problems.

[0011] Also, when forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate, the thin film transistors used in the pixel portion are required to have excellent switching characteristics, for example, a large on-off ratio, and for the thin film transistors used in the driving circuit, ​​​​​A high operating speed is required. In particular, the higher the definition of the display device, the shorter the writing time of the display image, so the thin film transistor used in the driving circuit preferably has a high operating speed.

[0012] In addition, it is also an issue to prevent a complicated process and an increase in manufacturing cost, form a plurality of types of circuits on the same substrate, and provide a semiconductor device including a plurality of types of thin film transistors respectively adapted to the characteristics of the plurality of types of circuits.

Means for Solving the Problems

[0013] In a thin film transistor having a bottom gate structure, an oxide insulating layer serving as a channel protection layer that contacts a part of the oxide semiconductor layer overlapping the gate electrode layer is formed, and an oxide insulating layer covering the peripheral portion (including the side surface) of the oxide semiconductor layer is formed when the oxide insulating layer is formed.

[0014] The oxide insulating layer covering the peripheral portion (including the side surface) of the oxide semiconductor layer increases the distance from the gate electrode layer and the wiring layer (such as a source wiring layer or a capacitor wiring layer) formed above or around it, and reduces the parasitic capacitance. Since the oxide insulating layer covering the peripheral portion of the oxide semiconductor layer is formed in the same process as the channel protection layer, the parasitic capacitance can be reduced without increasing the number of processes.

[0015] The oxide insulating layer covering the peripheral portion (including the side surface) of the oxide semiconductor layer can reduce the parasitic capacitance and suppress the blurring of the signal waveform.

[0016] In addition, in order to reduce the parasitic capacitance, it is preferable to use an insulating material with a small dielectric constant as the oxide insulating layer sandwiched between the wirings.

[0017] ​​​​​​​One aspect of the present invention disclosed in this specification is a gate electrode layer on an insulating surface, and on the gate electrode layer a gate insulating layer, an oxide semiconductor layer on the gate insulating layer, an oxide insulating layer on the oxide semiconductor layer, a source electrode layer or a drain electrode layer on the oxide insulating layer, and an insulating layer on the source electrode layer or also on the drain electrode layer. The oxide semiconductor layer has a first region in contact with the oxide insulating layer, a second region in contact with the source electrode layer or the drain electrode layer, and a third region in contact with the insulating layer. Among the first regions, the region overlapping through the gate electrode layer and the gate insulating layer is the channel formation region, and there is a third region between the channel formation region and the second region which is a semiconductor device.

[0018] The above configuration solves at least one of the above problems.

[0019] The drain electrode layer made of a metal electrode such as Ti is in contact with a part of the upper surface of the oxide semiconductor layer, and a high-resistance drain region (also called an HRD (High Resistance Drain) region) which is an oxygen-deficient type overlapping with the drain electrode layer is formed. Also, the source electrode layer is in contact with a part of the upper surface of the oxide semiconductor layer, and a high-resistance source region (also called an HRS (High Resistance Source) region) which is an oxygen-deficient type overlapping with the source electrode layer is formed .

[0020] Also, the source electrode layer and the drain electrode layer are configured not to overlap with the channel formation region of the oxide semiconductor layer, and the area of the region overlapping through the gate electrode layer and the gate insulating layer is also extremely small, or there is no region overlapping with the gate electrode layer, so the parasitic capacitance is also reduced . Also, the side surface of the source electrode layer and the width of the oxide insulating layer functioning as a channel protection layer ​, the distance between the side surface of the drain electrode layer facing the side surface is wider. Thin film transistor In order to increase the operating speed of the transistor, if the width of the oxide insulating layer (width in the channel length direction) that functions as a channel protection layer is designed to be small, the distance between the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface also becomes small, and there is a risk of short circuit between the source electrode layer and the drain electrode layer. Therefore, it is useful to widen the distance. Further, in the above configuration, the oxide insulating layer that functions as a channel protection layer uses an inorganic insulating film formed by sputtering. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, etc. are used. In the above configuration, on the upper surface of the oxide semiconductor layer, there is a region that does not overlap with the oxide insulating layer, the drain electrode layer, and the source electrode layer, that is, a third region. The width of this third region in the channel length direction is determined by the patterning position of the oxide semiconductor layer and the patterning positions of the drain electrode layer and the source electrode layer. If the width of this third region in the channel length direction is widened, the off-current of the thin film transistor can be reduced. Also,

[0021] if the width of this third region in the channel length direction is narrowed, the operating speed of the thin film transistor can be increased. Further, the insulating layer in contact with the third region also uses an inorganic insulating film formed by sputtering. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film, etc. are used. Note that the insulating layer in contact with the third region is the oxide insulating layer that functions as a channel protection layer.

[0022]

[0023] ​​​​​​​​​​​When using the same material, the oxide insulating layer that functions as a channel protection layer can be called the first oxide insulating layer, and the insulating layer in contact with the third region can be called the second oxide insulating layer. The boundary between the first oxide semiconductor layer and the second oxide insulating layer becomes unclear.

[0024] Note that as the oxide semiconductor layer, for example, a thin film represented by InMO3(ZnO) m (m > 0) is formed, and a thin film transistor using the thin film as the oxide semiconductor layer is manufactured. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga, such as Ga and Ni or Ga and F e, are included. Also, in the above oxide semiconductor, in addition to the metal elements included as M, there are those that contain impurity elements such as Fe, Ni, and other transition metal elements, or oxides of the transition metals. In this specification, among the oxide semiconductor layers having a structure represented by InM O3(ZnO) (m > 0), the oxide semiconductor having a structure containing Ga as M is called an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also called an In -Ga-Zn-O-based non-single crystal film. O3(ZnO) m (m > 0), among the oxide semiconductor layers having a structure represented by, the oxide semiconductor having a structure containing Ga as M is called an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also called an In -Ga-Zn-O-based non-single crystal film. -Ga-Zn-O-based non-single crystal film.

[0025] In addition to the above, as the metal oxide applied to the oxide semiconductor layer, In-Sn-Zn-O systems, In-Al-Zn-O systems, Sn-Ga-Zn-O systems, Al-Ga-Zn-O systems, Sn -Al-Zn-O systems, In-Zn-O systems, Sn-Zn-O systems, Al-Zn-O systems, In- O systems, Sn-O systems, Zn-O systems of metal oxides can be applied. Also, silicon oxide can be included in the oxide semiconductor layer composed of the above metal oxides.

[0026] Also, in the above configuration, the source electrode layer and the drain electrode layer are made of an element selected from Ti, Mo, W, Al, C r, Cu, Ta, an alloy containing the above-described elements as components, or an alloy obtained by combining the above-described elements is used. The source electrode layer and the drain electrode layer are not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used.

[0027] Also, one aspect of the present invention for realizing the above structure is to form a gate electrode layer on a substrate having an insulating surface, form a gate insulating layer on the gate electrode layer, and form an oxide semiconductor layer on the gate insulating layer. After dehydrating or dehydrogenating the oxide semiconductor layer, without exposing it to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented. An oxide insulating layer that is in contact with a part of the oxide semiconductor layer and covers the periphery and side surfaces of the oxide semiconductor layer is formed. A source electrode layer and a drain electrode layer are formed on the oxide insulating layer. This is a method for manufacturing a semiconductor device that forms an insulating layer in contact with the oxide insulating layer, the source electrode layer, the drain electrode layer, and the oxide semiconductor layer.

[0028] The dehydration or dehydrogenation is a heat treatment at 400°C or higher and lower than the strain point of the substrate, preferably 420°C or higher and 570°C or lower, in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), which reduces impurities such as the contained moisture in the oxide semiconductor layer.

[0029] When a heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and its resistance is reduced, that is, it is made N-type ( N -type conversion, etc.). Then, formation of an oxide insulating film in contact with the oxide semiconductor layer and heating after formation - are performed. ​By performing heat treatment to make the oxide semiconductor layer in an oxygen-excessive state, the resistance is increased, that is, it can be said that the layer is made into the I type. Also, solid-phase oxidation to make the oxide semiconductor layer in an oxygen-excessive state is carried out which can also be called such. Thereby, it becomes possible to fabricate and provide a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability.

[0030] For the oxide semiconductor layer subjected to dehydration or dehydrogenation, even when measurement is performed up to 450 °C by TDS on the oxide semiconductor layer after dehydration or dehydrogenation, the heat treatment conditions are such that two peaks of water and at least one peak that appears around 300 °C are not detected. Therefore, even when measurement is performed up to 45 0 °C by TDS on the thin-film transistor using the oxide semiconductor layer subjected to dehydration or dehydrogenation, the peak of water that appears around at least 300 °C is not detected.

[0031] When the temperature is lowered from the heating temperature T at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, it is important not to expose it to the atmosphere using the same furnace in which dehydration or dehydrogenation has been performed, so that water or hydrogen is not mixed in again. After performing dehydration or dehydrogenation to make the oxide semiconductor layer have a lower resistance, that is, to make it N-type (N etc.), and then making it have a higher resistance to make it into the I type, when a thin-film transistor is fabricated using the oxide semiconductor layer, the threshold voltage value of the thin-film transistor can be made into a plus value, and a so-called normally-off switching element can be realized. It is desirable for the semiconductor device (display device) that the channel is formed at a positive threshold voltage as close as possible to 0 V for the gate voltage of the thin-film transistor. - Note that when the threshold voltage value of the thin-film transistor is negative, current flows between the source electrode and the drain electrode even when the gate voltage is 0 V. ​​​​​​​​It tends to become a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistors, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, when the driving voltage is low, it cannot perform the switching function as a TFT and may become a load. In the case of an n-channel type thin film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied to the gate voltage. A transistor that cannot form a channel unless the driving voltage is increased, or a transistor in which a channel is formed even in a negative voltage state and a drain current flows, is not suitable as a thin film transistor used in a circuit.

[0032] Also, the gas atmosphere for lowering the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere when the temperature is raised to the heating temperature T. For example, without exposing to the atmosphere in the same furnace after dehydration or dehydrogenation, the inside of the furnace is filled with high-purity oxygen gas or N2O gas, or ultra-dry air (dew point is -40 °C or lower, preferably -60 °C or lower) and cooled.

[0033] After reducing the contained moisture in the film by a heat treatment for dehydration or dehydrogenation, the electrical characteristics of the thin film transistor are improved and mass production is achieved using an oxide semiconductor film slowly cooled (or cooled) in an atmosphere free of moisture (dew point is -40 °C or lower, preferably -60 °C or lower). ​​​​​​​​​​Realize a thin-film transistor having both properties and high performance.

[0034] In this specification, heat treatment in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) is called heat treatment for dehydration or dehydrogenation. In this specification, this heat treatment is not only called dehydrogenation when desorbing as H2, but also includes desorbing H , OH, etc., and is conveniently called dehydration or dehydrogenation.

[0035] When heat treatment is performed in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), the oxide semiconductor layer becomes oxygen-deficient type by heat treatment and its resistance decreases, that is, it becomes N-type ( N - type conversion, etc.).

[0036] In addition, a high-resistance drain region (also called the HRD region) that is oxygen-deficient and overlaps with the drain electrode layer is formed. Also, a high-resistance source region ( also called the HRS region) that is oxygen-deficient and overlaps with the source electrode layer is formed.

[0037] Specifically, the carrier concentration of the high-resistance drain region is in the range of 1×10 18 / cm 3 or more, and is higher than at least the carrier concentration (less than 1×10 18 / cm 3 of the channel formation region). Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature.

[0038] And by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excessive state, the resistance is further increased, that is, it is made into the I-type to form a channel formation region. Note that the de ​​​As a process for making the hydrated or dehydrogenated oxide semiconductor layer in an oxygen-excess state, dehydration or dehydrogenation is performed by forming an oxide insulating film in contact with the hydrated or dehydrogenated oxide semiconductor layer by sputtering, or by heat treatment after forming the oxide insulating film, or by heat treatment in an atmosphere containing oxygen after forming the oxide insulating film , or by cooling in an oxygen atmosphere after heating in an inert gas atmosphere after forming the oxide insulating film , or by cooling with ultra-dry air (dew point is -40 °C or lower, preferably -60 °C or lower) after heating in an inert gas atmosphere after forming the oxide insulating film.

[0039] Also, at least a part (the part overlapping with the gate electrode layer) of the dehydrated or dehydrogenated oxide semiconductor layer is used as the channel formation region, and by selectively making it in an oxygen-excess state, it can be made highly resistive, that is, type-I.

[0040] As a result, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0041] Note that by forming a high-resistance drain region in the oxide semiconductor layer overlapping with the drain electrode layer, the reliability when forming a drive circuit can be improved. Specifically, by forming a high-resistance drain region, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region and the channel formation region. Therefore, when operating by connecting to a wiring for supplying a high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region serves as a buffer and a local high electric field is not applied, and a configuration can be obtained in which the breakdown voltage of the transistor is improved.

[0042] Also, in the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer), a high-resistance drain region is formed to reduce the leakage current in the channel formation region when a drive circuit is formed. Specifically, by forming the high-resistance drain region, the path of the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer is the drain electrode layer, the high-resistance drain region on the drain electrode layer side, the channel formation region, the source electrode layer, and the high-resistance source region on the source electrode layer side in that order. At this time, in the channel formation region, the leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region is concentrated near the interface between the gate insulating layer, which becomes high resistance when the transistor is off, and the channel formation region, and the leakage current in the back channel portion (a part of the surface of the channel formation region away from the gate electrode layer) can be reduced. In addition, examples of the display device having a drive circuit include, in addition to a liquid crystal display device, a light-emitting display device using a light-emitting element and a display device also referred to as electronic paper using an electrophoretic display element. In the light-emitting display device using a light-emitting element, a pixel portion has a plurality of thin-film transistors, and there is a location in the pixel portion where the gate electrode of a certain thin-film transistor is connected to the source wiring or the drain wiring of another transistor. Also, in the drive circuit of the light-emitting display device using a light-emitting element, there is a location where the gate electrode of the thin-film transistor is connected to the source wiring or the drain wiring of that thin-film transistor.

[0043]

[0044]

[0045] In addition, since thin film transistors are easily damaged by static electricity or the like, a protection circuit for protecting the thin film transistors in the pixel portion may be provided on the same substrate with respect to the gate line or the source line. Preferably, the protection circuit is configured using a non-linear element using an oxide semiconductor layer.

[0046] Note that the ordinal numbers attached as first and second are used for convenience and do not indicate the process order or the stacking order. Also, the specific names used as matters for specifying the invention in this specification do not indicate anything.

Advantages of the Invention

[0047] A thin film transistor with a reduced parasitic capacitance can be fabricated by covering the peripheral portion of the oxide semiconductor layer with an oxide insulating layer. Also, by increasing the distance between the source electrode layer and the drain electrode layer, a thin film transistor with a reduced off-current can be realized.

Brief Description of the Drawings

[0048]

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Embodiments for Carrying Out the Invention

[0049] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description content of the embodiments shown below.

[0050] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 and 2.

[0051] Further, FIG. 1(A) is a plan view of a channel protection type thin film transistor 448 disposed in a pixel, FIG. 1(B) is a cross-sectional view taken along line D1-D2 of FIG. 1(A) and a cross-sectional view taken along line D5 -D6 of FIG. 1(A). Also, FIG. 1(C) is a cross-sectional view taken along line D3-D4 of FIG. 1(A). Note that FIG. 2(E) is the same as FIG. 1(B).

[0052] The thin film transistor 448 disposed in the pixel is a channel protection type (also referred to as a channel stop type) thin film transistor, and includes a gate electrode layer 421a, a gate insulating layer 402, an oxide semiconductor layer 442 including a channel formation region 423, an oxide insulating layer 426a functioning as a channel protection layer, a source electrode layer 425a, and a drain electrode layer 425b on a substrate 400 having an insulating surface. Further, covering the thin film transistor 448, an oxide insulating layer 426a, a so An insulating layer 428, a protective insulating layer 403, and a planarizing insulating layer 404 are laminated in contact with the source electrode layer 425a and the drain electrode layer 425b. On the planarizing insulating layer 404, a pixel electrode layer 427 in contact with the drain electrode layer 425b is provided and is electrically connected to the thin film transistor 448.

[0053] The thin film transistor 448 for pixels has an oxide semiconductor layer 442 including a high-resistance source region 424a overlapping with the source electrode layer, a high-resistance drain region 424b overlapping with the drain electrode layer, a high-resistance source region 424e not overlapping with the source electrode layer, a high-resistance drain region 424f not overlapping with the drain electrode layer, and a channel formation region 423. Note that a high-resistance source region 424a is formed in contact with the lower surface of the source electrode layer 425a. Also, a high-resistance drain region 424b is formed in contact with the lower surface of the drain electrode layer 425b. The thin film transistor 448 has a configuration in which even when a high electric field is applied, two high-resistance drain regions or two high-resistance source regions serve as a buffer and a local high electric field is not applied, improving the breakdown voltage of the transistor.

[0054] Also, in FIG. 1(B), a region of the oxide semiconductor layer where the oxide insulating layer 426a functioning as a channel protection layer and the gate electrode layer overlap via the gate insulating layer is called the channel formation region. Therefore, the channel length L of the thin film transistor 448 is equal to the width in the channel length direction of the oxide insulating layer 426a. Note that the channel length L of the thin film transistor 448 is the length at the interface with the oxide insulating layer 426a, that is, the length of the base of the trapezoid shown for the oxide insulating layer 426a in the cross-sectional view shown in FIG. 1(B).

[0055] In addition, in order to reduce parasitic capacitance, at the wiring intersection where the gate wiring and the source wiring cross, a gate insulating layer 402 and an oxide insulating layer 426b are provided between the gate electrode layer 421b and the source electrode layer 425a. Note that the oxide insulating layer 426a in the region overlapping with the channel formation region 423 and the oxide insulating layer 426b in the region not overlapping with the channel formation region 423 are denoted by different reference numerals, but they are layers formed of the same material and in the same process.

[0056] Hereinafter, with reference to FIGS. 2(A) to 2(E), the process of fabricating the thin film transistor 448 and the wiring intersection on the same substrate will be described. Also, thin film transistors in not only the pixel portion but also the driving circuit may be formed, and they can be fabricated on the same substrate in the same process.

[0057] First, after forming a conductive film on a substrate 400 having an insulating surface, the gate electrode layers 421a and 421b are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring layer is formed of the same material as the gate electrode layers 421a and 421b and by the same first photolithography process. Also, when forming not only the pixel portion but also the driving circuit, if a capacitor is required in the driving circuit, a capacitive wiring layer is also formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0058] As the conductive film for forming the gate electrode layers 421a and 421b, an element selected from Al, Cr, Ta, Ti, Mo, W, an alloy containing the above-described elements as components, or a combination of the above-described elements ​​​​Examples include a mated alloy film or the like. Further, as the conductive film forming the gate electrode layers 421a and 421b, a conductive film having translucency may be used, such as indium oxide (In2O3) or indium tin oxide alloy (In2O3—SnO2, abbreviated as ITO). In this specification, a film having translucency with respect to visible light refers to a film having a film thickness with a visible light transmittance of 75 to 100%, and when the film has conductivity, it is also called a transparent conductive film. Further, as the metal oxide applied to the gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrode layer, or other wiring layer, a semi-transparent conductive film with respect to visible light may be used. By semi-transparent with respect to visible light is meant that the transmittance of visible light is 50 to 75%.

[0059]

[0060] Also, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is good to use one with a strain point of 730°C or higher. Further, as the glass substrate, for example, glass materials such as aluminosilicate glass, aluminophosphate glass, and barium borate glass are used. By including more barium oxide (BaO) compared to boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0061] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, quartz substrate, or sapphire substrate may be used. In addition, crystallized glass or the like can be used.

[0062] Also, an insulating film serving as an underlayer is provided between the substrate 400 and the gate electrode layers 421a and 421b.​​​​​​​​​​​​​ is also acceptable. The base film has a function of preventing the diffusion of impurity elements from the substrate 400, and is made of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film, and can be formed by a laminated structure.

[0063] Next, a gate insulating layer 402 is formed on the gate electrode layers 421a and 421b.

[0064] The gate insulating layer 402 can be formed by using a plasma CVD method, a sputtering method, or the like, by forming a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the gate insulating layer 402 is 100 nm or more and 5 00 nm or less. In the case of lamination, for example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less, and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer are laminated. In this embodiment, the gate insulating layer 402 is a silicon nitride layer with a film thickness of 200 nm or less formed by the plasma CVD method.

[0065] Next, an oxide semiconductor film 430 having a film thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 20 nm or less, is formed on the gate insulating layer 402 (see FIG. 2(A)). After the formation of the oxide semiconductor film 430, a heat treatment for dehydration or dehydrogenation may be performed. In order to make the oxide semiconductor film

[0066] in an amorphous state, it is preferably made thinner to a film thickness of 50 nm or less. By making the film thickness of the oxide semiconductor film thinner, when heat treatment is performed after the formation of the oxide semiconductor layer, crystallization can be suppressed. ​​​​​​​​

[0067] The oxide semiconductor film 430 is an In-Ga-Zn-O-based non-single crystal film, an In-Sn-Zn-O-based , an In-Al-Zn-O-based, a Sn-Ga-Zn-O-based, an Al-Ga-Zn-O-based, a Sn- Al-Zn-O-based, an In-Zn-O-based, a Sn-Zn-O-based, an Al-Zn-O-based, an In-O -based, a Sn-O-based, a Zn-O-based oxide semiconductor film. In this embodiment, an In-Ga -Zn-O-based oxide semiconductor target is used to form a film by sputtering. Also, the oxide semiconductor film 430 can be formed by sputtering in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or an inert gas (typically argon) and oxygen atmosphere. Also, when using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used for film formation, and SiO (X>0) that inhibits crystallization is included in the oxide semiconductor film 430, and crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process is preferably suppressed. x (X>0) The oxide semiconductor is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In and

[0068] Ga. It is effective to go through a dehydration or dehydrogenation process to make the oxide semiconductor layer of type I (intrinsic).

[0069] In this embodiment, an In-Ga-Zn-O-based oxide semiconductor film is used.

[0070] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [mole ratio]) is used, and the distance between the substrate and the target is 1 00 mm, pressure 0.2 Pa, DC power supply 0.5 kW, argon and oxygen (argon : oxygen = 30 sccm: 20 sccm oxygen flow ratio 40%) is deposited in an atmosphere. Note that , when using a pulsed DC power supply, dust can be reduced and the film thickness distribution becomes uniform, so it is preferable. The film thickness of the In-Ga-Zn-O-based non-single crystal film is set to 5 nm to 200 nm. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based oxide semiconductor target is used to deposit an In-Ga-Zn-O-based non-single crystal film with a thickness of 20 nm by sputtering. .

[0071] There are an RF sputtering method that uses a high-frequency power supply as the sputtering power supply and a DC sputtering method in sputtering methods, and there is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal film .

[0072] There is also a multi-source sputtering device that can install multiple targets made of different materials. The multi-source sputtering device can deposit different material films in a stacked manner in the same chamber, or can also discharge multiple types of materials simultaneously in the same chamber to deposit a film.

[0073] There is also a sputtering device that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber or an ECR sputtering method that uses plasma generated using microwaves without using glow discharge.

[0074] In addition, as a film deposition method using sputtering, a reactive sputtering method that forms a compound thin film by chemically reacting a target substance and a sputtering gas component during film deposition, or during film deposition There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0075] Next, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0076] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than the distortion point of the substrate, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. For example, the heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is prevented from being exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. In this embodiment, a semiconductor layer is obtained by a heating method for dehydrating or dehydrogenating an oxide semiconductor layer. From temperature T, use the same furnace to a temperature high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below T. First, dehydration or dehydrogenation is performed under a rare gas atmosphere such as helium, neon, or argon. cormorant.

[0077] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. , preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0078] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur and a microcrystalline film or a polycrystalline film may be formed.

[0079] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 430 before it is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating device and a photolithography process is performed.

[0080] Also, before forming the oxide semiconductor film 430, a heat treatment (at 400 °C or higher and below the strain point of the substrate) may be performed under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under an oxygen atmosphere to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0081] Next, after forming an oxide insulating film by sputtering on the gate insulating layer 402 and the oxide semiconductor layer, a resist mask is formed by a third photolithography process, and selective etching is performed to form the oxide insulating layers 426a and 426b, and then the resist mask is removed. At this stage, in the oxide semiconductor layer, a region in contact with the oxide insulating layer is formed, and among this region, the region that overlaps via the gate electrode layer and the gate insulating layer and also overlaps with the oxide insulating layer 426a becomes the channel formation region. Also, a region that overlaps with the oxide insulating layer 426b that covers the periphery and side surfaces of the oxide semiconductor layer is formed.

[0082] The oxide insulating film has a film thickness of at least 1 nm or more, and is formed by a method such as sputtering for oxide insulation. It can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the film. In this embodiment, as the oxide insulating film, a silicon oxide film with a thickness of 300 nm is formed by sputtering. The substrate temperature during film formation may be from room temperature to 300 °C, and in this embodiment, it is set to room temperature. The film formation of the silicon oxide film by sputtering can be carried out in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, silicon oxide can be formed by sputtering in an atmosphere of oxygen and nitrogen. The oxide insulating film formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. -

[0083] Next, a second heat treatment (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere (see Fig. 2(B)). For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, the end of the oxide semiconductor layer 442 that overlaps with the oxide insulating layer 426b and a part of the oxide semiconductor layer 442 that overlaps with the oxide insulating layer 426a are heated in a state of being in contact with the oxide insulating layer. The portion is heated in an exposed state. When heat treatment is performed in a nitrogen or inert gas atmosphere with the oxide semiconductor layer 442 exposed, the highly resistive (type-I) region exposed in the oxide semiconductor layer 442 can be made to have a lower resistance. Also, the oxide insulating layer 426a is provided in contact with the region that becomes the channel formation region of the oxide semiconductor layer 442 and functions as a channel protection layer. Next, after forming a conductive film over the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer 442, a resist mask is formed by a fourth photolithography process, and selective etching is performed to form the source electrode layer 425a and the drain electrode layer 425b (see FIG. 2(C)). As the method for forming the conductive film, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method is used. As the conductive film, an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above-described elements, or an alloy combining the above-described elements, etc. is used. The conductive film is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used. In this embodiment mode, a three-layer conductive film of a titanium film, an aluminum film, and a titanium film is formed. Also, a titanium nitride film may be used instead of the Ti film. Moreover, in the fourth photolithography process, there is a portion where only the conductive film in contact with the oxide semiconductor layer is selectively removed. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, aqueous ammonia peroxide (31 wt% hydrogen peroxide) is used as an alkaline etchant.

[0084] Next, after forming a conductive film over the gate insulating layer 402, the oxide insulating layers 426a, 426b, and the oxide semiconductor layer 442, a resist mask is formed by a fourth photolithography process, and selective etching is performed to form the source electrode layer 425a and the drain electrode layer 425b (see FIG. 2(C)). As the method for forming the conductive film, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method is used. As the conductive film, an element selected from Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above-described elements, or an alloy combining the above-described elements, etc. is used. The conductive film is not limited to a single layer containing the above-described elements, and a laminate of two or more layers can be used. In this embodiment mode, a three-layer conductive film of a titanium film, an aluminum film, and a titanium film is formed. Also, a titanium nitride film may be used instead of the Ti film.

[0085] Moreover, in the fourth photolithography process, there is a portion where only the conductive film in contact with the oxide semiconductor layer is selectively removed. Therefore, in order to selectively remove only the conductive film in contact with the oxide semiconductor layer, aqueous ammonia peroxide (31 wt% hydrogen peroxide) is used as an alkaline etchant. ​​​​​​​Using hydrogen water: 28% by weight aqueous ammonia: water = 5:2:2), etc., the conductive film can be selectively removed, leaving an oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor. This can be achieved.

[0086] Note that a resist mask for forming the source electrode layer 425a and the drain electrode layer 425b may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0087] Next, an insulating layer 428 and a protective insulating layer 403 are formed on the oxide insulating layers 426a, 426b, the source electrode layer 425a, and the drain electrode layer 42 5b. In this embodiment, a sputtering method is used to laminate and form an insulating layer 428 of a silicon oxide film and a protective insulating layer 403 of a silicon nitride film. .

[0088] Note that, for clarity in indicating the oxide insulating layer 426a and the insulating layer 428, a boundary is shown in the figure, but in reality, both are silicon oxide films formed by the same sputtering method, so it becomes unclear.

[0089] The RF sputtering method is preferable as a film formation method for the protective insulating layer 403 because of its good mass productivity. The protective insulating layer 403 does not contain impurities such as moisture, hydrogen ions, and OH - and blocks these from entering from the outside. An inorganic insulating film is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film. Of course, the protective insulating layer 403 is a transparent insulating film. This is an insulating film having transparency.

[0090] Next, a planarizing insulating layer 404 is formed on the protective insulating layer 403. As the planarizing insulating layer 404, Then, organic materials having heat resistance such as polyimide, acrylic resin, benzocyclobutene-based resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Note that a planarized insulating layer 404 may be formed by laminating a plurality of insulating films formed of these materials. In addition, the siloxane-based resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. As substituents, the siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group. Further, the organic group may have a fluoro group. The method for forming the planarized insulating layer 404 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. Next, a fifth photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 425b is formed by etching the planarized insulating layer 404, the insulating layer 428, and the protective insulating layer 403, and the resist mask is removed (see Fig. 2(D)). As shown in Fig. 2(D), an oxide insulating layer 426b is provided below the contact hole. Compared with the case where no oxide insulating layer is provided below the contact hole, the drain electrode layer 425b can be protected.

[0091] Note that the siloxane-based resin corresponds to a resin containing a Si-O-Si bond formed using a siloxane-based material as a starting material. As substituents, the siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group. Further, the organic group may have a fluoro group.

[0092] The method for forming the planarized insulating layer 404 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used.

[0093] Next, a fifth photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 425b is formed by etching the planarized insulating layer 404, the insulating layer 428, and the protective insulating layer 403, and the resist mask is removed (see Fig. 2(D)). As shown in Fig. 2(D), an oxide insulating layer 426b is provided below the contact hole. Compared with the case where no oxide insulating layer is provided below the contact hole, the drain electrode layer 425b can be protected. (See.). As shown in Fig. 2(D), an oxide insulating layer 426b is provided below the contact hole. Compared with the case where no oxide insulating layer is provided below the contact hole, the drain electrode layer 425b The thickness of the planarization insulating layer to be removed can be reduced, and the etching time can be shortened. The contact hole has a larger insulating oxide layer than when no insulating oxide layer is provided below the contact hole. The depth of the contact hole 441 can be made shallow, and in the area overlapping with the contact hole 441, The coverage of a light-transmitting conductive film formed in a later step can be improved. In addition, a contact hole reaching the gate electrode layer 421b is also formed by this etching. In addition, a resist pattern is formed to form a contact hole that reaches the drain electrode layer 425b. The resist mask may be formed by an ink-jet method. When formed, no photomask is used, thereby reducing manufacturing costs.

[0094] Next, a light-transmitting conductive film is formed. Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT The transparent conductive film (abbreviated as O) is formed by sputtering or vacuum deposition. As another material for the conductive film, a nitrogen-containing Al-Zn-O-based non-single crystal film, i.e., Al-Zn- ON-based non-single crystal film, Zn-ON-based non-single crystal film, Sn-Zn-ON-based non-single crystal film The composition ratio (atomic %) of zinc in the Al-Zn-ON non-single crystal film may be: The composition ratio (atomic %) of aluminum in the non-single crystal film is 47 atomic % or less, which is larger than the composition ratio (atomic %) of aluminum in the non-single crystal film. The aluminum composition ratio (atomic %) in the crystalline film is the same as the nitrogen composition ratio (atomic %) in the non-single-crystalline film. The etching process for such materials is carried out with a hydrochloric acid-based solution. ITO etching tends to leave residue, so we used an oxidizing agent to improve etching processability. An indium zinc oxide alloy (In2O3—ZnO) may be used.

[0095] Note that the unit of the composition ratio of the transparent conductive film is atomic %, and it shall be evaluated by analysis using an electron probe X-ray microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer ).

[0096] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 427, and the resist mask is removed (see Fig. 2( E)). ).

[0097] Through the above processes, using six masks, a thin film transistor 448 and a wiring intersection portion with reduced parasitic capacitance can be fabricated on the same substrate. The thin film transistor 44 8 for pixels is a channel protection type thin film transistor including a high-resistance source region 424a overlapping with the source electrode layer, a high-resistance drain region 424b overlapping with the drain electrode layer, a high-resistance source region 424e not overlapping with the source electrode layer, a high-resistance drain region 424f not overlapping with the drain electrode layer, and an oxide semiconductor layer 442 including a channel formation region 423. Therefore, the thin film transistor 44 8 has a structure in which two high-resistance drain regions or two high-resistance source regions serve as buffers even when a high electric field is applied, and a local high electric field is not applied, improving the breakdown voltage of the thin film transistor. Further, the off-current of the thin film transistor is reduced by increasing the distance between the source electrode layer and the drain electrode layer. Also, a holding capacitor formed by using the gate insulating layer 402 as a dielectric and the capacitance wiring layer and the capacitance electrode also has a structure in which the off-current of the thin film transistor is reduced. By increasing the distance between the source electrode layer and the drain electrode layer, the off-current of the thin film transistor is reduced.

[0098] In addition, a holding capacitor formed by using the gate insulating layer 402 as a dielectric and the capacitance wiring layer and the capacitance electrode also It can be formed on the same substrate. The thin-film transistors 448 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and it can be used as one substrate for manufacturing an active matrix type display device. In this specification, for convenience, such a substrate is called an active matrix substrate. Correspondingly arranged in a matrix to form a pixel portion, and it can be used as one substrate for manufacturing an active matrix type display device. In this specification, for convenience, such a substrate is called an active matrix substrate.

[0099] Also, thin-film transistors of the driving circuit can be provided on the same substrate. By forming the driving circuit and the pixel portion on the same substrate, the connection wiring between the driving circuit and the external signal can be shortened, and miniaturization and cost reduction of the semiconductor device are possible. By forming the driving circuit and the pixel portion on the same substrate, the connection wiring between the driving circuit and the external signal can be shortened, and miniaturization and cost reduction of the semiconductor device are possible.

[0100] Also, the oxide semiconductor layer 442 of the thin-film transistor 448 for pixels shown in FIG. 1(B) has a first region 424c and a second region 424d overlapping the oxide insulating layer 426b at the peripheral portion. The first region 424c and the second region 424d, which are the peripheral portions of the oxide semiconductor layer 442, are in the same oxygen-excessive state as the channel formation region 423. When wiring or an oxide semiconductor layer with a different potential is arranged nearby, reduction of leakage current and reduction of parasitic capacitance can be realized. The first region 424c and the second region 424d, which are the peripheral portions of the oxide semiconductor layer 442, are in the same oxygen-excessive state as the channel formation region 423. When wiring or an oxide semiconductor layer with a different potential is arranged nearby, reduction of leakage current and reduction of parasitic capacitance can be realized.

[0101] Especially in the driving circuit, for high integration, it is preferable to arrange the intervals between a plurality of wirings and a plurality of oxide semiconductor layers in a narrowed manner. Providing the first region 424c and the second region 424d overlapping the oxide insulating layer 426b is effective for reducing leakage current and parasitic capacitance. Especially in the driving circuit, for high integration, it is preferable to arrange the intervals between a plurality of wirings and a plurality of oxide semiconductor layers in a narrowed manner. Providing the first region 424c and the second region 424d overlapping the oxide insulating layer 426b is effective for reducing leakage current and parasitic capacitance. Also, when arranging a plurality of thin-film transistors in series or in parallel, the oxide semiconductor layers of the plurality of thin-film transistors are made into one island, and element isolation is performed by overlapping the oxide insulating layer 426b, and the region overlapping the oxide insulating layer 426b is used as the element isolation region. Also, when arranging a plurality of thin-film transistors in series or in parallel, the oxide semiconductor layers of the plurality of thin-film transistors are made into one island, and element isolation is performed by overlapping the oxide insulating layer 426b, and the region overlapping the oxide insulating layer 426b is used as the element isolation region. ​​​​​This enables the placement of a plurality of thin-film transistors in a narrow area. By doing so, high integration of the drive circuit can be achieved. Since this is possible, high integration of the drive circuit can be achieved.

[0102] (Embodiment 2) In this embodiment, an example of manufacturing an active matrix type liquid crystal display device is shown by forming a pixel portion and a drive circuit on the same substrate using the thin-film transistor shown in Embodiment 1. An example of the cross-sectional structure of the active matrix substrate is shown in Fig. 3(A).

[0103] In Embodiment 1, the thin-film transistor and the wiring intersection portion in the pixel portion were illustrated. In this embodiment, in addition to the thin-film transistor and the wiring intersection portion, the thin-film transistor in the drive circuit, the holding capacitor, and the terminal portions of the gate wiring and the source wiring will also be illustrated and described. The terminal portions of the capacitor, the gate wiring, and the source wiring can be formed by the same process as the manufacturing process shown in Embodiment 1.

[0104]

[0105]

[0106] <At 3(A)>, the thin-film transistor 220 electrically connected to the pixel electrode layer 227 is a channel protection type thin-film transistor provided in the pixel portion. In this embodiment, the same structure as the thin-film transistor 448 in Embodiment 1 is used.

[0107] ​​​​​​​​​​Note that the holding capacitance is provided below the pixel electrode layer 227, and the capacitive electrode 231 is electrically connected to the pixel electrode layer 2 27.

[0108] In this embodiment, an example of forming the holding capacitance using the capacitive electrode 231 and the capacitive wiring layer 230 is shown, but the structure for forming the holding capacitance is not particularly limited. For example, the holding capacitance may be formed by overlapping the pixel electrode layer with the gate wiring of adjacent pixels, the planarization insulating layer, the protective insulating layer, and the gate insulating layer without providing the capacitive wiring layer.

[0109] Also, in FIG. 3(A), since the holding capacitance forms a large capacitance, only the gate insulating layer 202 is provided between the capacitive wiring layer and the capacitive electrode. For the wiring intersection portion, in order to reduce the parasitic capacitance, a gate insulating layer 202 and an oxide insulating layer 266b are provided between the gate electrode layer 421b and the wiring formed above it. In the holding capacitance, when only the gate insulating layer 202 is provided between the capacitive wiring layer and the capacitive electrode, during the etching for removing the oxide insulating layer 266b, etching conditions are selected such that only the gate insulating layer 202 remains selectively, or the material of the gate insulating layer is selected. In this embodiment, since the oxide insulating layer 266b is a silicon oxide film obtained by sputtering and the gate insulating layer 202 is a silicon nitride film obtained by plasma CVD, it can be selectively removed. Note that when the oxide insulating layer 266b and the gate insulating layer 202 are made of materials removed under the same etching conditions, even if a part of the gate insulating layer is thinned by etching, it is preferable that at least the gate insulating layer remains and has a film thickness capable of forming a capacitance. When the oxide insulating layer 266b and the gate insulating layer 202 are made of materials removed under the same etching conditions, even if a part of the gate insulating layer is thinned by etching, it is preferable that at least the gate insulating layer remains and has a film thickness capable of forming a capacitance. To increase the holding capacitance, it is preferable to reduce the film thickness of the gate insulating layer. Therefore, when selectively etching the oxide insulating layer 266b, the gate insulating layer on the capacitor wiring may be formed into a structure with a reduced film thickness.

[0110] Also, the thin film transistor 260 is a channel protection type thin film transistor provided in the driving circuit, and has a shorter channel length L compared to the thin film transistor 220 to increase the operating speed. The channel length L of the channel protection type thin film transistor provided in the driving circuit is preferably 0.1 μm or more and 2 μm or less. Also, the thin film transistor 260 has a different structure from the thin film transistor 220, and the source electrode layer 265a and the drain electrode layer 265b are formed so as to overlap the oxide insulating layer 266a.

[0111] The thin film transistor 260 includes a gate electrode layer 261, a gate insulating layer 202, at least a channel formation region 263, an oxide semiconductor layer having a high resistance source region 264a and a high resistance drain region 264b, a source electrode layer 265a, and a drain electrode layer 265b on a substrate 200 having an insulating surface. Also, an oxide insulating layer 26 6a in contact with the channel formation region 263 is provided.

[0112] Also, the gate electrode layer of the thin film transistor 260 in the driving circuit may be electrically connected to a conductive layer 267 provided above the oxide semiconductor layer. In that case, the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227 is used, and the planarization insulating layer 204, the insulating layer 216, the protective insulating layer 203, the oxide insulating layer 266b, and the gate insulating layer 202 are selectively etched to form a contact. ​​​​A contact hole is formed. Through this contact hole, the conductive layer 267 and the gate electrode layer 261 of the thin film transistor of the driving circuit are electrically connected.

[0113] Also, the insulating layer 216 uses an inorganic insulating film, such as a silicon oxide film, an aluminum oxide film, a silicon oxynitride film, or an aluminum oxynitride film. In this embodiment, a silicon oxide film obtained by a sputtering method is used.

[0114] The protective insulating layer 203 uses an inorganic insulating film, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film. In this embodiment, a silicon nitride film obtained by a sputtering method is used.

[0115] Also, the thin film transistor 260 has a structure in which the width of the gate electrode layer 261 (the width in the channel length direction) is wider than the width of the oxide semiconductor layer. Also, the oxide insulating layer 266b overlaps with the peripheral portion of the oxide semiconductor layer and further overlaps with the gate electrode layer 261. The oxide insulating layer 266b widens the distance between the drain electrode layer 265b and the gate electrode layer 261, and functions to reduce the parasitic capacitance formed between the drain electrode layer 265b and the gate electrode layer 261. Also, the first region 264c and the second region 264d of the oxide semiconductor layer that overlap with the oxide insulating layer 266b are in the same oxygen-excessive state as the channel formation region 263, and also function to reduce leakage current and parasitic capacitance.

[0116] Also, a plurality of gate wirings, source wirings, and capacitor wiring layers are provided according to the pixel density. Also, at the terminal portion, a first terminal electrode having the same potential as the gate wiring, a source wiring ​​​​​​​​​​​​A plurality of second terminal electrodes at the same potential, third terminal electrodes at the same potential as the capacitive wiring layer, etc. are arranged side by side. The number of each terminal electrode may be set to any number, and the implementer may make an appropriate decision.

[0117] In the terminal portion, the first terminal electrode at the same potential as the gate wiring can be formed of a material having the same light transmissibility as the pixel electrode layer 227. The first terminal electrode is electrically connected to the gate wiring through a contact hole reaching the gate wiring. The contact hole reaching the gate wiring uses the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227, and selectively etches the planarization insulating layer 204, the insulating layer 216, the protective insulating layer 203, the oxide insulating layer 266b, and the gate insulating layer 202.

[0118] Also, the second terminal electrode 255 at the same potential as the source wiring in the terminal portion can be formed of a material having the same light transmissibility as the pixel electrode layer 227. The second terminal electrode 255 is electrically connected to the source wiring through a contact hole reaching the source wiring. The source wiring is a metal wiring, and is formed of the same material and in the same process as the source electrode layer 265a of the thin film transistor 260, and is at the same potential.

[0119] Also, the third terminal electrode at the same potential as the capacitive wiring layer 230 can be formed of a material having the same light transmissibility as the pixel electrode layer 227. Also, the contact hole reaching the capacitive wiring layer 230 can be formed in the same photomask and the same process as the contact hole for electrically connecting the capacitive electrode 231 and the pixel electrode layer 227.

[0120] Also, when manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between an active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. Note that a common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrode electrically connected to the common electrode is provided at the terminal portion. This fourth terminal electrode is a terminal for setting the common electrode to a fixed potential, for example, GND, 0 V, etc. The fourth terminal electrode can be formed of a material having the same light transmissivity as the pixel electrode layer 227.

[0121] Also, if the same material is used for the gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrode layers, and other wiring layers, a common sputtering target and a common manufacturing apparatus can be used, and the material cost and the cost required for the etchant (or etching gas) used during etching can be reduced, and as a result, the manufacturing cost can be reduced.

[0122] Also, in the structure of FIG. 3(A), when a photosensitive resin material is used as the planarization insulating layer 204, the step of forming a resist mask can be omitted.

[0123] Also, FIG. 3(B) shows a cross-sectional structure partially different from that of FIG. 3(A). Since FIG. 3(B) is the same as FIG. 3( A) except that the planarization insulating layer 204 does not exist at the terminal portion and the structure of the thin film transistor of the driving circuit is different, the same reference numerals are used for the same portions, and the detailed description of the same portions is omitted. In FIG. 3(B), a thin film transistor 270 using a metal wiring is arranged. Also Also, the terminal electrode is formed of the same material and in the same process as the metal wiring.

[0124] Further, in the structure of FIG. 3(B), a photosensitive resin material is used as the planarization insulating layer 204 and the step of forming a resist mask is omitted. Therefore, the planarization insulating layer 204 can be configured not to exist at the terminal portion without using a resist mask. At the terminal portion, if the planarization insulating layer does not exist, it is easy to make good connection with the FPC.

[0125] The thin film transistor 270 includes a gate electrode layer 271, a gate insulating layer 202, at least a channel formation region 273, a high resistance source region 274a, and a drain electrode layer 275b on a substrate 200 having an insulating surface. An oxide semiconductor layer having a high resistance drain region 274b, a source electrode layer 275a, and a drain electrode layer 275b are included. Also, an oxide insulating layer 27 6a in contact with the channel formation region 273 is provided. Also, an insulating layer 216 and a protective insulating layer 203 are provided on the source electrode layer 275a and the drain electrode layer 275b.

[0126] Also, a first region 274c and a second region 27 4d of the oxide semiconductor layer overlapping with the oxide insulating layer 276b are in the same oxygen-excessive state as the channel formation region 273, and also function to reduce leakage current and parasitic capacitance. Also, a third region 274e of the oxide semiconductor layer in contact with the insulating layer 216 is provided between the channel formation region 273 and the high resistance source region 274a. Also, a fourth region 274f of the oxide semiconductor layer in contact with the insulating layer 216 is provided between the channel formation region 273 and the high resistance drain region 274b. The third region 274e and the fourth region 274f of the oxide semiconductor layer in contact with the insulating layer 216 can reduce the off-current.

[0127] In addition, for a channel-protected thin-film transistor, to shorten the channel length L of the channel formation region, the width of the oxide insulating layer is narrowed, and when a source electrode layer and a drain electrode layer are provided on the narrow oxide insulator layer, there is a risk of short-circuiting on the oxide insulator layer. Therefore, the source electrode layer 275a and the drain electrode layer 275b are provided leaving the ends from the narrow oxide insulating layer 276a.

[0128] In addition, the gate electrode layer of the thin-film transistor 270 in the driving circuit may be structured to be electrically connected to a conductive layer 277 provided above the oxide semiconductor layer.

[0129] In addition, the second terminal electrode 257 at the same potential as the source wiring 256 in the terminal portion can be formed of a material having the same light-transmitting property as the pixel electrode layer 227. The source wiring is a metal wiring, which is formed of the same material and in the same process as the source electrode layer 275a of the thin-film transistor 270 and is at the same potential.

[0130] In addition, since the thin-film transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the driving circuit. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is disposed between the pixel portion and the scanning line input terminal and the signal line input terminal. In this embodiment, a plurality of protection circuits are provided so that a surge voltage is applied to the scanning line, the signal line, and the capacitance bus line due to static electricity or the like, and the pixel transistor or the like is not damaged. Therefore, the protection circuit is configured to release the charge to the common wiring or the common wiring when a surge voltage is applied. Also, the protection ​​​​​​​​​​​​​​The protection circuit is composed of nonlinear elements arranged in parallel with respect to the scanning lines. Nonlinear elements are composed of two-terminal elements such as diodes or three-terminal elements such as transistors . For example, it is also possible to form them in the same process as the thin-film transistor 220 in the pixel portion, and for example, by connecting the gate terminal and the drain terminal, characteristics similar to those of a diode can be obtained .

[0131] Note that the step of forming the planarization insulating layer 204 may be omitted, and a structure without the planarization insulating layer 204 may be adopted . In this case, the pixel electrode layer 227 and the second terminal electrode 255 are provided in contact with the protection insulating layer 203 .

[0132] This embodiment can be freely combined with Embodiment 1

[0133] (Embodiment 3) Further, in this embodiment, an example of the configuration of the terminal portion provided on the same substrate as the thin-film transistor is shown . In Embodiment 2, an example of the terminal portion of the source wiring was shown, but in this embodiment , the terminal portion of the source wiring having a configuration different from that of Embodiment 2 and the terminal portion of the gate wiring are illustrated . In FIG. 4, the same reference numerals are used for the same portions as in FIG. 3(A) or FIG. 3(B) for explanation .

[0134] FIGS. 4(A1) and 4(A2) respectively illustrate a cross-sectional view and a top view of the gate wiring terminal portion . FIG. 4(A1) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 4(A2). In FIG. 4 (A1), the conductive layer 225 formed on the stack of the insulating layer 216 and the protection insulating layer 203 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 4(A1), the end In the terminal portion, the first terminal 221 is formed of the same material as the gate electrode layer 421b in FIG. and a connection electrode layer 223 formed of the same material as the source wiring, with the gate insulating layer 202 interposed therebetween. The two overlap and are electrically connected by a conductive layer 225 .

[0135] 4(B1) and 4(B2) are different from the source line terminal portion shown in FIG. 3(B). 4(B1) shows a cross-sectional view and a top view of the source wiring terminal portion. This corresponds to a cross-sectional view taken along the line C3-C4 in FIG. 4(B2). The conductive layer 225 formed on the stack of the layer 216 and the protective insulating layer 203 functions as an input terminal. In FIG. 4(B1), the terminal portion is a terminal electrode for connection with the gate wiring. An electrode layer 226 made of the same material is formed on the second terminal 22 which is electrically connected to the source line. The electrode layer 226 is electrically connected to the second terminal 222. The electrode layer 226 is not electrically connected to the second terminal 222, and is at a different potential from the second terminal 222, for example, a floating potential. Setting the input to GND, 0V, etc. will allow you to set capacitance for noise prevention or static electricity prevention. The second terminal 222 is electrically connected to the insulating layer 216 and the protective insulating layer 218. The layer 203 is electrically connected to the conductive layer 225 through a contact hole formed in the stack of layers. There are.

[0136] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0137] This embodiment mode can be freely combined with Embodiment Mode 1 or 2.

[0138] (Fourth embodiment) Here, in a liquid crystal display device in which a liquid crystal layer is sealed between a first substrate and a second substrate, A common connection portion is formed on the first substrate for electrically connecting with the counter electrode provided on the second substrate. An example in which a thin film transistor is formed as a switching element on the first substrate is shown. The manufacturing process of the common connection part is made common to the manufacturing process of the switching element of the pixel part. This allows the formation without complicating the process.

[0139] The common connection portion is disposed at a position overlapping the sealant for bonding the first substrate and the second substrate. The sealing material is electrically connected to the counter electrode via conductive particles contained in the sealing material. The common connection part is provided in a place where it does not overlap with the sealing material (excluding the pixel part), and the common connection part A paste containing conductive particles is provided separately from the sealing material so as to overlap the opposing electrode. A connection is made.

[0140] FIG. 5A is a cross section of a semiconductor device in which a thin film transistor and a common connection portion are fabricated on the same substrate. FIG.

[0141] In FIG. 5A, the thin film transistor 220 electrically connected to the pixel electrode layer 227 is This is a channel protection type thin film transistor provided in a pixel portion. The same structure as the thin film transistor 448 of the first embodiment is used.

[0142] FIG. 5B is a diagram showing an example of a top view of the common connection portion, and the chain line C5-C6 in the diagram It corresponds to the cross-section of the common connection part in Fig. 5(A). In Fig. 5(B), the same reference numerals are used for the parts that are the same as those in Fig. 5(A) for description.

[0143] The common potential line 205 is provided on the gate insulating layer 202 and is fabricated using the same material and the same process as the source electrode layer and the drain electrode layer of the thin film transistor 220.

[0144] Also, the common potential line 205 is covered with a laminate of the insulating layer 216 and the protective insulating layer 203, and the laminate of the insulating layer 2 16 and the protective insulating layer 203 has a plurality of openings at positions overlapping the common potential line 205 These openings are fabricated in the same process as the contact holes that connect the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227.

[0145] Here, since the area sizes are significantly different, the contact holes in the pixel portion and the openings in the common connection portion will be referred to separately. Also, in Fig. 5(A), the pixel portion and the common connection portion are not shown at the same scale. For example, the length of the dashed line C5 - C6 in the common connection portion is about 500 μm, while the width of the thin film transistor is less than 50 μm, and actually the area size is more than 10 times larger. However, for clarity, in Fig. 5(A), the scales of the pixel portion and the common connection portion are shown with different scales respectively.

[0146] Also, the common electrode layer 206 is provided on the laminate of the insulating layer 216 and the protective insulating layer 203 and is fabricated using the same material and the same process as the pixel electrode layer 227 in the pixel portion.

[0147] In this way, the manufacturing process of the common connection portion is made common with the manufacturing process of the switching element in the pixel portion. Perform.

[0148] ​A first substrate provided with a pixel portion and a common connection portion, and a second substrate having a counter electrode are fixed using a sealing material.

[0149] When conductive particles are included in the sealing material, alignment of a pair of substrates is performed so that the sealing material overlaps with the common connection portion. For example, in a small liquid crystal panel, two common connection portions are arranged so as to overlap with the sealing material at diagonal corners of the pixel portion. In a large liquid crystal panel, four or more common connection portions are arranged so as to overlap with the sealing material. For example, in a small liquid crystal panel, two common connection portions are arranged so as to overlap with the sealing material at diagonal corners of the pixel portion. In a large liquid crystal panel, four or more common connection portions are arranged so as to overlap with the sealing material. For example, in a small liquid crystal panel, two common connection portions are arranged so as to overlap with the sealing material at diagonal corners of the pixel portion. In a large liquid crystal panel, four or more common connection portions are arranged so as to overlap with the sealing material. For example, in a small liquid crystal panel, two common connection portions are arranged so as to overlap with the sealing material at diagonal corners of the pixel portion. In a large liquid crystal panel, four or more common connection portions are arranged so as to overlap with the sealing material.

[0150] Note that the common electrode layer 206 is an electrode that contacts the conductive particles included in the sealing material, and is electrically connected to the counter electrode of the second substrate. Note that the common electrode layer 206 is an electrode that contacts the conductive particles included in the sealing material, and is electrically connected to the counter electrode of the second substrate.

[0151] When the liquid crystal injection method is used, after fixing a pair of substrates with a sealing material, liquid crystal is injected between the pair of substrates. When the liquid crystal droplet method is used, a sealing material is drawn on the second substrate or the first substrate, the liquid crystal is dropped, and then the pair of substrates are bonded together under reduced pressure. When the liquid crystal injection method is used, after fixing a pair of substrates with a sealing material, liquid crystal is injected between the pair of substrates. When the liquid crystal droplet method is used, a sealing material is drawn on the second substrate or the first substrate, the liquid crystal is dropped, and then the pair of substrates are bonded together under reduced pressure. When the liquid crystal injection method is used, after fixing a pair of substrates with a sealing material, liquid crystal is injected between the pair of substrates. When the liquid crystal droplet method is used, a sealing material is drawn on the second substrate or the first substrate, the liquid crystal is dropped, and then the pair of substrates are bonded together under reduced pressure.

[0152] Note that, in this embodiment, an example of a common connection portion that is electrically connected to the counter electrode is shown, but it is not particularly limited, and it can be used for a connection portion that is connected to other wirings or a connection portion that is connected to an external connection terminal or the like. Note that, in this embodiment, an example of a common connection portion that is electrically connected to the counter electrode is shown, but it is not particularly limited, and it can be used for a connection portion that is connected to other wirings or a connection portion that is connected to an external connection terminal or the like. Note that, in this embodiment, an example of a common connection portion that is electrically connected to the counter electrode is shown, but it is not particularly limited, and it can be used for a connection portion that is connected to other wirings or a connection portion that is connected to an external connection terminal or the like.

[0153] This embodiment can be freely combined with any one of Embodiments 1 to 3.

[0154] (Embodiment 5) In Embodiment 1 or Embodiment 2, an example of a single-layer gate insulating layer was shown, but in this embodiment, an example of a stacked structure is shown. In FIG. 6, the same reference numerals as those in FIG. 3(A) or FIG. 3(B) are used for the description of the same locations. In Embodiment 1 or Embodiment 2, an example of a single-layer gate insulating layer was shown, but in this embodiment, an example of a stacked structure is shown. In FIG. 6, the same reference numerals as those in FIG. 3(A) or FIG. 3(B) are used for the description of the same locations. In Embodiment 1 or Embodiment 2, an example of a single-layer gate insulating layer was shown, but in this embodiment, an example of a stacked structure is shown. In FIG. 6, the same reference numerals as those in FIG. 3(A) or FIG. 3(B) are used for the description of the same locations.

[0155] In FIG. 6(A), the thin film transistor 280 is a channel protection type thin film transistor provided in the pixel portion, and is an example in which the gate insulating layer has two layers. Except for the point that the gate insulating layer has two layers, it is the same as the thin film transistor 220. In this embodiment, a gate insulating layer is formed by laminating a first gate insulating layer 282a having a thickness of 50 nm or more and 200 nm or less and a second gate insulating layer 282b having a thickness of 50 nm or more and 300 nm or less. As the first gate insulating layer 282a, a silicon nitride film or a silicon oxynitride film having a thickness of 100 nm is used. As the second gate insulating layer 282b, a silicon oxide film having a thickness of 100 nm is used. Except for the point that the gate insulating layer has two layers, it is the same as the thin film transistor 220.

[0156] In this embodiment, a first gate insulating layer 282a having a thickness of 50 nm or more and 200 nm or less and a second gate insulating layer 282b having a thickness of 50 nm or more and 300 nm or less are laminated to form a gate insulating layer. As the first gate insulating layer 282a, a silicon nitride film or a silicon oxynitride film having a thickness of 100 nm is used. As the second gate insulating layer 282b, a silicon oxide film having a thickness of 100 nm is used. As the first gate insulating layer 282a, a silicon nitride film or a silicon oxynitride film having a thickness of 100 nm is used. As the second gate insulating layer 282b, a silicon oxide film having a thickness of 100 nm is used.

[0157] The holding capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is electrically connected to the pixel electrode layer 227.

[0158] In this embodiment, the holding capacitor is formed using the capacitor electrode 231 and the capacitor wiring layer 230.

[0159] Also, in FIG. 6(A), since the holding capacitor forms a large capacitance, only the gate insulating layer is provided between the capacitor wiring and the capacitor electrode.

[0160] In this embodiment, a silicon oxide film obtained by sputtering is used as the oxide insulating layer 282b. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, the second gate insulating layer, which is a silicon oxide film, is also etched to be thinned to form a third gate insulating layer 282c. The first gate insulating layer 282a is a silicon nitride film or a silicon oxynitride film, and is resistant to etching. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, the second gate insulating layer, which is a silicon oxide film, is also etched to be thinned to form a third gate insulating layer 282c. The first gate insulating layer 282a is a silicon nitride film or a silicon oxynitride film, and is resistant to etching. ​​​​​It functions as a topper to prevent etching damage to the gate electrode layer and substrate.

[0161] By making the third gate insulating layer 282c thin, it is possible to increase the storage capacitance. can.

[0162] FIG. 6B shows a cross-sectional structure that is partially different from that shown in FIG. 6A.

[0163] In the thin film transistor 290 shown in FIG. 6B, the first a first gate insulating layer 292a and a second gate insulating layer 292b having a thickness of 1 nm to 50 nm; The first gate insulating layer 292a is a 100 nm thick oxide film. The second gate insulating layer 292b is a silicon nitride film having a thickness of 10 nm. A bare film or a silicon nitride oxide film is used.

[0164] The thin film transistor 290 is a channel protection type thin film transistor provided in the pixel portion. This is an example of a thin film transistor with two gate insulating layers. It is the same as Transistor 220.

[0165] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 4.

[0166] (Sixth embodiment) In this embodiment, an example in which a part of the manufacturing process of a thin film transistor is different from that in Embodiment 1 is shown in FIG. 7 and 8 are the same as those in FIGS. 1 and 2 except for some differences in the process. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted.

[0167] First, according to the first embodiment, a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer are formed on a substrate. The film 430 is formed, and the steps up to the step shown in FIG. 2(A) in the first embodiment are carried out. This is the same as Figure 8(A).

[0168] Then, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. Process into body layers.

[0169] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than the distortion point of the substrate, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. For example, the heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is prevented from being exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. After that, the same furnace is filled with high-purity oxygen gas, high-purity N2O gas, or ultra-dry Cooling is performed by introducing air (dew point below -40°C, preferably below -60°C). Oxygen gas Alternatively, it is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the or 7N (99.99999%) or more (i.e., impurity concentration in oxygen gas or N2O gas) It is preferable to set the concentration of the HCl-containing compound to 1 ppm or less, preferably 0.1 ppm or less.

[0170] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0171] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 430 before it is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out of the heating apparatus, and a photolithography process is performed.

[0172] By going through the above steps to make the entire oxide semiconductor film in an oxygen-excessive state, high resistance oxidation, that is, type I conversion, is achieved.

[0173] Next, after forming an oxide insulating film by sputtering on the gate insulating layer 402 and the oxide semiconductor layer, a resist mask is formed by a third photolithography process, and selective etching is performed to form the oxide insulating layers 426a and 426b, and then the resist mask is removed (see FIG. 8(B)).

[0174] Next, after forming a conductive film on the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer 422, a resist mask is formed by a fourth photolithography process, and selective etching is performed to form the source electrode layer 425a and the drain electrode layer 425b (see FIG. 8(C)).

[0175] Next, in order to reduce the variation in the electrical characteristics of the thin film transistor, heat treatment (preferably at 150°C or higher and lower than �50°C) may be performed in an inert gas atmosphere or in a nitrogen gas atmosphere. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0176] Next, a laminate of the insulating layer 428 and the protective insulating layer 403 is formed on the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 425b.

[0177] ​​​​​​​​​​​​ Next, a planarization insulating layer 404 is formed on the protective insulating layer 403.

[0178] Next, a fifth photolithography process is performed to form a resist mask, and a contact hole 441 reaching the drain electrode layer 425b is formed by etching the planarization insulating layer 4 04, the protective insulating layer 403, and the insulating layer 428, and the resist mask is removed (see Fig. 8(D). .).

[0179] Next, a conductive film having translucency is formed.

[0180] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 427, and the resist mask is removed (see Fig. 8( E).).

[0181] Through the above processes, using six masks, a thin film transistor 420 and a wiring intersection portion with reduced parasitic capacitance can be fabricated on the same substrate.

[0182] The thin film transistor 420 for pixels is a channel protection type thin film transistor including an oxide semiconductor layer 422 including a channel formation region.

[0183] Further, Fig. 7(A) is a plan view of the channel protection type thin film transistor 420 arranged in a pixel, Fig. 7(B) is a cross-sectional view taken along line D7-D8 in Fig. 7(A) and a cross-sectional view taken along line D 11-D12 in Fig. 7(A). Fig. 7(C) is a cross-sectional view taken along line D9-D10 in Fig. 7(A). Note that Fig. 8(E) is the same as Fig. 7(B).

[0184] This embodiment can be freely combined with any one of Embodiments 1 to 5.

[0185] (Embodiment 7) In this embodiment, an example different from that of Embodiment 2 regarding the configuration of the holding capacitance is shown in FIGS. 9(A) and FIG. 9(B). Since FIG. 9(A) is the same as FIG. 3(A) except for the difference in the configuration of the holding capacitance, the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted. Note that FIG. 9 (A) shows a cross-sectional structure of the thin film transistor 220 in the pixel portion and the holding capacitance. (A) shows a cross-sectional structure of the thin film transistor 220 in the pixel portion and the holding capacitance.

[0186] FIG. 9(A) shows an example in which the dielectric is the protective insulating layer 203 and the planarization insulating layer 204, and the holding capacitance is formed by the pixel electrode layer 2 27 and the capacitance wiring layer 250 overlapping the pixel electrode layer 227. The capacitance wiring layer 250 is formed of a material different from the drain electrode layer of the thin film transistor 220 in the pixel portion. Also, the capacitance wiring layer 250 is formed of a material different from the oxide semiconductor layer of the thin film transistor 220. The capacitance wiring layer 250 is formed using a conductive film having translucency. Note that one more photomask for patterning the capacitance wiring layer 250 is added compared to Embodiment 2. Also, etching for forming the capacitance wiring layer 250 is performed under the condition that the oxide semiconductor layer of the exposed thin film transistor 220 does not disappear. Note that one more photomask for patterning the capacitance wiring layer 250 is added compared to Embodiment 2. Also, etching for forming the capacitance wiring layer 250 is performed under the condition that the oxide semiconductor layer of the exposed thin film transistor 220 does not disappear. Note that one more photomask for patterning the capacitance wiring layer 250 is added compared to Embodiment 2. Also, etching for forming the capacitance wiring layer 250 is performed under the condition that the oxide semiconductor layer of the exposed thin film transistor 220 does not disappear.

[0187] The holding capacitance shown in FIG. 9(A) has translucency for a pair of electrodes and the dielectric, and has translucency as a whole. By making the holding capacitance translucent, the aperture ratio can be improved. The holding capacitance shown in FIG. 9(A) has translucency for a pair of electrodes and the dielectric, and has translucency as a whole. By making the holding capacitance translucent, the aperture ratio can be improved. The holding capacitance shown in FIG. 9(A) has translucency for a pair of electrodes and the dielectric, and has translucency as a whole. By making the holding capacitance translucent, the aperture ratio can be improved.

[0188] Also, FIG. 9(B) shows an example of a configuration of the holding capacitance different from that of FIG. 9(A). Since FIG. 9(B) is the same as FIG. 3(A) except for the difference in the configuration of the holding capacitance, the same reference numerals are used for the same parts, and the detailed description of the same parts is omitted. and the detailed description of the same parts is omitted.

[0189] FIG. 9(B) shows an example in which a dielectric is used as the gate insulating layer 202, and a storage capacitor is formed by laminating a capacitive wiring layer 230, an oxide semiconductor layer 251 overlapping the capacitive wiring layer 2 30, and a capacitive electrode 231. The capacitive electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. The oxide semiconductor layer 251 is formed of the same material and by the same process as the oxide semiconductor layer of the thin film transistor 22 0. Further, since the capacitive wiring layer 230 is formed of the same material and by the same process as the gate electrode layer of the thin film transistor 220, the layout is such that it does not overlap with the gate wiring layer of the thin film transistor 22 0. Also, the capacitive electrode 23 1 is electrically connected to the pixel electrode layer 227. Also, the capacitive wiring layer 230 is formed of a material different from that of the oxide semiconductor layer of the thin film transistor 220. The capacitive electrode 231 is formed using a conductive film having translucency. Note that one more photomask for patterning the capacitive electrode 231 is added compared to Embodiment 2. Also, in the etching for forming the capacitive electrode 231, etching is performed under the condition that the exposed oxide semiconductor layer of the thin film transistor 22 0 does not disappear. The storage capacitor shown in FIG. 9(B) also has translucency for a pair of electrodes and a dielectric, and has translucency as a whole storage capacitor.

[0190] The storage capacitors shown in FIGS. 9(A) and 9(B) have translucency. In order to increase the definition of a displayed image by increasing the number of gate wirings or the like, even if the pixel size is miniaturized, a sufficient capacitance can be obtained, and a high aperture ratio can be realized. The storage capacitors shown in FIGS. 9(A) and 9(B) have translucency. In order to increase the definition of a displayed image by increasing the number of gate wirings or the like, even if the pixel size is miniaturized, a sufficient capacitance can be obtained, and a high aperture ratio can be realized. The storage capacitors shown in FIGS. 9(A) and 9(B) have translucency. In order to increase the definition of a displayed image by increasing the number of gate wirings or the like, even if the pixel size is miniaturized, a sufficient capacitance can be obtained, and a high aperture ratio can be realized. 0 does not disappear. The storage capacitor shown in FIG. 9(B) also has translucency for a pair of electrodes and a dielectric, and has translucency as a whole storage capacitor.

[0191] The storage capacitor shown in FIG. 9(B) also has translucency for a pair of electrodes and a dielectric, and has translucency as a whole storage capacitor. The storage capacitors shown in FIGS. 9(A) and 9(B) have translucency. In order to increase the definition of a displayed image by increasing the number of gate wirings or the like, even if the pixel size is miniaturized, a sufficient capacitance can be obtained, and a high aperture ratio can be realized.

[0192] The storage capacitors shown in FIGS. 9(A) and 9(B) have translucency. In order to increase the definition of a displayed image by increasing the number of gate wirings or the like, even if the pixel size is miniaturized, a sufficient capacitance can be obtained, and a high aperture ratio can be realized. The storage capacitors shown in FIGS. 9(A) and 9(B) have translucency. In order to increase the definition of a displayed image by increasing the number of gate wirings or the like, even if the pixel size is miniaturized, a sufficient capacitance can be obtained, and a high aperture ratio can be realized. The storage capacitors shown in FIGS. 9(A) and 9(B) have translucency. In order to increase the definition of a displayed image by increasing the number of gate wirings or the like, even if the pixel size is miniaturized, a sufficient capacitance can be obtained, and a high aperture ratio can be realized.

[0193] This embodiment mode can be freely combined with other embodiment modes.

[0194] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0195] The thin film transistors arranged in the pixel portion are formed according to the first, second, fifth and sixth embodiments. In addition, since the thin film transistors shown in the first, second, fifth and sixth embodiments are n-channel TFTs, Among the driver circuits, a part of the driver circuit that can be configured with an n-channel TFT is The thin film transistor is formed on the same substrate as the thin film transistor.

[0196] An example of a block diagram of an active matrix display device is shown in FIG. On a substrate 5300, a pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a The pixel portion 5301 has a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0197] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The gate line driving circuit 5304 is formed on the same substrate 5300 as the pixel section 5301. Therefore , the number of components such as the driving circuit provided outside is reduced, so that the cost can be reduced. Also , when a driving circuit is provided outside the substrate 5300, the number of connections at the connection part due to extending the wiring can be reduced, and the reliability or the yield can be improved.

[0198] Note that the timing control circuit 5305 supplies, for example, a start signal (GSP1) for the first gate line driving circuit and a clock signal (GCK1) for the gate line driving circuit to the first gate line driving circuit 5302. Also, the timing control circuit 5305 supplies, for example, a start signal (GSP2) (also referred to as a start pulse) for the second gate line driving circuit and a clock signal (GCK2) to the second gate line driving circuit 5303. A start signal (SSP) for the signal line driving circuit, a clock signal (SCK) for the signal line driving circuit, video signal data (simply referred to as a video signal) (DATA), and a latch signal (LAT) are supplied to the signal line driving circuit 5304. Each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. It should be noted that one of the first gate line driving circuit 5302 and the second gate line driving circuit 53 03 can be omitted.

[0199] In FIG. 14(B), a configuration is shown in which a circuit with a low driving frequency (for example, the first gate line driving circuit 5302, the second gate line driving circuit 5303) is formed on the same substrate 5300 as the pixel section 5301, and the signal line driving circuit 5304 is formed on a substrate different from the pixel section 5301. The Due to its structure, compared with a transistor using a single-crystal semiconductor, the field-effect mobility is small in the thin film transistor, and a driving circuit formed on the substrate 5300 can be configured. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield.

[0200] In addition, the thin film transistors shown in Embodiments 1, 2, 5, and 6 are n-channel type TFTs. In FIGS. 15(A) and 15(B), an example of the configuration and operation of a signal line driving circuit composed of n-channel type TFTs will be shown and described.

[0201] The signal line driving circuit includes a shift register 5601 and a switching circuit section 5602. The switching circuit section 5602 includes a plurality of circuits, namely switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each include a plurality of transistors, namely thin film transistors 5603_1 to 5603_k (k is a natural number). An example where the thin film transistors 5603_1 to 5603_k are n-channel type TFTs will be described.

[0202] The connection relationship of the signal line driving circuit will be described by taking the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are each connected to wirings 5604_1 to 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gates of the thin film transistors 5603_1 to 5603_ k are connected to the wiring 5605_1.

[0203] The shift register 5601 sequentially supplies H level (H signal) to the wirings 5605_1 to 5605_N. outputs a signal (also referred to as a high power potential level), and has a function of sequentially selecting the switching circuits 5602_1 to 56 02_N.

[0204] The switching circuit 5602_1 has a function of controlling the conduction state (conduction between the first terminal and the second terminal) between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk , that is, a function of controlling whether to supply the potentials of the wirings 5604_ 1 to 5604_k to the signal lines S1 to Sk. Thus, the switching circuit 5602_1 has a function as a selector. Also, the thin film transistors 5603_1 to 5603_k each have a function of controlling the conduction state between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of supplying the potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. Thus, the thin film transistors 560 3_1 to 5603_k each have a function as a switch.

[0205] Note that video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal.

[0206] Next, the operation of the signal line driving circuit in Fig. 15(A) will be described with reference to the timing chart in Fig. 15(B). In Fig. 15(B), examples of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k are shown. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 5601, and the signals Vdata_1 to Vdata _k are each an example of the signals input to the wirings 5604_1 to 5604_k. Note that One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN, for example. Periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row. There is.

[0207] Note that the distortion of the signal waveform of each configuration shown in the drawings and the like of the present embodiment may be exaggerated for clarity. Therefore, it is noted that it is not necessarily limited to that scale. Therefore, it is noted that it is not necessarily limited to that scale. is appended.

[0208] During periods T1 to TN, the shift register 5601 outputs H-level signals to wirings 560 5_1 to 5605_N in order. For example, during period T1, the shift register 5 601 outputs a high-level signal to wiring 5605_1. Then, the thin film transistors 5603_1 to 5603_k turn on, so that wirings 5604_1 to 5604_k and the signal lines S1 to Sk are in a conductive state. At this time, Data(S1) to Data(Sk) are input to wirings 5604_1 to 5604_k. Data(S1) to Data(Sk ) are written to the pixels in the first column to the k-th column among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k, respectively. In this way, during periods T1 to TN, video signal data (DATA) is written to the pixels belonging to the selected row in units of k columns in order. ) are written to the pixels in the first column to the k-th column among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k, respectively. In this way, during periods T1 to TN, video signal data (DATA) is written to the pixels belonging to the selected row in units of k columns in order. In this way, by writing the video signal data (DATA) to the pixels in units of a plurality of columns, the number of the video signal data (DATA) or the number of wirings can be reduced. In this way, by writing the video signal data (DATA) to the pixels in units of a plurality of columns, the number of the video signal data (DATA) or the number of wirings can be reduced. is written.

[0209] As described above, by writing the video signal data (DATA) to the pixels in units of a plurality of columns, the number of the video signal data (DATA) or the number of wirings can be reduced. By writing the video signal data (DATA) to the pixels in units of a plurality of columns, the number of the video signal data (DATA) or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced. Also, since the video signal is written pixel by pixel in multiple columns at a time, the writing time can be extended, preventing insufficient writing of the video signal. By writing the video signal pixel by pixel in multiple columns at a time, the writing time can be extended, preventing insufficient writing of the video signal.

[0210] Note that as the shift register 5601 and the switching circuit 5602, it is possible to use circuits composed of thin film transistors shown in Embodiments 1, 2, 5, and 6. In this case, all the transistors of the shift register 5601 can be configured with only either N-channel type or P-channel type polarity.

[0211] One form of the shift register used in part of the scanning line driving circuit and / or the signal line driving circuit will be described with reference to FIGS. 16 and 17.

[0212] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, etc. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. The gates of the transistors of the pixels for one line are connected to the scanning line. Therefore, since the transistors of the pixels for one line must be turned on all at once, a buffer that can pass a large current is used.

[0213] The shift register has a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more) (see FIG. 16(A)). The shift register shown in FIG. 16(A) ​​​​​​​The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the jitter receive the first clock signal CK1 from the first wiring 11 and the second clock signal CK2 from the second wiring 12 , the third clock signal CK3 from the third wiring 13, and the fourth clock signal CK4 from the fourth wiring 14. In addition, in the first pulse output circuit 10_1, a start pulse SP1 (the first start pulse) from the fifth wiring 15 is input. In addition, in the nth pulse output circuit 10_n (n is a natural number from 2 to N) after the second stage, a signal (referred to as the previous stage signal OUT(n - 1)(SR)) from the pulse output circuit of the previous stage (n is a natural number from 2 to N ) is input. In addition, in the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages later is input. Similarly, in the nth pulse output circuit 10_n after the second stage, a signal (referred to as the subsequent stage signal OUT(n + 2)(SR)) from the (n + 2)th pulse output circuit two stages later is input. Therefore, each stage of the pulse output circuit outputs a first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the pulse output circuit two stages before, and a second output signal (OUT(1) to OUT(N)) for input to another circuit or the like. As shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input. Here, the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the Nth clock signal (CKN) are all signals that repeat the H level and the L level at regular intervals. The first output signal (OUT(1)(SR) to OUT(N)(SR)) and the second output signal (OUT(1) to OUT(N)) are output from each stage of the pulse output circuit for input to the subsequent stage and / or the pulse output circuit two stages before, and for input to another circuit or the like. As shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the last two stages of the shift register, as an example, a separate second start pulse SP2 and third start pulse SP3 may be respectively input. Note that the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the Nth clock signal (CKN) are all signals that repeat the H level and the L level at regular intervals.

[0214] Note that the clock signal (CK) is a signal that repeats the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the Nth clock signal (CKN) are all signals that repeat the H level and the L level at regular intervals. Nth clock signal (CKN) are all signals that repeat the H level and the L level at regular intervals. The clock signal (CK4) of 4 is sequentially delayed by 1 / 4 cycle. In this embodiment, using the first clock signal (CK1) to the fourth clock signal (CK4), the pulse output path is controlled, etc. Note that the clock signal may be referred to as GCK or SCK depending on the input drive circuit, but here it will be described as CK.

[0215] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 16(A), for the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, for the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14 .

[0216] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is assumed to have a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, the third clock signal CK3 is input to the third input terminal 23, and the start is input to the fourth input terminal 24 (see FIG. 16(B)). signal is input to the fourth input terminal 24, and the start clock signal CK3 is input to the third input terminal 23, and the start ​​A pulse is input, the subsequent-stage signal OUT(3) is input to the fifth input terminal 25, and the first output signal OUT(1)(SR) is output from the first output terminal 26, and the second output signal OUT(1) is output from the second output terminal 27.

[0217] Note that the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N can use, in addition to the three-terminal thin film transistor (also referred to as TFT: Thin Film Transistor), the four-terminal thin film transistor described in the above embodiment. FIG. 16(C) shows the symbol of the four-terminal thin film transistor 28 described in the above embodiment. FIG. 16(C) shows the symbol of the thin film transistor 28, which means the four-terminal thin film transistor described in any one of the above Embodiments 1, 2, 5, and 6, and will be used hereinafter in the drawings and the like. In this specification, when a thin film transistor has two gate electrodes via a semiconductor layer, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is also called the upper gate electrode. The thin film transistor 28 is an element capable of electrically controlling between the In terminal and the Out terminal by the first control signal G1 input to the lower gate electrode and the second control signal G2 input to the upper gate electrode.

[0218] When an oxide semiconductor is used for the semiconductor layer including the channel formation region of the thin film transistor, the threshold voltage may shift to the minus side or the plus side during the manufacturing process. Therefore, for a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region, a configuration capable of controlling the threshold voltage is preferable. The thin film transistor shown in FIG. 16(C) The threshold voltage of the transistor 28 can be controlled to a desired value by providing a gate electrode via a gate insulating film above and below the channel formation region of the thin film transistor 28 and controlling the potential of the upper and / or lower gate electrodes. Next, an example of the specific circuit configuration of the pulse output circuit shown in FIG. 16(B) will be described with reference to FIG. 16(D). The pulse output circuit shown in FIG. 16(D) includes the first transistor 31 to the thirteenth transistor 43 (see FIG. 16(D)). In addition to the first input terminal 21 to the fifth input terminal 25, and the first output terminal 26 and the second output terminal 27 described above, a power supply line 51 to which the first high power supply potential VDD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied supply signals or power supply potentials to the first transistor 31 to the thirteenth transistor 43. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3

[0219] Next, regarding an example of the specific circuit configuration of the pulse output circuit shown in FIG. 16(B), it will be described with reference to FIG. 16(D). (D).

[0220] The pulse output circuit shown in FIG. 16(D) has the first transistor 31 to the thirteenth transistor 43 (see FIG. 16(D)). Also, in addition to the first input terminal 21 to the fifth input terminal 25, and the first output terminal 26 and the second output terminal 27 described above, a power supply line 51 to which the first high power supply potential VDD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied supply signals or power supply potentials to the first transistor 31 to the thirteenth transistor 43. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 has (see FIG. 16(D)). Also, in addition to the first input terminal 21 to the fifth input terminal 25, and the first output terminal 26 and the second output terminal 27 described above, a power supply line 51 to which the first high power supply potential VDD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied supply signals or power supply potentials to the first transistor 31 to the thirteenth transistor 43. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 input terminal 21 to the fifth input terminal 25, and the first output terminal 26, the second output terminal 27, in addition, a power supply line 51 to which the first high power supply potential VDD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied supply signals or power supply potentials to the first transistor 31 to the thirteenth transistor 43. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 A power supply line 51 to which the first high power supply potential VDD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied supply signals or power supply potentials to the first transistor 31 to the thirteenth transistor 43. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 The power supply line 51 to which the first high power supply potential VDD is supplied, the power supply line 52 to which the second high power supply potential VCC is supplied, and the power supply line 53 to which the low power supply potential VSS is supplied supply signals or power supply potentials to the first transistor 31 to the thirteenth transistor 43. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 The signal or power supply potential is supplied to the first transistor 31 to the thirteenth transistor 43 from the power supply line 51 to which the first high power supply potential VDD is supplied, the power supply line 52 to which the second high power supply potential VCC is supplied, and the power supply line 53 to which the low power supply potential VSS is supplied. Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 The magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 The second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 The first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 The first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are VDD at the H level and VSS at the L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 Without affecting the operation, the potential applied to the gate electrode of the transistor can be suppressed low, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 The threshold voltage of the transistor 28 can be controlled to a desired value by providing a gate electrode via a gate insulating film above and below the channel formation region of the thin film transistor 28 and controlling the potential of the upper and / or lower gate electrodes. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, the shift of the threshold value of the transistor can be reduced, and the degradation can be suppressed. Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 Among the first transistor 31 to the thirteenth transistor 43, the first transistor 3 1. For the sixth transistor 36 to the ninth transistor 39, it is preferable to use a four-terminal thin-film transistor 28. The operations of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 are transistors that require switching the potential of a node to which one of the electrodes serving as a source or a drain is connected by a control signal of a gate electrode, and the transistor has a fast response to the control signal input to the gate electrode (the rise of the on-current is steep), so that the malfunction of the pulse output circuit can be further reduced. Therefore, by using a four-terminal thin-film transistor, the threshold voltage can be controlled, and a pulse output circuit with further reduced malfunction can be obtained. In FIG. 16(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. For the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. For the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. For the fourth transistor 34, the first terminal is electrically connected to the power supply line 53,

[0221] and the second terminal is electrically connected to the first output terminal 26. For the fifth transistor 35, the first terminal is electrically connected to the power supply line 53, and the second terminal is the gate of the second transistor 32 electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24. For the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. For the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. For the fourth transistor 34, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. For the fifth transistor 35, the first terminal is electrically connected to the power supply line 53, and the second terminal is the gate of the second transistor 32 is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal connected to the power supply line 53, and its second terminal is connected to the first output terminal 26. The fifth transistor 35 has its first terminal connected to the power supply line 53, and its second terminal is connected to the first output terminal 26. The fifth transistor 35 has its first terminal connected to the power supply line 53, and its second terminal is connected to the gate of the second transistor 32 electrically connected to the electrode and the gate electrode of the fourth transistor 34, and the gate electrode is the fourth electrically connected to the input terminal 24. The sixth transistor 36 has its first terminal electrically connected to the power supply line 52, and its second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power supply line 52, and its second terminal is electrically connected to the second terminal of the eighth transistor 38, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the second input terminal 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the power supply line 52 The tenth transistor 40 has its first terminal electrically connected to the first input terminal 2 1, its second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power supply line 53, and its second terminal is electrically connected to the second output terminal 27, and the gate electrode is the gate electrode of the second transistor 32 and the fourth transistor 32 is electrically connected to the gate electrode of the 34th stage. The 12th transistor 42 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27 , and its gate electrode electrically connected to the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper gate electrode). The 13th transistor 43 has its first terminal electrically connected to the power supply line 5 3, its second terminal electrically connected to the first output terminal 26, and its gate electrode electrically connected to the gate electrode of the 7th transistor 37 (the lower gate electrode and the upper gate electrode).

[0222] In FIG. 16(D), the connection point of the gate electrode of the 3rd transistor 33, the gate electrode of the 10th transistor 40, and the second terminal of the 9th transistor 39 is defined as node A. Also, the connection point of the gate electrode of the 2nd transistor 32, the gate electrode of the 4th transistor 34, the second terminal of the 5th transistor 35, the second terminal of the 6th transistor 36, the first terminal of the 8th transistor 38, and the gate electrode of the 11th transistor 41 is defined as node B.

[0223] In FIG. 17(A), when the pulse output circuit described in FIG. 16(D) is applied to the first pulse output circuit 10_ 1, the signals input or output to / from the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the second output terminal 27 are shown.

[0224] Specifically, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal is input to the third input terminal 23 Signal CK3 is input, a start pulse is input to the fourth input terminal 24, and the subsequent stage signal OUT(3) is input to the fifth input terminal 25. The first output signal OUT (1)(SR) is output from the first output terminal 26, and the second output signal OUT(1) is output from the second output terminal 27 .

[0225] Note that a thin film transistor is an element having at least three terminals including a gate, a drain, and a source. Further, it has a semiconductor body in which a channel region is formed in a region overlapping with the gate, and by controlling the potential of the gate, the current flowing between the drain and the source through the channel region can be controlled. Here, since the source and the drain vary depending on the structure and operating conditions of the thin film transistor, etc., it is difficult to limit which one is the source or the drain . Therefore, the regions functioning as the source and the drain may not be called the source or the drain. In that case, as an example, they may be denoted as the first terminal and the second terminal, respectively.

[0226] Note that in FIGS. 16(D) and 17(A), a capacitive element may be separately provided for performing a bootstrap operation by making the node A in a floating state. Also, a capacitive element having one electrode electrically connected to the node B may be separately provided to hold the potential of the node B

[0227] .

[0227] Here, the timing chart of a shift register including a plurality of pulse output circuits shown in FIG. 17(A) is shown in FIG. 17(B). When the shift register is a scanning line driving circuit , period 61 in FIG. 17(B) is a vertical blanking period, and period 62 corresponds to a gate selection period .

[0228] ​ Note that, as shown in FIG. 17(A), by providing a ninth transistor 39 to which a second power supply potential VCC is applied to the gate, the following advantages exist before and after the bootstrap operation. There are advantages as follows.

[0229] When there is no ninth transistor 39 to which the second potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may be a factor in transistor degradation. Therefore, by providing a ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the bootstrap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed. Note that, regarding the location where the ninth transistor 39 is provided, the second of the first transistor 31 can be used. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, by adopting the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that degradation of the first transistor 31 due to stress can be suppressed. transistor 31 can be suppressed due to stress. Therefore, degradation of the first transistor 31 due to stress can be suppressed.

[0230] Note that, regarding the location where the ninth transistor 39 is provided, it is at the second and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0231] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and This allows for increased field effect mobility and reduced degradation. In addition, a transistor using an oxide semiconductor, Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is This allows the number of power supply lines to be reduced, thereby enabling the circuit to be made smaller.

[0232] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 the clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38 The voltage supplied to the gate electrodes (lower gate electrode and upper gate electrode) by the second input terminal 22 is The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). a clock signal provided by the second input terminal 22 to the gate electrode of the eighth transistor; The gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode 38 are connected to the third input terminal 23. Therefore, even if the connection relationship is switched so as to obtain a supplied clock signal, the same operation is achieved. At this time, in the shift register shown in FIG. 17(A), from the state where the seventh transistor 37 and the eighth transistor 38 are both on, the seventh transistor 37 turns off, and the eighth transistor 38 is on. Next, by setting the seventh transistor 37 to off and the eighth transistor 38 to off, the potential drop of node B caused by the potential drops of the second input terminal 22 and the third input terminal 23 occurs twice due to the potential drop of the gate electrode of the seventh transistor 37 and the potential drop of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in FIG. 17(A), during the period of FIG. 17(B) as shown in 61, from the state where the seventh transistor 37 and the eighth transistor 38 are both on, the seventh transistor 37 turns on and the eighth transistor 38 turns off. Next, by setting the seventh transistor 37 to off and the eighth transistor 38 to off, the potential drop of node B caused by the potential drops of the second input terminal 22 and the third input terminal 23 can be reduced once by the potential drop of the gate electrode of the eighth transistor 38. Therefore, it is preferable that a clock signal is supplied from the third input terminal 23 to the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37, and a clock signal is supplied from the second input terminal 22 to the gate electrode (lower gate electrode and upper gate electrode) of the eighth transistor 38. This is because the number of fluctuations in the potential of node B is reduced, and noise can also be reduced.

[0233] In this way, by configuring the potential of the first output terminal 26 and the second output terminal 27 to be held at the L level, and by periodically supplying a signal of the H level to node B during the period, malfunction of the pulse output circuit can be suppressed. During the period when the potential of the first output terminal 26 and the second output terminal 27 is held at the L level, a signal of the H level is periodically supplied to node B, thereby suppressing malfunction of the pulse output circuit.

[0234] (Embodiment 9) A thin film transistor can be fabricated, and the thin film transistor can be used in a pixel portion and further in a driving circuit to fabricate a semiconductor device (also referred to as a display device) having the functions shown. Further, a part or the whole of the driving circuit can be integrally formed on the same substrate as the pixel portion to form a system on panel. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Further, electronic ink or a display medium whose contrast changes by an electrical action can also be applied. The display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Further, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or may be in a state after a conductive film to be the pixel electrode is formed and before etching to form the pixel electrode. The display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Further, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or may be in a state after a conductive film to be the pixel electrode is formed and before etching to form the pixel electrode.

[0235] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Further, electronic ink or a display medium whose contrast changes by an electrical action can also be applied. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Further, electronic ink or a display medium whose contrast changes by an electrical action can also be applied. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, etc. Also, electronic ink or a display medium whose contrast changes due to an electrical action can also be applied.

[0236] Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. In the process of manufacturing the display device, regarding the element substrate corresponding to a form before the display element is completed, the element substrate includes means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or may be in a state after a conductive film to be the pixel electrode is formed and before etching to form the pixel electrode. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or may be in a state after a conductive film to be the pixel electrode is formed and before etching to form the pixel electrode. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or may be in a state after a conductive film to be the pixel electrode is formed and before etching to form the pixel electrode. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or may be in a state after a conductive film to be the pixel electrode is formed and before etching to form the pixel electrode. It applies to all forms.

[0237] In addition, the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, an FPC (Flexible pr inted circuit) or a TAB (Tape Automated Bon ding) tape or a TCP (Tape Carrier Package) attached module, a module with a printed wiring board provided at the tip of a TAB tape or a TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by the COG (Chip On Glass) method are all included in the display device. For the appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device, it will be described with reference to FIG. 10. FIGS. 10(A1)(A2) are a plan view of the panel in which thin film transistors 4010, 4011, and a liquid crystal element 4013 are sealed between a first substrate 4001 and a second substrate 4006 by a sealing material 4005, and FIG. 10(B) corresponds to a cross-sectional view taken along M

[0238] -N of FIGS. 10(A1)(A2). The sealing material 4005 is provided so as to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, the seal on the first substrate 4001 material

[0239] On the first substrate 4001, a sealing material 4005 is provided so as to surround the pixel portion 4002 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Thus, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, the seal on the first substrate 4001 On the first substrate 4001, a sealing material 4005 is provided so as to surround the pixel portion 4002 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, the seal on the first substrate 4001 4001 and the second substrate 4006. Also, the seal on the first substrate 4001 A signal line driving circuit 4003 formed of a single-crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the material 4005. The signal line driving circuit 4003 formed of a single-crystal semiconductor film or a polycrystalline semiconductor film is mounted.

[0240] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method or the like can be used. FIG. 10(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 10(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0241] In addition, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 each have a plurality of thin film transistors. In FIG. 10(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. Insulating layers 4041a, 40 41b, 4042a, 4042b, 4020, and 4021 are provided on the thin film transistors 4010 and 4011.

[0242] As the thin film transistors 4010 and 4011, highly reliable thin film transistors including the oxide semiconductor layers shown in Embodiments 1, 2, 5, and 6 can be applied. As the thin film transistor 4011 for the driving circuit, the thin film transistors 260 and 270 shown in Embodiments 1, 2, 5, and 6 can be used, and as the thin film transistor 4010 for the pixel, the thin film transistors 420, 448, 220, 280, and 290 can be used. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. As the thin film transistor 4011 for the driving circuit, the thin film transistors 260 and 270 shown in Embodiments 1, 2, 5, and 6 can be used, and as the thin film transistor 4010 for the pixel, the thin film transistors 420, 448, 220, 280, and 290 can be used. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. As the thin film transistor 4011 for the driving circuit, the thin film transistors 260 and 270 shown in Embodiments 1, 2, 5, and 6 can be used, and as the thin film transistor 4010 for the pixel, the thin film transistors 420, 448, 220, 280, and 290 can be used. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. As the thin film transistor 4011 for the driving circuit, the thin film transistors 260 and 270 shown in Embodiments 1, 2, 5, and 6 can be used, and as the thin film transistor 4010 for the pixel, the thin film transistors 420, 448, 220, 280, and 290 can be used. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0243] On the insulating layer 4021, at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driving circuit a conductive layer 4040 is provided. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, it is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test. Also, the potential of the conductive layer 4040 may be the same as that of the gate electrode layer of the thin film transistor 4011, or it may be different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0244] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided for the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0245] Note that as the first substrate 4001 and the second substrate 4006, a light-transmissive substrate can be used, and glass, ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used.

[0246] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, for controlling the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 and is provided there. Note that spherical spacers may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010 and the counter electrode layer 4031 and the common potential line can be electrically connected through conductive particles disposed between a pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005.

[0247] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 1 msec or less, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependence.

[0248] In addition to the transmissive liquid crystal display device, it can also be applied to a transflective liquid crystal display device.

[0249] Also, in the liquid crystal display device, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate, and a coloring layer and an electrode layer used for display elements are provided in this order on the inside, but the polarizing plate may be provided on the inside of the substrate. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to the present embodiment, and may be appropriately set according to the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. Also, in addition to the display portion, a black matrix ​​​​​​​A light-shielding film that functions as such may be provided.

[0250] The thin film transistor 4011 is formed with an insulating layer 4041a that functions as a channel protection layer and an insulating layer 4041b that covers the peripheral portion (including the side surface) of the oxide semiconductor layer. Similarly the thin film transistor 4010 is formed with an insulating layer 4042a that functions as a channel protection layer and an insulating layer 4042b that covers the peripheral portion (including the side surface) of the oxide semiconductor layer. The insulating layers 4041b and 4042b, which are oxide insulating layers that cover the peripheral portion (including the side surface) of the oxide semiconductor layer, can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer or the capacitor wiring layer) formed above or around it, and can reduce the parasitic capacitance. The insulating layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the surface of the thin film transistor is covered with an insulating layer 4021 that functions as a planarizing insulating film to reduce the unevenness. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1.

[0251] The insulating layers 4041a, 4041b, 4042a, and 4042b, which are oxide insulating layers that cover the peripheral portion (including the side surface) of the oxide semiconductor layer, can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer or the capacitor wiring layer) formed above or around it, and can reduce the parasitic capacitance. The insulating layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the surface of the thin film transistor is covered with an insulating layer 4021 that functions as a planarizing insulating film to reduce the unevenness. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. 042b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer or the capacitor wiring layer) formed above or around it, and can reduce the parasitic capacitance. The insulating layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the surface of the thin film transistor is covered with an insulating layer 4021 that functions as a planarizing insulating film to reduce the unevenness. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. 042b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer or the capacitor wiring layer) formed above or around it, and can reduce the parasitic capacitance. The insulating layers 4041a, 4041b, 4042a, and 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the surface of the thin film transistor is covered with an insulating layer 4021 that functions as a planarizing insulating film to reduce the unevenness. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. 41a, 4041b, 4042a, 4042b may be formed of the same materials and by the same method as the oxide insulating layers 426a and 426b shown in Embodiment 1. Further, the surface of the thin film transistor is covered with an insulating layer 4021 that functions as a planarizing insulating film to reduce the unevenness. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. 6a, 426b. Further, the surface of the thin film transistor is covered with an insulating layer 4021 that functions as a planarizing insulating film to reduce the unevenness. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. The surface of the thin film transistor is covered with an insulating layer 4021 that functions as a planarizing insulating film to reduce the unevenness. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1. Here, as the insulating layers 4041a, 4041b, 4042a, and 4042b, a silicon oxide film is formed by sputtering using Embodiment 1.

[0252] An insulating layer 4020 is also formed on the insulating layers 4041a, 4041b, 4042a, and 4042b. The insulating layer 4020 may be formed by laminating the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1 with the same materials and by the same method. Although shown as a single layer in Fig. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here is a silicon oxide film and a silicon nitride film are laminated by sputtering as the insulating layer 4020. 020 may be formed by laminating the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1 with the same materials and by the same method. Although shown as a single layer in Fig. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here 020 may be formed by laminating the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1 with the same materials and by the same method. Although shown as a single layer in Fig. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here is a silicon oxide film and a silicon nitride film are laminated by sputtering as the insulating layer 4020. is a silicon oxide film and a silicon nitride film are laminated by sputtering as the insulating layer 4020.​

[0253] Also, an insulating layer 4021 is formed as a planarization insulating film. As the insulating layer 4021, it may be formed by the same materials and methods as the planarization insulating layer 404 shown in Embodiment 1, and polyimide, acrylic resin, benzocyclobutene-based resin, polyamide, epoxy resin, etc., heat-resistant organic materials can be used. In addition to the above organic materials, low dielectric constant materials (low -k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass) etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

[0254] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group.

[0255] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. By combining the baking process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0256] The pixel electrode layer 4030 and the counter electrode layer 4031 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0257] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0258] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0259] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0260] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0261] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0262] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0263] FIG. 19 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0264] FIG. 19 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0265] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. Alignment) mode, PVA (Patterned Vertical Alig nment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, etc. can be used.

[0266] Through the above steps, a highly reliable liquid crystal display panel can be fabricated as a semiconductor device. can be fabricated.

[0267] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0268] (Embodiment 10) An example of an electronic paper is shown as one form of the semiconductor device.

[0269] An electronic paper that drives electronic ink using an element electrically connected to a switching element may be used. The electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and light. An electronic paper that drives electronic ink using an element electrically connected to a switching element may be used. The electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and light. An electronic paper that drives electronic ink using an element electrically connected to a switching element may be used. The electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and light. has the advantage of being able to be made thin and light.

[0270] Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dissolved in a solvent or solute. Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dissolved in a solvent or solute. They are dispersed plurally, and by applying an electric field to the microcapsules, the particles in the micro capsules are moved in opposite directions to each other, and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0271] In this way, the electrophoretic display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0272] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is also possible by using color filters or particles having dyes.

[0273] Also, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1, 2, 5, and 6 can be used.

[0274] Note that the first particle and the second particle in the microcapsule may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0275] ​​​​​​​Figure 18 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiment 1. The thin film transistor can be fabricated in the same manner as the oxide semiconductor layer, and is highly reliable. The thin film transistors shown in the second, fifth and sixth embodiments may also be used as the thin film transistor 581 of this embodiment. It can also be applied.

[0276] The electronic paper in Figure 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0277] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The first electrode layer 587 and the insulating layer 585 are formed as a source electrode layer or a drain electrode layer. The first electrode layer 587 and the substrate 596 are in contact with each other through the opening and are electrically connected. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided that includes a cavity 594 that is filled with a liquid, The area around the pixel 589 is filled with a filler 595 such as resin. The second electrode layer 588 corresponds to a thin film transistor. It is electrically connected to a common potential line provided on the same substrate as the transistor 581. The second electrode layer 588 and the common electrode layer 589 are connected to each other via conductive particles disposed between the pair of substrates. The position line can be electrically connected.

[0278] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0279] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0280] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0281] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. This is shown using a light-emitting device that utilizes electroluminescence. Electroluminescence Light-emitting devices that utilize electroluminescence are classified depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL device, and the latter is called an inorganic EL device.

[0282] In an organic EL device, when a voltage is applied to the light-emitting device, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting device is called a current-excited type light-emitting device. and emits light when the excited state returns to the ground state. From such a mechanism, such a light-emitting device is called a current-excited type light-emitting device.

[0283] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. A dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. A thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL device is used as the light-emitting device for explanation.

[0284] FIG. 12 is a diagram showing an example of a pixel configuration to which digital time-division driving can be applied as an example of a semiconductor device.

[0285] The configuration and operation of a pixel to which digital time-division driving can be applied will be described. Here, ​​​​An example is shown in which one pixel uses an n-channel transistor that uses an oxide semiconductor layer for a channel formation region. Two of them are used.

[0286] Pixel 6400 has a switching transistor 6401, a light-emitting element driving transistor 6 402, a light-emitting element 6404, and a capacitor element 6403. The switching transistor 6401 has its gate connected to the scanning line 6406, and a first electrode (one of the source electrode and the drain electrode) is connected to the signal line 6405, and a second electrode (the other of the source electrode and the drain electrode is connected to the gate of the light-emitting element driving transistor 6402. The light-emitting element driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitor element 6403 , a first electrode connected to the power supply line 6407, and a second electrode connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0287] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404 . Note that the low power supply potential is a potential that satisfies the low power supply potential < high power supply potential with respect to the high power supply potential set on the power supply line 6407, and examples of the low power supply potential may include GND, 0V, etc. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 to emit light from the light-emitting element 6404. Therefore, the potential difference between the high power supply potential and the low power supply potential is set so as to be equal to or higher than the forward threshold voltage of the light-emitting element 6404. Each potential is set accordingly.

[0288] Note that the capacitance element 6403 can be used as a substitute for the gate capacitance of the transistor 6402 for driving the light-emitting element. It is also possible to omit it. Regarding the gate capacitance of the transistor 6402 for driving the light-emitting element a capacitance may be formed between the channel region and the gate electrode.

[0289] Here, in the case of the voltage input voltage drive method, the gate of the transistor 6402 for driving the light-emitting element is input with a video signal that causes the transistor 6402 for driving the light-emitting element to be either fully on or off. That is, the driving transistor 6402 operates in the linear region. Since the transistor 6402 for driving the light-emitting element operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the transistor 6402 for driving the light-emitting element. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the transistor 6402 for driving the light-emitting element) is applied to the signal line 6405.

[0290]

[0291] Also, when performing analog gradation driving instead of digital time gradation driving, by changing the input of the signal, the same pixel configuration as in FIG. 12 can be used.

[0291] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light-emitting element 6404 + the Vth of the transistor 6402 for driving the light-emitting element is applied to the gate of the transistor 6402 for driving the light-emitting element. The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. By inputting a video signal that causes the transistor 6402 for driving the light-emitting element to operate in the saturation region, current can be made to flow through the light-emitting element 6404. In order to operate the transistor 6402 for driving the light-emitting element in the saturation region, the power supply line 6 The potential of the transistor 407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal flows to the light emitting element 6404, Analog gray scale driving is possible.

[0292] Note that the pixel configuration shown in Fig. 12 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0293] Next, the configuration of the light emitting element will be described with reference to FIG. 13. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 13(A), (B), and (C). The TFTs 7001, 7011, and 7021, which are driving TFTs used in semiconductor devices, are actually The thin film transistor can be fabricated in the same manner as in the first embodiment, and has high reliability including an oxide semiconductor layer. The thin film transistors shown in the second, fifth and sixth embodiments are also referred to as TF It can also be applied as T7001, 7011, 7021.

[0294] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0295] A light emitting element with a top emission structure will be described with reference to FIG.

[0296] Figure 13(A) shows a cross-sectional view of a pixel in the case where the TFT 7001, which is a TFT for driving a light-emitting element, is of the n-type and the light emitted from the light-emitting element 700 2 escapes to the anode 7005 side. In Figure 13(A ), the cathode 7003 of the light-emitting element 7002 and the driving TFT 7001 are electrically connected through the contact holes formed in the planarization insulating layer 7007, the protective insulating layer 7000, and the insulating layer 7006. A partition wall 7009 is provided on the contact hole, and the light-emitting layer 7004 and the anode 7005 are sequentially laminated on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film with a low work function and capable of reflecting light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7004 can be either composed of a single layer or configured to have a plurality of layers laminated. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. Note that it is not necessary to provide all of these layers . The anode 7005 is formed using a conductive material having light-transmitting properties, such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc. A light-transmitting conductive film may be used . The region sandwiching the light-emitting layer 7004 between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Figure 13(A), the light emitted from the light-emitting element 7002 is emitted to the anode 7005 side as indicated by the arrow . . . . . . .

[0297] . . .

[0298] Next, the light-emitting element with a bottom emission structure will be described with reference to FIG. 13(B). For driving the light-emitting element FIG. 13(B) shows a cross-sectional view of a pixel in the case where the TFT 7011 is of the n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side In FIG. 13(B), the cathode 7013 of the light-emitting element 7012 is formed on a light-transmissive conductive film 7017 that is electrically connected to the TFT 7011 for driving the light-emitting element and the light-emitting layer 7014 and the anode 7015 are sequentially stacked on the cathode 7013 If the anode 7015 has light-transmitting properties, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode The cathode 7013 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of FIG. 13(A). However, the film thickness should be such that light can pass through it (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013 And the light-emitting layer 7014 may be composed of a single layer or multiple stacked layers, similar to the case of FIG. 13(A). The anode 7015 does not necessarily need to transmit light, but it can be formed using a light-transmissive conductive material, similar to the case of FIG. 13(A). And the shielding film 7016 can be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin with a black pigment added can also be used The region sandwiched by the cathode 7013 and the anode 7015 and containing the light-emitting layer 7014 corresponds to the light-emitting element 7012 In the case of the pixel shown in FIG. 13(B), the light emitted from the light-emitting element 7012 is not necessarily required to pass through, but can be formed using a light-transmissive conductive material, similar to the case of FIG. 13(A). And the shielding film 7016 can be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin with a black pigment added can also be used[[ID=3Q]] For example, a resin with a black pigment added can also be used

[0299] The region sandwiched by the cathode 7013 and the anode 7015 with the light-emitting layer 7014 in between corresponds to the light-emitting element 7012 In the case of the pixel shown in FIG. 13(B), the light emitted from the light-emitting element 7012 As shown by the arrow, it is injected toward the cathode 7013 side. In FIG. 13(B), an example is shown in which a conductive film having translucency is used as the gate electrode layer, and the light emitted from the light-emitting element 7012 passes through the gate electrode layer and is emitted.

[0300] Next, the light-emitting element having a double-sided emission structure will be described with reference to FIG. 13(C). In FIG. 13(C) , a cathode 7023 of a light-emitting element 7022 is formed on a translucent conductive film 702 7 that is electrically connected to the TFT 7021 for driving the light-emitting element. A light-emitting layer 7 024 and an anode 7025 are sequentially laminated on the cathode 7023. The cathode 7023 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of FIG. 13(A). However, its film thickness should be such that light can pass through. For example, Al having a film thickness of 20 nm can be used as the cathode 702 3. And the light-emitting layer 7024 can be composed of a single layer or a plurality of layers laminated, either way, similar to the case of FIG. 13(A). The anode 7025 can be formed using a translucent conductive material that transmits light, similar to the case of FIG. 13(A).

[0301] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in FIG. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0302] Here, although the organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0303] Note that although an example in which a thin film transistor (TFT for driving a light emitting element) that controls driving of the light emitting element and the light emitting element are electrically connected has been shown, a configuration in which a current control TFT is connected between the driving TFT and the light emitting element may also be used. However, a configuration in which a current control TFT is connected between the driving TFT and the light emitting element may also be used. Note that the semiconductor device is not limited to the configuration shown in FIG. 13, and various modifications based on the technical idea disclosed in this specification are possible.

[0304] Note that the semiconductor device is not limited to the configuration shown in FIG. 13, and various modifications based on the technical idea disclosed in this specification are possible. Note that the semiconductor device is not limited to the configuration shown in FIG. 13, and various modifications based on the technical idea disclosed in this specification are possible.

[0305] Next, the appearance and cross section of a light emitting display panel (also referred to as a light emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 11. FIG. 11(A) is a plan view of a panel in which thin film transistors and light emitting elements formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 11(B) corresponds to a cross-sectional view taken along line H-I in FIG. 11(A). Next, the appearance and cross section of a light emitting display panel (also referred to as a light emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 11. FIG. 11(A) is a plan view of a panel in which thin film transistors and light emitting elements formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 11(B) corresponds to a cross-sectional view taken along line H-I in FIG. 11(A). Next, the appearance and cross section of a light emitting display panel (also referred to as a light emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 11. FIG. 11(A) is a plan view of a panel in which thin film transistors and light emitting elements formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 11(B) corresponds to a cross-sectional view taken along line H-I in FIG. 11(A). Next, the appearance and cross section of a light emitting display panel (also referred to as a light emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 11. FIG. 11(A) is a plan view of a panel in which thin film transistors and light emitting elements formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 11(B) corresponds to a cross-sectional view taken along line H-I in FIG. 11(A).

[0306] A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on a first substrate 4501. Also, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on a first substrate 4501. Also, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on a first substrate 4501. Also, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on a first substrate 4501. Also, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air. Therefore, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) so as not to be exposed to the outside air.

[0307] Also, the pixel portion 4502, the signal line driving circuits 4503a, 4 503b, and the scanning line driving circuits 4504a, 4504b provided on the first substrate 4501 have a plurality of thin film transistors and, in FIG. 11(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are illustrated. The thin film transistors 4509 and 4510 can apply highly reliable thin film transistors including the oxide semiconductor layer shown in Embodiments 1, 2, 5, and 6. As the thin film transistor 4509 for the driving circuit, the thin film transistors 26

[0308] 0, 270 shown in Embodiments 1, 2, 5, and 6 can be used, and as the thin film transistor 4510 for the pixel, the thin film transistors 420, 4 48, 220, 280, 290 can be used. In the present embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors. 0, 270 shown in Embodiments 1, 2, 5, and 6 can be used, and as the thin film transistor 4510 for the pixel, the thin film transistors 420, 4 48, 220, 280, 290 can be used. In the present embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors. On the insulating layer 4544, a conductive layer 4540 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driving circuit. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the thin film transistor 4509 before and after the BT test can be reduced. Also, the potential of the conductive layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4

[0309] On the insulating layer 4544, a conductive layer 4540 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driving circuit. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the thin film transistor 4509 before and after the BT test can be reduced. Also, the potential of the conductive layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4 540 may be GND, 0V, or in a floating state. 540 may be GND, 0V, or in a floating state. 540 may be GND, 0V, or in a floating state. 540 may be GND, 0V, or in a floating state. 540 may be GND, 0V, or in a floating state. 540 may be GND, 0V, or in a floating state.

[0310] The thin film transistor 4509 is formed with an insulating layer 4541a that functions as a channel protection layer and an insulating layer 4541b that covers the peripheral portion (including the side surface) of the oxide semiconductor layer. Similarly, the thin film transistor 4510 is formed with an insulating layer 4542a that functions as a channel protection layer and an insulating layer 4542b that covers the peripheral portion (including the side surface) of the oxide semiconductor layer. The insulating layers 4541b and 4542b, which are oxide insulating layers that cover the peripheral portion (including the side surface) of the oxide semiconductor layer, can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1.

[0311] Moreover, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 may be formed by the same materials and methods as the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1. Although it is shown as a single layer in FIG. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here, as the insulating layer 4543, a silicon oxide film is formed by sputtering and a silicon nitride film is formed by sputtering and laminated. The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1. The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1. The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1. The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1. The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1. The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1. The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1.

[0312] The insulating layers 4541a, 4541b, 4542a, and 4542b can increase the distance between the gate electrode layer and the wiring layer (such as the source wiring layer and the capacitor wiring layer) formed above or around it, thereby reducing the parasitic capacitance. The insulating layers 4541a, 4541b, 4542a, and 4542b may be formed by the same materials and methods as the oxide insulating layers 426a and 426b shown in Embodiment 1. Also, it is configured to be covered with an insulating layer 4543 that functions as a planarization insulating film to reduce the surface irregularities of the thin film transistor. Here, a silicon oxide film is formed by sputtering as the insulating layers 4541a, 4541b, 4542a, and 4542b using Embodiment 1. Moreover, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 may be formed by the same materials and methods as the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1. Although it is shown as a single layer in FIG. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here, as the insulating layer 4543, a silicon oxide film is formed by sputtering and a silicon nitride film is formed by sputtering and laminated. Moreover, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 may be formed by the same materials and methods as the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1. Although it is shown as a single layer in FIG. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here, as the insulating layer 4543, a silicon oxide film is formed by sputtering and a silicon nitride film is formed by sputtering and laminated. Moreover, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 may be formed by the same materials and methods as the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1. Although it is shown as a single layer in FIG. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here, as the insulating layer 4543, a silicon oxide film is formed by sputtering and a silicon nitride film is formed by sputtering and laminated. Moreover, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 may be formed by the same materials and methods as the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1. Although it is shown as a single layer in FIG. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here, as the insulating layer 4543, a silicon oxide film is formed by sputtering and a silicon nitride film is formed by sputtering and laminated. Moreover, an insulating layer 4543 is formed on the insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 may be formed by the same materials and methods as the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1. Although it is shown as a single layer in FIG. 10(B), it is a laminate of the insulating layer 428 and the protective insulating layer 403 made of a material different from that of the insulating layer 428. Here, as the insulating layer 4543, a silicon oxide film is formed by sputtering and a silicon nitride film is formed by sputtering and laminated.

[0313] Also, an insulating layer 4544 is formed as a planarization insulating film. As the insulating layer 4544, it may be formed by the same material and method as the planarization insulating layer 404 shown in Embodiment Form 1. Here, acrylic is used as the insulating layer 4544.

[0314] In this embodiment, a configuration may be adopted in which a plurality of thin film transistors in the pixel portion are collectively surrounded by a nitride insulating film. Using a nitride insulating film for the insulating layer 4543 and the gate insulating layer, as shown in FIG. 11 it is sufficient to provide a region where the insulating layer 4543 and the gate insulating layer are in contact with each other so as to surround at least the periphery of the pixel portion of the active matrix substrate. With such a configuration it is possible to prevent the intrusion of moisture from the outside. Also, even after the device is completed as a semiconductor device, for example, a display device, it is possible to prevent the intrusion of moisture from the outside for a long period of time, and the long-term reliability of the device can be improved. Moreover, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. The configuration of the light-emitting element 4511 can be appropriately changed

[0315] in accordance with the direction of light extracted from the light-emitting element 4511 and the like. The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and to form the side wall of the opening so as to be an inclined surface formed with a continuous curvature. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. can be changed as appropriate.

[0316] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and to form the side wall of the opening so as to be an inclined surface formed with a continuous curvature.

[0317] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0318] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0319] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0320] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0321] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0322] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 must be light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0323] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. Fats or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler if necessary.

[0324] Also, if necessary, a polarizing plate, or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or other optical films may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection.

[0325] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b may be implemented by drive circuits formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or a part thereof may be separately formed and implemented, and is not limited to the configuration of FIG. 11.

[0326] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.

[0327] This embodiment can be implemented in appropriate combination with the configurations described in Embodiments 1 to 4 and 6 to 8.

[0328] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as an electronic paper. The electronic paper can be used in electronic devices in any field as long as it can display information.​​​​​ For example, it can be applied to electronic books (e-books), posters, in-vehicle advertisements in vehicles such as trains, and displays on various cards such as credit cards, etc. using electronic paper. An example of an electronic device is shown in FIG. 20.

[0329] FIG. 20 shows an example of an e-book 2700. For example, the e-book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can perform an opening and closing operation with the shaft portion 2711 as an axis. With such a configuration, it becomes possible to perform operations similar to those of a paper book.

[0330] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen, or may be configured to display different screens. In the case of a configuration for displaying different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 20), and an image can be displayed on the left display unit (display unit 2707 in FIG. 20).

[0331] Also, in FIG. 20, an example in which the housing 2701 is provided with an operation unit etc. is shown. For example, in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, etc. are provided. The operation keys 2723 can be used to turn the page. In addition, it may be configured to be provided with a key board, a pointing device, etc. on the same surface as the display unit of the housing. Also, on the back or side surface of the housing, external connection terminals (earphone terminals, USB terminals, or an AC adapter and a USB cable etc.) can be provided. a configuration including terminals connectable to various cables such as cables, a recording medium insertion part, etc. is also possible. Further, the electronic book 2700 may have a configuration with a function as an electronic dictionary as well.

[0332] Also, the electronic book 2700 may have a configuration capable of wirelessly transmitting and receiving information. By wireless means, it is possible to purchase and download desired book data, etc. from an electronic book server as well.

[0333] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of the electronic devices include, for example, a television device (also called a TV or a television receiver), a monitor for a computer, a digital camera, a digital video camera , a digital photo frame, a mobile phone (also called a mobile phone or a mobile phone device), a portable game machine, a portable information terminal, an audio playback device, a large game machine such as a pachinko machine, etc. are included.

[0334] FIG. 21(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. An image can be displayed by the display unit 9603. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0335] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control unit 9610. Channel and volume operations can be performed by operation keys 9609 provided in the remote control unit 9610, and are displayed on the display unit 9603 The video can be operated. Further, the remote control operation unit 9610 may be configured to include a display unit 9607 for displaying information output from the remote control operation unit 9610.

[0336] Note that the television device 9600 is configured to include a receiver, a modem, and the like. The receiver can receive more general television broadcasts, and can be connected to a communication network by wire or wirelessly via a modem, enabling one-way (sender to receiver) or two-way (between the sender and the receiver, or between receivers, etc.) information communication. (between the sender and the receiver, or between receivers, etc.) information communication.

[0337] FIG. 21(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, by displaying image data taken with a digital camera or the like, it can function in the same way as a normal photo stand.

[0338] Note that the digital photo frame 9700 is configured to include an operation unit, external connection terminals (terminals connectable to various cables such as USB cables, USB cables, etc.), a recording medium insertion unit, and the like. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or the back surface to improve the design. For example, by inserting a memory storing image data taken with a digital camera into the recording medium insertion unit of the digital photo frame, the image data can be captured, and the captured image data can be displayed on the display unit 9703.

[0339] Further, the digital photo frame 9700 may be configured to be able to transmit and receive information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0340] FIG. 22(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 22(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 22(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0341] FIG. 22(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an input port, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above-mentioned ones, and any configuration with at least the semiconductor device disclosed in this specification is acceptable. , and other accessory equipment can be appropriately provided.

[0342] Figure 23(A) is a perspective view showing an example of a portable computer.

[0343] The portable computer in Figure 23(A) can be in a state where the upper housing 9301 having a display unit 9303 and the lower housing 9302 having a keyboard 9304 are stacked with the hinge unit connecting them in a closed state, which is convenient for carrying. When the user inputs via the keyboard, the hinge unit can be opened, and the input operation can be performed while looking at the display unit 9303. The upper housing 9301 having a display unit 9303 and the lower housing 9302 having a keyboard 9304 can be stacked with the hinge unit connecting them in a closed state, which is convenient for carrying. When the user inputs via the keyboard, the hinge unit can be opened, and the input operation can be performed while looking at the display unit 9303. The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted. The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted. The upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, and a wide display screen can be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. The retractable display unit 9307 can also be a touch input panel.

[0344] The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted. The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted. The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted. The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted. The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted. The lower housing 9302 has a pointing device 9306 for performing input operations in addition to the keyboard 9304. If the display unit 9303 is a touch input panel, the input operation can also be performed by touching a part of the display unit. The lower housing 9302 has a computing function unit such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, can be inserted.

[0345] The upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, and a wide display screen can be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. The retractable display unit 9307 can also be a touch input panel. The upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, and a wide display screen can be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. The retractable display unit 9307 can also be a touch input panel. The upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, and a wide display screen can be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. The retractable display unit 9307 can also be a touch input panel. If it is a panel, an input operation can also be performed by touching a part of the retractable display unit 9307. This is possible.

[0346] The display unit 9303 or the retractable display unit 9307 uses a video display device such as a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. This is also possible.

[0347] In addition, the portable computer in Fig. 23(A) is configured with a receiver and the like, and can receive a television broadcast and display the video on the display unit. Also, with the hinge unit connecting the upper housing 9301 and the lower housing 9302 in the closed state, the display unit 9307 can be slid to expose the entire screen, and the screen angle can be adjusted so that the user can watch the television broadcast. In this case, with the hinge unit in the open state, the display unit 9303 is not displayed, and only the circuit for displaying only the television broadcast is activated, so that the power consumption can be minimized, which is useful for a portable computer with a limited battery capacity. This is also possible. This is also possible. In this case, with the hinge unit in the open state, the display unit 9303 is not displayed, and only the activation of the circuit for displaying only the television broadcast is performed, so that the minimum power consumption can be achieved, which is useful for a portable computer with a limited battery capacity. This is also possible. This is also possible.

[0348] Fig. 23(B) is a perspective view showing an example of a mobile phone that can be worn on the user's wrist like a wristwatch. This is also possible.

[0349] This mobile phone includes a communication device having at least a telephone function, a main body having a battery, a band portion 92, a fixing portion 92, a display portion 92, a speaker 92, and a microphone 92. This is also possible. This is also possible. This is also possible.

[0350] In addition, the main body has an operation switch 9203, a power input switch, and a display switching switch. In addition to the shutter button and the imaging start instruction switch, for example, when a button is pressed, a program for the Internet can be activated, and each function can be associated with each other.

[0351] The input operation of this mobile phone is performed by touching the display unit 9201 with a finger, an input pen, etc., or by operating the operation switch 9203, or by voice input to the microphone 9208. In FIG. 23(B), the display button 9202 displayed on the display unit 9201 is illustrated, and input can be performed by touching it with a finger or the like.

[0352] In addition, the main body has a camera unit 9206 having an imaging stage that converts a subject image formed through a photographing lens into an electronic image signal. Note that the camera unit may not be provided particularly.

[0353] In addition, the mobile phone shown in FIG. 23(B) is configured to include a TV broadcast receiver, etc., and can receive TV broadcasts and display the video on the display unit 9201. Furthermore, as a configuration including a storage device such as a memory, etc., it can record TV broadcasts in the memory. Also, the mobile phone shown in FIG. 23( B) may have a function of collecting position information such as GPS.

[0354] The display unit 9201 uses a video display device such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 23(B) is small and lightweight and thus has a limited battery capacity. Therefore, it is preferable to use a panel that can be driven with low power consumption for the display device used for the display unit 9201.

[0355] Note that in FIG. 23(B), an electronic device of the type worn on the "arm" is illustrated, but it is not particularly limited It suffices if it has a shape that can be carried around.

[0356] (Embodiment 14) In this embodiment, as one form of the semiconductor device, an example of a display device having the thin film transistors shown in Embodiments 1, 2, 5, and 6 will be described with reference to FIGS. 24 to 35. This embodiment will describe an example of a liquid crystal display device using a liquid crystal element as a display element with reference to FIGS. 24 to 35. The TFTs 628 and 629 used in the liquid crystal display device of FIGS. 24 to 35 can apply the thin film transistors shown in Embodiments 1, 2, 5, and 6, and are thin film transistors with high electrical characteristics and reliability that can be manufactured in the same manner in the processes shown in Embodiments 1, 2, 5, and 6. The TFT 628 has a channel protection layer 608, and the TFT 629 has a channel protection layer 611, and is a bottom gate type thin film transistor having a semiconductor layer film as a channel formation region. 1, 2, 5, and 6, and can be manufactured with the same electrical characteristics and reliability as those in the processes shown in Embodiments 1, 2, 5, and 6. The TFT 628 has a channel protection layer 608, and the TFT 629 has a channel protection layer 611, and is a bottom gate type thin film transistor having a semiconductor layer film as a channel formation region. FT628 has a channel protection layer 608, and TFT629 has a channel protection layer 611, respectively, and is a bottom gate type thin film transistor having a semiconductor layer film as a channel formation region.

[0357] First, a VA (Vertical Alignment) type liquid crystal display device will be described The VA type liquid crystal display device is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is a method in which liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied. In this embodiment, in particular, pixels (picture elements) are divided into several regions (sub-pixels), and the molecules are arranged so as to be tilted in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described. design will be described.

[0358] FIGS. 25 and 26 show a pixel electrode and a counter electrode, respectively. Note that FIG. 25 shows a pixel It is a plan view of the substrate side where the electrode is formed, and shows the cross-sectional structure corresponding to the cutting line E-F shown in the figure. It is represented in Fig. 24. Fig. 26 is a plan view of the substrate side where the counter electrode is formed. In the following explanation, these figures will be referred to for explanation.

[0359] Fig. 24 shows the substrate 600 on which the TFT 628, the pixel electrode 624 connected thereto, and the holding capacitor portion 630 are formed superposed with the counter substrate 601 on which the counter electrode 640 and the like are formed, showing the state where the liquid crystal is injected.

[0360] Although not shown, at the position where the spacer is formed on the counter substrate 601, the first coloring film, the second coloring film, the third coloring film, and the counter electrode 640 are formed. With this structure, the height of the protrusion 644 for controlling the alignment of the liquid crystal is made different from that of the spacer. On the pixel electrode 624 an alignment film 648 is formed, and similarly an alignment film ⑥46 is formed on the counter electrode 640. A liquid crystal layer 650 is formed therebetween. The spacer may be formed as a columnar spacer or beads spacers may be dispersed. When the spacer is light-transmissive [[ID=2�]]

[0361] it may be formed on the pixel electrode 624 formed on the substrate 600. On the substrate 600, the TFT 628, the pixel electrode 624 connected thereto, and the holding capacitor portion

[0362] 630 are formed. The pixel electrode 624 is connected to the wiring 618 through contact holes 623 that penetrate through the insulating film 620 covering the TFT 628, the wiring 616, and the holding capacitor portion 630, and the third insulating film 622 covering the insulating film 620 respectively. The insulating film 620 is a laminate of an insulating layer and a protective insulating layer. The insulating layer in contact with the semiconductor layer is formed as a silicon oxide film by sputtering, and the protective insulating layer thereon is... ... ... is... Use a silicon nitride film formed by sputtering. In FIG. 24, for simplicity of illustration, the laminated insulating film 62 0 is shown as a single layer. The TFT 628 can be appropriately used as the thin film transistor shown in Embodiments 1, 2, 5, and 6. Further, the holding capacitance section 630 is composed of a first capacitance wiring 604 formed simultaneously with the gate wiring 602 of the TFT 628, a gate insulating film 606, and a second capacitance wiring 617 formed simultaneously with the wirings 61 6, 618. The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap each other to form a liquid crystal element.

[0363] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap each other to form a liquid crystal element. is formed.

[0364] FIG. 25 shows the structure on the substrate 600. The pixel electrode 624 is formed using the material shown in Embodiment 1. A slit 625 is provided in the pixel electrode 624. The slit 625 is for controlling the alignment of the liquid crystal. is for controlling the alignment of the liquid crystal.

[0365] The TFT 629 shown in FIG. 25, the pixel electrode 626 connected thereto, and the holding capacitance section 631 can be formed in the same manner as the TFT 628, the pixel electrode 624, and the holding capacitance section 630, respectively. The TFT 628 and the TFT 629 are both connected to the wiring 616. The pixel (pixel) of this liquid crystal display panel is composed of the pixel electrode 624 and the pixel electrode 626. The pixel electrodes 624 and 626 are sub-pixels. 624 and 626 are sub-pixels.

[0366] FIG. 26 shows the structure on the counter substrate side. The counter electrode 640 is formed on the light-shielding film 632. The counter electrode 640 is preferably formed using the same material as the pixel electrode 624. Protrusions 644 for controlling the alignment of the liquid crystal are formed on the counter electrode 640. Protrusions 644 for controlling the alignment of the liquid crystal are formed on the counter electrode 640.

[0367] The equivalent circuit of this pixel structure is shown in FIG. 27. Both TFT628 and TFT629 are connected to the gate wiring 602 and the wiring 616. In this case, by making the potentials of the capacitor wiring 604 and the capacitor wiring 605 different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, by individually controlling the potentials of the capacitor wiring 604 and the capacitor wiring 605, the orientation of the liquid crystal is precisely controlled to widen the viewing angle. When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the counter substrate 601 side so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, so that the direction in which the liquid crystal is oriented is made different depending on the location. That is, it is made into a multi-domain to widen the viewing angle of the liquid crystal display panel. Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. FIGS. 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 29 is a plan view of the substrate 600, and the cross-sectional structure corresponding to the cut line Y-Z shown in the figure is shown in FIG. 28. In the following description, both of these figures will be referred to for explanation. This pixel structure has a plurality of pixel electrodes in one pixel, and each pixel electrode is followed by a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed with a multi-domain, the signals applied to the individual pixel electrodes have a configuration that is independently controlled.

[0368] When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the counter substrate 601 side so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, so that the direction in which the liquid crystal is oriented is made different depending on the location. That is, it is made into a multi-domain to widen the viewing angle of the liquid crystal display panel. When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the counter substrate 601 side so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, so that the direction in which the liquid crystal is oriented is made different depending on the location. That is, it is made into a multi-domain to widen the viewing angle of the liquid crystal display panel. When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the counter substrate 601 side so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, so that the direction in which the liquid crystal is oriented is made different depending on the location. That is, it is made into a multi-domain to widen the viewing angle of the liquid crystal display panel. When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the counter substrate 601 side so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, so that the direction in which the liquid crystal is oriented is made different depending on the location. That is, it is made into a multi-domain to widen the viewing angle of the liquid crystal display panel. When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (oblique electric field) occurs in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the counter substrate 601 side so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, so that the direction in which the liquid crystal is oriented is made different depending on the location. That is, it is made into a multi-domain to widen the viewing angle of the liquid crystal display panel.

[0369] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31.

[0370] FIGS. 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 29 is a plan view of the substrate 600, and the cross-sectional structure corresponding to the cut line Y-Z shown in the figure is shown in FIG. 28. In the following description, both of these figures will be referred to for explanation. FIGS. 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 29 is a plan view of the substrate 600, and the cross-sectional structure corresponding to the cut line Y-Z shown in the figure is shown in FIG. 28. In the following description, both of these figures will be referred to for explanation. In the following description, both of these figures will be referred to for explanation.

[0371] This pixel structure has a plurality of pixel electrodes in one pixel, and each pixel electrode is followed by a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed with a multi-domain, the signals applied to the individual pixel electrodes have a configuration that is independently controlled. This pixel structure has a plurality of pixel electrodes in one pixel, and each pixel electrode is followed by a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed with a multi-domain, the signals applied to the individual pixel electrodes have a configuration that is independently controlled. This pixel structure has a plurality of pixel electrodes in one pixel, and each pixel electrode is followed by a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed with a multi-domain, the signals applied to the individual pixel electrodes have a configuration that is independently controlled. This pixel structure has a plurality of pixel electrodes in one pixel, and each pixel electrode is followed by a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed with a multi-domain, the signals applied to the individual pixel electrodes have a configuration that is independently controlled.

[0372] The pixel electrode 624 is connected to the TFT 628 by the wiring 618 at the contact hole 623. Also, the pixel electrode 626 is connected to the TFT 629 by the wiring 619 at the contact hole 627. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be applied. On the other hand, the wiring 616 that functions as a data line is commonly used by the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 can be appropriately used as the thin film transistors shown in Embodiments 1, 2, 5, and 6. Also, a capacitor wiring 690 is provided. The insulating film 620 is a laminate of an insulating layer and a protective insulating layer. The insulating layer in contact with the semiconductor layer is an oxide silicon film formed by sputtering, and the protective insulating layer thereon is a silicon nitride film formed by sputtering. Note that in FIG. 28, for simplicity, the insulating film 620, which is a laminate, is shown as a single layer.

[0373] The shapes of the pixel electrode 624 and the pixel electrode 626 are different and are separated by the slit 625. The pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. By varying the timing of the voltages applied to the pixel electrode 624 and the pixel electrode 626 by the TFT 628 and the TFT 629, the alignment of the liquid crystal is controlled. The equivalent circuit of this pixel structure is shown in FIG. 31. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. By applying different gate signals to the gate wiring 602 and the gate wiring 603, the operation timings of the TFT 628 and the TFT 629 can be made different.

[0374] On the counter substrate 601, a second color filter 636 and a counter electrode 640 are formed. Also, a planarization film 637 is formed between the second color filter 636 and the counter electrode 640 to prevent the alignment disorder of the liquid crystal. FIG. 30 shows the structure on the counter substrate side. The counter electrode 640 is an electrode that is common among different pixels, but a slit 641 is formed. By arranging this slit 641 and the slit 625 on the pixel electrode 624 and pixel electrode 626 sides to alternately engage with each other, an oblique electric field can be effectively generated to control the alignment of the liquid crystal. As a result, the direction in which the liquid crystal aligns can be made different depending on the location, expanding the viewing angle.

[0375] When the pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap, the first liquid crystal element is formed. Also, when the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 overlap, the second liquid crystal element is formed. Also, it is a multi-domain structure in which the first liquid crystal element and the second liquid crystal element are provided in one pixel.

[0376] Next, a lateral electric field type liquid crystal display device will be described. The lateral electric field method is a method of driving the liquid crystal to perform gradation display by applying an electric field in the horizontal direction to the liquid crystal molecules in the cell. By this method, the viewing angle can be expanded to about 180 degrees. In the following description, a liquid crystal display device adopting the lateral electric field method will be described. FIG. 32 shows a state in which the substrate 600 on which the TFT 628 and the pixel electrode 624 connected thereto are formed and the counter substrate 601 are overlapped and liquid crystal is injected. On the counter substrate 601, a second color filter 636, a planarization film 637, etc. are formed. The pixel electrode is provided on the substrate 600 side.

[0377] Therefore, it is not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601.

[0378] On the substrate 600, a first pixel electrode 607, a capacitance wiring 604 connected to the first pixel electrode 607, and TFTs 628 shown in Embodiments 1, 2, 5, and 6 are formed. The first pixel electrode 607 can be made of the same material as the pixel electrode layer 427 shown in Embodiment 1. Also, the first pixel electrode 607 is formed in a shape partitioned into a substantially pixel shape. Note that a gate insulating film 606 is formed over the first pixel electrode 607 and the capacitance wiring 604.

[0379] Wiring 616 and wiring 618 of the TFT 628 are formed over the gate insulating film 606. Wiring 616 is a data line on which a video signal is loaded in the liquid crystal display panel, and is a wiring extending in one direction. At the same time, it is connected to the source region or the drain region of the TFT 628 and serves as one electrode of the source and the drain. Wiring 618 serves as the other electrode of the source and the drain, and is a wiring connected to the second pixel electrode 624.

[0380] A second insulating film 620 is formed over the wiring 616 and the wiring 618. The insulating film 620 is a laminate of an insulating layer and a protective insulating layer. The insulating layer in contact with the semiconductor layer is formed of a silicon oxide film by sputtering, and the protective insulating layer thereover is formed of a silicon nitride film by sputtering. Note that in FIG. 32, for simplicity, the insulating film 620 which is a laminate is illustrated as a single layer. Also, a second pixel electrode 624 connected to the wiring 618 is formed in a contact hole formed in the insulating film 620. The pixel electrode 624 is formed using the same material as the pixel electrode layer 427 shown in Embodiment 1. ​​​​​​​​​​​​​​​

[0381] In this way, the TFT 628 and the pixel electrode 624 connected thereto are formed on the substrate 600. Note that the holding capacitor is formed between the pixel electrode 607 and the pixel electrode 624.

[0382] FIG. 33 is a plan view showing the configuration of the pixel electrode. The cross-sectional structure corresponding to the cutting line O-P shown in FIG. 33 is shown in FIG. 32. A slit 625 is provided in the pixel electrode 624. The slit 625 is for controlling the alignment of the liquid crystal. In this case, an electric field is generated between the pixel electrode 607 and the pixel electrode 624. A gate insulating film 606 is formed between the pixel electrode 607 and the pixel electrode 624. However, the thickness of the gate insulating film 606 is 50 to 200 nm, which is sufficiently thin compared to the thickness of the liquid crystal layer of 2 to 10 μm. Therefore, an electric field is generated substantially in the direction parallel to the substrate 600 (horizontal direction). The alignment of the liquid crystal is controlled by this electric field. The liquid crystal molecules are rotated horizontally by utilizing the electric field in the direction substantially parallel to this substrate. In this case, since the liquid crystal molecules are horizontal in any state, the influence of contrast depending on the viewing angle is small, and the viewing angle is widened. In addition, since both the pixel electrode 607 and the pixel electrode 624 are light-transmissive electrodes, the aperture ratio can be improved. Next, another example of the horizontal electric field type liquid crystal display device will be described.

[0383] [[ID=This]]

[0384] FIGS. 34 and 35 show the pixel structure of the IPS type liquid crystal display device. FIG. 35 is a plan view, and the cross-sectional structure corresponding to the cutting line V-W shown in the figure is shown in FIG. 34. In the following description, these two figures will be referred to for explanation.

[0385] ​​​​​​​FIG. 34 shows a state where a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed is overlaid with a counter substrate 601 and liquid crystal is injected. On the counter substrate 601, a second coloring film 636, a planarization film 637, etc. are formed. Since the pixel electrode 624 is on the substrate 600 side, it is not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601.

[0386] On the substrate 600, a common potential line 609 and a TFT 62 8 shown in Embodiments 1, 2, 5, and 6 are formed. The common potential line 609 can be formed simultaneously with the gate wiring 602 of the TFT 628.

[0387] The wirings 616 and 618 of the TFT 628 are formed on the gate insulating film 606. The wiring 61 6 is a data line for carrying a video signal in a liquid crystal display panel and is a wiring extending in one direction. At the same time, it is connected to the source region or the drain region of the TFT 628 and becomes one electrode of the source and the drain. The wiring 618 becomes the other electrode of the source and the drain and is a wiring connected to the second pixel electrode 624.

[0388] A second insulating film 620 is formed on the wirings 616 and 618. Further, on the insulating film 620, at a contact hole 623 formed in the insulating film 620, a pixel electrode 624 connected to the wiring 618 is formed. The insulating film 620 is a laminate of an insulating layer and a protective insulating layer. The insulating layer in contact with the semiconductor layer is a silicon oxide film formed by sputtering, and the protective insulating layer thereon is a silicon nitride film formed by sputtering. In the figure, for simplicity, the insulating film 620 which is a laminate is shown as a single layer. The pixel electrode 624 uses the same material as the pixel electrode layer 427 shown in Embodiment 1. ​​​​​​ It is formed by... As shown in FIG. 35, the pixel electrode 624 is formed simultaneously with the common potential line 609. It is formed so that a horizontal electric field is generated with the comb-shaped electrode formed simultaneously. Also, the comb teeth portion of the pixel electrode 624 is formed so as to alternately mesh with the comb-shaped electrode formed simultaneously with the common potential line 609. ... ...

[0389] When an electric field is generated between the potential applied to the pixel electrode 624 and the potential of the common potential line 609, the alignment of the liquid crystal is controlled by this electric field. By utilizing the electric field in a direction substantially parallel to this substrate, the liquid crystal molecules are rotated horizontally. In this case, since the liquid crystal molecules are horizontal in any state, the influence such as contrast depending on the viewing angle is small, and the viewing angle is widened. ... ... ...

[0390] In this way, the TFT 628 and the pixel electrode 624 connected thereto are formed on the substrate 600. The holding capacitor is formed by providing a gate insulating film 606 between the common potential line 609 and the capacitor electrode 615. The capacitor electrode 615 and the pixel electrode 624 are connected via a contact hole 633. ... ... ...

[0391] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device of this embodiment is a highly reliable liquid crystal display device. ...

Explanation of Reference Numerals

[0392] 10 Pulse output circuit 11 First wiring 12 Second wiring 13 Third wiring 14 Fourth wiring 15 Fifth wiring 21 First input terminal 22 Second input terminal 23 Third input terminal 24 Fourth input terminal 25 Fifth input terminal 26 First output terminal 27 Second output terminal 28 Thin film transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power supply line 52 Power supply line 53 Power supply line 61 Period 62 Period 200 Substrate 202 Gate insulating layer 203 Protection insulating layer 204 Planarization insulating layer 205 Common potential line 206 Common electrode layer 207 Oxide semiconductor layer 208 Oxide insulating layer 209 Common potential line 216 Insulating layer 220 Thin film transistor 221 Terminal 222 Terminal 223 Connection electrode layer 225 Conductive layer 226 Electrode layer 227 Pixel electrode layer 230 Capacitance wiring layer 231 Capacitance electrode 236 Metal wiring layer 237 Metal wiring layer 241 Metal wiring layer 242 Metal wiring layer 243 Metal wiring layer 244 Metal wiring layer 250 Capacitor wiring layer 251 Oxide semiconductor layer 254 Source wiring 255 Terminal electrode 256 Source wiring 257 Terminal electrode 260 Thin film transistor 261 Gate electrode layer 263 Channel formation region 264a High-resistance source region 264b High-resistance drain region 264c Region 264d Region 265a Source electrode layer 265b Drain electrode layer 266a Oxide insulating layer 266b Oxide insulating layer 267 Conductive layer 270 Thin film transistor 271 Gate electrode layer 273 Channel formation region 274a High-resistance source region 274b High-resistance drain region 274c Region 274d Region 274e Region 274f Region 275a Source electrode layer 275b Drain electrode layer 276a Oxide insulating layer 276b Oxide insulating layer 277 Conductive layer 280 Thin film transistor 282a First gate insulating layer 282b Second gate insulating layer 282c Gate insulating layer 286b Oxide insulating layer 290 Thin film transistor 292a First gate insulating layer 292b Second gate insulating layer 400 Substrate 402 Gate insulating layer 403 Protection insulating layer 404 Planarization insulating layer 420 Thin film transistor 421a Gate electrode layer 421b Gate electrode layer 422 Oxide semiconductor layer 423 Channel formation region 424a High resistance source region 424b High resistance drain region 424c Region 424d Region 424e High resistance source region 424f High resistance drain region 425a Source electrode layer 425b Drain electrode layer 426a Oxide insulating layer 426b Oxide insulating layer 427 Pixel electrode layer 428 Insulating layer 429 Oxide semiconductor layer 441 Contact hole 442 Oxide semiconductor layer 448 Thin film transistor 580 Substrate 581 Thin film transistor 583 Insulating film 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a Black region 590b White region 594 Cavity 595 Filling material 596 Substrate 600 Substrate 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating film 607 Electrode layer 608 Channel protection layer 609 Common potential line 611 Channel protection layer 615 Capacitance electrode 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 Insulating film 621 Insulating film 622 Insulating film 623 Contact hole 624 Pixel electrode 625 Slit 626 Pixel electrode [[ID=T30]]627 Contact hole 628 TFT 629 TFT 630 Holding capacitance section 631 Holding capacitance section 632 Light-shielding film 633 Contact hole 636 Coloring film [[ID=4F6]]637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Alignment film 648 Alignment film 650 Liquid crystal layer F651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 2600 TFT substrate 2601 Counter substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Coloring layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring substrate 2610 Cold cathode tube 2611 Reflector [[ID=T90]]2612 Circuit substrate 2613 Diffuser 2700 E-books 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft portion 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel portion 4003 Signal line drive circuit 4004 Scan line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4040 Conductive layer 4041a Insulating layer 4041b Insulating layer 4042a Insulating layer 4042b Insulating layer 4501 Substrate 4502 Pixel portion 4503a, 4503b Signal line drive circuit 4504a, 4504b Scan line drive circuit 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a, 4518b FPC 4519 Anisotropic conductive film 4520 Partition wall 4540 Conductive layer 4541a Insulating layer 4541b Insulating layer 4542a Insulating layer 4542b Insulating layer 4543 Insulating layer 4544 Insulating layer 5300 Substrate 5301 Pixel section 5302 Scanning line drive circuit 5303 Scanning line drive circuit 5304 Signal line drive circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit 5603 Thin film transistor 5604 Wiring 5605 Wiring 6400 Pixel 6401 Switching transistor 6402 Light emitting element driving transistor 6403 Capacitive element 6404 Light emitting element 6405 Signal line 6406 Scanning line 6407 Power supply line 6408 Common electrode 7000 Protective insulating layer 7001 TFT 7002 Light emitting element 7003 Cathode 7004 Light emitting layer 7005 Anode 7006 Insulating layer 7007 Planarizing insulating layer 7009 Partition wall 7011 Light emitting element driving TFT 7012 Light-emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Masking film 7017 Conductive film 7021 TFT for driving light-emitting element 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9201 Display unit 9202 Display button 9203 Operation switch 9204 Band part 9205 Adjustment part 9206 Camera part 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display unit 9304 Keyboard 9305 External connection port 9306 Pointing device 9307 Display unit 9600 Television apparatus 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display unit 9881 Housing 9882 Display unit 9883 Display unit 9884 Speaker part 9885 Input means (operation key) 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Housing 9893 Connecting Part 9900 Slot Machine 9901 Housing 9903 Display Unit

Claims

1. A pixel having a light-emitting element, a first transistor electrically connected to the light-emitting element, and a capacitor element electrically connected to the light-emitting element and the first transistor; A display device having a scanning line driving circuit having a second transistor, The first transistor includes a first oxide semiconductor layer having a channel formation region, a first conductive layer having a function as a gate electrode, and a second conductive layer electrically connected to the pixel electrode of the light-emitting element and having a function as one of a source electrode and a drain electrode. The second transistor includes a second oxide semiconductor layer having a channel formation region, a third conductive layer having a function as a gate electrode, a fourth conductive layer having a function as one of a source electrode and a drain electrode, and a fifth conductive layer having a region overlapping with the second oxide semiconductor layer and having the same material as the pixel electrode. The capacitor element includes a sixth conductive layer electrically connected to the first oxide semiconductor layer and having a function as a first electrode, and a seventh conductive layer having a region located below the sixth conductive layer and having a function as a second electrode. In a cross-sectional view, it has a third oxide semiconductor layer having a region in contact with the lower surface of the sixth conductive layer. The pixel electrode has a region overlapping with the sixth conductive layer, the third oxide semiconductor layer, and the seventh conductive layer. In a cross-sectional view, it has an oxide insulating layer having a region covering the peripheral portion of the first oxide semiconductor layer, a region covering the peripheral portion of the second oxide semiconductor layer, and a region covering the peripheral portion of the third oxide semiconductor layer. In a cross-sectional view, the oxide insulating layer has a region in contact with the upper surface and side surface of the first oxide semiconductor layer, a region in contact with the upper surface and side surface of the second oxide semiconductor layer, and a region in contact with the upper surface and side surface of the third oxide semiconductor layer. The second conductive layer is electrically connected to the first oxide semiconductor layer through a first contact hole provided in the oxide insulating layer. The fourth conductive layer is electrically connected to the second oxide semiconductor layer through a second contact hole provided in the oxide insulating layer. A display device.

2. A pixel having a light-emitting element, a first transistor electrically connected to the light-emitting element, and a capacitor element electrically connected to the light-emitting element and the first transistor; A display device having a scanning line driving circuit including a second transistor The pixel includes a first oxide semiconductor layer having a channel formation region of the first transistor, a first conductive layer having a region overlapping with the first oxide semiconductor layer and functioning as a gate electrode, and a second conductive layer electrically connected to the first oxide semiconductor layer and functioning as one of a source electrode and a drain electrode The scanning line driving circuit includes a second oxide semiconductor layer having a channel formation region of the second transistor, a third conductive layer having a region overlapping with the second oxide semiconductor layer and functioning as a gate electrode, and a fourth conductive layer functioning as one of a source electrode and a drain electrode A fifth conductive layer having the same material as the pixel electrode of the light emitting element and having a region overlapping with each of the second oxide semiconductor layer, the third conductive layer, and the fourth conductive layer The capacitive element includes a sixth conductive layer electrically connected to the first oxide semiconductor layer and functioning as a first electrode, and a seventh conductive layer having a region positioned below the sixth conductive layer and functioning as a second electrode A third oxide semiconductor layer having a region in contact with the lower surface of the sixth conductive layer An oxide insulating layer having a region positioned above the first oxide semiconductor layer, a region positioned above the second oxide semiconductor layer, and a region positioned above the third oxide semiconductor layer The second conductive layer is electrically connected to the first oxide semiconductor layer through a first contact hole provided in the oxide insulating layer The fourth conductive layer is electrically connected to the second oxide semiconductor layer through a second contact hole provided in the oxide insulating layer A peripheral portion of the first oxide semiconductor layer has a region in contact with the oxide insulating layer A peripheral portion of the second oxide semiconductor layer has a region in contact with the oxide insulating layer A peripheral portion of the third oxide semiconductor layer has a region in contact with the oxide insulating layer An inorganic insulating layer having a region provided above the oxide insulating layer A planarizing insulating layer having a region provided above the inorganic insulating layer Each of the pixel electrode and the fifth conductive layer has a region in contact with the upper surface of the planarizing insulating layer The pixel electrode has a region overlapping each of the sixth conductive layer and the seventh conductive layer, a display device. **Claim 3** In claim 2, The inorganic insulating layer has silicon nitride, a display device. **Claim 4** In any one of claims 1 to 3, The oxide insulating layer has silicon oxide, a display device. **Claim 5** In any one of claims 1 to 4, Each of the first to third oxide semiconductor layers has In, Ga, and Zn, a display device.

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