Semiconductor device and manufacturing method thereof

Abstract

To suppress floating body effects without impairing the advantages of an SOI structure.SOLUTION: A semiconductor device equipped with a fin-structure transistor comprises: a channel layer 14 which is formed above a substrate 11 and connected to the substrate 11 via a semiconductor layer 19; a source layer 21a which is provided above the substrate 11 by being spaced from the substrate 11 via an insulating layer 20a and provided on the first side surface of the channel layer 14; a drain layer 21b which is provided above the substrate 11 by being spaced from the substrate 11 via an insulating layer 20b and provided on the second side surface of the channel layer 14 facing the first side surface; and a first portion which is provided above the channel layer 14 and a second portion (portion 22a) provided between the substrate 11 and the channel layer 14. A side surface 22a1 or a side surface 22a2 of the second portion includes a gate electrode 22 facing the semiconductor layer 19.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device having a fin-type transistor (having a transistor structure that protrudes in a fin shape) on an SOI (Silicon On Insulator) substrate is known. Further, a fin-type transistor having a GAA (Gate All Around) structure that completely surrounds the periphery of the channel of the transistor with a gate has been proposed (see, for example, Patent Documents 1 to 3).

[0003] By the way, since the channel of the fin-type transistor formed on the SOI substrate is electrically separated from the semiconductor substrate, charges depending on the previous operation history accumulate, and variations in characteristics such as changes in the threshold voltage are likely to occur. Such a phenomenon is sometimes called the floating body effect.

[0004] In order to eliminate the floating body effect, a technique for making the channel and the substrate conductive has been proposed (see, for example, Patent Document 4).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in order to eliminate the floating body effect, if there is electrical continuity between the channel and the substrate, the advantages of the SOI structure may be impaired, such as a reduction in the change in the potential of the channel portion due to the gate voltage.

[0007] On one hand, an object of the present invention is to provide a semiconductor device capable of suppressing the floating body effect without impairing the advantages of the SOI structure.

Means for Solving the Problems

[0008] In one embodiment, in a semiconductor device including a fin-type structure transistor, a channel layer formed above the substrate and connected to the substrate via a semiconductor layer, a source of the transistor, provided above the substrate and spaced apart from the substrate via a first insulating layer, and provided on a first side surface of the channel layer, a source layer, a drain of the transistor, provided above the substrate and spaced apart from the substrate via a second insulating layer, and provided on a second side surface opposite to the first side surface of the channel layer, a drain layer, a gate of the transistor, including a first portion provided above the channel layer and a second portion provided between the substrate and the channel layer, and a gate electrode in which a third side surface of the second portion or a fourth side surface opposite to the third side surface faces the semiconductor layer is provided.

[0009] Also, in one embodiment, in a method of manufacturing a semiconductor device including a fin-type structure transistor, a channel layer connected to the substrate via a semiconductor layer is formed above the substrate, and a source layer provided above the substrate and spaced apart from the substrate via a first insulating layer and provided on a first side surface of the channel layer is formed as the source of the transistor, and a drain layer provided above the substrate and spaced apart from the substrate via a second insulating layer and provided on a second side surface of the channel layer opposite to the first side surface is formed as the drain of the transistor, and a gate electrode including a first portion provided above the channel layer and a second portion provided between the substrate and the channel layer is formed as the gate of the transistor, and a third side surface of the second portion or a fourth side surface opposite to the third side surface faces the semiconductor layer. A method of manufacturing a semiconductor device is provided.

Advantages of the Invention

[0010] On one side, the present invention can suppress the floating body effect without sacrificing the advantages of the SOI structure.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. (First Embodiment) FIG. 1 is a perspective view showing an example of a semiconductor device according to the first embodiment. Further, FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2, FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2, and FIG. 5 is a cross-sectional view taken along line V-V of FIG. 2.

[0013] The semiconductor device 10 according to the first embodiment includes a fin-type transistor formed above a substrate 11 and including a channel layer 14 (see FIG. 2), a source layer 21a, a drain layer 21b, and a gate electrode 22.

[0014] The substrate 11 is, for example, a silicon substrate. Further, as shown in FIG. 2, an impurity layer (hereinafter referred to as a channel cut layer) 12 that contains an impurity of the same conductivity type as the impurity contained in the channel layer 14 and has an impurity concentration higher than the impurity concentration of the channel layer 14 is formed on the surface of the substrate 11. In the example of FIG. 2, the channel layer 14 is a p-type impurity region containing p-type impurities, and the channel cut layer 12 is a p+-type impurity region having a higher p-type impurity concentration than the channel layer 14.

[0015] Note that the channel cut layer 12 may not be provided, but it is desirable to provide the channel cut layer 12 in order to suppress the leakage current between the source and the drain as described later.

[0016] In addition, STI (Shallow Trench Isolation) 15a and 15b for electrically separating adjacent elements are formed on the substrate 11. As shown in FIG. 2, the channel layer 14 is connected to the substrate 11 having the channel cut layer 12 formed on the surface via the semiconductor layer 19. In the example of FIG. 2, impurity diffusion regions 14a and 14b containing impurities diffused from the source layer 21a and the drain layer 21b are formed in the channel layer 14. The impurity diffusion regions 14a and 14b contain impurities of the same conductivity type (a conductivity type different from that of the impurities contained in the channel layer 14) as the impurities contained in the source layer 21a and the drain layer 21b at an impurity concentration lower than that of the source layer 21a and the drain layer 21b.

[0017] The source layer 21a is the source of the fin-type structure transistor, and is provided above the substrate 11 with a separation from the substrate 11 via the insulating layer 20a, and is provided on one side surface of the channel layer 14.

[0018] The drain layer 21b is the drain of the fin-type structure transistor, and is provided above the substrate 11 with a separation from the substrate 11 via the insulating layer 20b, and is provided on the side surface facing the side surface of the channel layer 14 where the source layer 21a is provided.

[0019] The source layer 21a and the drain layer 21b contain impurities of a conductivity type different from that of the impurities contained in the channel layer 14 (n-type in the example of FIG. 2). The gate electrode 22 is the gate of the fin-type structure transistor, and as shown in FIG. 2, includes a first portion provided above the channel layer 14 and a second portion (portion 22a in FIG. 2) provided between the substrate 11 and the channel layer 14. Here, the side surface 22a1 of the portion 22a and the side surface 22a2 facing the side surface 22a1 face the semiconductor layer 19.

[0020] In addition, a sidewall insulating film 18 is formed on the side surface of the gate electrode 22. Although not shown in the figure, a gate insulating film is formed between the portion of the gate electrode 22 above the channel layer 14 and the channel layer 14, between the portion 22a and the semiconductor layer 19, between the portion 22a and the channel layer 14, and between the portion 22a and the channel cut layer 12. The gate insulating film is, for example, a SiO2 film (silicon oxide film) or a High-k film. Examples of the material of the High-k film include, but are not limited to, HfO2 (hafnium oxide), Hf-Si-O (hafnium silicon oxide), and HfSiON (hafnium silicon oxynitride).

[0021] The semiconductor layer 19 is, for example, a silicon epitaxial layer formed by the method described later. The semiconductor layer 19 is provided between the insulating layers 20a and 20b and the side surfaces 22a1 and 22a2, and connects the channel layer 14 and the substrate 11. Note that the semiconductor layer 19 may be provided only on one side of the side surfaces 22a1 and 22a2.

[0022] Also, as shown in FIG. 2, the semiconductor layer 19 may be provided between the channel cut layer 12 and the insulating layers 20a and 20b, and between the insulating layers 20a and 20b and the channel layer 14. In the example of FIG. 2, a part of the upper surface of the insulating layers 20a and 20b below the sidewall insulating film 18 formed on the sidewall of the portion of the gate electrode 22 above the channel layer 14 is in contact with the lower surface of the semiconductor layer 19 formed on the lower surface of the channel layer 14.

[0023] The semiconductor layer 19 may contain impurities of a conductivity type opposite to that of the impurities contained in the channel layer 14, may contain impurities of the same conductivity type as the impurities contained in the channel layer 14, or may contain impurities of the same conductivity type as the impurities contained in the channel layer 14 at the same impurity concentration as the channel layer 14 or at an impurity concentration lower than that of the channel layer 14.

[0024] Also, the semiconductor layer 19 may be an undoped layer. Note that the semiconductor layer 19 has, for example, an impurity concentration of 1.0×10 15 cm -3If it is as follows, it can be said that it is substantially a non-doped layer even if an n-type impurity or a p-type impurity is present.

[0025] In such a semiconductor device 10, a transistor 25 having a conductivity type opposite to that of the fin-type transistor is provided by the substrate 11, the channel layer 14, the semiconductor layer 19, and the portion 22a in the gate electrode 22. In the transistor 25, the substrate 11 functions as one of the source or the drain, the channel layer 14 functions as the other of the source or the drain, the semiconductor layer 19 functions as the channel, and the portion 22a functions as the gate.

[0026] A similar transistor is also provided on the drain layer 21b side. When a voltage for turning on the fin-type structure transistor is applied to the gate electrode 22, in the semiconductor layer 19, the density of carriers (electrons or holes) having the same conductivity type as the impurity in the channel layer 14 decreases. As a result, the transistor 25 becomes an off state, and the channel layer 14 becomes in a state electrically separated from the substrate 11 (floating state). Therefore, the change in the potential of the channel layer 14 due to the gate voltage becomes large, and a large source-drain current can be obtained. That is, the advantages of the SOI structure can be obtained.

[0027] On the other hand, when a voltage for turning off the fin-type structure transistor is applied to the gate electrode 22, the density of carriers having the same conductivity type as the impurity in the channel layer 14 increases in the semiconductor layer 19. As a result, the transistor 25 becomes an on state, and the channel layer 14 becomes in a state electrically connected to the substrate 11. Therefore, the floating body effect is suppressed, and the occurrence of characteristic variations such as a change in the threshold voltage due to the accumulation of charges depending on the previous operation history in the channel layer 14 can be suppressed.

[0028] In the case of a fin-type structure transistor being an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the channel layer 14 contains p-type impurities. When the semiconductor layer 19 contains n-type impurities and the substrate 11 contains p-type impurities, the transistor 25 becomes a p-channel MOSFET. In this case, when a voltage (a positive voltage equal to or higher than the threshold value) that turns on the fin-type transistor is applied to the gate electrode 22, the electrical separation between the channel layer 14 and the substrate is good.

[0029] On the other hand, when the semiconductor layer 19 contains p-type impurities at the same impurity concentration as the channel layer 14 or at an impurity concentration lower than that of the channel layer 14 and the substrate 11 contains p-type impurities, the transistor 25 becomes a depletion-type p-channel MOSFET. In this case, the insulation between the channel layer 14 and the substrate 11 when a positive voltage equal to or higher than the threshold value is applied to the gate electrode 22 is inferior to that in the case where the transistor 25 is the above-mentioned p-channel MOSFET. However, when the transistor 25 becomes a depletion-type p-channel MOSFET, when a voltage (0 V) that turns off the fin-type transistor is applied to the gate electrode 22, the channel layer 14 and the substrate 11 can be connected with a lower resistance. Therefore, the effect of reducing the floating body effect can be further improved.

[0030] Also, since the source layer 21a and the drain layer 21b are insulated from the substrate 11 by the insulating layers 20a and 20b, leakage current between the source and the drain through the upper part of the substrate 11 is prevented. Furthermore, the capacitances between the source layer 21a and the substrate 11 and between the drain layer 21b and the substrate 11 can also be reduced.

[0031] Also, a part of the upper surfaces of the insulating layers 20a and 20b below the sidewall insulating film 18 shown in FIG. 2 is in contact with the lower surface of the semiconductor layer 19 formed on the lower surface of the channel layer 14. In other words, the semiconductor layer 19 is formed on the lower surface of the channel layer 14 below the sidewall insulating film 18. As a result, the thickness (length in the vertical direction) of the channel layer 14 is substantially increased partially, which also has the effect of reducing the parasitic resistance between the source and the drain. On the other hand, since the thickness of the channel layer 14 below the gate electrode 22 remains unchanged, the controllability of the gate with respect to the channel layer 14 remains unchanged.

[0032] As described above, according to the semiconductor device 10 of the first embodiment, the floating body effect can be suppressed without impairing the advantages of the SOI structure. (Comparative Example 1) FIG. 6 is a diagram showing an example of a semiconductor device provided without a channel cut layer. In FIG. 6, the same elements as those shown in FIG. 2 are denoted by the same reference numerals.

[0033] When there is no channel cut layer 12, as indicated by the arrow 26 in FIG. 6, a leakage current may occur flowing from the source layer 21a through the channel layer 14, the semiconductor layer 19, and the substrate 11 to the drain layer 21b.

[0034] Therefore, it is desirable to provide the channel cut layer 12 as shown in FIG. 2. (Comparative Example 2) FIG. 7 is a diagram showing an example of a semiconductor device when the thickness of the insulating layer is at the lower limit. In FIG. 7, the same elements as those shown in FIG. 2 are denoted by the same reference numerals.

[0035] In the example of FIG. 7, the thicknesses of the insulating layers 20a and 20b are smaller than those in the case of FIG. 2. A part of the upper surfaces of the insulating layers 20a and 20b below the sidewall insulating film 18 shown in FIG. 7 is in contact with the lower surface of the channel layer 14 (in FIG. 7, the semiconductor layer 19 is shown as impurity diffusion regions 14a and 14b in the lower surface portion). In FIG. 7, the portions of the impurity diffusion regions 14a and 14b in contact with the insulating layers 20a and 20b are portions formed by diffusion of impurities from the source layer 21a and the drain layer 21b into the semiconductor layer 19.

[0036] When the thicknesses of the insulating layers 20a and 20b become even smaller, the following Comparative Example 3 results. (Comparative Example 3) FIG. 8 is a diagram showing an example of a semiconductor device when the thickness of the insulating layer is below the lower limit. In FIG. 8, the same elements as those shown in FIG. 2 are denoted by the same reference numerals.

[0037] In the example of FIG. 8, the upper surfaces of the insulating layers 20a and 20b are at a position lower than the lower surface of the channel layer 14 shown in FIG. 7. In this case, the source layer 21a and the drain layer 21b enter between the lower surface of the channel layer 14 and the upper surfaces of the insulating layers 20a and 20b, and the distance between the source layer 21a and the drain layer 21b becomes short at the lower part of the channel layer 14, and there is a possibility of generating a leakage current between the source and the drain.

[0038] Therefore, it is desirable that the thickness of the insulating layers 20a and 20b be such that the upper surfaces of the insulating layers 20a and 20b below the sidewall insulating film 18 are at a height equal to or higher than the lower surface of the channel layer 14. However, when the insulating layers 20a and 20b are too thick, the source layer 21a and the drain layer 21b decrease, the connection area between the channel layer 14 and the source layer 21a and the drain layer 21b becomes small, and the path through which the source-drain current flows becomes small (high resistance). For this reason, for example, when the thickness of the channel layer 14 is 30 nm, it is desirable to form the insulating layers 20a and 20b to have a thickness such that the upper surfaces of the insulating layers 20a and 20b are about 5 nm higher than the lower surface of the channel layer 14.

[0039] (Method for manufacturing semiconductor device 10) Next, an example of the method for manufacturing the semiconductor device 10 according to the first embodiment will be described. Figs. 9 to 19 are perspective views showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0040] In the following example of the manufacturing method, it is assumed that a silicon substrate is used as the substrate 11. As shown in Fig. 9, first, by impurity implantation into the surface of the substrate 11, an impurity having the same conductivity type as the impurity contained in the later-formed channel layer 14 and having an impurity concentration higher than that of the channel layer 14 is formed as a channel cut layer 12.

[0041] Examples of the impurity implantation technique include ion implantation, vapor phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, etc. n-type impurities are P (phosphorus), As (arsenic), etc., and p-type impurities are B (boron), BF2 (boron fluoride), Ga (gallium), In (indium), etc.

[0042] Thereafter, an epitaxial layer 13 of SiGe (silicon germanium) is formed by epitaxial growth on the channel cut layer 12, and a channel layer 14 made of undoped silicon is formed by epitaxial growth again on the epitaxial layer 13. Examples of the epitaxial growth technique include VPE (Vapor-Phase Epitaxy), MBE (Molecular Beam Epitaxy), LPE (Liquid Phase Epitaxy), etc.

[0043] The thickness of the epitaxial layer 13 of silicon germanium is, for example, 5 to 10 nm, and the thickness of the channel layer 14 is, for example, 30 to 50 nm. Thereafter, in the substrate 11, the stacked structure shown in FIG. 9 is etched by an etching process so that the STI formation region is formed to a depth of about 30 to 50 nm, for example. Then, a silicon oxide film is embedded in the STI formation region by, for example, HDP (High Density Plasma)-CVD (Chemical Vapor Deposition) process with respect to the structure after etching. Further, a planarization process by CMP (Chemical Mechanical Polishing) and an HF (hydrofluoric acid) process are performed, the silicon oxide film recedes, and a fin structure and STI15a, 15b as shown in FIG. 10 are formed. STI15a, 15b are formed such that the upper surface is at the height of the lower surface of the epitaxial layer 13 of silicon germanium.

[0044] Subsequently, impurity implantation into the channel layer 14 is performed. In the case of a fin-type structure transistor being an n-channel type MOSFET, p-type impurities are implanted, and in the case of a p-channel type MOSFET, n-type impurities are implanted. Note that the impurity implantation into the channel layer 14 may be performed when the channel layer 14 is formed by epitaxial growth. Furthermore, for example, when p-type impurities are previously implanted into the channel layer 14 for an n-channel type MOSFET during epitaxial growth, n-type impurities may be implanted on top of this at this time into the channel layer 14 in the region where a p-channel type MOSFET is to be formed. Similarly, for example, when n-type impurities are previously implanted into the channel layer 14 for a p-channel type MOSFET during epitaxial growth, p-type impurities may be implanted on top of this at this time into the channel layer 14 in the region where an n-channel type MOSFET is to be formed.

[0045] Note that when p-type impurities are implanted into the channel layer 14, a channel region (inversion layer) that becomes n-type is formed in the channel layer 14 when the fin-type structure transistor is in the on state, and when n-type impurities are implanted into the channel layer 14, a channel region that becomes p-type is formed in the channel layer 14 when the fin-type structure transistor is in the on state.

[0046] Next, by thermal oxidation, a gate oxide film (not shown) is formed, for example, to a thickness of about 1 to 3 nm on the side and top surfaces of the stacked structure of the silicon germanium epitaxial layer 13 and the channel layer 14 shown in FIG. 10. Further, a polysilicon film and a hard mask layer are sequentially deposited by CVD treatment. The hard mask layer is, for example, a SiN (silicon nitride) film or a silicon oxide film. Then, an etching process is performed on the stacked film of the polysilicon film and the hard mask layer. Note that the etching process stops on the gate oxide film, and the gate oxide film is not removed.

[0047] By the etching process, the polysilicon film is patterned so as to have a shape straddling the fin structure, thereby forming a dummy electrode (hereinafter referred to as a dummy gate) 16 as shown in FIG. 11 and a hard mask 17 provided on top of the dummy gate 16. The dummy gate 16 is formed such that, for example, the gate width Wg is about 10 to 14 nm.

[0048] Note that the dummy gate 16 is replaced by a gate electrode 22 (excluding the portion 22a in FIG. 2) in a later-described process. Next, in order to form the sidewall insulating film 18, a silicon nitride film is deposited, for example, by CVD treatment on the structure shown in FIG. 11. Then, by anisotropic etching, the silicon nitride film is etched back so as to remain on the sidewalls of the silicon germanium epitaxial layer 13, the channel layer 14, the dummy gate 16, and the hard mask 17, thereby forming a sidewall insulating film 18 as shown in FIG. 12.

[0049] Note that the width Ws of the sidewall insulating film 18 is, for example, about 8 to 12 nm. The height Hs of the sidewall insulating film 18 formed on the sidewalls of the silicon germanium epitaxial layer 13 and the channel layer 14 is formed to be thicker than the thickness of the silicon germanium epitaxial layer 13 so as to serve as a mask when etching the channel layer 14 in a later-described process. For example, Hs is about 10 to 15 nm.

[0050] In order to form the sidewall insulating film 18 by such an etch-back, in the step of depositing the above silicon nitride film, it is deposited to be about 30% thicker than the target Ws. Next, using the hard mask 17 and the sidewall insulating film 18 as masks, anisotropic etching is performed in the direction of the arrow as shown in FIG. 13. As a result, in the silicon germanium epitaxial layer 13 and the channel layer 14, portions other than those masked by the hard mask 17 and the sidewall insulating film 18 are removed. Note that, from FIG. 13 onward, the dummy gate 16 is not shown.

[0051] After the above anisotropic etching, as shown in FIG. 14, the silicon germanium epitaxial layer 13 remaining on the lower surface of the channel layer 14 is etched by isotropic etching so that the central portion of the lower surface of the channel layer 14 (the portion sandwiched by the dummy gate 16) remains.

[0052] At this time, if the width of the remaining epitaxial layer 13 is too large compared to the gate width Wg, when the metal material of the gate electrode 22 is filled in the space formed by further removing the remaining epitaxial layer 13 in a later step, it may not be filled properly. In that case, the gate electrode 22 and the semiconductor layer 19 may be separated, etc., and there is a possibility that the gate potential does not affect the semiconductor layer 19 and the function as the transistor 25 described above cannot be obtained.

[0053] Therefore, it is desirable that the etching time is adjusted so that the width of the remaining epitaxial layer 13 is the same as the gate width Wg or narrower than the gate width Wg in consideration of the process margin. Hereinafter, it will be described assuming that the width of the remaining epitaxial layer 13 is the same as the gate width Wg.

[0054] Next, using the epitaxial growth method as described above, as shown in FIG. 15, a semiconductor layer 19 made of silicon is formed on the upper surface of the channel cut layer 12, the exposed side surfaces of the silicon germanium epitaxial layer 13, and the exposed side surfaces and the exposed lower surface of the channel layer 14. The semiconductor layer 19 is formed, for example, with a thickness of 1 to 5 nm.

[0055] As described above, the semiconductor layer 19 may be doped with impurities of a conductivity type opposite to that of the impurities contained in the channel layer 14, or impurities of the same conductivity type as the impurities contained in the channel layer 14 may be doped at an impurity concentration lower than that in the channel layer 14. Further, the semiconductor layer 19 may not be doped with n-type or p-type impurities. Even when n-type or p-type impurities are doped, for example, if the impurity concentration is 1.0×10 15 cm -3 or less, the semiconductor layer 19 can be treated as a substantially undoped non-doped layer.

[0056] Next, as shown in FIG. 16, insulating layers 20a and 20b, which are silicon oxide films, are embedded in the region sandwiched by the sidewall insulating film 18 and below the channel layer 14 (the portion where the silicon germanium epitaxial layer 13 has been removed). In order to perform the embedding appropriately, the embedding may be performed by appropriately combining the deposition and etching of the silicon oxide film. For example, the deposition of the silicon oxide film by CVD, anisotropic etching, and HDP-CVD treatment may be performed in this order, or anisotropic etching may be performed finally.

[0057] When a silicon oxide film remains on the sidewalls of the semiconductor layer 19 formed on the side surfaces of the channel layer 14, the silicon oxide film is removed, for example, by hydrofluoric acid or the like. Subsequently, the semiconductor layer 19 formed on the side surface of the channel layer 14 may be removed (see FIG. 17). The removal of the semiconductor layer 19 may be performed by isotropic etching or anisotropic etching using the hard mask 17 and the sidewall insulating film 18 as masks. The reason for removing the semiconductor layer 19 formed on the side surface of the channel layer 14 will be described later (see FIG. 21).

[0058] Next, as shown in FIG. 18, a source layer 21a and a drain layer 21b are formed. The source layer 21a and the drain layer 21b are formed by epitaxial growth on two opposing side surfaces of the channel layer 14. The shapes of the formed source layer 21a and drain layer 21b vary depending on the crystal planes of the two side surfaces of the channel layer 14 on which the epitaxial growth of the source layer 21a and drain layer 21b is performed. Further, impurities of a conductivity type opposite to that of the impurities contained in the channel layer 14 are implanted into the source layer 21a and the drain layer 21b.

[0059] Thereafter, although not shown, a silicon oxide film serving as an interlayer insulating film is deposited, for example, by CVD treatment so as to cover the structure shown in FIG. 18. Then, CMP is performed to planarize the silicon oxide film.

[0060] When the hard mask 17 is a silicon oxide film, the hard mask 17 is also removed by CMP, and the upper surface of the dummy gate 16 made of polysilicon is exposed. When the hard mask 17 is a silicon nitride film, the upper surface of the hard mask 17 is exposed by CMP. Subsequently, the hard mask 17 made of silicon nitride film is etched using the silicon oxide film of the interlayer insulating film as a mask, the hard mask 17 is removed, and the upper surface of the dummy gate 16 made of polysilicon is exposed.

[0061] Thereafter, by the RMG (Replacement Metal Gate) process, the dummy gate 16 and the epitaxial layer 13 of silicon germanium remaining below the channel layer 14 are replaced with the gate electrode 22 (see FIG. 19). Note that in FIG. 19, the illustration of the channel layer 14 is omitted.

[0062] In the RMG process, the dummy gate 16 is removed by vapor etching, wet etching, or the like. A gate oxide film (not shown) protects the channel layer 14 and the like during the removal of the dummy gate 16. After the gate oxide film is removed by hydrofluoric acid treatment or the like, the epitaxial layer 13 remaining below the channel layer 14 is removed by isotropic etching. Thereafter, a gate insulating film (not shown) is formed on the surface of the channel layer 14 and the surface of the substrate 11 that are exposed in the space from which the dummy gate 16 and the epitaxial layer 13 have been removed. Further, a metal material is filled on the gate insulating film and at the locations where the dummy gate 16, the hard mask 17 have been removed and where the epitaxial layer 13 remaining below the channel layer 14 has been removed. Thereby, the gate electrode 22 as shown in FIG. 19 is formed.

[0063] The gate insulating film is, for example, a silicon oxide film, a High-k film, or the like. As the metal material for the gate electrode 22, for example, TiN (titanium nitride), TiAl (titanium aluminide), TiAlN (aluminum titanium nitride), W (tungsten), Ti (titanium), Ta (tantalum), Ru (ruthenium), Zr (zirconium), Co (cobalt), Cu (copper), or the like can be used. Also, the gate electrode 22 may be formed by a combination of a plurality of metal materials.

[0064] The gate insulating film and the gate electrode 22 can be formed by deposition methods such as CVD, plating, ALD (Atomic Layer Deposition), evaporation, or the like. By the manufacturing method as described above, the semiconductor device 10 as shown in FIGS. 1 to 5 can be manufactured.

[0065] The reason for removing the semiconductor layer 19 formed on the side surface of the channel layer 14 is as follows. FIG. 20 is a diagram showing an example of transistors of two adjacent fin-type structures. In FIG. 20, the source layer 21a and the drain layer 21b are not shown.

[0066] If the semiconductor layer 19 on the side surface of the channel layer 14 is not removed, there may be a case where the space for forming the source layer 21a and the drain layer 21b between the transistors of the two fin-type structures is too narrow.

[0067] In the example of FIG. 20, for example, the gate width Wg of the gate electrode 22 is about 10 to 14 nm, and the width Ws of the sidewall insulating film 18 is about 8 to 12 nm. For example, when the gate-to-gate distance (distance between adjacent sidewall insulating films) La between the transistors of the two fin-type structures is about 12 nm, and when the semiconductor layer 19 is formed on the side surface of the channel layer 14 with a thickness of 1 to 2 nm, the distance Lb between the semiconductor layers where the source layer 21a and the drain layer 21b are formed becomes 8 to 10 nm, which is 20 to 30% shorter than La.

[0068] Therefore, it is desirable to remove the semiconductor layer 19 on the side surface of the channel layer 14 before forming the source layer 21a and the drain layer 21b. However, when La is long and there is sufficient space for forming the source layer 21a and the drain layer 21b, the semiconductor layer 19 does not have to be removed.

[0069] (Comparative Example 4) FIG. 21 is a cross-sectional view showing an example of a semiconductor device in which the gate width below the channel layer is narrower than the gate width above the channel layer.

[0070] ] When removing the epitaxial layer 13 of silicon germanium by the isotropic etching shown in FIG. 14, if the etching time is adjusted so that the width of the remaining epitaxial layer 13 becomes narrower than the gate width Wg, a structure as shown in FIG. 21 can be obtained. That is, in the gate electrode 22, the width Wga of the portion 22a below the channel layer 14 is narrower than the gate width Wg of the portion above the channel layer 14.

[0071] (Second Embodiment) FIG. 22 is a perspective view showing an example of a semiconductor device according to the second embodiment. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII of FIG. 22, FIG. 24 is a cross-sectional view taken along line XXIV-XXIV of FIG. 23, FIG. 25 is a cross-sectional view taken along line XXV-XXV of FIG. 23, and FIG. 26 is a cross-sectional view taken along line XXVI-XXVI of FIG. 23.

[0072] The semiconductor device 30 according to the second embodiment includes a fin-type transistor formed above a substrate 31 and including channel layers 34a and 34b (see FIG. 23), a source layer 41a, a drain layer 41b, and a gate electrode 42.

[0073] The substrate 31 is, for example, a silicon substrate. As shown in FIG. 23, an impurity layer (hereinafter referred to as a channel cut layer) 32 that contains impurities of the same conductivity type as the impurities contained in the channel layers 34a and 34b and has an impurity concentration higher than the impurity concentrations of the channel layers 34a and 34b is formed on the surface of the substrate 31. In the example of FIG. 23, the channel layers 34a and 34b are p-type impurity regions containing p-type impurities, and the channel cut layer 32 is a p+-type impurity region having a higher p-type impurity concentration than the channel layers 34a and 34b.

[0074] Note that the channel cut layer 32 may not be provided, but it is desirable to provide the channel cut layer 32 in order to suppress the leakage current between the source and the drain as described later.

[0075] In addition, STI 35a and 35b for electrically separating adjacent elements are formed on the substrate 31. As shown in FIG. 23, the channel layer 34a is connected to the substrate 31 having a channel cut layer 32 formed on its surface via a semiconductor layer 39. The channel layer 34b is also connected to the substrate 31 via the semiconductor layer 39 and the channel layer 34a. In the example of FIG. 23, impurity diffusion regions 34c and 34d containing impurities diffused from the source layer 41a and the drain layer 41b are formed in the channel layers 34a and 34b. The impurity diffusion regions 34c and 34d contain impurities of the same conductivity type (different from the impurities contained in the channel layers 34a and 34b) as the impurities contained in the source layer 41a and the drain layer 41b at an impurity concentration lower than that of the source layer 41a and the drain layer 41b.

[0076] The source layer 41a is the source of a fin-type transistor, is provided above the substrate 31 with a separation from the substrate 31 via an insulating layer 40a, and is provided on a certain side surface of the channel layers 34a and 34b.

[0077] The drain layer 41b is the drain of a fin-type transistor, is provided above the substrate 31 with a separation from the substrate 31 via an insulating layer 40b, and is provided on the side surface facing the side surface of the channel layers 34a and 34b where the source layer 41a is provided.

[0078] The source layer 41a and the drain layer 41b contain impurities of a conductivity type different from that of the impurities contained in the channel layers 34a and 34b (n-type in the example of FIG. 23). The gate electrode 42 is the gate of a fin-type transistor and includes a first portion provided above the channel layer 34b, a second portion (portion 42a in FIG. 23) provided between the substrate 31 and the channel layer 34a, and a third portion (portion 42b in FIG. 23) provided between the channel layer 34a and the channel layer 34b, as shown in FIG. 23.

[0079] Here, the side surface 42a1 of the portion 42a and the side surface 42a2 facing the side surface 42a1 face the semiconductor layer 39. The side surface 42b1 of the portion 42b and the side surface 42b2 facing the side surface 42b1 also face the semiconductor layer 39.

[0080] Also, a sidewall insulating film 38 is formed on the side surface of the gate electrode 42. Although not shown, a gate insulating film is formed between the portion of the gate electrode 42 above the channel layer 34b and the channel layer 34b, between the portions 42a, 42b and the semiconductor layer 39, between the portion 42a and the channel layer 34a, between the portion 42b and the channel layers 34a, 34b, and between the portion 42a and the channel cut layer 32. The gate insulating film is, for example, a silicon oxide film or a High-k film.

[0081] The semiconductor layer 39 is, for example, a silicon epitaxial layer formed by a method described later. The semiconductor layer 39 is provided between the insulating layers 40a, 40b and the side surfaces 42a1, 42a2, 42b1, 42b2, and connects the channel layers 34a, 34b and the substrate 31. Note that the semiconductor layer 39 may be provided only on one side of the side surfaces 42a1, 42b1 and the side surfaces 42a2, 42b2.

[0082] Also, the semiconductor layer 39 may be provided between the channel cut layer 32 and the insulating layers 40a, 40b, and between the insulating layers 40a, 40b and the channel layers 34a, 34b as shown in FIG. 23. In the example of FIG. 23, a part of the upper surface of the insulating layers 40a, 40b below the sidewall insulating film 38 formed on the sidewall of the portion of the gate electrode 42 above the channel layer 34b is in contact with the lower surface of the semiconductor layer 39 formed on the lower surface of the channel layers 34a, 34b.

[0083] The semiconductor layer 39 may contain impurities of a conductivity type opposite to that of the impurities contained in the channel layers 34a and 34b, may contain impurities of the same conductivity type as the impurities contained in the channel layers 34a and 34b, or may contain impurities of the same conductivity type as the impurities contained in the channel layers 34a and 34b at the same impurity concentration as the channel layers 34a and 34b or at an impurity concentration lower than that of the channel layers 34a and 34b.

[0084] Also, the semiconductor layer 39 may be an undoped layer. Note that if the impurity concentration of the semiconductor layer 39 is, for example, 1.0×10 15 cm -3 or less, it can be said that it is substantially an undoped layer even if n-type impurities or p-type impurities are present.

[0085] In such a semiconductor device 30, a transistor 45a of a conductivity type opposite to that of the fin-type transistor is provided by the substrate 31, the channel layer 34a, the semiconductor layer 39, and the portion 42a of the gate electrode 42. In the transistor 45a, the substrate 31 functions as one of the source or drain, the channel layer 34a functions as the other of the source or drain, the semiconductor layer 39 functions as the channel, and the portion 42a functions as the gate.

[0086] Furthermore, a transistor 45b of a conductivity type opposite to that of the fin-type transistor is provided by the channel layer 34a, the channel layer 34b, the semiconductor layer 39, and the portion 42b of the gate electrode 42. In the transistor 45b, the channel layer 34a functions as one of the source or drain, the channel layer 34b functions as the other of the source or drain, the semiconductor layer 39 functions as the channel, and the portion 42b functions as the gate.

[0087] Similar transistors are also provided on the drain layer 41b side. When a voltage for turning on the fin-type transistor is applied to the gate electrode 42, in the semiconductor layer 39, the density of carriers (electrons or holes) having the same conductivity type as the impurities in the channel layers 34a and 34b decreases. As a result, the transistors 45a and 45b are turned off, and the channel layers 34a and 34b are in a state of being electrically separated (floating state) from the substrate 31. For this reason, the change in the potential of the channel layers 34a and 34b due to the gate voltage becomes large, and a large source-drain current can be obtained. That is, the advantages of the SOI structure can be obtained.

[0088] On the other hand, when a voltage for turning off the fin-type structure transistor is applied to the gate electrode 42, the density of carriers having the same conductivity type as the impurities in the channel layers 34a and 34b increases in the semiconductor layer 39. As a result, the transistors 45a and 45b are turned on, and the channel layers 34a and 34b are in a state of being electrically connected to the substrate 31. For this reason, the floating body effect is suppressed, and the occurrence of characteristic variations such as changes in the threshold voltage due to the accumulation of charges depending on the previous operation history in the channel layers 34a and 34b can be suppressed.

[0089] When the fin-type structure transistor is an n-channel type MOSFET, the channel layers 34a and 34b contain p-type impurities. When the semiconductor layer 39 contains n-type impurities and the substrate 31 contains p-type impurities, the transistors 45a and 45b become p-channel type MOSFETs. In this case, when a voltage (a positive voltage equal to or higher than the threshold value) for turning on the fin-type structure transistor is applied to the gate electrode 42, the electrical separation between the channel layers 34a and 34b and the substrate is good.

[0090] On the other hand, when the semiconductor layer 39 contains p-type impurities at the same impurity concentration as the channel layers 34a and 34b or at an impurity concentration lower than that of the channel layers 34a and 34b, and the substrate 31 contains p-type impurities, the transistors 45a and 45b become depletion-type p-channel MOSFETs. In this case, the insulation between the channel layers 34a and 34b and the substrate 31 when a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode 42 is inferior to that in the case where the transistors 45a and 45b are the above-described p-channel MOSFETs. However, when the transistors 45a and 45b become depletion-type p-channel MOSFETs, the channel layers 34a and 34b and the substrate 31 can be connected with lower resistance when a voltage (0V) for turning off the fin-type structure transistor is applied to the gate electrode 42. Therefore, the effect of reducing the floating body effect can be further improved.

[0091] Further, since the source layer 41a and the drain layer 41b are insulated from the substrate 31 by the insulating layers 40a and 40b, a leakage current between the source and the drain through the upper part of the substrate 31 is prevented. Furthermore, the capacitances between the source layer 41a and the substrate 31 and between the drain layer 41b and the substrate 31 can also be reduced.

[0092] Also, a part of the upper surfaces of the insulating layers 40a and 40b below the sidewall insulating film 38 shown in FIG. 23 is in contact with the lower surface of the semiconductor layer 39 formed on the lower surfaces of the channel layers 34a and 34b. In other words, the semiconductor layer 39 is formed on the lower surfaces of the channel layers 34a and 34b below the sidewall insulating film 38. Thereby, the thickness (length in the vertical direction) of the channel layers 34a and 34b is substantially increased partially, and there is also an effect of reducing the parasitic resistance between the source and the drain.

[0093] On the other hand, since the thickness of the channel layers 34a and 34b below the gate electrode 42 does not change, the controllability of the gate with respect to the channel layers 34a and 34b does not change. In the semiconductor device 30 of the second embodiment, since the thickness of the channel layers 34a and 34b is thinner than that of the channel layer 14 of the semiconductor device 10 of the first embodiment, the effect of thickening using the semiconductor layer 39 is higher than that of the semiconductor device 10 of the first embodiment.

[0094] As described above, also in the semiconductor device 30 of the second embodiment, the floating body effect can be suppressed without impairing the advantages of the SOI structure. In the above example, the case where the channel layers 34a and 34b are two layers is shown, but the present invention is not limited to this, and the channel layer may have three or more layers.

[0095] (Comparative Example 1) FIG. 27 is a diagram showing an example of a semiconductor device in which a channel cut layer is not provided. In FIG. 27, the same elements as those shown in FIG. 23 are denoted by the same reference numerals.

[0096] When the channel cut layer 32 is not present, as indicated by the arrow 46 in FIG. 27, a leakage current may occur that flows from the source layer 41a, through the channel layer 34a, the semiconductor layer 39, and the substrate 31, to the drain layer 41b.

[0097] Therefore, it is desirable that the channel cut layer 32 be provided as shown in FIG. 23. (Comparative Example 2) FIG. 28 is a diagram showing an example of a semiconductor device when the thickness of the insulating layer is large. In FIG. 28, the same elements as those shown in FIG. 23 are denoted by the same reference numerals.

[0098] In the example of FIG. 28, the thicknesses of the insulating layers 40a and 40b are larger than those in the case of FIG. 23. As the insulating layers 40a and 40b become thicker, the source layer 41a and the drain layer 41b become smaller, the connection area between the channel layer 34a and the source layer 41a and the drain layer 41b becomes smaller, and the path through which the source-drain current flows becomes smaller (higher resistance). Therefore, the upper surface of the thick portion of the insulating layers 40a and 40b is within a range that is higher than the lower surface of the semiconductor layer 39 (this portion functions as the channel layer 34a) provided between the channel layer 34a and the thin portions of the insulating layers 40a and 40b, and is about 3 nm higher than the lower surface. It is desirable that the insulating layers 40a and 40b be formed with such a thickness.

[0099] (Comparative Example 3) FIG. 29 is a diagram showing an example of a semiconductor device when the thickness of the insulating layer is below the lower limit. In FIG. 29, the same elements as those shown in FIG. 23 are denoted by the same reference numerals.

[0100] In the example of FIG. 29, the upper surfaces of the insulating layers 40a and 40b are located lower than the lower surface of the channel layer 34a (in FIG. 29, the semiconductor layer 39 constituting a part of the lower surface portion of the channel layer 34a is shown as part of the impurity diffusion regions 34c and 34d).

[0101] In this case, the source layer 41a and the drain layer 41b enter between the lower surface and the upper surfaces of the insulating layers 40a and 40b, and at the lower part of the channel layer 34a, the distance between the source layer 41a and the drain layer 41b becomes short, and there is a possibility that a leakage current between the source and the drain may occur.

[0102] Therefore, it is desirable that the thickness of the insulating layers 40a and 40b be such that the upper surfaces of the insulating layers 40a and 40b below the sidewall insulating film 38 are at a height equal to or higher than the lower surface (the lower surface of the semiconductor layer 39 constituting the lower surface portion of the channel layer 34a) of the channel layer 34a.

[0103] (Method for manufacturing the semiconductor device 30) Next, an example of a method for manufacturing the semiconductor device 30 according to the second embodiment will be described. FIGS. 30 to 40 are perspective views showing one step of a method for manufacturing a semiconductor device according to the second embodiment.

[0104] In the following example of the manufacturing method, it is described assuming that a silicon substrate is used as the substrate 31. As shown in FIG. 30, first, by impurity implantation into the surface of the substrate 31, an impurity of the same conductivity type (hereinafter referred to as p-type) as the impurity contained in the later-formed channel layers 34a and 34b and having an impurity concentration higher than the impurity concentration of the channel layers 34a and 34b is formed to form a channel cut layer 32.

[0105] Thereafter, an epitaxial layer 33a of silicon germanium is formed by epitaxial growth on the channel cut layer 32, and a channel layer 34a made of undoped silicon is formed by epitaxial growth again on the epitaxial layer 33a. Then, an epitaxial layer 33b of silicon germanium is formed by epitaxial growth on the channel layer 34a, and a channel layer 34b made of undoped silicon is formed by epitaxial growth on the epitaxial layer 33b.

[0106] The thicknesses of the epitaxial layers 33a and 33b and the channel layers 34a and 34b are, for example, 4 to 8 nm respectively. Thereafter, the stacked structure shown in FIG. 30 is etched by an etching process so that the STI formation region in the substrate 31 is formed to a depth of about 30 to 50 nm, for example. Then, a silicon oxide film is embedded in the STI formation region by, for example, HDP-CVD processing for the structure after etching. Further, a planarization process by CMP and a hydrofluoric acid treatment are performed, the silicon oxide film recedes, and a fin structure and STIs 35a and 35b as shown in FIG. 31 are formed. The STIs 35a and 35b are formed such that the upper surface is at the height of the lower surface of the epitaxial layer 33a of silicon germanium.

[0107] Subsequently, impurities are implanted into the channel layers 34a and 34b. In the case of a fin-type structure transistor being an n-channel MOSFET, p-type impurities are implanted, and in the case of a p-channel MOSFET, n-type impurities are implanted. Note that the impurity implantation into the channel layers 34a and 34b may be performed when the channel layers 34a and 34b are formed by epitaxial growth. Furthermore, for example, when p-type impurities are previously implanted into the channel layers 34a and 34b for an n-channel MOSFET during epitaxial growth, n-type impurities may be implanted on top of this at this time into the channel layers 34a and 34b in the region where a p-channel MOSFET is to be formed. Similarly, for example, when n-type impurities are previously implanted into the channel layers 34a and 34b for a p-channel MOSFET during epitaxial growth, p-type impurities may be implanted on top of this at this time into the channel layers 34a and 34b in the region where an n-channel MOSFET is to be formed.

[0108] Note that when p-type impurities are implanted into the channel layers 34a and 34b, a channel region (inversion layer) that becomes n-type is formed in the channel layers 34a and 34b when the fin-type structure transistor is in the on state, and when n-type impurities are implanted into the channel layers 34a and 34b, a channel region that becomes p-type is formed in the channel layers 34a and 34b when the fin-type structure transistor is in the on state.

[0109] Next, a gate oxide film (not shown) is formed, for example, to a thickness of about 1 to 3 nm on the side and top surfaces of the laminated structure shown in FIG. 31 by thermal oxidation. Further, a polysilicon film and a hard mask layer are sequentially deposited by CVD processing. The hard mask layer is, for example, a silicon nitride film or a silicon oxide film. Then, an etching process is performed on the laminated film formed by the polysilicon film and the hard mask layer. Note that the etching process stops on the gate oxide film and the gate oxide film is not removed.

[0110] By etching, the polysilicon film is patterned so as to have a shape straddling the fin structure, thereby forming a dummy gate 36 as shown in FIG. 32 and a hard mask 37 provided on top of the dummy gate 36. The dummy gate 36 is formed such that, for example, the gate width Wg is about 10 to 14 nm.

[0111] Note that the dummy gate 36 is replaced by a gate electrode 42 (excluding the portions 42a and 42b in FIG. 23) in a later-described process. Next, in order to form the sidewall insulating film 38, a silicon nitride film is deposited, for example, by CVD on the structure shown in FIG. 32. Then, by anisotropic etching, the silicon nitride film is etched back so as to remain on the sidewalls of the silicon germanium epitaxial layer 33a, the dummy gate 36, and the hard mask 37, thereby forming a sidewall insulating film 38 as shown in FIG. 33.

[0112] Note that the width Ws of the sidewall insulating film 38 is, for example, about 8 to 12 nm. The height Hs of the sidewall insulating film 38 formed on the sidewalls of the epitaxial layer 33a is about 4 to 8 nm so as to be approximately the same as the thickness of the epitaxial layer 33a.

[0113] In order to form the sidewall insulating film 38 by such etching back, in the step of depositing the silicon nitride film, the film is deposited to be about 30% thicker than the target Ws. Next, using the hard mask 37 and the sidewall insulating film 38 as masks, anisotropic etching is performed in the direction of the arrow as shown in FIG. 34. As a result, in the silicon germanium epitaxial layers 33a and 33b and the channel layers 34a and 34b, portions other than the portions masked by the hard mask 37 and the sidewall insulating film 38 are removed. Note that the illustration of the dummy gate 36 is omitted from FIG. 34 onward.

[0114] After the anisotropic etching, as shown in FIG. 35, the epitaxial layers 33a and 33b of silicon germanium are etched by isotropic etching so that the central portion of the lower surface of the channel layers 34a and 34b (the portion sandwiched by the dummy gates 36) remains.

[0115] At this time, if the width of the remaining epitaxial layers 33a and 33b is too large compared to the gate width Wg, when further removing the remaining epitaxial layers 33a and 33b in a later process and filling the metal material of the gate electrode 42 into the removed space, there is a possibility that it cannot be properly filled. In that case, the gate electrode 42 and the semiconductor layer 39 may be separated, etc., and there is a possibility that the gate potential does not affect the semiconductor layer 39 and the functions as the transistors 45a and 45b described above cannot be obtained.

[0116] Therefore, it is desirable that the etching time is adjusted so that the width of the remaining epitaxial layers 33a and 33b is the same as the gate width Wg or thinner than the gate width Wg in consideration of the process margin. Hereinafter, it will be described assuming that the width of the remaining epitaxial layers 33a and 33b is the same as the gate width Wg.

[0117] Next, using the epitaxial growth method as described above, as shown in FIG. 36, the semiconductor layer 39 made of silicon is formed on the upper surface of the channel cut layer 32, the exposed side surfaces of the epitaxial layers 33a and 33b of silicon germanium, the exposed side surface, upper surface and lower surface of the channel layer 34a, and the exposed side surface and lower surface of the channel layer 34b. The semiconductor layer 39 is formed, for example, with a thickness of 1 to 5 nm.

[0118] As described above, the semiconductor layer 39 may be doped with impurities of a conductivity type opposite to that of the impurities contained in the channel layers 34a and 34b, or may be doped with impurities of the same conductivity type as the impurities contained in the channel layers 34a and 34b at an impurity concentration lower than that in the channel layers 34a and 34b. Further, the semiconductor layer 39 may not be doped with n-type or p-type impurities. Even when n-type or p-type impurities are doped, for example, if the impurity concentration is 1.0×10 15 cm -3 or less, the semiconductor layer 39 can be treated as a substantially undoped non-doped layer.

[0119] Next, as shown in FIG. 37, the insulating layers 40a and 40b, which are silicon oxide films, are embedded in the region sandwiched by the sidewall insulating film 38 and below the channel layers 34a and 34b (the portion where the epitaxial layers 33a and 33b of silicon germanium are removed). In order to perform the embedding appropriately, the embedding may be performed by appropriately combining the deposition and etching of the silicon oxide film. For example, the deposition of the silicon oxide film by CVD, anisotropic etching, and HDP-CVD treatment may be performed in this order, or anisotropic etching may be performed finally.

[0120] When a silicon oxide film remains on the sidewalls of the semiconductor layer 39 formed on the side surfaces of the channel layers 34a and 34b, the silicon oxide film is removed by, for example, hydrofluoric acid. Thereafter, the semiconductor layer 39 formed on the side surfaces of the channel layers 34a and 34b may be removed (see FIG. 38). The removal of the semiconductor layer 39 may be performed by isotropic etching or anisotropic etching using the hard mask 37 and the sidewall insulating film 38 as masks. The reason for removing the semiconductor layer 39 formed on the side surfaces of the channel layers 34a and 34b will be described later (see FIG. 41).

[0121] Next, as shown in FIG. 39, a source layer 41a and a drain layer 41b are formed. The source layer 41a and the drain layer 41b are formed by epitaxial growth on two opposing side surfaces of the channel layers 34a and 34b. The shapes of the formed source layer 41a and drain layer 41b vary depending on the crystal planes of the two side surfaces of the channel layers 34a and 34b on which the epitaxial growth of the source layer 41a and drain layer 41b is performed. Also, impurities of a conductivity type opposite to that of the impurities contained in the channel layers 34a and 34b are implanted into the source layer 41a and the drain layer 41b.

[0122] Thereafter, although not shown in the figure, a silicon oxide film serving as an interlayer insulating film is deposited, for example, by CVD treatment so as to cover the structure shown in FIG. 39. Then, CMP is performed to planarize the silicon oxide film.

[0123] When the hard mask 37 is a silicon oxide film, the hard mask 37 is also removed by CMP, and the upper surface of the dummy gate 36 made of polysilicon is exposed. When the hard mask 37 is a silicon nitride film, the upper surface of the hard mask 37 is exposed by CMP. Subsequently, the hard mask 37 of the silicon nitride film is etched using the silicon oxide film of the interlayer insulating film as a mask, the hard mask 37 is removed, and the upper surface of the dummy gate 36 made of polysilicon is exposed.

[0124] Thereafter, by the RMG process, the dummy gate 36 and the epitaxial layers 33a and 33b of silicon germanium remaining below the channel layers 34a and 34b are replaced with gate electrodes 42 (see FIG. 40). Note that in FIG. 40, the channel layers 34a and 34b are not shown.

[0125] In the RMG process, the dummy gate 36 is removed by, for example, gas-phase etching or wet etching. A gate oxide film (not shown) protects the channel layers 34a and 34b during the removal of the dummy gate 36. After the gate oxide film is removed by hydrofluoric acid treatment or the like, the epitaxial layers 33a and 33b remaining below the channel layers 34a and 34b are removed by isotropic etching. Thereafter, a gate insulating film (not shown) is formed on the surfaces of the channel layers 34a and 34b and the substrate 31 that are exposed in the space from which the dummy gate 36 and the epitaxial layers 33a and 33b have been removed. Further, a metal material is filled in the portions on the gate insulating film where the dummy gate 36, the hard mask 37 have been removed and where the epitaxial layers 33a and 33b remaining below the channel layers 34a and 34b have been removed. Thereby, a gate electrode 42 as shown in FIG. 40 is formed.

[0126] For the gate insulating film and the gate electrode 42, for example, those similar to the semiconductor device 10 of the first embodiment can be used. By the manufacturing method as described above, a semiconductor device 30 as shown in FIGS. 22 to 26 can be manufactured.

[0127] The reason for removing the semiconductor layer 39 formed on the side surfaces of the channel layers 34a and 34b is as follows. FIG. 41 is a diagram showing an example of two adjacent fin-type transistors. In FIG. 41, the source layer 41a and the drain layer 41b are not shown.

[0128] If the semiconductor layer 39 on the side surfaces of the channel layers 34a and 34b is not removed, the space for forming the source layer 41a and the drain layer 41b between the two fin-type transistors may be too narrow.

[0129] In the example of FIG. 41, for example, the gate width Wg of the gate electrode 42 is about 10 to 14 nm, and the width Ws of the sidewall insulating film 38 is about 8 to 12 nm. For example, when the gate pitch (distance between adjacent sidewall insulating films) La between two fin-type transistors is about 12 nm, and when the semiconductor layer 39 is formed on the side surfaces of the channel layers 34a and 34b with a thickness of 1 to 2 nm, the distance Lb between the semiconductor layers where the source layer 41a and the drain layer 41b are formed becomes 8 to 10 nm, which is 20 to 30% shorter than La.

[0130] Therefore, it is desirable to remove the semiconductor layer 39 on the side surfaces of the channel layers 34a and 34b before forming the source layer 41a and the drain layer 41b. However, when La is long and there is sufficient space to form the source layer 41a and the drain layer 41b, it is not necessary to remove the semiconductor layer 39.

[0131] (Comparative Example 4) FIG. 42 is a cross-sectional view showing an example of a semiconductor device in which the gate width below the channel layer is narrower than the gate width above the channel layer.

[0132] When removing the epitaxial layers 33a and 33b of silicon germanium by the isotropic etching shown in FIG. 35, if the etching time is adjusted so that the widths of the remaining epitaxial layers 33a and 33b become narrower than the gate width Wg, a structure as shown in FIG. 42 can be obtained. That is, the width Wga of the portions 42a and 42b below the channel layers 34a and 34b is narrower than the gate width Wg of the portion above the channel layer 34b in the gate electrode 42.

[0133] (Comparative Example 5) FIG. 43 is a cross-sectional view showing an example of a semiconductor device in which the semiconductor layer is thick and the space between two channel layers and the space between the lower channel layer and the substrate are filled with the semiconductor layer.

[0134] In the example of FIG. 43, the semiconductor layer 39 is thick, and the space between the channel layer 34a and the channel layer 34b and the space between the channel layer 34a and the substrate 31 are filled with the semiconductor layer 39. In this case, as shown in FIG. 43, the insulating layers 40a and 40b are not formed between the channel layer 34a and the channel layer 34b and between the channel layer 34a and the substrate 31 below the sidewall insulating film 38, but the same effects as those of the semiconductor device 30 of the second embodiment described above can be obtained.

[0135] As described above, from the perspective of the semiconductor device and its manufacturing method of the present invention based on the embodiments, these are merely examples and are not limited to the above description. For example, in FIGS. 2 and 22, the case where the fin-type transistors of the semiconductor devices 10 and 30 are n-channel MOSFETs is shown, but they may also be p-channel MOSFETs. In that case, the conductivity types (n-type and p-type) of each element may be interchanged.

[0136] Also, in the above example, the substrates 11 and 31 are described as silicon substrates, but are not limited thereto. Other materials such as silicon germanium can be used as the substrates 11 and 31. The materials of each element of the semiconductor devices 10 and 30 can also be appropriately changed. For example, when the substrates 11 and 31 are silicon germanium substrates, silicon can be used as the epitaxial layers 13, 33a, and 33b, and silicon germanium can be used as the channel layers 14, 34a, and 34b.

[0137] Regarding the plurality of embodiments described above, the following additional remarks are further disclosed. (Additional Remark 1) In a semiconductor device including a fin-type transistor, a channel layer formed above the substrate and connected to the substrate via a semiconductor layer, and a source layer that is a source of the transistor, is provided above the substrate and spaced apart from the substrate via a first insulating layer, and is provided on a first side surface of the channel layer. It is the drain of the transistor, which is provided above the substrate and spaced apart from the substrate via a second insulating layer, and is provided on a second side surface facing the first side surface of the channel layer, a drain layer; It is the gate of the transistor, including a first portion provided above the channel layer and a second portion provided between the substrate, the channel layer, and the semiconductor layer, and a third side surface of the second portion or a fourth side surface facing the third side surface faces the semiconductor layer, a gate electrode; A semiconductor device having the above.

[0138] (Appendix 2) The semiconductor device according to Appendix 1, wherein the channel layer is connected to the substrate via the semiconductor layer provided between the first insulating layer or the second insulating layer and the third side surface or the fourth side surface of the second portion.

[0139] (Appendix 3) The semiconductor device according to Appendix 1 or 2, wherein a first transistor having a conductivity type opposite to that of the transistor is provided by the substrate, the channel layer, the semiconductor layer, and the second portion in the gate electrode.

[0140] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein the semiconductor layer contains a second impurity having a conductivity type opposite to that of the first impurity contained in the channel layer. (Appendix 5) The semiconductor device according to any one of Appendices 1 to 3, wherein the semiconductor layer contains a second impurity having the same conductivity type as the first impurity contained in the channel layer, and the impurity concentration of the semiconductor layer is lower than the impurity concentration of the channel layer.

[0141] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 3, wherein the semiconductor layer is a non-doped layer. (Appendix 7) On the surface of the substrate, an impurity layer containing a third impurity having the same conductivity type as the first impurity contained in the channel layer and having an impurity concentration higher than the impurity concentration of the channel layer is formed. The semiconductor device according to any one of Appendices 1 to 6.

[0142] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein a part of the upper surfaces of the first insulating layer and the second insulating layer below the sidewall insulating film formed on the sidewall of the first part is in contact with the lower surface of the semiconductor layer formed on the lower surface of the channel layer.

[0143] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the width of the second part is narrower than the width of the gate electrode of the first part. (Supplementary Note 10) The channel layer includes a first channel layer and a second channel layer provided above the first channel layer, and a third part of the gate electrode is further provided between the first channel layer and the second channel layer. The semiconductor device according to any one of Supplementary Notes 1 to 9.

[0144] (Supplementary Note 11) The semiconductor device according to Supplementary Note 10, wherein a second transistor having a conductivity type opposite to that of the transistor is provided by the first channel layer, the second channel layer, the semiconductor layer, and the third part in the gate electrode.

[0145] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the semiconductor layer is also provided between the substrate and the first insulating layer and the second insulating layer. (Supplementary Note 13) The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein a sidewall insulating film is provided on the side surface of the gate electrode, and the material of the sidewall insulating film is a silicon nitride film.

[0146] (Supplementary Note 14) In a method of manufacturing a semiconductor device including a fin-type structure transistor, a channel layer connected to the substrate via a semiconductor layer is formed above the substrate, a source layer which is a source of the transistor and is provided above the substrate, separated from the substrate via a first insulating layer, and provided on a first side surface of the channel layer is formed, It is the drain of the transistor, provided spaced apart from the substrate via a second insulating layer above the substrate, and forms a drain layer provided on a second side surface facing the first side surface of the channel layer. It is the gate of the transistor, including a first portion provided above the channel layer and a second portion provided between the substrate, the channel layer, and a third side surface of the second portion or a fourth side surface facing the third side surface forms a gate electrode facing the semiconductor layer. A method of manufacturing a semiconductor device.

[0147] (Appendix 15) The method of manufacturing a semiconductor device according to Appendix 14, wherein the semiconductor layer is epitaxially grown on the first side surface, the second side surface, and a part of the lower surface of the channel layer.

[0148] (Appendix 16) The method of manufacturing a semiconductor device according to Appendix 15, which includes a step of removing the semiconductor layer formed on the first side surface and the second side surface of the channel layer. (Appendix 17) The channel layer is formed to include a first channel layer and a second channel layer provided above the first channel layer. The first portion is provided above the second channel layer, the second portion is provided between the substrate and the first channel layer, and a third portion of the gate electrode is provided between the first channel layer and the second channel layer to form the gate electrode. The method of manufacturing a semiconductor device according to any one of Appendices 14 to 16.

[0149] (Appendix 18) The method of manufacturing a semiconductor device according to any one of Appendices 14 to 17, wherein a first transistor having a conductivity type opposite to that of the transistor is provided by the substrate, the channel layer, the semiconductor layer, and the second portion in the gate electrode.

[0150] (Appendix 19) The method of manufacturing a semiconductor device according to any one of Appendices 14 to 18, wherein a sidewall insulating film made of a silicon nitride film is formed on the side surface of the gate electrode. (Supplementary Note 20) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 14 to 19, wherein a dummy electrode is formed before forming the gate electrode and the dummy electrode is replaced with the gate electrode.

Explanation of Signs

[0151] 10 Semiconductor device 11 Substrate 12 Impurity layer (channel cut layer) 13 Epitaxial layer 14 Channel layer 14a, 14b Impurity diffusion region 15a, 15b STI 16 Dummy gate 17 Hard mask 18 Sidewall insulating film 19 Semiconductor layer 20a, 20b Insulating layer 21a Source layer 21b Drain layer 22 Gate electrode 22a Portion 22a1, 22a2 Side surfaces 25 Transistor

Claims

1. In a semiconductor device including a fin-type structure transistor, a channel layer formed above a substrate and connected to the substrate via a semiconductor layer; a source layer that is a source of the transistor, is provided above the substrate and spaced apart from the substrate via a first insulating layer, and is provided on a first side surface of the channel layer; a drain layer that is a drain of the transistor, is provided above the substrate and spaced apart from the substrate via a second insulating layer, and is provided on a second side surface of the channel layer that faces the first side surface; a gate of the transistor, including a first portion provided above the channel layer and a second portion provided between the substrate, the channel layer, and the semiconductor layer, and a gate electrode in which a third side surface of the second portion or a fourth side surface facing the third side surface faces the semiconductor layer; A semiconductor device having the above.

2. The semiconductor device according to claim 1, wherein the channel layer is connected to the substrate via the semiconductor layer provided between the first insulating layer or the second insulating layer and the third side surface or the fourth side surface of the second portion.

3. The semiconductor device according to claim 1 or 2, wherein a first transistor having a conductivity type opposite to that of the transistor is provided by the substrate, the channel layer, the semiconductor layer, and the second portion in the gate electrode.

4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer contains a second impurity having a conductivity type opposite to that of a first impurity contained in the channel layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor layer contains a second impurity having the same conductivity type as a first impurity contained in the channel layer, and an impurity concentration of the semiconductor layer is lower than an impurity concentration of the channel layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein an impurity layer containing a third impurity having the same conductivity type as a first impurity contained in the channel layer and having an impurity concentration higher than an impurity concentration of the channel layer is formed on a surface of the substrate.

7. The semiconductor device according to any one of claims 1 to 6, wherein a part of upper surfaces of the first insulating layer and the second insulating layer below a sidewall insulating film formed on a sidewall of the first portion is in contact with a lower surface of the semiconductor layer formed on a lower surface of the channel layer.

8. The channel layer includes a first channel layer and a second channel layer provided above the first channel layer. A third portion of the gate electrode is further provided between the first channel layer and the second channel layer. The semiconductor device according to any one of claims 1 to 7.

9. The semiconductor device according to claim 8, wherein a second transistor having a conductivity type opposite to that of the transistor is provided by the first channel layer, the second channel layer, the semiconductor layer, and the third portion of the gate electrode.

10. In a method of manufacturing a semiconductor device including a fin-type structure transistor, a channel layer connected to the substrate via a semiconductor layer is formed above the substrate. A source layer that is a source of the transistor, is provided above the substrate and spaced apart from the substrate via a first insulating layer, and is provided on a first side surface of the channel layer is formed. [[ID=~9]]A drain layer that is a drain of the transistor, is provided above the substrate and spaced apart from the substrate via a second insulating layer, and is provided on a second side surface of the channel layer opposite to the first side surface is formed. A gate electrode that is a gate of the transistor, includes a first portion provided above the channel layer and a second portion provided between the substrate and the channel layer, and a third side surface or a fourth side surface opposite to the third side surface of the second portion faces the semiconductor layer is formed. A method of manufacturing a semiconductor device.

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