Semiconductor device, semiconductor device manufacturing method, and electronic device

Abstract

To achieve a high-quality semiconductor device including a diamond layer.SOLUTION: A semiconductor device 1 includes: a semiconductor layer 10; a diamond layer 20 provided in an inner region AR2 provided inside an outer peripheral region AR1 on a principal surface 10a of the semiconductor layer; and a protection film 140 provided in the outer peripheral region AR1. A via hole 80 extending into a semiconductor layer 10 while penetrating through the diamond layer 20 in the inner region AR2 is provided, and a via wire 90 is provided in the via hole 80. The semiconductor device 1 is obtained by dicing at a position on a lateral face 10b of the semiconductor layer 10. Since the diamond layer 20 does not exist at the position, a blade is used for dicing. In the semiconductor device 1, generation of dust of the via wire 90 at the dicing using the blade is suppressed, and thereby, short circuit caused by the dust of the via wire 90 can be suppressed. A high-quality semiconductor device 1 can be obtained at a high yield.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, and an electronic device.

Background Art

[0002] There is known a technique in which a nucleation layer is provided on the lower surface of an active layer provided with a metal contact on the upper surface of a gallium nitride (GaN)-based high electron mobility transistor (HEMT), and a diamond layer is provided using a chemical vapor deposition (CVD) method. Regarding this technique, further, there is known a technique of providing a via extending from a back contact metal provided on the back surface of the diamond layer to the middle of the active layer, or a via extending from the back contact metal to the metal contact on the upper surface of the active layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Regarding a semiconductor device, there is known a technique of bonding a diamond layer having a high thermal conductivity as a heat spreader to a semiconductor layer that generates heat during operation, and a technique of providing a via wiring that penetrates the diamond layer and extends into the semiconductor layer.

[0005] By the way, in the manufacture of such semiconductor devices using a diamond layer, it is conceivable to divide and separate the semiconductor layers of a plurality of semiconductor devices formed in a wafer state integrally with the diamond layer. As one of the general methods of separation, there is a method of dicing using a blade. However, in semiconductor devices using a diamond layer, the diamond layer is hard and it is difficult to adopt. As another method of separation, there is also a method of dicing using a laser. However, in this method, there is a risk that the semiconductor device may be damaged by heat during laser irradiation, or a short circuit may occur due to dust generated by laser ablation.

[0006] As yet another method of separation, at the same time as forming via holes for via wirings penetrating the diamond layer and the semiconductor layer, a trench is formed by removing the diamond layer and the semiconductor layer in a region corresponding to the dicing line by etching, and a method of dicing is also conceivable. However, in this method, when forming the via wiring, the metal material of the via wiring formed in the trench at the same time as in the via hole may generate dust during dicing and cause a short circuit.

[0007] On one aspect, the present invention aims to realize a high-quality semiconductor device including a diamond layer.

Means for Solving the Problems

[0008] In one aspect, a semiconductor device is provided, which includes a semiconductor layer, a diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer, a protective film provided in the outer peripheral region on the main surface of the semiconductor layer, a via hole penetrating the diamond layer and extending into the semiconductor layer, and a via wiring provided in the via hole.

[0009] Also, in one aspect, a step of forming a diamond layer on a main surface of a semiconductor layer, etching the diamond layer in a first region corresponding to a dicing line for dividing the semiconductor layer into individual pieces, and the diamond layer in a second region corresponding to a first via hole formed in the semiconductor layer of each divided individual piece, forming a trench penetrating the diamond layer in the first region and forming a second via hole penetrating the diamond layer in the second region, forming a protective film covering the main surface of the semiconductor layer in the trench, etching the semiconductor layer in the second via hole using the protective film as a mask to form the first via hole communicating with the second via hole and extending into the semiconductor layer, forming a via wiring in the communicating first via hole and second via hole, and dicing the semiconductor layer and the protective film covering the main surface in the trench at a position where the trench is formed, are included in a method of manufacturing a semiconductor device.

[0010] Also, in one aspect, an electronic device including the semiconductor device as described above is provided.

Effects of the Invention

[0011] On one side, it becomes possible to realize a high-quality semiconductor device including a diamond layer.

Brief Description of the Drawings

[0012]

Figure 1

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Embodiments for Carrying Out the Invention

[0013] First, an example of a semiconductor device will be described. FIG. 1 is a diagram for explaining an example of a semiconductor device. FIG. 1(A) schematically shows a cross-sectional view of a main part of a first example of the semiconductor device. FIG. 1(B) schematically shows a cross-sectional view of a main part of a second example of the semiconductor device.

[0014] The semiconductor device 1A shown in FIG. 1(A) is an example of a semiconductor device including a HEMT. The semiconductor device 1A has a semiconductor layer 10 including a stacked structure of a first semiconductor layer 11 and a second semiconductor layer 12. For example, SiC (silicon carbide) is used for the first semiconductor layer 11, and a nitride semiconductor such as GaN or AlGaN (aluminum gallium nitride) is used for the second semiconductor layer 12. A gate electrode 30, a source electrode 40, and a drain electrode 50 are provided on the second semiconductor layer 12, and a HEMT that forms a current path between the source electrode 40 and the drain electrode 50 using, as carriers, electrons of a two-dimensional electron gas (2DEG), for example, is formed as a transistor. An etching stopper 60 connected to the source electrode 40 through a wiring 70 is further provided on the second semiconductor layer 12. For example, a metal material is used for the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70. For the wiring 70, in addition to a metal layer formed on an insulating film (not shown), a metal wire or the like is used.

[0015] The semiconductor device 1A is provided with a via hole 80 that penetrates the semiconductor layer 10 (the first semiconductor layer 11 and the second semiconductor layer 12) and reaches the etching stopper 60. The etching stopper 60 has a function of stopping etching from the main surface 10a side of the semiconductor layer 10 using the mask layer 120 as a mask when forming the via hole 80 by etching, and also has a function as an electrode layer connected to the source electrode 40 through the wiring 70. A via wiring 90 is provided in the via hole 80. The via wiring 90 extends from inside the via hole 80 to the main surface 10a of the semiconductor layer 10. For example, a metal material is used for the via wiring 90.

[0016] In the semiconductor device 1A, the via wiring 90 is set to the ground (GND) potential. The source electrode 40 is GND-connected through the wiring 70, the etching stopper 60, and the via wiring 90. The structure for GND-connecting the source electrode 40 through the via wiring 90 is one of the structures capable of reducing the source inductance and is advantageous in terms of characteristics.

[0017] By the way, a semiconductor device generates heat during operation, and the characteristics of the transistor may deteriorate due to the heat. So far, various heat dissipation techniques for operating the transistor while suppressing the influence of such heat have been proposed. As one of the heat dissipation techniques, a technique of using a diamond layer with high thermal conductivity as a heat spreader is known.

[0018] The semiconductor device 1B shown in FIG. 1(B) is an example of a semiconductor device using a diamond layer 20 as a heat spreader. For example, in the semiconductor device 1B, the semiconductor layer 10 (its first semiconductor layer 11) is thinned, and the diamond layer 20 is bonded to the main surface 10a of the thinned semiconductor layer 10. When the semiconductor layer 10 is thinned, the thermal resistance between the transistor that generates heat during operation and the diamond layer 20 is reduced, which is advantageous for heat dissipation. Here, if the thermal resistance of the bonding interface between the semiconductor layer 10 and the diamond layer 20 is large, the heat conduction efficiency from the semiconductor layer 10 to the diamond layer 20 decreases, and the effect of using the diamond layer 20 as a heat spreader is weakened. Therefore, for the bonding between the semiconductor layer 10 and the diamond layer 20, a method with relatively low interfacial thermal resistance, such as surface activated bonding or atomic diffusion bonding, is adopted.

[0019] In the semiconductor device 1B, a via hole 80 is formed by etching using the mask layer 120 as a mask, and penetrates the diamond layer 20 and the semiconductor layer 10 to reach the etching stopper 60. A via wiring 90 is provided in the via hole 80. The via wiring 90 extends from inside the via hole 80 to the main surface 20a on the side opposite to the semiconductor layer 10 side of the diamond layer 20.

[0020] The semiconductor device 1B shown in FIG. 1(B) is different from the semiconductor device 1A shown in FIG. 1(A) in that it has such a configuration. In the semiconductor device 1B, a diamond layer 20 with high thermal conductivity joined to the semiconductor layer 10 functions as a heat spreader. As a result, the heat dissipation performance of the transistors formed in the semiconductor layer 10 and generating heat during operation is enhanced, and the degradation of their characteristics due to heat is suppressed.

[0021] By the way, in the manufacture of the semiconductor device 1B using the diamond layer 20 as described above, it is conceivable to integrally divide and separate into individual pieces the semiconductor layer 10 of a plurality of semiconductor devices 1B formed in a wafer state and the diamond layer 20 joined thereto.

[0022] As one of the general methods for separating into individual pieces, there is a method of dicing using a blade. However, in the semiconductor device 1B using the diamond layer 20, the diamond layer 20 is hard and it is difficult to adopt. As another method for separating into individual pieces, there is also a method of dicing using a laser. However, in this method, there is a risk that the semiconductor device 1B may be damaged by the heat during laser irradiation, or a short circuit may occur due to the dust generated by laser ablation.

[0023] As yet another method for separating into individual pieces, the following method is also conceivable. That is, simultaneously with the formation of via holes 80 for via wirings 90 penetrating the diamond layer 20 and the semiconductor layer 10, the diamond layer 20 and the semiconductor layer 10 in the region corresponding to the dicing line are removed by etching to form trenches, and it is a method of dicing. Such a method will be described with reference to FIGS. 2 to 7.

[0024] FIGS. 2 to 7 are diagrams for explaining an example of a method for manufacturing a semiconductor device. FIGS. 2 to 7 schematically show cross-sectional views of the main parts of each process of an example of a method for manufacturing a semiconductor device. Hereinafter, each process will be described in order.

[0025] FIG. 2 is a diagram showing an example of a process of attaching a support to a laminate and forming a mask layer. FIG. 2(A) schematically shows a plan view of the main part of the process. FIG. 2(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 2(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 2(B). FIG. 2(B) is a schematic cross-sectional view taken along line II-II of FIG. 2(A).

[0026] A laminate 2 as shown in FIGS. 2(A) and 2(B), that is, a laminate 2 including a semiconductor layer 10 (a first semiconductor layer 11 and a second semiconductor layer 12) provided with a gate electrode 30, a source electrode 40, a drain electrode 50, etc., and a diamond layer 20 joined to the semiconductor layer 10 is prepared. The laminate 2 includes semiconductor layers 10 and diamond layers 20 for a plurality of semiconductor devices formed in a wafer state. FIGS. 2(A) and 2(B) (as well as FIGS. 3(A) and 3(B), FIGS. 4(A) and 4(B), FIGS. 5(A) and 5(B), FIGS. 6(A) and 6(B), FIGS. 7(A) and 7(B)) illustrate a part of such a laminate 2 in a wafer state.

[0027] For example, a semiconductor layer 10 is formed in which a second semiconductor layer 12 including a channel layer such as GaN and a barrier layer such as AlGaN is laminated on a first semiconductor layer 11 such as SiC as a base. A gate electrode 30, a source electrode 40, a drain electrode 50, an etching stopper 60, and a wiring 70 are formed at predetermined positions of the second semiconductor layer 12 in the semiconductor layer 10. Thereby, a structure including a HEMT in which a current path is formed in the second semiconductor layer 12 of the semiconductor layer 10 is formed. The diamond layer 20 is joined to the main surface 10a of the semiconductor layer 10 on the first semiconductor layer 11 side of the formed structure by a method such as surface activation bonding or atomic diffusion bonding. For example, such a method is used to obtain a laminate 2 having a laminated structure as shown in FIG. 2(B).

[0028] On the main surface side of the obtained laminate 2 where gate electrodes 30, source electrodes 40, drain electrodes 50, etc. are provided, as shown in Fig. 2(B), a support 110 is attached using an adhesive 100. On the main surface 20a of the diamond layer 20 joined to the semiconductor layer 10 of the laminate 2, a mask layer 120 having openings 121 in a predetermined region is formed. The openings 121 of the mask layer 120 are provided in the dicing line region 2a (first region) and the via formation region 2b (second region) of the laminate 2. The dicing line region 2a is a region corresponding to the dicing line for dicing the laminate 2 into individual semiconductor devices (their semiconductor layers 10). The via formation region 2b is a region corresponding to the vias formed in the individual semiconductor devices (their semiconductor layers 10) divided by dicing the laminate 2.

[0029] The mask layer 120 is made of a material that is resistant to dry etching of the diamond layer 20 using a gas containing oxygen (O-based gas) as described later, and dry etching of the semiconductor layer 10 using a gas containing fluorine (F-based gas) or a gas containing chlorine (Cl-based gas). For example, insulating materials such as SiO2 (silicon oxide) and metal materials such as Ni (nickel) and Al (aluminum) are used for the mask layer 120. Incidentally, when an insulating material such as SiO2 is used for the mask layer 120, its thickness is set to, for example, 10 μm or more. When a metal material such as Ni or Al is used for the mask layer 120, its thickness is set to, for example, on the order of several μm.

[0030] Fig. 3 is a diagram showing an example of the diamond layer etching process. Fig. 3(A) schematically shows a plan view of the main part of the process. Fig. 3(B) schematically shows a cross-sectional view of the main part of the process. Incidentally, Fig. 3(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in Fig. 3(B). Fig. 3(B) is a schematic cross-sectional view taken along the line III-III of Fig. 3(A).

[0031] After preparing the laminate 2 in which the support 110 is attached using the adhesive 100 on the semiconductor layer 10 side and the mask layer 120 is formed on the diamond layer 20 side, dry etching of the diamond layer 20 is performed using the mask layer 120 as a mask. An O-based gas is used for the dry etching of the diamond layer 20. By the dry etching using the mask layer 120 as a mask, as shown in FIGS. 3(A) and 3(B), the diamond layer 20 in the dicing line region 2a and the via formation region 2b of the laminate 2 is removed. The semiconductor layer 10 (its first semiconductor layer 11) functions as an etching stopper during the dry etching of the diamond layer 20.

[0032] By the dry etching of the diamond layer 20 using the mask layer 120, as shown in FIGS. 3(A) and 3(B), a trench 21 that penetrates the diamond layer 20 and reaches the semiconductor layer 10 is formed in the dicing line region 2a of the laminate 2. By the dry etching of the diamond layer 20 using the mask layer 120, as shown in FIGS. 3(A) and 3(B), a via hole 22 that penetrates the diamond layer 20 and reaches the semiconductor layer 10 is formed in the via formation region 2b of the laminate 2.

[0033] The trenches 21 are formed so as to surround (or separate) each diamond layer 20 of the semiconductor devices included in the laminate 2 in plural. The via holes 22 are formed in each diamond layer 20 of the semiconductor devices included in the laminate 2 in plural.

[0034] FIG. 4 is a diagram showing an example of the semiconductor layer etching process. FIG. 4(A) schematically shows a plan view of the main part of the process. FIG. 4(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 4(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 4(B). FIG. 4(B) is a cross-sectional schematic view taken along the line IV-IV of FIG. 4(A).

[0035] After the formation of trenches 21 and via holes 22 by dry etching of the diamond layer 20, dry etching of the semiconductor layer 10 in the trenches 21 and via holes 22 is further performed using the mask layer 120 as a mask. For the dry etching of the semiconductor layer 10, an F-based gas, or an F-based gas and a Cl-based gas are used. For example, when an F-based gas is used, both the first semiconductor layer 11 of SiC and the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN in the semiconductor layer 10 are dry-etched. Alternatively, when an F-based gas is used, the first semiconductor layer 11 of SiC in the semiconductor layer 10 is dry-etched, and when a Cl-based gas is used, the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN is dry-etched.

[0036] By dry etching the semiconductor layer 10 using the mask layer 120 as a mask, in the dicing line region 2a of the laminate 2, as shown in FIGS. 4(A) and 4(B), a trench 13 that communicates with the trench 21 of the diamond layer 20 and penetrates the semiconductor layer 10 is formed. As a result, in the dicing line region 2a of the laminate 2, a trench 81 that extends so as to penetrate the diamond layer 20 and the semiconductor layer 10 and reaches the adhesive 100 is formed. By dry etching the semiconductor layer 10 using the mask layer 120 as a mask, in the via formation region 2b of the laminate 2, as shown in FIGS. 4(A) and 4(B), a via hole 14 that communicates with the via hole 22 of the diamond layer 20 and penetrates the semiconductor layer 10 is formed. As a result, in the via formation region 2b of the laminate 2, a via hole 80 that extends so as to penetrate the diamond layer 20 and the semiconductor layer 10 and reaches the etch stopper 60 is formed.

[0037] In addition, for the formation of the trenches 13 and via holes 14 in the semiconductor layer 10, wet etching can also be used in addition to dry etching. In this case, a material resistant to wet etching is used for the mask layer 120.

[0038] The trenches 81 are formed to surround (or separate) each of the diamond layers 20 and semiconductor layers 10 of the semiconductor devices included in the plurality in the laminate 2. The via holes 80 are formed in each of the diamond layers 20 and semiconductor layers 10 of the semiconductor devices included in the plurality in the laminate 2.

[0039] FIG. 5 is a diagram showing an example of a via wiring formation process. FIG. 5(A) schematically shows a plan view of the main part of the process. FIG. 5(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 5(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 5(B). FIG. 5(B) is a schematic cross-sectional view taken along the line V-V of FIG. 5(A).

[0040] After the trenches 81 penetrating the diamond layer 20 and semiconductor layer 10 in the dicing line region 2a of the laminate 2 and the via holes 80 penetrating the diamond layer 20 and semiconductor layer 10 in the via formation region 2b are formed, as shown in FIGS. 5(A) and 5(B), the via wiring 90 is formed. For example, a stacked structure of Ti (titanium) and Au (gold) is formed as a seed layer in the trenches 81, via holes 80, and on the mask layer 120 in the laminate 2 using a sputtering method, and the via wiring 90 is formed by electrolytic plating of Au using this as a power supply layer.

[0041] The via wiring 90 is continuously formed in the via hole 80 provided to penetrate the diamond layer 20 and semiconductor layer 10 from above the mask layer 120 and is connected to the etching stopper 60 at the bottom of the via hole 80. The via wiring 90 is formed in the via hole 80 in this way, and is also continuously formed in the trench 81 provided to penetrate the diamond layer 20 and semiconductor layer 10 from above the mask layer 120. The via wiring 90 formed in the trench 81 is provided on the adhesive 100 at the bottom of the trench 81.

[0042] FIG. 6 is a diagram showing an example of the support separation process. FIG. 6(A) schematically shows a plan view of the main part of the process. FIG. 6(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 6(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 6(B). FIG. 6(B) is a schematic cross-sectional view taken along the line VI-VI of FIG. 6(A).

[0043] After the formation of the via wiring 90, as shown in FIGS. 6(A) and 6(B), the support 110 is peeled off and separated from the laminate 2 together with the adhesive 100. The laminate 2 after the separation of the support 110 and the adhesive 100 has a structure in which the via wiring 90 is exposed in the region of the trench 81, that is, the dicing line region 2a, as shown in the P1 part of FIG. 6(B).

[0044] FIG. 7 is a diagram showing an example of the dicing process. FIG. 7(A) schematically shows a plan view of the main part of the process. FIG. 7(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 7(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 7(B). The illustration of the dicing tape 150 shown in FIG. 7(B) is omitted in FIG. 7(A). FIG. 7(B) is a schematic cross-sectional view taken along the line VII-VII of FIG. 7(A).

[0045] After the separation of the support 110 and the adhesive 100, as shown in FIGS. 7(A) and 7(B), the diamond layer 20 side of the laminate 2 is attached to the dicing tape 150, and dicing is performed at the position of the dicing line region 2a, and the laminate 2 is divided into individual pieces. Each individual piece divided by dicing is obtained as a semiconductor device 1Ba.

[0046] Here, for example, a dicing method using a blade 130 as shown in FIG. 7(B) can be used for dicing the laminate 2. In the laminate 2, since the element existing in the dicing line region 2a is the via wiring 90 and the diamond layer 20 does not exist, dicing can be relatively easily performed at the position of the dicing line region 2a using the blade 130, and the laminate 2 can be fragmented.

[0047] When the diamond layer 20 is present in the dicing line area 2a, since the diamond layer 20 is hard, it is difficult to perform dicing with the blade 130. However, if the dicing line area 2a is the via wiring 90 as in this laminate 2, dicing with the blade 130 is possible. Further, by not using a laser for dicing, damage to the semiconductor device 1Ba due to heat during laser irradiation or short circuits caused by dust generated by laser ablation can be suppressed. Constraints on the structure and manufacturing process of the semiconductor device 1Ba due to providing laser transmissivity to the portion to be cut can also be suppressed.

[0048] However, in the method of dicing the via wiring 90 in the dicing line area 2a with the blade 130, when the via wiring 90 is diced, dust can be generated from the metal material of the relatively fragile via wiring 90 in the diced P2 portion. If such dust of the metal material adheres to conductor portions such as the gate electrode 30, source electrode 40, drain electrode 50, etching stopper 60, and wiring 70, there is a risk of causing a short circuit. Therefore, in the method as shown in FIGS. 2 to 7 above, it may happen that a high-quality semiconductor device 1Ba including a diamond layer cannot be realized.

[0049] In view of the above points, here, a configuration and method as shown in the following first embodiment are adopted to realize a high-quality semiconductor device including a diamond layer. [First Embodiment] FIG. 8 is a diagram for explaining an example of a semiconductor device according to the first embodiment. FIG. 8 schematically shows a cross-sectional view of a main part of an example of a semiconductor device according to the first embodiment.

[0050] The semiconductor device 1 shown in Fig. 8 is an example of a semiconductor device including a HEMT. The semiconductor device 1 has a semiconductor layer 10 including a stacked structure of a first semiconductor layer 11 and a second semiconductor layer 12. For example, SiC is used for the first semiconductor layer 11, and a nitride semiconductor such as GaN or AlGaN is used for the second semiconductor layer 12. A gate electrode 30, a source electrode 40, and a drain electrode 50 are provided on the second semiconductor layer 12, and a HEMT, which forms a current path between the source electrode 40 and the drain electrode 50 using, for example, 2DEG electrons as carriers, is formed as an example of a transistor. An etching stopper 60 (electrode layer) connected to the source electrode 40 through a wiring 70 is further provided on the second semiconductor layer 12. For example, a metal material is used for the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70. For the wiring 70, in addition to a metal layer formed on an insulating film (not shown), a metal wire or the like is used.

[0051] In the semiconductor device 1, a diamond layer 20 functioning as a heat spreader is provided on a main surface 10a of the semiconductor layer 10 on the side opposite to the main surface side where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided. For example, by thinning the semiconductor layer 10 (the first semiconductor layer 11 thereof), the thermal resistance between the HEMT that generates heat during operation and the diamond layer 20 is reduced. In the semiconductor device 1, the diamond layer 20 is provided in an inner region AR2 of the main surface 10a of the semiconductor layer 10, which is inside the outer peripheral region AR1. Here, the inner region AR2 is a region surrounded by the outer peripheral region AR1 around it. The diamond layer 20 is joined to the inner region AR2 of the main surface 10a of the semiconductor layer 10 by a method such as surface activation bonding or atomic diffusion bonding, which results in a relatively small interfacial thermal resistance with the semiconductor layer 10.

[0052] In the semiconductor device 1, on the main surface 20a of the diamond layer 20, which is opposite to the semiconductor layer 10 side, a mask layer 120 having openings 121 is provided in a region corresponding to the outer peripheral region AR1 and a region corresponding to the via hole 80 provided in the inner region AR2. The mask layer 120 is made of a material resistant to dry etching of the diamond layer 20 using an O-based gas and dry etching of the semiconductor layer 10 using an F-based gas or a Cl-based gas. For example, as the mask layer 120, an insulating material such as SiO2 (e.g., with a thickness of 10 μm or more) or a metal material such as Ni or Al (e.g., with a thickness on the order of several μm) is used.

[0053] In the semiconductor device 1, a protective film 140 is provided on the outer peripheral region AR1 of the main surface 10a of the semiconductor layer 10, that is, the outer peripheral region AR1 of the main surface 10a of the semiconductor layer 10 that is not covered by the diamond layer 20. The protective film 140 covers the outer peripheral region AR1 of the main surface 10a of the semiconductor layer 10 and is provided so as to extend from the outer peripheral region AR1 to the side surface 20b of the diamond layer 20 (corresponding to the inner side surface of the trench 21 described later) and further onto the mask layer 120 provided on the main surface 20a of the diamond layer 20. The protective film 140 is made of a material resistant to dry etching of the semiconductor layer 10 using an F-based gas or a Cl-based gas. For example, as the protective film 140, a metal material such as Ni or Al with a thickness of 1 μm to 5 μm is used.

[0054] The semiconductor device 1 is provided with a via hole 80 that penetrates the diamond layer 20 and extends into the semiconductor layer 10. The via hole 80 is provided so as to penetrate the diamond layer 20 provided in the inner region AR2 of the main surface 10a of the semiconductor layer 10 and the semiconductor layer 10 (the first semiconductor layer 11 and the second semiconductor layer 12) and reach the etching stopper 60. The etching stopper 60 has a function of stopping etching from the main surface 20a side of the diamond layer 20 when forming the via hole 80 by etching, and also has a function as an electrode layer connected to the source electrode 40 through the wiring 70.

[0055] The protective film 140 is continuously provided on the surface of the diamond layer 20 excluding the via hole 80, that is, on the main surface 20a and the side surface 20b. In the example of FIG. 8, it extends from the outer peripheral region AR1 of the main surface 10a of the semiconductor layer 10 to the side surface 20b of the diamond layer 20, and further extends to a part on the mask layer 120 provided on the main surface 20a of the diamond layer 20 (on the main surface 20a). In addition, as long as the protective film 140 is provided on the surface of the diamond layer 20 excluding the via hole 80, it may be provided so as to extend over the entire mask layer 120.

[0056] In the semiconductor device 1, a via wiring 90 is provided in the via hole 80. The via wiring 90 extends from within the via hole 80 onto the mask layer 120 provided on the main surface 20a of the diamond layer 20. The via wiring 90 is further provided so as to extend onto the mask layer 120, the side surface 20b of the diamond layer 20, and the protective film 140 provided in the outer peripheral region AR1 on the main surface 10a of the semiconductor layer 10. The via wiring 90 is provided so as to cover the protective film 140 and the diamond layer 20, and a part thereof is provided in the via hole 80. For example, a metal material is used for the via wiring 90.

[0057] In the manufacture of the semiconductor device 1 having the above configuration, the semiconductor layers 10 of a plurality of semiconductor devices 1 formed in a wafer state are divided and separated integrally with the diamond layer 20 to which they are joined, and are singulated. In the case of the semiconductor device 1 shown in FIG. 8, it is singulated by dicing at the position of the side surface 10b of the semiconductor layer 10. In the semiconductor device 1, the semiconductor layer 10, the protective film 140, and the via wiring 90 exist at the dicing position, while the hard diamond layer 20 does not exist. Therefore, the semiconductor device 1 is singulated by dicing using a blade.

[0058] In the semiconductor device 1, as in the methods shown in FIGS. 2 to 7 above, since there is no via wiring 90 on the main surface where the gate electrode 30, source electrode 40, drain electrode 50, etc. are provided, even when dicing with a blade from the main surface side, generation of dust of the metal material of the via wiring 90 can be suppressed. In the semiconductor device 1, since generation of dust of the metal material during dicing is suppressed in this way, adhesion of dust to conductor portions such as the gate electrode 30, source electrode 40, drain electrode 50, etching stopper 60, and wiring 70, and generation of a short circuit due to this can be suppressed. Therefore, a high-quality semiconductor device 1 including the diamond layer 20 is realized.

[0059] Subsequently, an example of a method for manufacturing the semiconductor device 1 having the above-described configuration will be described with reference to FIGS. 9 to 14. FIGS. 9 to 14 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. In the method for manufacturing a semiconductor device according to the first embodiment, the steps up to the steps shown in FIGS. 2 and 3 above can be made the same. The steps after the steps shown in FIGS. 2 and 3 above will be sequentially described below with reference to FIGS. 9 to 14.

[0060] FIG. 9 is a diagram showing an example of a protective film formation step according to the first embodiment. FIG. 9(A) schematically shows a plan view of the main part of the step. FIG. 9(B) schematically shows a cross-sectional view of the main part of the step. Note that FIG. 9(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 9(B). FIG. 9(B) is a schematic cross-sectional view taken along line IX-IX of FIG. 9(A).

[0061] In the manufacture of the semiconductor device 1, as described above, a laminate 2 including a semiconductor layer 10 (a first semiconductor layer 11 and a second semiconductor layer 12) provided with a gate electrode 30, a source electrode 40, a drain electrode 50, etc., and a diamond layer 20 joined to the semiconductor layer 10 is prepared (FIG. 2). The laminate 2 includes semiconductor layers 10 and diamond layers 20 for a plurality of semiconductor devices 1 formed in a wafer state. FIGS. 2(A) and 2(B) (as well as FIGS. 3(A) and 3(B), FIGS. 9(A) and 9(B), FIGS. 10(A) and 10(B), FIGS. 11(A) and 11(B), FIGS. 12(A) and 12(B), FIGS. 13(A) and 13(B), FIG. 14) illustrate a part of such a wafer-state laminate 2.

[0062] On the main surface side of such a laminate 2 where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, a support 110 is attached using an adhesive 100, and a mask layer 120 having an opening 121 in a predetermined region is formed on the main surface 20a of the diamond layer 20 (FIG. 2). The opening 121 of the mask layer 120 is provided in a dicing line region 2a and a via formation region 2b (FIG. 2). The dicing line region 2a is a region corresponding to a dicing line for dividing the laminate 2 into individual semiconductor devices 1 (their semiconductor layers 10) by dicing. The via formation region 2b is a region corresponding to vias formed in each individual semiconductor device 1 (its semiconductor layer 10) divided by dicing the laminate 2.

[0063] Next, using the mask layer 120 as a mask, dry etching of the diamond layer 20 using an O-based gas is performed (FIG. 3). By this dry etching, a trench 21 that penetrates the diamond layer 20 and reaches the semiconductor layer 10 is formed in the dicing line region 2a of the laminate 2, and a via hole 22 that penetrates the diamond layer 20 and reaches the semiconductor layer 10 is formed in the via formation region 2b (FIG. 3).

[0064] The trenches 21 are formed to surround (or separate) each diamond layer 20 of the semiconductor devices 1 included in the plurality in the laminate 2. The via holes 22 are formed in each diamond layer 20 of the semiconductor devices 1 included in the plurality in the laminate 2.

[0065] After the formation of the trenches 21 and the via holes 22 by dry etching of the diamond layer 20, as shown in FIGS. 9(A) and 9(B), a protective film 140 is formed in the trenches 21 in the dicing line region 2a. The protective film 140 is formed using a metal material such as Ni or Al, which has resistance to F-based gas or Cl-based gas used for dry etching of the semiconductor layer 10. The protective film 140 is formed to cover the inner surface of the trench 21, that is, the main surface 10a of the semiconductor layer 10 at the bottom of the trench 21 and the side surfaces inside the trench 21, and to extend onto the mask layer 120 provided on the main surface 20a of the diamond layer 20.

[0066] As shown in FIGS. 9(A) and 9(B), the protective film 140 is continuously formed from the main surface 10a of the semiconductor layer 10 at the bottom of the trench 21 so as to cover the surface of the diamond layer 20 except for the via holes 22. The protective film 140 is not formed in the via holes 22. That is, in the via formation region 2b, the main surface 10a of the semiconductor layer 10 at the bottom of the via hole 22 and the side surfaces inside the via hole 22 are in an exposed state. In the examples of FIGS. 9(A) and 9(B), the protective film 140 formed to extend from the inner surface of the trench 21 to a part on the mask layer 120 is shown. In addition, the protective film 140 may be formed to extend over the entire mask layer 120 as long as it is formed on the surface of the diamond layer 20 except for the via holes 22. Here, taking the case where the protective film 140 is formed as shown in FIGS. 9(A) and 9(B) as an example, the subsequent steps will be described.

[0067] FIG. 10 is a diagram showing an example of a semiconductor layer etching process according to the first embodiment. FIG. 10(A) schematically shows a plan view of the main part of the process. FIG. 10(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 10(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 10(B). FIG. 10(B) is a schematic cross-sectional view taken along the line X-X of FIG. 10(A).

[0068] After the formation of the protective film 140, as shown in FIGS. 10(A) and 10(B), dry etching of the semiconductor layer 10 is performed using the mask layer 120 and the protective film 140 as masks. When the protective film 140 is formed over the entire mask layer 120, dry etching of the semiconductor layer 10 is performed using the protective film 140 covering the mask layer 120 as a mask. For the dry etching of the semiconductor layer 10, an F-based gas, or an F-based gas and a Cl-based gas are used. For example, when an F-based gas is used, both the first semiconductor layer 11 of SiC and the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN in the semiconductor layer 10 are dry-etched. Alternatively, when an F-based gas is used, the first semiconductor layer 11 of SiC in the semiconductor layer 10 is dry-etched, and when a Cl-based gas is used, the second semiconductor layer 12 of a nitride semiconductor such as GaN or AlGaN is dry-etched.

[0069] By dry-etching the semiconductor layer 10 using the mask layer 120 and the protective film 140 as masks, as shown in FIGS. 10(A) and 10(B), a via hole 14 that communicates with the via hole 22 of the diamond layer 20 and penetrates the semiconductor layer 10 is formed in the via formation region 2b of the laminate 2. Thereby, in the via formation region 2b of the laminate 2, a via hole 80 is formed that extends so as to penetrate the diamond layer 20 and the semiconductor layer 10 and reaches the etching stopper 60.

[0070] Note that, in addition to dry etching, wet etching can also be used for the formation of the via hole 14 in the semiconductor layer 10. In this case, a material having resistance to wet etching is used for the mask layer 120 and the protective film 140.

[0071] The via holes 80 are formed in the diamond layers 20 and semiconductor layers 10 of each of the semiconductor devices 1 included in the plurality in the laminate 2. On the other hand, during the dry etching of the semiconductor layer 10 in the via formation region 2b, in the dicing line region 2a of the laminate 2, the trenches 21 of the diamond layer 20 formed therein are covered with a protective film 140 having resistance to the dry etching of the semiconductor layer 10. Therefore, in the dicing line region 2a, the semiconductor layer 10 is not etched, and the trenches 21 of the diamond layer 20 remain covered with the protective film 140.

[0072] FIG. 11 is a diagram showing an example of a via wiring formation process according to the first embodiment. FIG. 11(A) schematically shows a plan view of the main part of the process. FIG. 11(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 11(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 11(B). FIG. 11(B) is a cross-sectional schematic view taken along line XI-XI of FIG. 11(A).

[0073] After the formation of the via holes 80 penetrating the diamond layer 20 and the semiconductor layer 10 in the via formation region 2b of the laminate 2, as shown in FIGS. 11(A) and 11(B), the via wiring 90 is formed. The via wiring 90 is formed so as to cover the inner surface of the via hole 80, that is, the etching stopper 60 at the bottom of the via hole 80 and the inner side surface of the via hole 80, and extend onto the mask layer 120 provided on the main surface 20a of the diamond layer 20. The via wiring 90 is also formed on the protective film 140 that covers the inner surface of the trench 21 of the diamond layer 20 in the dicing line region 2a, that is, the trench 21 that penetrates the diamond layer 20 but does not extend into the semiconductor layer 10, and extends onto the mask layer 120. The via wiring 90 covers the diamond layer 20 provided with the mask layer 120 and the protective film 140 of the trench 21, and is formed so that a part thereof is provided in the via hole 80 (via holes 22, 14).

[0074] For example, a stacked structure of Ti and Au is formed as a seed layer by sputtering within the via hole 80 of the laminate 2, on the mask layer 120, and on the protective film 140 covering the trench 21, and the via wiring 90 is formed by electrolytic plating of Au using this as a power supply layer.

[0075] FIG. 12 is a diagram showing an example of a support separation process according to the first embodiment. FIG. 12(A) schematically shows a plan view of the main part of the process. FIG. 12(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 12(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 12(B). FIG. 12(B) is a schematic cross-sectional view taken along the line XII-XII of FIG. 12(A).

[0076] After the formation of the via wiring 90, as shown in FIGS. 12(A) and 12(B), the support 110 is peeled off and separated from the laminate 2 together with the adhesive 100. In the laminate 2 after the separation of the support 110 and the adhesive 100, the via wiring 90 is not exposed on the main surface where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, and the via wiring 90 is not exposed in the dicing line region 2a on the main surface side.

[0077] FIG. 13 is a diagram showing an example of a dicing process according to the first embodiment. FIG. 13(A) schematically shows a plan view of the main part of the process. FIG. 13(B) schematically shows a cross-sectional view of the main part of the process. Note that FIG. 13(A) is a schematic plan view when viewed from the diamond layer 20 side of the laminate 2 shown in FIG. 13(B). In FIG. 13(A), the illustration of the dicing tape 150 shown in FIG. 13(B) is omitted. FIG. 13(B) is a schematic cross-sectional view taken along the line XIII-XIII of FIG. 13(A).

[0078] After the separation of the support 110 and the adhesive 100, as shown in FIGS. 13(A) and 13(B), the laminated body 2 has the diamond layer 20 side attached to the dicing tape 150, and dicing is performed at the position of the dicing line region 2a to be divided into individual pieces. Each individual piece divided by dicing becomes a semiconductor device 1. For dicing the laminated body 2, for example, a dicing method using a blade 130 as shown in FIG. 13(B) is used. In the laminated body 2, the semiconductor layer 10, the protective film 140, and the via wiring 90 exist at the position to be diced, while the hard diamond layer 20 does not exist. Therefore, the semiconductor device 1 is fragmented by dicing using the blade 130.

[0079] In dicing using the blade 130, from the main surface side where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, the semiconductor layer 10, the protective film 140, and the via wiring 90 are diced with the blade 130. Since the via wiring 90 does not exist on the main surface where the gate electrode 30, the source electrode 40, and the drain electrode 50, etc. are provided, even if dicing is performed with the blade 130 from the main surface side, the generation of dust from the metal material of the via wiring 90 can be suppressed. Since the generation of dust of the metal material during dicing is thus suppressed, the adhesion of dust of the metal material to the conductor portions such as the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70, and the occurrence of a short circuit due thereto can be suppressed.

[0080] In each semiconductor device 1 fragmented by dicing, in the main surface 10a of the semiconductor layer 10, the region (the cut bottom surface of the trench 21) where the trench 21 (the trench 21 cut by dicing) of the diamond layer 20 is formed corresponds to the outer peripheral region AR1 shown in FIG. 8 above. In each semiconductor device 1 fragmented by dicing, in the main surface 10a of the semiconductor layer 10, the region inside the region (the cut bottom surface of the trench 21) where the trench 21 (the trench 21 cut by dicing) of the diamond layer 20 is formed corresponds to the inner region AR2 shown in FIG. 8 above.

[0081] FIG. 14 is a diagram showing an example of a pickup process according to the first embodiment. FIG. 14 schematically shows a cross-sectional view of the main part of the process. After dicing using the blade 130, as shown in FIG. 14, each diced individual piece is picked up from the dicing tape 150. Thereby, the semiconductor device 1 having the configuration shown in FIGS. 14 and 8 above is obtained.

[0082] In the manufacture of the semiconductor device 1 (FIGS. 9 to 14), trenches 21 are formed in the diamond layer 20 in the dicing line region 2a, and the trenches 21 are covered with a protective film 140. Then, dicing is performed along the dicing line region 2a, and the semiconductor layer 10 is cut at the positions of the trenches 21 of the diamond layer 20 covered with the protective film 140. As a result, each semiconductor device 1 (FIG. 8) obtained by dicing has a structure in which the diamond layer 20 is formed in the inner region AR2 inside the outer peripheral region AR1 corresponding to the bottom surface of the trench 21 on the main surface 10a of the semiconductor layer 10, and the outer peripheral region AR1 is covered with the protective film 140.

[0083] Alternatively, it can be said that the side surface 10b of the semiconductor layer 10 protrudes outside the side surface 20b of the diamond layer 20 in each semiconductor device 1 (FIG. 8) obtained by dicing. Each obtained semiconductor device 1 also has a structure in which the diamond layer 20 is formed in the inner region AR2 inside the outer peripheral region AR1 corresponding to the protruding portion on the main surface 10a of the semiconductor layer 10, and the outer peripheral region AR1 is covered with the protective film 140.

[0084] Each semiconductor device 1 (FIG. 8) obtained by dicing is provided with via holes 80 so as to penetrate the diamond layer 20 surrounded by the outer peripheral region AR1 and the protective film 140 provided therein and extend into the semiconductor layer 10, and via wirings 90 are provided therein.

[0085] In the manufacture of the semiconductor device 1 (Figs. 9 to 14), as described above, the blade 130 is used for dicing the semiconductor layer 10, the protective film 140, and the via wiring 90 in the dicing line region 2a. In the dicing using the blade 130 from the main surface side where the gate electrode 30, the source electrode 40, the drain electrode 50, etc. are provided, since the via wiring 90 does not exist on the main surface, generation of dust of the metal material of the via wiring 90 is suppressed. Therefore, adhesion of dust of the metal material to conductor portions such as the gate electrode 30, the source electrode 40, the drain electrode 50, the etching stopper 60, and the wiring 70, and occurrence of a short circuit due to this are suppressed. As a result, it becomes possible to manufacture the semiconductor device 1 while suppressing a decrease in yield.

[0086] In the manufacture of the semiconductor device 1 (Figs. 9 to 14), since dicing using the blade 130 is possible, it is not necessary to perform dicing using a laser. By not using a laser for dicing, damage to the semiconductor device 1 due to heat during laser irradiation and occurrence of a short circuit due to dust generated by laser ablation can be suppressed. It is also possible to suppress restrictions on the structure and manufacturing process of the semiconductor device 1 in order to give laser transparency to the portion to be cut.

[0087] According to the configuration and method as described in the first embodiment, a high-quality semiconductor device 1 including the diamond layer 20 is realized, and such a high-quality semiconductor device 1 is realized while suppressing a decrease in yield.

[0088] Still, in the semiconductor device 1 described above, in addition to SiC, silicon (Si), GaN, aluminum nitride (AlN), semiconductor on insulator (SOI), etc. may be used for the first semiconductor layer 11 of the semiconductor layer 10. For the second semiconductor layer 12 of the semiconductor layer 10, in addition to GaN and AlGaN, nitride semiconductors such as InGaN (indium gallium nitride), InAlGaN (indium aluminum gallium nitride), and AlN may be used. The second semiconductor layer 12 may contain one or more of such nitride semiconductors. Further, for the second semiconductor layer 12, semiconductors such as Si, compound semiconductors such as SiC, GaAs (gallium arsenide), InP (indium phosphide), and SiGe (silicon germanium) may be used, and one or more of such compound semiconductors may be contained. Even when such various materials are used for the semiconductor layer 10, the semiconductor device 1 can be formed according to the above example.

[0089] Also, in the semiconductor device 1 described above, in addition to the HEMT using 2DEG electrons as carriers, transistors using holes of two-dimensional hole gas (2DHG) as carriers, insulated gate transistors having a metal insulator semiconductor (MIS) structure, insulated gate bipolar transistors (IGBTs), diodes, etc., various semiconductor elements may be provided in the semiconductor layer 10. A plurality of the same type or different types of semiconductor elements may be mounted on the semiconductor layer 10.

[0090] Also, in the semiconductor device 1 described above, the number of via holes 80 and the number of etching stoppers 60 are not limited to one each. The semiconductor device 1 may be provided with a plurality of via holes 80 that penetrate the diamond layer 20 and the semiconductor layer 10 and are connected to one or more etching stoppers 60.

[0091] The above describes the first embodiment. The semiconductor device 1 having the configuration as described in the first embodiment can be applied to various electronic devices. As an example, the case where the semiconductor device 1 having the above configuration is applied to a semiconductor package, a power factor improvement circuit, a power supply device, and an amplifier will be described below.

[0092] [Second Embodiment] Here, an application example of the semiconductor device 1 having the above configuration to a semiconductor package will be described as the second embodiment.

[0093] FIG. 15 is a diagram for explaining an example of a semiconductor package according to the second embodiment. FIG. 15 schematically shows a plan view of a main part of an example of a semiconductor package according to the second embodiment.

[0094] The semiconductor package 200 shown in FIG. 15 is an example of a discrete package. The semiconductor package 200 includes the semiconductor device 1 (FIG. 8 etc.) as described in the above first embodiment, a lead frame 210 on which the semiconductor device 1 is mounted, and a resin 220 that seals them.

[0095] The semiconductor device 1 including a transistor such as HEMT is mounted on the die pad 210a of the lead frame 210 using a die attach material or the like (not shown). The semiconductor device 1 is provided with a pad 30a connected to the gate electrode 30, a pad 40a connected to the source electrode 40, and a pad 50a connected to the drain electrode 50. The pad 30a, the pad 40a, and the pad 50a are respectively connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 using a wire 230 such as Al. A via wiring 90 connected to the source electrode 40 may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder. The lead frame 210, the semiconductor device 1 mounted thereon, and the wire 230 connecting them are sealed with the resin 220 so that a part of each of the gate lead 211, the source lead 212, and the drain lead 213 is exposed.

[0096] The semiconductor device 1 described in the above first embodiment is used, and a semiconductor package 200 having such a configuration is obtained. As described above, in the manufacture of the semiconductor device 1, a trench 21 penetrating the diamond layer 20 in the dicing line region 2a of the wafer-like laminate 2 including the semiconductor layer 10 and the diamond layer 20 joined to the main surface 10a thereof is formed by etching. Then, the trench 21 is covered with the protective film 140, a via hole 80 is formed in the semiconductor layer 10 by etching, a via wiring 90 is formed therein, and dicing is performed at the position of the trench 21 covered with the protective film 140. By dicing, a diamond layer 20 is provided in the inner region AR2 inside the outer peripheral region AR1 on the main surface 10a of the semiconductor layer 10 on the side where the diamond layer 20 is joined, and a semiconductor device 1 provided with the protective film 140 in the outer peripheral region AR1 is obtained. In the manufacture of the semiconductor device 1, a blade 130 is used for dicing, and since the diamond layer 20 in the dicing line region 2a is removed and the semiconductor layer 10 remains, generation of dust of the metal material of the via wiring 90 is suppressed, and generation of a short circuit due to the dust is suppressed. Thereby, a high-quality semiconductor device 1 including the diamond layer 20 is realized. Such a semiconductor device 1 is used, and a high-quality semiconductor package 200 is realized.

[0097] [Third Embodiment] Here, an application example of the semiconductor device 1 having the above configuration to a power factor improvement circuit will be described as a third embodiment.

[0098] FIG. 16 is a diagram for explaining an example of a power factor improvement circuit according to the third embodiment. FIG. 16 shows an equivalent circuit diagram of an example of a power factor improvement circuit according to the third embodiment. The power factor correction (PFC) circuit 300 shown in FIG. 16 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0099] In the PFC circuit 300, the drain electrode of the switch element 310 is connected to the anode terminal of the diode 320 and one terminal of the choke coil 330. The source electrode of the switch element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to the cathode terminal of the diode 320. Also, a gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a DC power supply (DC) is taken out between both terminals of the capacitor 350.

[0100] For example, the semiconductor device 1 including a transistor such as a HEMT is used for the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in the manufacture of the semiconductor device 1, in the diamond layer 20 in the dicing line region 2a of the wafer-like laminate 2 including the semiconductor layer 10 and the diamond layer 20 joined to the main surface 10a thereof, a trench 21 penetrating therethrough is formed by etching. Then, the trench 21 is covered with the protective film 140, a via hole 80 is formed in the semiconductor layer 10 by etching, a via wiring 90 is formed therein, and dicing is performed at the position of the trench 21 covered with the protective film 140. By dicing, the diamond layer 20 is provided in the inner region AR2 inside the outer peripheral region AR1 on the main surface 10a on the side where the diamond layer 20 of the semiconductor layer 10 is joined, and the semiconductor device 1 provided with the protective film 140 in the outer peripheral region AR1 is obtained. In the manufacture of the semiconductor device 1, a blade 130 is used for dicing, and in the structure where the diamond layer 20 in the dicing line region 2a is removed and the semiconductor layer 10 remains, generation of dust of the metal material of the via wiring 90 is suppressed, and generation of a short circuit due to the dust is suppressed. Thereby, a high-quality semiconductor device 1 including the diamond layer 20 is realized. Such a semiconductor device 1 is used, and a high-quality PFC circuit 300 is realized.

[0101] [Fourth Embodiment] Here, an application example of the semiconductor device 1 having the above-described configuration to a power supply device will be described as a fourth embodiment.

[0102] FIG. 17 is a diagram for explaining an example of a power supply device according to the fourth embodiment. FIG. 17 shows an equivalent circuit diagram of an example of a power supply device according to the fourth embodiment. The power supply device 400 shown in FIG. 17 includes a primary-side circuit 410, a secondary-side circuit 420, and a transformer 430 provided between the primary-side circuit 410 and the secondary-side circuit 420.

[0103] The primary-side circuit 410 includes a PFC circuit 300 as described in the above third embodiment, and an inverter circuit connected between both terminals of the capacitor 350 of the PFC circuit 300, for example, a full-bridge inverter circuit 440. The full-bridge inverter circuit 440 includes a plurality (here, four as an example) of switch elements 441, 442, 443, and 444.

[0104] The secondary-side circuit 420 includes a plurality (here, three as an example) of switch elements 421, 422, and 423. For example, the above-described semiconductor device 1 including a transistor such as a HEMT is used for the switch element 310 of the PFC circuit 300 and the switch elements 441 to 444 of the full-bridge inverter circuit 440 included in the primary-side circuit 410 of the power supply device 400 having such a configuration. For example, normal MIS-type transistors using Si are used for the switch elements 421 to 423 of the secondary-side circuit 420 of the power supply device 400.

[0105] As described above, in the manufacture of the semiconductor device 1, a trench 21 penetrating therethrough is formed by etching in the diamond layer 20 in the dicing line region 2a of the wafer-like laminate 2 including the semiconductor layer 10 and the diamond layer 20 joined to the main surface 10a thereof. Then, the trench 21 is covered with the protective film 140, a via hole 80 is formed by etching in the semiconductor layer 10, a via wiring 90 is formed therein, and dicing is performed at the position of the trench 21 covered with the protective film 140. By dicing, the diamond layer 20 is provided in the inner region AR2 inside the outer peripheral region AR1 on the main surface 10a on the side where the diamond layer 20 of the semiconductor layer 10 is joined, and the semiconductor device 1 provided with the protective film 140 in the outer peripheral region AR1 is obtained. In the manufacture of the semiconductor device 1, a blade 130 is used for dicing, and in the structure where the diamond layer 20 in the dicing line region 2a is removed and the semiconductor layer 10 is left, the generation of dust of the metal material of the via wiring 90 is suppressed, and the generation of a short circuit due to the dust is suppressed. Thereby, a high-quality semiconductor device 1 including the diamond layer 20 is realized. Such a semiconductor device 1 is used, and a high-quality power supply device 400 is realized.

[0106] [Fifth Embodiment] Here, an application example of the semiconductor device 1 having the above-described configuration to an amplifier will be described as a fifth embodiment.

[0107] FIG. 18 is a diagram for explaining an example of an amplifier according to the fifth embodiment. FIG. 18 shows an equivalent circuit diagram of an example of an amplifier according to the fifth embodiment. The amplifier 500 shown in FIG. 18 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0108] The digital predistortion circuit 510 compensates for nonlinear distortion in the input signal. The mixer 520 mixes the input signal SI, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 540 amplifies the signal resulting from mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with the AC signal in the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-power amplifier.

[0109] The power amplifier 540 of the amplifier 500 having such a configuration uses the semiconductor device 1 including a transistor such as a HEMT. As described above, in the manufacture of the semiconductor device 1, trenches 21 are formed by etching through the diamond layer 20 in the dicing line region 2a of the wafer-state stack 2, which includes the semiconductor layer 10 and the diamond layer 20 bonded to the main surface 10a. The trenches 21 are then covered with a protective film 140, and via holes 80 are etched in the semiconductor layer 10, through which via wiring 90 is formed. Dicing is then performed at the trenches 21 covered with the protective film 140. Dicing results in a semiconductor device 1 in which the diamond layer 20 is provided in an inner region AR2, located inside the outer peripheral region AR1, on the main surface 10a of the semiconductor layer 10 on the side where the diamond layer 20 is bonded, and the protective film 140 is provided in the outer peripheral region AR1. In the manufacture of the semiconductor device 1, a blade 130 is used for dicing. The diamond layer 20 in the dicing line region 2a is removed, leaving the semiconductor layer 10. This structure reduces dust from the metal material of the via wiring 90 and reduces the occurrence of short circuits due to the dust. This makes it possible to realize a high-quality semiconductor device 1 including the diamond layer 20. Using such a semiconductor device 1, a high-quality amplifier 500 is realized.

[0110] Various electronic devices to which the semiconductor device 1 is applied (such as the semiconductor package 200, PFC circuit 300, power supply device 400, and amplifier 500 described in the second to fifth embodiments) can be mounted in various electronic devices or electronic devices, such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, and manufacturing devices.

[0111] The following additional notes are provided regarding the above-described embodiment. (Supplementary Note 1) A semiconductor layer; a diamond layer provided in an inner region on the main surface of the semiconductor layer, the inner region being more inward than an outer circumferential region; a protective film provided in the outer peripheral region of the main surface of the semiconductor layer; a via hole extending through the diamond layer into the semiconductor layer; a via wiring provided in the via hole; A semiconductor device comprising:

[0112] (Appendix 2) The semiconductor device according to appendix 1, wherein the protective film is made of a metal material. (Appendix 3) The semiconductor device according to appendix 1 or 2, wherein the protective film is provided continuously from the outer periphery region on the surface of the diamond layer excluding the via hole.

[0113] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein the via wiring is provided so as to cover the protective film and the diamond layer, and a portion of the via wiring is provided in the via hole.

[0114] (Supplementary Note 5) An electrode layer is provided on the semiconductor layer on the side opposite to the diamond layer, the via hole penetrates the semiconductor layer and reaches the electrode layer; 5. The semiconductor device according to claim 1, wherein the via wiring is connected to the electrode layer.

[0115] (Supplementary Note 6) The semiconductor layer is a first semiconductor layer on the diamond layer side; a second semiconductor layer that is stacked on the side of the first semiconductor layer opposite to the diamond layer side and that forms a current path; 6. The semiconductor device according to any one of claims 1 to 5, comprising:

[0116] (Appendix 7) A step of forming a diamond layer on a main surface of a semiconductor layer; a step of etching the diamond layer in a first region corresponding to a dicing line along which the semiconductor layer is divided into individual pieces and the diamond layer in a second region corresponding to a first via hole to be formed in the semiconductor layer of each of the divided individual pieces, thereby forming a trench penetrating the diamond layer in the first region and a second via hole penetrating the diamond layer in the second region; forming a protective film covering the main surface of the semiconductor layer in the trench; etching the semiconductor layer in the second via hole using the protective film as a mask to form the first via hole communicating with the second via hole and extending into the semiconductor layer; forming a via wiring in the first via hole and the second via hole that are in communication with each other; dicing the semiconductor layer and the protective film covering the main surface in the trench at the position of the first region where the trench is formed; 10. A method for manufacturing a semiconductor device, comprising:

[0117] (Appendix 8) The method for manufacturing a semiconductor device according to appendix 7, wherein the protective film is made of a metal material. (Supplementary Note 9) The step of forming the protective film includes a step of forming the protective film continuously provided from the main surface of the semiconductor layer in the trench on the surface of the diamond layer excluding the second via hole. The manufacturing method of the semiconductor device according to Supplementary Note 7 or 8, characterized in that it has.

[0118] (Supplementary Note 10) The step of etching the first region and the second region of the diamond layer to form the trench and the second via hole includes a step of dry etching the first region and the second region of the diamond layer using a gas containing oxygen. The step of forming the first via hole by etching the semiconductor layer in the second via hole using the protective film as a mask includes a step of dry etching the semiconductor layer in the second via hole using a gas containing fluorine or chlorine. The manufacturing method of the semiconductor device according to any one of Supplementary Notes 7 to 9, characterized in that it has.

[0119] (Supplementary Note 11) The step of forming the via wiring includes a step of forming the via wiring so as to cover the protective film and the diamond layer and a part thereof is provided in the first via hole and the second via hole. The manufacturing method of the semiconductor device according to any one of Supplementary Notes 7 to 10, characterized in that it has.

[0120] (Supplementary Note 12) includes a step of forming an electrode layer on the side of the semiconductor layer opposite to the diamond layer side. The step of forming the first via hole includes a step of forming the first via hole reaching the electrode layer. The step of forming the via wiring includes a step of forming the via wiring connected to the electrode layer. The manufacturing method of the semiconductor device according to any one of Supplementary Notes 7 to 11, characterized in that it has.

[0121] (Supplementary Note 13) The semiconductor layer is a first semiconductor layer on the diamond layer side, a second semiconductor layer laminated on the side of the first semiconductor layer opposite to the diamond layer side, through which a current path is formed The manufacturing method of the semiconductor device according to any one of Appendices 7 to 12, characterized by having

[0122] (Appendix 14) A semiconductor layer, A diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer, A protective film provided in the outer peripheral region on the main surface of the semiconductor layer, A via hole penetrating the diamond layer and extending into the semiconductor layer, A via wiring provided in the via hole An electronic device comprising a semiconductor device including

Description of symbols

[0123] 1, 1A, 1B, 1Ba Semiconductor device 2 Laminated body 2a Dicing line region 2b Via formation region 10 Semiconductor layer 10a, 20a Main surface 10b, 20b Side surface 11 First semiconductor layer 12 Second semiconductor layer 13, 21, 81 Trench 14, 22, 80 Via hole 20 Diamond layer 30 Gate electrode 30a, 40a, 50a Pad 40 Source electrode 50 Drain electrode 60 Etching stopper 70 Wiring 90 Via wiring 100 Adhesive 110 Support 120 Mask layer 121 Opening 130 Blade 140 Protective film 150 Dicing tape 200 Semiconductor package 210 Lead frame 210a die pad 211 Gate Lead 212 Source Read 213 Drain Lead 220 Resin 230 Wire 300 PFC circuit 310,421,422,423,441,442,443,444 Switching elements 320 Diode 330 Choke Coil 340,350 capacitors 360 Diode Bridge 370 AC power supply 400 power supply 410 Primary circuit 420 Secondary circuit 430 transformer 440 Full-bridge inverter circuit 500 Amplifier 510 Digital Pre-Distortion Circuit 520,530 Mixer 540 Power Amplifier AR1 outer area AR2 medial area

Claims

1. A semiconductor layer, a diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer, a protective film provided in the outer peripheral region on the main surface of the semiconductor layer, a via hole penetrating the diamond layer and extending into the semiconductor layer, and a via wiring provided in the via hole characterized in that it comprises a semiconductor device.

2. The semiconductor device according to claim 1, characterized in that a metal material is used for the protective film.

3. The semiconductor device according to claim 1 or 2, characterized in that the protective film is continuously provided from the outer peripheral region on the surface of the diamond layer excluding the via hole.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the via wiring is provided so as to cover the protective film and the diamond layer, and a part thereof is provided in the via hole.

5. including an electrode layer provided on the side of the semiconductor layer opposite to the diamond layer side, the via hole penetrates the semiconductor layer and reaches the electrode layer, The semiconductor device according to any one of claims 1 to 4, characterized in that the via wiring is connected to the electrode layer.

6. A step of forming a diamond layer on the main surface of a semiconductor layer, etching the diamond layer in a first region corresponding to a dicing line for dividing the semiconductor layer into individual chips and the diamond layer in a second region corresponding to a first via hole formed in each of the semiconductor layers of the divided individual chips, forming a trench penetrating the diamond layer in the first region, and forming a second via hole penetrating the diamond layer in the second region, a step of forming a protective film covering the main surface of the semiconductor layer in the trench, a step of etching the semiconductor layer in the second via hole using the protective film as a mask to form the first via hole communicating with the second via hole and extending into the semiconductor layer, a step of forming a via wiring in the communicating first via hole and second via hole, and a step of dicing the semiconductor layer and the protective film covering the main surface in the trench at the position of the first region where the trench is formed characterized in that it comprises a method for manufacturing a semiconductor device.

7. The step of forming the protective film includes a step of forming the protective film continuously provided from the main surface of the semiconductor layer in the trench on a surface of the diamond layer excluding the second via hole. The manufacturing method of the semiconductor device according to claim 6, characterized in that.

8. The step of forming the via wiring includes a step of forming the via wiring so as to cover the protective film and the diamond layer and a part thereof is provided in the first via hole and the second via hole. The manufacturing method of the semiconductor device according to claim 6 or 7, characterized in that.

9. Including a step of forming an electrode layer on a side of the semiconductor layer opposite to the diamond layer side, The step of forming the first via hole includes a step of forming the first via hole reaching the electrode layer, The step of forming the via wiring includes a step of forming the via wiring connected to the electrode layer. The manufacturing method of the semiconductor device according to any one of claims 6 to 8, characterized in that.

10. A semiconductor layer, A diamond layer provided in an inner region inside the outer peripheral region on the main surface of the semiconductor layer, A protective film provided in the outer peripheral region on the main surface of the semiconductor layer, A via hole penetrating the diamond layer and extending into the semiconductor layer, And a via wiring provided in the via hole An electronic device comprising a semiconductor device characterized by that.

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