Semiconductor device manufacturing method

Abstract

To provide a technique capable of satisfactorily peeling a device layer from a semiconductor wafer by reducing warpage of the semiconductor wafer.SOLUTION: A manufacturing method of a semiconductor device includes: a groove forming step of forming a groove on a first principal surface of a semiconductor wafer 1 comprising a first principal surface 1a and a second principal surface 1b, a device structure being formed on the side of the first principal surface of the semiconductor wafer in the groove forming step; a laser radiating step of radiating a laser to a face 3 extending in a predetermined depth of the semiconductor wafer, the laser being radiated from the second principal surface to the predetermined depth of the semiconductor wafer in the laser radiating step; and a peeling step of peeling a device layer 2, in which the device structure is formed, from the semiconductor wafer along the face to which the laser is radiated. The peeling step is implemented in a state where the groove is not filled or is filled with a material of a lower thermal expansion coefficient than that of the semiconductor wafer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

[0002] After forming a device structure on one main surface side of a semiconductor substrate, a technology has been developed to peel off the device layer on which the device structure is formed from the semiconductor substrate. By using this technology, the semiconductor substrate after the device layer is peeled off can be reused, so that the manufacturing cost of the semiconductor device can be reduced. Patent Document 1 discloses a technology of forming a modified layer inside the semiconductor substrate by irradiating a surface extending a predetermined depth of the semiconductor substrate with a laser, and peeling off the device layer from the semiconductor substrate along the surface on which the modified layer is formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The semiconductor substrate may be warped. When the semiconductor substrate is warped, the modified layer in the semiconductor substrate is also warped and formed. Therefore, when peeling off the device layer from the semiconductor substrate, the peeling force is difficult to be transmitted along the modified layer, which may cause peeling failure or breakage of the semiconductor substrate. This specification provides a technology capable of reducing the warp of the semiconductor substrate and peeling off the device layer from the semiconductor substrate well.

Means for Solving the Problems

[0005] The manufacturing method of the semiconductor device disclosed in this specification includes a groove forming step of forming a groove on the first main surface (1a) of a semiconductor substrate (1) having a first main surface (1a) and a second main surface (1b), wherein a device structure is formed on the first main surface side of the semiconductor substrate; a laser irradiation step of irradiating a surface (3) extending to a predetermined depth of the semiconductor substrate with a laser, wherein the laser is irradiated from the second main surface to the predetermined depth of the semiconductor substrate; and a peeling step of peeling a device layer (2) in which the device structure is formed from the semiconductor substrate along the surface irradiated with the laser. The peeling step is carried out in a state where the groove is unfilled or filled with a material having a lower coefficient of thermal expansion than the semiconductor substrate.

[0006] In this manufacturing method, by forming the groove in the semiconductor substrate, the stress applied to the semiconductor substrate is relaxed and the warpage of the semiconductor substrate is reduced. Further, the groove formed in the groove forming step remains unfilled or filled with a material having a lower coefficient of thermal expansion even in the peeling step. Therefore, the peeling step can be carried out while suppressing the warpage of the semiconductor substrate. According to this manufacturing method, when the device layer is peeled from the semiconductor substrate, the peeling force is well transmitted along the altered layer, so that the device layer can be peeled well from the semiconductor substrate.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] The manufacturing method of the semiconductor device disclosed in this specification can include a groove formation step, a laser irradiation step, and a peeling step. In the groove formation step, grooves are formed on the first main surface of a semiconductor substrate having a first main surface and a second main surface. The semiconductor substrate is not particularly limited, and may be a compound semiconductor. The semiconductor substrate may be, for example, a nitride semiconductor containing gallium nitride, silicon carbide, or gallium oxide. Since the manufacturing method of the semiconductor device disclosed in this specification can reuse the semiconductor substrate, it is particularly useful when applied to the expensive compound semiconductor substrate. A device structure is formed on the first main surface side of the semiconductor substrate. In the laser irradiation step, the semiconductor substrate is irradiated with a laser on a surface extending to a predetermined depth. In the laser irradiation step, the laser is irradiated from the second main surface where the grooves are not formed to the predetermined depth of the semiconductor substrate. The peeling step peels the device layer on which the device structure is formed from the semiconductor substrate along the surface irradiated with the laser. In the peeling step, the peeling is performed in a state where the grooves are unfilled or filled with a material having a lower coefficient of thermal expansion than the semiconductor substrate.

[0009] In the groove formation step, when the semiconductor substrate is viewed in plan view, the grooves may be formed so as to repeatedly appear along at least one direction on the first main surface. Since the grooves are formed so as to repeatedly appear, the warpage of the semiconductor substrate in the at least one direction is reduced. In this case, the grooves may be arranged at equal intervals along the at least one direction.

[0010] When the grooves are formed so as to repeatedly appear, the maximum pitch of the grooves measured along the at least one direction may be 0.0177 times or less of the diameter of the semiconductor substrate. Here, the pitch of the grooves refers to the distance between adjacent grooves. According to this manufacturing method, the peeling success rate can be significantly improved.

[0011] When the grooves are formed to repeatedly appear, in the peeling step, the device layer may be peeled from the semiconductor substrate from one end to the other end of the semiconductor substrate in at least one direction. Since the device layer is peeled from the semiconductor substrate in the direction in which the warp of the semiconductor substrate is reduced, the device layer can be peeled well from the semiconductor substrate.

[0012] The device layer may be provided with a plurality of device regions partitioned by dicing lines. In this case, each of the plurality of device regions is a region where the device structure is formed. The groove may extend across the plurality of device regions.

[0013] The groove may have a first groove extending along a first direction and a second groove extending along a second direction orthogonal to the first direction when the semiconductor substrate is viewed in plan. The first groove and the second groove may be connected in a planar T shape. According to this manufacturing method, the stress at the portion where the first groove and the second groove are connected is relaxed, and breakage of the semiconductor substrate is suppressed.

[0014] The semiconductor substrate may be a hexagonal semiconductor. In this case, the groove may extend so that hexagons are arranged without gaps when the semiconductor substrate is viewed in plan. According to this manufacturing method, since the grooves are formed to repeatedly appear along three directions when the semiconductor substrate is viewed in plan, the warp of the semiconductor substrate is reduced in a well-balanced manner as a whole. Also, since the angle between the grooves at the portion where the grooves are connected becomes an obtuse angle, the stress at that portion is relaxed, and breakage of the semiconductor substrate is suppressed.

Example

[0015] [[ID=ID=18]] Hereinafter, with reference to the drawings, the groove formation step, the laser irradiation step, the peeling step, and the dicing step in the method for manufacturing a semiconductor device will be described. Note that for various other steps other than the groove formation step, the laser irradiation step, the peeling step, and the dicing step, for example, the step of forming a device structure, known manufacturing techniques can be used. Note that the step of forming a device structure may be performed between the groove formation step and the laser irradiation step.

[0016] FIG. 1 shows the flow of the groove formation step (step S1), the laser irradiation step (step S2), the peeling step (step S3), and the dicing step (step S4). The method for manufacturing a semiconductor device disclosed in this specification manufactures a plurality of semiconductor devices (also referred to as chips) by performing these steps on the semiconductor substrate 1 shown in FIGS. 2 and 3.

[0017] As shown in FIG. 2, the semiconductor substrate 1 has an upper surface 1a and a lower surface 1b that each extend in a plane and are parallel to each other. These upper surface 1a and lower surface 1b are also referred to as main surfaces. The semiconductor substrate 1 is not particularly limited, but in this example, it is a gallium nitride substrate. The surface 3 that extends to a predetermined depth of the semiconductor substrate 1 is the surface irradiated with a laser, that is, the surface where a plurality of laser beam spots are gathered, as will be described later. In this specification, the portion above the surface 3 of the semiconductor substrate 1 irradiated with the laser, that is, the portion peeled off from the semiconductor substrate 1 is referred to as the device layer 2. Hereinafter, one direction parallel to the upper surface 1a of the semiconductor substrate 1 is defined as the x direction, the direction parallel to the upper surface 1a of the semiconductor substrate 1 and orthogonal to the x direction is defined as the y direction, and the direction orthogonal to the x direction and the y direction is defined as the z direction (also referred to as the thickness direction of the semiconductor substrate 1).

[0018] As shown in FIGS. 2 and 3, a plurality of device regions 4 partitioned by dicing lines 5 are provided in the device layer 2 of the semiconductor substrate 1. A device structure is formed in each of the plurality of device regions 4. The device structure is not particularly limited, but is, for example, a switching element structure. Specifically, when viewed from a direction orthogonal to the upper surface 1a of the semiconductor substrate 1 (hereinafter referred to as "when the semiconductor substrate 1 is viewed in plan"), the device structure has an element region disposed on the central side of the device region 4 and a termination region disposed around the element region. The element region is a region where an insulating gate is disposed and is a region where current flows. The termination region is a region where a breakdown voltage structure (for example, a guard ring or a RESURF layer) is disposed. As an example of such a type of switching element structure, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor) may be mentioned.

[0019] As shown in FIGS. 4 and 5, in the groove forming step (step S1 in FIG. 1), grooves 6 are formed in the upper surface 1a of the semiconductor substrate 1 using a dry etching technique. In this example, the groove 6 has a plurality of first grooves 6a formed to extend along the y direction and repeatedly appear in the x direction, and a plurality of second grooves 6b formed to extend along the x direction and repeatedly appear in the y direction. Each of the plurality of first grooves 6a extends from one end face to the other end face of the semiconductor substrate 1 in the y direction and is arranged at equal intervals in the x direction. Similarly, each of the plurality of second grooves 6b extends from one end face to the other end face of the semiconductor substrate 1 in the x direction and is arranged at equal intervals in the y direction. Note that in FIG. 5, only a part of the plurality of first grooves 6a and the plurality of second grooves 6b are shown for the purpose of clarity of the drawing.

[0020] A part of the plurality of first grooves 6a extends across the plurality of device regions 4 and extends within the element region of the device structure formed in the device region 4. Similarly, a part of the plurality of second grooves 6b also extends across the plurality of device regions 4 and extends within the element region of the device structure formed in the device region 4. Such an arrangement of the first grooves 6a and the second grooves 6b reduces the area of the element region of the device structure, thereby reducing the maximum current that the device structure can conduct. Therefore, the arrangement of the first grooves 6a and the second grooves 6b is appropriately set in consideration of both stress relaxation and electrical characteristics of the device structure, which will be described later.

[0021] Before the groove formation process is performed, the semiconductor substrate 1 is often warped such that the lower surface 1b is convex due to thermal stress applied during processes such as crystal growth processing and annealing processing. When the groove formation process is performed, the thermal stress of the semiconductor substrate 1 is relaxed and the warp of the semiconductor substrate 1 is reduced. After the groove formation process, a process of forming a device structure is performed.

[0022] As shown in FIG. 6, in the laser irradiation process (step S2 in FIG. 1), the laser is irradiated onto the surface 3 extending to a predetermined depth of the semiconductor substrate 1. The laser is irradiated so as to be focused at a predetermined depth of the semiconductor substrate 1 from the lower surface 1b of the semiconductor substrate 1 where the grooves 6 are not formed. The laser is a laser in a wavelength range that is transmissive to the semiconductor substrate (in this example, a gallium nitride substrate). At the position of the focus point, the crystal (in this example, a single crystal of gallium nitride) constituting the semiconductor substrate 1 is heated and decomposed. As a result, at the position of the focus point, a modified layer is formed, which is constituted by a deposited layer of constituent atoms of the crystal constituting the semiconductor substrate 1 (in this example, a deposited layer of gallium, etc.). The strength of the modified layer is lower than that of the crystal constituting the semiconductor substrate 1. Therefore, the strength of the modified layer is lower than that of the surrounding crystals.

[0023] As shown in FIG. 7, in the peeling step (step S3 in FIG. 1), the device layer 2 in which the device structure is formed is peeled from the semiconductor substrate 1 along the surface 3 irradiated with the laser. Specifically, an adhesive sheet is attached to each of the upper surface 1a and the lower surface 1b of the semiconductor substrate 1, and the device layer 2 is peeled from the semiconductor substrate 1 by operating to pull these adhesive sheets apart. In this example, the device layer 2 is peeled from the semiconductor substrate 1 from one end (the left end in the drawing) to the other end (the right end in the drawing) of the semiconductor substrate 1 in the x direction. In this peeling step, the groove 6 formed in the groove forming step remains unfilled. For this reason, since the warp of the semiconductor substrate 1 is suppressed, the altered layer formed by the laser irradiation extends in the same plane within the semiconductor substrate 1. As a result, when the device layer 2 is peeled from the semiconductor substrate 1, as shown by the arrow in the figure, the peeling force can be transmitted well along the altered layer, so that the device layer 2 can be peeled well from the semiconductor substrate 1.

[0024] Also, as described above, in this peeling step, the device layer 2 is peeled from the semiconductor substrate 1 from one end to the other end of the semiconductor substrate 1 in the x direction. The warp of the semiconductor substrate 1 is reduced well in the direction in which the pitch of the grooves 6 is narrow and the grooves 6 repeatedly appear. In the semiconductor substrate 1, the x direction is the direction in which the pitch of the grooves 6 is the smallest, and the warp in the x direction is reduced well. In this peeling step, since the device layer 2 is peeled from the semiconductor substrate 1 in the x direction, the peeling force can be transmitted well along the altered layer. For the same reason, in the peeling step, the device layer 2 may be peeled from the semiconductor substrate 1 from one end to the other end of the semiconductor substrate 1 in the y direction.

[0025] In the peeling process of this example, the groove 6 formed in the groove forming process was maintained without being filled. Instead of this example, the groove 6 may be filled with a material having a lower coefficient of thermal expansion than the material of the semiconductor substrate 1 (gallium nitride substrate in this example). By filling the groove 6 with a material having a lower coefficient of thermal expansion, generation of foreign matter due to process residues remaining in the groove 6 can be suppressed while suppressing warping of the semiconductor substrate 1. Such a material having a lower coefficient of thermal expansion is not particularly limited, but may be, for example, silicon oxide (SiO2) or silicon nitride (SiN). When these insulating materials are used, they can also be used as part of the breakdown voltage structure in the terminal region of the device structure.

[0026] Note that the semiconductor substrate 1 after the device layer 2 is peeled off is reused for manufacturing a semiconductor device. For example, after performing polishing, etching, etc. on the peeled surface of the semiconductor substrate 1, an epitaxial layer can be formed on the peeled surface using epitaxial crystal growth technology, and a device structure can be formed in the formed epitaxial layer.

[0027] As shown in FIG. 8, in the dicing process (step S4 in FIG. 1), after performing a polishing process, an electrode forming process, etc. on the device layer 2 peeled off from the semiconductor substrate 1, a plurality of devices (also referred to as dice) are cut out from the device layer 2, and the semiconductor device is completed.

[0028] In the above embodiment, when the semiconductor substrate 1 is viewed in plan, the first groove 6a and the second groove 6b are arranged so as to intersect. Instead of this example, as in the modified example shown in FIG. 9, when the semiconductor substrate 1 is viewed in plan, the first groove 6a and the second groove 6b may be connected in a planar T shape. Compared with the intersecting case of the above embodiment, the stress at the connection portion between the first groove 6a and the second groove 6b is relaxed, and breakage of the semiconductor substrate 1 is suppressed.

[0029] Also, as in the modification shown in FIG. 10, when the semiconductor substrate 1 is viewed in plan view, the grooves 6 may extend in a hexagonal pattern with no gaps between them. Further, the grooves 6 may extend to form a honeycomb structure in which regular hexagons are arranged with no gaps between them. In this example, the semiconductor substrate 1 is a hexagonal gallium nitride substrate, and the thickness direction (z-axis) of the semiconductor substrate 1 is the c-axis. Also, each side forming the hexagon extends so as to be parallel to the m-plane, a-plane, or any other arbitrary plane. In this modification, when the semiconductor substrate 1 is viewed in plan view, the grooves 6 are formed to repeatedly appear along three directions divided at an angle of 120°, so that the warpage of the semiconductor substrate 1 is reduced in a well-balanced manner as a whole. Also, since the angle between the grooves 6 at the portion where the grooves 6 connect becomes an obtuse angle, the stress at that portion is relaxed, and breakage of the semiconductor substrate 1 is suppressed.

[0030] Also, in each of the above-described embodiments and modifications, the grooves 6 continuously extend without interruption on the upper surface of the semiconductor substrate 1. Instead of or in addition to these examples, the grooves may be dispersedly arranged. For example, when the semiconductor substrate 1 is viewed in plan view, grooves that loop within the device region 4 may be formed, or grooves that loop around the periphery of the device region 4 along the dicing line 5 may be formed.

[0031] The cross-sectional shape of the groove 6 is not particularly limited. For example, the bottom surface may be formed as a convex curved surface facing downward. In the groove 6 having such a cross-sectional shape, the stress applied to the bottom of the groove 6 is relaxed, and breakage of the semiconductor substrate 1 is suppressed.

[0032] Also, the depth of the groove 6 is not particularly limited, but it may be deeper than the epitaxial layer. The warpage of the semiconductor substrate 1 is considered to be caused in part by the stress (mainly tensile stress) applied to the epitaxial layer when the epitaxial layer is crystal-grown. Therefore, by forming the groove 6 deeper than the epitaxial layer, the warpage of the semiconductor substrate 1 can be effectively reduced.

[0033] (Regarding the pitch of the grooves) In the semiconductor substrate 1 of the above embodiment, a peeling test was carried out under the following conditions. Diameter of the semiconductor substrate 1: 50 mm Thickness of the semiconductor substrate 1: 0.4 mm Width of the first groove 6a: 10 μm Depth of the first groove 6a: 10 μm Pitch of the first groove 6a: 1 mm Width of the second groove 6b: 10 μm Depth of the second groove 6b: 10 μm Pitch of the second groove 6b: 1 mm

[0034] As a result of the above peeling test, it was confirmed that the probability of successful peeling (peeling success rate) was significantly improved compared to the case where no grooves were formed. Specifically, the peeling success rate in the example without grooves was 25%, while in the example with grooves, the peeling success rate was 75%. In the dimensions of the wafer corresponding to the SEMI standard shown below, the pitch of the grooves for obtaining the same load distribution as in the above peeling test was calculated using the formula for uniformly distributed load of a simple beam, and the result was plotted in FIG. 11. The x-axis represents the diameter of the semiconductor substrate, and the y-axis represents the pitch of the grooves.

Table 1

[0035] It was suggested from the regression line in FIG. 11 that when the pitch of the groove 6 is 0.0177 times the diameter of the semiconductor substrate 1, a peeling success rate equivalent to that of the peeling test can be obtained. From this result, it was suggested that in the grooves formed so as to repeatedly appear at least in one direction on one main surface when the semiconductor substrate is viewed in plan view, if the maximum pitch of the grooves measured along at least that one direction is 0.0177 times or less the diameter of the semiconductor substrate, a peeling success rate equivalent to or higher than that of the peeling test can be obtained.

[0036] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Description of Reference Numerals

[0037] 1: Semiconductor substrate, 2: Device layer, 4: Device region, 5: Dicing line, 6: Groove, 6a: First groove, 6b: Second groove,

Claims

1. A method for manufacturing a semiconductor device, comprising: a groove forming step of forming a groove in the first main surface of a semiconductor substrate (1) having a first main surface (1a) and a second main surface (1b) and having a device layer (2) disposed on the first main surface side; a laser irradiation step of irradiating a surface (3) extending to a predetermined depth of the semiconductor substrate with a laser, wherein the laser is irradiated from the second main surface to the predetermined depth of the semiconductor substrate; a peeling step of peeling the device layer (2) in which a device structure is formed from the semiconductor substrate along the surface irradiated with the laser; the peeling step is performed in a state where the groove is unfilled or filled with a material having a lower coefficient of thermal expansion than the semiconductor substrate; a plurality of device regions (4) partitioned by dicing lines (5) are provided in the device layer; each of the plurality of device regions is a region where the device structure is formed; the groove extends across the plurality of device regions. A method for manufacturing a semiconductor device.

2. In the groove forming step, the groove is formed so as to repeatedly appear along at least one direction on the first main surface when the semiconductor substrate is viewed in plan. The method for manufacturing a semiconductor device according to Claim 1.

3. The grooves are arranged at equal intervals along the at least one direction. The method for manufacturing a semiconductor device according to Claim 2.

4. The maximum pitch of the grooves measured along the at least one direction is 0.0177 times or less of the diameter of the semiconductor substrate. The method for manufacturing a semiconductor device according to Claim 2 or 3.

5. In the peeling step, the device layer is peeled from the semiconductor substrate from one end to the other end of the semiconductor substrate in the at least one direction. The method for manufacturing a semiconductor device according to any one of Claims 2 to 4.

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