Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing increase of a chip area.SOLUTION: A semiconductor device comprises: an inter-layer insulation film; and a plurality of resistance films arranged onto the inter-layer insulation film. Each of the plurality of resistance films is extended to a first direction along an upper surface of the plurality of resistance films in a plan view. The plurality of resistance films is along the upper surface of the plurality of resistance films in the plan view, and is arranged with an interval to a second direction orthogonal to a first direction. The plurality of resistance films is divided into a first group; a second group; and a third group. The first group is positioned between the second group and the third group to a second direction. Each second width modulation amount of the plurality of second resistance films belongs to the second group and each third width modulation amount of the plurality of third resistance films belong to the third group are larger than each first width modulation amount of the plurality of first resistance films belonged to the first group.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] The semiconductor device described in Japanese Patent Application Laid-Open No. 2011-155192 (Patent Document 1) has an interlayer insulating film and a plurality of resistance films. The plurality of resistance films are arranged on the interlayer insulating film. Each of the plurality of resistance films extends along a first direction. The plurality of resistance films are arranged side by side at intervals along a second direction orthogonal to the first direction.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The width of each of the plurality of resistance films is designed to be constant. However, it is difficult to make the width of each of the plurality of resistance films constant, and if some of the plurality of resistance films whose widths do not fall within a predetermined range are used in a circuit, the accuracy of the circuit will decrease. Therefore, it is necessary to increase the number of the plurality of resistance films and use dummy resistance films that do not have widths falling within a predetermined range in the circuit, which increases the chip area. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0005] The semiconductor device of the present disclosure includes an interlayer insulating film and a plurality of resistance films disposed on the interlayer insulating film. Each of the plurality of resistance films extends in a first direction along the upper surface of the interlayer insulating film in a plan view. The plurality of resistance films are arranged at intervals in a second direction along the upper surface of the interlayer insulating film and orthogonal to the first direction in a plan view. The plurality of resistance films are divided into a first group, a second group, and a third group. The first group is located between the second group and the third group in the second direction. The second width variation amount of each of the plurality of second resistance films belonging to the second group and the third width variation amount of each of the plurality of third resistance films belonging to the third group are larger than the first width variation amount of each of the plurality of first resistance films belonging to the first group. The first width variation amount is the difference between the reference width and the width of each of the plurality of first resistance films. The second width variation amount is the difference between the reference width and the width of each of the plurality of second resistance films. The third width variation amount is the difference between the reference width and the width of each of the plurality of third resistance films. The reference width is the width of one of the plurality of resistance films at the center in the second direction. The plurality of first resistance films are electrically connected to a first circuit group. At least a part of the plurality of second resistance films and / or at least a part of the plurality of third resistance films are electrically connected to a second circuit group different from the first circuit group.

Advantages of the Invention

[0006] According to the semiconductor device of the present disclosure, an increase in chip area can be suppressed.

Brief Description of the Drawings

[0007] [Figure 1] It is a cross-sectional view of the semiconductor device DEV1. [Figure 2] It is a plan layout diagram of a plurality of resistance films RF in the semiconductor device DEV1. [Figure 3] It is a schematic block diagram of the semiconductor device DEV1. [Figure 4] It is a manufacturing process diagram of the semiconductor device DEV1. [Figure 5] It is a cross-sectional view for explaining the first wiring formation step S1. [Figure 6] It is a cross-sectional view for explaining the first interlayer insulating film formation step S2. [Figure 7]It is a cross-sectional view for explaining the first via hole forming step S3. [Figure 8] It is a cross-sectional view for explaining the first via plug forming step S4. [Figure 9] It is a cross-sectional view for explaining the resistor film forming step S5. [Figure 10] It is a cross-sectional view for explaining the second interlayer insulating film forming step S6. [Figure 11] It is a cross-sectional view for explaining the second via hole forming step S7. [Figure 12] It is a cross-sectional view for explaining the second via plug forming step S8. [Figure 13] It is a cross-sectional view for explaining the second wiring forming step S9. [Figure 14] It is a plan layout view of the resistor film RF in the semiconductor device DEV2. [Figure 15] It is a plan layout view of the resistor film RF in the semiconductor device DEV3. [Figure 16] It is a plan layout view of the resistor film RF in the semiconductor device DEV4. [Figure 17] It is a plan layout view of the resistor film RF in the semiconductor device DEV5. [Figure 18] It is a plan layout view of the resistor film RF in a modified example of the semiconductor device DEV5.

Embodiments for Carrying Out the Invention

[0008] Details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First Embodiment) A semiconductor device according to the first embodiment will be described. The semiconductor device according to the first embodiment is referred to as semiconductor device DEV1.

[0010] <Configuration of Semiconductor Device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0011] Figure 1 is a cross-sectional view of the semiconductor device DEV1. Figure 2 is a plan layout view of the resistive film RF in the semiconductor device DEV1. As shown in FIGS. 1 and 2, the semiconductor device DEV1 has a semiconductor substrate SUB and a plurality of interlayer insulating films ILD. The semiconductor substrate SUB is formed of, for example, single crystal silicon (Si). The plurality of interlayer insulating films ILD are disposed on the semiconductor substrate SUB. Each of the plurality of interlayer insulating films ILD is formed of, for example, silicon oxide (SiO2). One of the plurality of interlayer insulating films ILD is defined as the interlayer insulating film ILD1.

[0012] The semiconductor device DEV1 has a wiring WL1 and a wiring WL2. The wiring WL1 and the wiring WL2 are disposed on the interlayer insulating film ILD1. The wiring WL1 and the wiring WL2 are formed of, for example, aluminum (Al) or an aluminum alloy. A barrier metal BM1 is disposed between the wiring WL1 and the interlayer insulating film ILD1 and between the wiring WL2 and the interlayer insulating film ILD1. A barrier metal BM2 is disposed on the wiring WL1 and on the wiring WL2. The barrier metal BM1 and the barrier metal BM2 each consist of, for example, a laminated film of a titanium nitride (TiN) film and a titanium (Ti) film.

[0013] Another one of the plurality of interlayer insulating films ILD is defined as the interlayer insulating film ILD2. The interlayer insulating film ILD2 is disposed on the interlayer insulating film ILD1 so as to cover the wiring WL1 and the wiring WL2. A via hole VH1 and a via hole VH2 are formed in the interlayer insulating film ILD2. The via hole VH1 and the via hole VH2 penetrate the interlayer insulating film ILD2 in the thickness direction. At the bottom of the via hole VH1 and at the bottom of the via hole VH2, a part of the wiring WL1 and a part of the wiring WL2 are respectively exposed.

[0014] The semiconductor device DEV1 has a via plug VP1 and a via plug VP2. The via plug VP1 and the via plug VP2 are buried in a via hole VH1 and a via hole VH2, respectively. The via plug VP1 and the via plug VP2 are formed of, for example, tungsten (W). The lower end of the via plug VP1 is electrically connected to a wiring WL1. The lower end of the via plug VP2 is electrically connected to a wiring WL2.

[0015] The semiconductor device DEV1 has a plurality of resistive films RF. The resistive films RF are disposed on an interlayer insulating film ILD2. The resistive films RF are formed of a conductive material. The resistive films RF are preferably formed of a material containing at least one selected from the group consisting of silicon chromium (SiCr), silicon chromium doped with carbon (C), nickel chromium (NiCr), titanium nitride, and tantalum nitride (TaN). However, the resistive films RF may be formed of other conductive materials (e.g., polycrystalline silicon).

[0016] The resistive film RF is electrically connected to the upper ends of the via plugs VP1 and VP2. As a result, the resistive film RF is electrically connected to the wirings WL1 and WL2. The semiconductor device DEV1 may have a plurality of insulating films IF. The insulating film IF is disposed on the resistive film RF. As will be described later, the insulating film IF is a mask (hard mask) for patterning the resistive film RF. The insulating film IF is formed of, for example, silicon oxide or silicon oxynitride (SiON).

[0017] Another one of the plurality of interlayer insulating films ILD is an interlayer insulating film ILD3. The interlayer insulating film ILD3 is disposed on the interlayer insulating film ILD2 so as to cover the plurality of resistive films RF and the plurality of insulating films IF.

[0018] In the interlayer insulating films ILD2 and ILD3, via holes VH3 and VH4 are formed. The via holes VH3 and VH4 penetrate the interlayer insulating films ILD2 and ILD3 along the thickness direction. At the bottoms of the via hole VH3 and the via hole VH4, a part of the wiring WL1 and a part of the wiring WL2 are respectively exposed.

[0019] The semiconductor device DEV1 has a via plug VP3 and a via plug VP4. The via plug VP3 and the via plug VP4 are respectively embedded in the via holes VH3 and VH4. The via plug VP3 and the via plug VP4 are formed of, for example, tungsten. The lower end of the via plug VP3 is electrically connected to the wiring WL1, and the lower end of the via plug VP4 is electrically connected to the wiring WL2.

[0020] The semiconductor device DEV1 has a wiring WL3 and a wiring WL4. The wirings WL3 and WL4 are disposed on the interlayer insulating film ILD3. The wirings WL3 and WL4 are formed of, for example, aluminum or an aluminum alloy. A barrier metal BM3 is disposed between the wiring WL3 and the interlayer insulating film ILD3 and between the wiring WL4 and the interlayer insulating film ILD3. A barrier metal BM4 is disposed on the wiring WL3 and on the wiring WL4. The barrier metal BM3 and the barrier metal BM4 are composed of, for example, a laminated film of a titanium nitride film and a titanium film. The wirings WL3 and WL4 are respectively electrically connected to the upper end of the via plug VP3 and the upper end of the via plug VP4. Thereby, the wiring WL3 is electrically connected to the wiring WL1, and the wiring WL4 is electrically connected to the wiring WL2.

[0021] Another one of the plurality of interlayer insulating films ILD is defined as the interlayer insulating film ILD4. The interlayer insulating film ILD4 is disposed on the interlayer insulating film ILD3 so as to cover the wirings WL3 and WL4. Although not shown, other wirings and other interlayer insulating films may be sequentially laminated on the interlayer insulating film ILD4.

[0022] Each of the plurality of resistance films RF extends in a first direction D1 along the upper surface of the interlayer insulating film ILD2 in a plan view. The plurality of resistance films RF are arranged at intervals in a second direction D2 along the upper surface of the interlayer insulating film ILD2. The second direction D2 is a direction orthogonal to the first direction D1.

[0023] The plurality of resistance films RF are divided into a first group, a second group, and a third group. The plurality of resistance films RF belonging to the first group are referred to as a plurality of resistance films RF1, the plurality of resistance films RF belonging to the second group are referred to as a plurality of resistance films RF2, and the plurality of resistance films RF belonging to the third group are referred to as a plurality of resistance films RF3. The second group is on one side (the left side in the example of FIG. 2) in the second direction D2 of the first group. That is, the first group is located between the second group and the third group in the second direction D2. The third group is on the other side (the right side in the example of FIG. 2) in the second direction D2 of the first group. The number of the plurality of resistance films RF1 is larger than the number of the plurality of resistance films RF2 and the number of the plurality of resistance films RF3. The length of each of the plurality of resistance films RF is, for example, equal to each other. Here, the length of the resistance film RF is the length of the resistance film RF in the first direction D1. Note that even if the lengths of the plurality of resistance films RF are different from each other due to manufacturing variations, it includes the case where the lengths of the plurality of resistance films RF are equal to each other.

[0024] The amount of variation (second width variation) in the width of each of the plurality of resistive films RF2 and the amount of variation (third width variation) in the width of each of the plurality of resistive films RF3 are greater than the amount of variation (first width variation) in the width of each of the plurality of resistive films RF1. The first width variation is the difference between the width of each of the plurality of resistive films RF1 and the reference width. The second width variation is the difference between the width of each of the plurality of resistive films RF2 and the reference width. The third width variation is the difference between the width of each of the plurality of resistive films RF3 and the reference width. The reference width is the width of the resistive film RF at the center in the second direction D2. When the number of the plurality of resistive films RF is even, the reference width is the width of either one of the two resistive films RF at the center in the second direction D2. The first width variation of each of the plurality of resistive films RF1 is, for example, within 0.5 percent of the reference width. The second width variation of each of the plurality of resistive films RF2 and the third width variation of each of the plurality of resistive films RF3 are each, for example, more than 0.5 percent of the reference width. In the example of FIG. 2, the width of each of the plurality of resistive films RF2 and the width of each of the plurality of resistive films RF3 are smaller than the width of each of the plurality of resistive films RF1. Here, the width of the resistive film RF is the width of the resistive film RF in the second direction D2.

[0025] FIG. 3 is a schematic block diagram of the semiconductor device DEV1. As shown in FIG. 3, the semiconductor device DEV1 has a plurality of circuits CIR1 and a plurality of circuits CIR2. The plurality of circuits CIR1 constitute a first circuit group. The plurality of circuits CIR2 constitute a second circuit group. The plurality of resistive films RF1 are electrically connected to the first circuit group. The plurality of resistive films RF2 and the plurality of resistive films RF3 are electrically connected to the second circuit group. The second circuit group is different from the first circuit group. Also, the plurality of resistive films RF2 may be electrically connected to the second circuit group, and the plurality of resistive films RF3 may be electrically connected to a third circuit group different from the first circuit group and the second circuit group.

[0026] Each of the plurality of circuits CIR1 is preferably at least one of an analog-to-digital converter circuit, a digital-to-analog converter circuit, a bandgap reference circuit, a high-frequency circuit, and an amplifier circuit. Each of the plurality of circuits CIR2 is preferably at least one of a circuit for which calibration is performed and a circuit that generates a voltage from a power supply voltage. That is, the second circuit group is preferably a circuit group for which the required accuracy of the electrical resistance value is lower than that of the first circuit group.

[0027] <Method for manufacturing semiconductor device DEV1> A method for manufacturing semiconductor device DEV1 will be described below.

[0028] FIG. 4 is a manufacturing process diagram of semiconductor device DEV1. As shown in FIG. 4, the manufacturing method of semiconductor device DEV1 includes a first wiring formation step S1, a first interlayer insulating film formation step S2, a first via hole formation step S3, a first via plug formation step S4, a resist film formation step S5, a second interlayer insulating film formation step S6, a second via hole formation step S7, a second via plug formation step S8, a second wiring formation step S9, and a third interlayer insulating film formation step S10.

[0029] Before the first wiring formation step S1 is performed, an interlayer insulating film ILD1 and a structure below it are formed. Since these structures may be formed by a conventionally known method, the description thereof is omitted here.

[0030] FIG. 5 is a cross-sectional view for explaining the first wiring formation step S1. As shown in FIG. 5, in the first wiring formation step S1, a wiring WL1, a wiring WL2, a barrier metal BM1, and a barrier metal BM2 are formed on the interlayer insulating film ILD1. In the first wiring formation step S1, first, for example, by a sputtering method, the constituent materials of the barrier metal BM1, the wiring WL1 (wiring WL2), and the barrier metal BM2 are sequentially formed into films. Second, a resist pattern is formed on the constituent material of the formed barrier metal BM2. The resist pattern is formed by exposing and developing a photoresist.

[0031] Third, using the resist pattern as a mask, the constituent materials of the formed barrier metal BM1, wiring WL1 (wiring WL2), and barrier metal BM2 are etched. As a result, the wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2 are formed. After the wiring WL1, wiring WL2, barrier metal BM1, and barrier metal BM2 are formed, the resist pattern is removed.

[0032] 6 is a cross-sectional view illustrating the first interlayer insulating film forming step S2. In the first interlayer insulating film forming step S2, as shown in FIG. 6, an interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1 so as to cover the wiring WL1, the wiring WL2, the barrier metal BM1, and the barrier metal BM2. In the first interlayer insulating film forming step S2, first, a constituent material of the interlayer insulating film ILD2 is deposited on the interlayer insulating film ILD1 by, for example, a CVD (Chemical Vapor Deposition) method so as to cover the wiring WL1, the wiring WL2, the barrier metal BM1, and the barrier metal BM2. Second, the upper surface of the deposited constituent material of the interlayer insulating film ILD2 is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. In this manner, the interlayer insulating film ILD2 is formed.

[0033] FIG. 7 is a cross-sectional view illustrating the first via hole forming step S3. In the first via hole forming step S3, as shown in FIG. 7, via holes VH1 and VH2 are formed in the interlayer insulating film ILD2. In the first via hole forming step S3, first, a resist pattern is formed on the interlayer insulating film ILD2. The resist pattern is formed by exposing and developing a photoresist. Second, the interlayer insulating film ILD2 is etched using the resist pattern as a mask. In this way, the via holes VH1 and VH2 are formed. After the via holes VH1 and VH2 are formed, the resist pattern is removed.

[0034] FIG. 8 is a cross-sectional view for explaining the first via plug forming step S4. In the first via plug forming step S4, as shown in FIG. 8, via plugs VP1 and VP2 are formed in via hole VH1 and via hole VH2. In the first via plug forming step S4, first, for example, by CVD method, via hole VH1 and via hole VH2 are filled with the constituent material of via plug VP1 (via plug VP2). Second, the constituent material of via plug VP1 (via plug VP2) protruding from via hole VH1 and via hole VH2 is removed, for example, by CMP method. Thus, via plugs VP1 and VP2 are formed.

[0035] FIG. 9 is a cross-sectional view for explaining the resistor film forming step S5. As shown in FIG. 9, in the resistor film forming step S5, a resistor film RF and an insulating film IF are formed on the interlayer insulating film ILD2. In the resistor film forming step S5, first, the constituent material of the resistor film RF is formed on the interlayer insulating film ILD2, for example, by sputtering method. Second, the constituent material of the insulating film IF is formed on the formed constituent material of the resistor film RF. Third, a resist pattern is formed on the formed constituent material of the insulating film IF. The resist pattern is formed by exposing and developing a photoresist.

[0036] Fourth, using the above resist pattern as a mask, the constituent material of the formed insulating film IF is etched. Thereby, the insulating film IF is formed. After the formation of the insulating film IF, the above resist pattern is removed. Fifth, using the insulating film IF as a mask (hard mask), the constituent material of the formed resistor film RF is etched. Thus, the resistor film RF is formed. Note that after the formation of the resistor film RF, the insulating film IF is not removed.

[0037] FIG. 10 is a cross-sectional view for explaining the second interlayer insulating film forming step S6. In the second interlayer insulating film forming step S6, as shown in FIG. 10, an interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 so as to cover the resist film RF. In the second interlayer insulating film forming step S6, first, the constituent material of the interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2 so as to cover the resist film RF by, for example, a CVD method. Second, the upper surface of the formed constituent material of the interlayer insulating film ILD3 is planarized by, for example, a CMP method. Thus, the interlayer insulating film ILD3 is formed.

[0038] FIG. 11 is a cross-sectional view for explaining the second via hole forming step S7. In the second via hole forming step S7, as shown in FIG. 11, via holes VH3 and VH4 are formed in the interlayer insulating film ILD2 and the interlayer insulating film ILD3.

[0039] In the second via hole forming step S7, first, a resist pattern is formed on the interlayer insulating film ILD3. The resist pattern is formed by exposing and developing a photoresist. Second, the interlayer insulating film ILD2 and the interlayer insulating film ILD3 are etched using the resist pattern as a mask. Thus, the via holes VH3 and VH4 are formed. Note that after the formation of the via holes VH3 and VH4, the resist pattern is removed.

[0040] FIG. 12 is a cross-sectional view for explaining the second via plug forming step S8. In the second via plug forming step S8, as shown in FIG. 12, via plugs VP3 and VP4 are formed in the via hole VH3 and the via hole VH4.

[0041] In the second via plug forming step S8, first, the via holes VH3 and VH4 are filled with the constituent material of the via plug VP3 (via plug VP4) by, for example, a CVD method. Second, the constituent material of the via plug VP3 (via plug VP4) protruding from the via holes VH3 and VH4 is removed by, for example, a CMP method. Thus, the via plugs VP3 and VP4 are formed.

[0042] FIG. 13 is a cross-sectional view for explaining the second wiring formation step S9. As shown in FIG. 13, in the second wiring formation step S9, wiring WL3, wiring WL4, barrier metal BM3, and barrier metal BM4 are formed on the interlayer insulating film ILD3. In the second wiring formation step S9, first, for example, by a sputtering method, constituent materials of the barrier metal BM3, the wiring WL3 (wiring WL4), and the barrier metal BM4 are sequentially formed into a film. Second, a resist pattern is formed on the constituent material of the formed barrier metal BM4. The resist pattern is formed by exposing and developing a photoresist.

[0043] Third, using the above resist pattern as a mask, the constituent materials of the formed barrier metal BM3, the wiring WL3 (wiring WL4), and the barrier metal BM4 are etched. Thus, the wiring WL3, the wiring WL4, the barrier metal BM3, and the barrier metal BM4 are formed. Note that the above resist pattern is removed after the formation of the wiring WL3, the wiring WL4, the barrier metal BM3, and the barrier metal BM4.

[0044] In the third interlayer insulating film formation step S10, an interlayer insulating film ILD4 is formed on the interlayer insulating film ILD3 so as to cover the wiring WL3, the wiring WL4, the barrier metal BM3, and the barrier metal BM4. In the third interlayer insulating film formation step S10, first, the constituent material of the interlayer insulating film ILD4 is formed into a film on the interlayer insulating film ILD3 so as to cover the wiring WL3, the wiring WL4, the barrier metal BM3, and the barrier metal BM4, for example, by a CVD method. Second, the upper surface of the formed constituent material of the interlayer insulating film ILD4 is planarized, for example, by a CMP method. Thus, the semiconductor device DEV1 having the structure shown in FIG. 1 is formed. After the third interlayer insulating film formation step S10 is performed, other wirings and other interlayer insulating films are sequentially laminated on the interlayer insulating film ILD4. Since these structures may be formed by a conventionally known method, the description thereof is omitted here.

[0045] <Effect of the semiconductor device DEV1> The effect of the semiconductor device DEV1 will be described below.

[0046] In the semiconductor device DEV1, due to the microloading effect when etching in the resistance film forming step S5, even if each width of a plurality of resistance films RF is designed to be constant, each width of the plurality of resistance films RF2 and each width of the plurality of resistance films RF3 may become smaller than the designed width.

[0047] When the plurality of resistance films RF2 and the plurality of resistance films RF3 are electrically connected to the first circuit group where resistance value accuracy is required, the accuracy of the circuits included in the first circuit group will decrease. On the other hand, there may be a case where the plurality of resistance films RF2 and the plurality of resistance films RF3 are made into dummy resistance films not electrically connected to the circuit, and another plurality of resistance films electrically connected to the second circuit group are formed. In this case, although a decrease in the accuracy of the circuits included in the first circuit group can be suppressed, since another resistance film electrically connected to the second circuit group is additionally formed, the chip area increases.

[0048] In the semiconductor device DEV1, since a plurality of resistance films RF1 are electrically connected to the first circuit group and a plurality of resistance films RF2 and a plurality of resistance films RF3 are electrically connected to the second circuit group, it is possible to suppress an increase in the chip area while suppressing a decrease in the accuracy of the circuits included in the first circuit group. This embodiment is not limited to the case where a plurality of resistance films RF are electrically connected to the first circuit group and the second circuit group. A plurality of resistance films RF may be electrically connected to three or more circuit groups. For example, a plurality of resistance films RF1 may be electrically connected to the first circuit group, a plurality of resistance films RF2 may be electrically connected to the second circuit group, and a plurality of resistance films RF3 may be electrically connected to the third circuit group. In this case, a plurality of resistance films RF can be used for more circuits while suppressing an increase in the chip size.

[0049] (Second Embodiment) The semiconductor device according to the second embodiment will be described. The semiconductor device according to the second embodiment is referred to as semiconductor device DEV2. Here, the differences from the semiconductor device DEV1 will be mainly described, and repeated descriptions will not be repeated.

[0050] The semiconductor device DEV2 includes a semiconductor substrate SUB, an interlayer insulating film ILD1, an interlayer insulating film ILD2, an interlayer insulating film ILD3, and an interlayer insulating film ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistor films RF1, a plurality of resistor films RF2, and a plurality of resistor films RF3, via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV2, the plurality of resistor films RF1 are electrically connected to the first circuit group, and the plurality of resistor films RF2 and the plurality of resistor films RF3 are electrically connected to the second circuit group. In this regard, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0051] FIG. 14 is a plan layout diagram of the resistor film RF in the semiconductor device DEV2. As shown in FIG. 14, in the semiconductor device DEV2, the width of each of the plurality of resistor films RF′2 and the width of each of the plurality of resistor films RF3 are larger than the width of each of the plurality of resistor films RF1. In this regard, the configuration of the semiconductor device DEV2 is different from the configuration of the semiconductor device DEV1.

[0052] Also in the semiconductor device DEV2, since the plurality of resistor films RF1 are electrically connected to the first circuit group and the plurality of resistor films RF2 and the plurality of resistor films RF3 are electrically connected to the second circuit group, similar to the semiconductor device DEV1, it is possible to suppress an increase in chip area while suppressing a decrease in the accuracy of the circuits included in the first circuit group.

[0053] (Third Embodiment) A semiconductor device according to the third embodiment will be described. The semiconductor device according to the third embodiment is referred to as a semiconductor device DEV3. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0054] The semiconductor device DEV3 includes a semiconductor substrate SUB, an interlayer insulating film ILD1, an interlayer insulating film ILD2, an interlayer insulating film ILD3, and an interlayer insulating film ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistor films RF1, a plurality of resistor films RF2, and a plurality of resistor films RF3, via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV3, the plurality of resistor films RF1 are electrically connected to the first circuit group, and the plurality of resistor films RF2 and the plurality of resistor films RF3 are electrically connected to the second circuit group. In these respects, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV1.

[0055] FIG. 15 is a plan layout view of the resistor film RF in the semiconductor device DEV3. As shown in FIG. 15, in the semiconductor device DEV3, each of the plurality of resistor films RF2 has a smaller width as it is on one side (the left side in the example of FIG. 15) in the second direction D2. That is, the width of each of the plurality of resistor films RF2 becomes smaller as the distance from the first group (the plurality of resistor films RF1) is larger in the second direction D2. Also, in the semiconductor device DEV3, the difference in width between two adjacent ones of the plurality of resistor films RF2 increases as it goes toward one side in the second direction D2. That is, the difference in width between two adjacent ones of the resistor films RF2 becomes larger as the distance from the first group is larger in the second direction D2. Similarly, each of the plurality of resistor films RF3 has a smaller width as it is on the other side (the right side in the example of FIG. 15) in the second direction D2, and the difference in width between two adjacent ones of the plurality of resistor films RF3 increases as it goes toward the other side in the second direction D2. That is, the width of each of the plurality of resistor films RF3 becomes smaller as the distance from the first group is larger in the second direction D2, and the difference in width between two adjacent ones of the plurality of resistor films RF3 becomes larger as the distance from the first group is larger. Stated from another perspective, the width of each of the plurality of resistor films RF2 changes exponentially as the distance from the first group becomes larger in the second direction D2, and the width of each of the plurality of resistor films RF3 changes exponentially as the distance from the first group becomes larger in the second direction D2.

[0056] In the semiconductor device DEV3, an image processing circuit is included in the second circuit group, and a plurality of resistance films RF2 and a plurality of resistance films RF3 are electrically connected to the image processing circuit. In the image processing circuit, it is possible to suitably use the plurality of resistance films RF2 and the plurality of resistance films RF3 whose widths vary as described above.

[0057] Also in the semiconductor device DEV3, since a plurality of resistance films RF1 are electrically connected to the first circuit group and a plurality of resistance films RF2 and a plurality of resistance films RF3 are electrically connected to the second circuit group, similar to the semiconductor device DEV1, it is possible to suppress an increase in chip area while suppressing a decrease in the accuracy of the circuits included in the first circuit group.

[0058] (Fourth Embodiment) A semiconductor device according to the fourth embodiment will be described. The semiconductor device according to the fourth embodiment is referred to as semiconductor device DEV4. Here, the differences from the semiconductor device DEV1 will be mainly described, and repeated descriptions will not be repeated.

[0059] The semiconductor device DEV4 includes a semiconductor substrate SUB, an interlayer insulating film ILD1, an interlayer insulating film ILD2, an interlayer insulating film ILD3, and an interlayer insulating film ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistance films RF1, a plurality of resistance films RF2, and a plurality of resistance films RF3, and via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV4, a plurality of resistance films RF1 are electrically connected to the first circuit group. In these respects, the configuration of the semiconductor device DEV4 is common to the configuration of the semiconductor device DEV1.

[0060] FIG. 16 is a plan layout diagram of the resistance film RF in the semiconductor device DEV4. As shown in FIG. 16, in the semiconductor device DEV4, a part of the plurality of resistance films RF2 forms a fourth group, and the remainder of the plurality of resistance films RF2 forms a fifth group. The plurality of resistance films RF2 belonging to the fourth group are referred to as a plurality of resistance films RF2a. The resistance film RF2 belonging to the fifth group is referred to as a resistance film RF2b. The resistance film RF2b is on one side (the left side in the example of FIG. 16) in the second direction D2 than the plurality of resistance films RF2a. That is, the plurality of resistance films RF2a are located between the plurality of resistance films RF1 and the resistance film RF2b in the second direction D2. The width of the resistance film RF2b is larger than the width of each of the plurality of resistance films RF2a.

[0061] Also, in the semiconductor device DEV4, a part of the plurality of resistance films RF3 forms a sixth group, and the remainder of the plurality of resistance films RF3 forms a seventh group. The plurality of resistance films RF3 belonging to the sixth group are referred to as a plurality of resistance films RF3a. The resistance film RF3 belonging to the seventh group is referred to as a resistance film RF3b. The resistance film RF3b is on the other side (the right side in the example of FIG. 16) in the second direction D2 than the plurality of resistance films RF3a. That is, the plurality of resistance films RF3a are located between the plurality of resistance films RF1 and the resistance film RF3b in the second direction D2. The width of the resistance film RF3b is larger than the width of each of the plurality of resistance films RF3a.

[0062] In the semiconductor device DEV4, the plurality of resistance films RF2a and the plurality of resistance films RF3a are electrically connected to the second circuit group. However, the resistance film RF2b and the resistance film RF3b are not electrically connected to the second circuit group and other circuits. That is, in the semiconductor device DEV4, a part of the plurality of resistance films RF2 and a part of the plurality of resistance films RF3 are electrically connected to the second circuit group, but the remainder of the plurality of resistance films RF2 and the remainder of the plurality of resistance films RF3 are dummy resistance films. In these respects, the configuration of the semiconductor device DEV4 is different from the configuration of the semiconductor device DEV1.

[0063] Note that, in the above example, the number of resistive films RF2 belonging to the fifth group and the number of resistive films RF3 belonging to the seventh group were both one, but the number of resistive films RF2 belonging to the fifth group and the number of resistive films RF3 belonging to the seventh group may be plural.

[0064] In the semiconductor device DEV4 as well, a plurality of resistive films RF1 are electrically connected to the first circuit group, and a part of the plurality of resistive films RF2 and a part of the plurality of resistive films RF3 are electrically connected to the second circuit group. Therefore, similar to the semiconductor device DEV1, it is possible to suppress an increase in chip area while suppressing a decrease in the accuracy of the circuits included in the first circuit group. Further, in the semiconductor device DEV4, since the remaining portions of the plurality of resistive films RF2 with large widths and the remaining portions of the plurality of resistive films RF3 are not electrically connected to the second circuit group, it is possible to suppress a decrease in the accuracy of the circuits included in the second circuit group.

[0065] (Fifth Embodiment) A semiconductor device according to the fifth embodiment will be described. Let the semiconductor device according to the fifth embodiment be the semiconductor device DEV5. Here, the differences from the semiconductor device DEV1 will mainly be described, and overlapping descriptions will not be repeated.

[0066] The semiconductor device DEV5 includes a semiconductor substrate SUB, an interlayer insulating film ILD1, an interlayer insulating film ILD2, an interlayer insulating film ILD3, and an interlayer insulating film ILD4, wirings WL1, WL2, WL3, and WL4, a plurality of resistive films RF1, a plurality of resistive films RF2, and a plurality of resistive films RF3, and via plugs VP1, VP2, VP3, and VP4. In the semiconductor device DEV5, a plurality of resistive films RF1 are electrically connected to the first circuit group, and a plurality of resistive films RF2 and a plurality of resistive films RF3 are electrically connected to the second circuit group. In these aspects, the configuration of the semiconductor device DEV5 is common to the configuration of the semiconductor device DEV1.

[0067] FIG. 17 is a plan layout diagram of the resistance film RF in the semiconductor device DEV5. As shown in FIG. 17, in the semiconductor device DEV5, the length of each of the plurality of resistance films RF2 is shorter than the length of each of the plurality of resistance films RF1. In this regard, the configuration of the semiconductor device DEV5 is different from the configuration of the semiconductor device DEV1.

[0068] Also in the semiconductor device DEV5, since the plurality of resistance films RF1 are electrically connected to the first circuit group and the plurality of resistance films RF2 and the plurality of resistance films RF3 are electrically connected to the second circuit group, similar to the semiconductor device DEV1, it is possible to suppress an increase in chip area while suppressing a decrease in the accuracy of the circuits included in the first circuit group. Further, in the semiconductor device DEV5, since the length of each of the plurality of resistance films RF2 can be adjusted according to the type of the circuit to which it is connected, the degree of freedom in layout is improved.

[0069] <Modification Example> In the above example, the resistance value of each of the plurality of resistance films RF2 is adjusted by adjusting the length of each of the plurality of resistance films RF2. FIG. 18 is a plan layout diagram of the resistance film RF in a modification example of the semiconductor device DEV5. As shown in FIG. 18, the resistance value of each of the plurality of resistance films RF2 may be adjusted by adjusting the interval between the via plug VP1 and the via plug VP2. More specifically, the interval in the first direction D1 between the via plug VP1 and the via plug VP2 electrically connected to the resistance film RF2 may be shorter than the interval in the first direction D1 between the via plug VP1 and the via plug VP2 electrically connected to the resistance film RF1.

[0070] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Description of Reference Numerals

[0071] BM1, BM2, BM3, BM4 barrier metals, CIR1, CIR2 circuits, D1 first direction, D2 second direction, DEV1, DEV2, DEV3, DEV4, DEV5 semiconductor devices, IF insulating film, ILD interlayer insulating film, ILD1, ILD2, ILD3, ILD4 interlayer insulating films, RF, RF1, RF2, RF2a, RF2b, RF3, RF3a, RF3b resistive films, S1 first wiring formation process, S2 first interlayer insulating film formation process, S3 first via hole formation process, S4 first via plug formation process, S5 resistive film formation process, S6 second interlayer insulating film formation process, S7 second via hole formation process, S8 second via plug formation process, S9 second wiring formation process, S10 third interlayer insulating film formation process, VH1, VH2, VH3, VH4 via holes, VP1, VP2, VP3, VP4 via plugs, WL1, WL2, WL3, WL4 wirings, SUB semiconductor substrate.

Claims

1. An interlayer insulating film, and a plurality of resistance films disposed on the interlayer insulating film, each of the plurality of resistance films extending in a first direction along the upper surface of the interlayer insulating film in a plan view, the plurality of resistance films being arranged at intervals in a second direction along the upper surface of the interlayer insulating film in a plan view and perpendicular to the first direction, the plurality of resistance films being divided into a first group, a second group, and a third group, the first group being located between the second group and the third group in the second direction, a second width fluctuation amount of each of a plurality of second resistance films belonging to the second group and a third width fluctuation amount of each of a plurality of third resistance films belonging to the third group being larger than a first width fluctuation amount of each of a plurality of first resistance films belonging to the first group, the first width fluctuation amount being a difference between a reference width and the width of each of the plurality of first resistance films, the second width fluctuation amount being a difference between the reference width and the width of each of the plurality of second resistance films, the third width fluctuation amount being a difference between the reference width and the width of each of the plurality of third resistance films, the reference width being the width of one of the plurality of resistance films at the center in the second direction, the plurality of first resistance films being electrically connected to a first circuit group, at least a part of the plurality of second resistance films and / or at least a part of the plurality of third resistance films being electrically connected to a second circuit group different from the first circuit group, a part of the plurality of second resistance films and a part of the plurality of third resistance films being electrically connected to the second circuit group, the remaining parts of the plurality of second resistance films and the remaining parts of the plurality of third resistance films being dummy resistance films, the remaining parts of the plurality of second resistance films being farther from the first group than the part of the plurality of second resistance films in the second direction, the remaining parts of the plurality of third resistance films being farther from the first group than the part of the plurality of third resistance films in the second direction, the width of each of the part of the plurality of second resistance films and the width of each of the part of the plurality of third resistance films being smaller than the reference width, the width of each of the remaining parts of the plurality of second resistance films being larger than the width of each of the part of the plurality of second resistance films, the width of each of the remaining parts of the plurality of third resistance films being larger than the width of each of the part of the plurality of third resistance films, a semiconductor device.

2. The semiconductor device according to claim 1, wherein each of the plurality of resistive films is formed of a material including at least one selected from the group consisting of silicon chromium, silicon chromium into which carbon is introduced, nickel chromium, titanium nitride, and tantalum nitride.

3. The first circuit group includes at least any one of an analog-to-digital converter circuit, a digital-to-analog converter circuit, a bandgap reference circuit, a high-frequency circuit, and an amplifier circuit. The semiconductor device according to claim 1, wherein the second circuit group includes at least any one of a circuit in which calibration is performed and a circuit that generates a voltage from a power supply voltage.

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