Semiconductor device having an insulated gate, method for manufacturing a semiconductor device having an insulated gate, and power module including a semiconductor device having an insulated gate

Abstract

The present disclosure relates to a semiconductor device, in particular a power semiconductor device, with an insulated gate, the semiconductor device with said insulated gate comprising a gate contact (9), the gate contact (9) being formed as a trench gate structure (11, 33), the semiconductor device further comprising a semiconductor body (2, 31) on which the gate contact (9) is arranged, the gate contact (9) being at least partially embedded in a nonlinear dielectric layer (10, 34).The present disclosure further relates to a method for manufacturing a semiconductor device, in particular a power semiconductor device, with an insulated gate, and to a power module including at least one power semiconductor device, in particular a power semiconductor device, with an insulated gate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having an insulated gate, particularly a power semiconductor device, including a gate contact and a semiconductor body. The present disclosure further relates to a method for manufacturing a semiconductor device having such an insulated gate, and a power module including such a semiconductor device having such an insulated gate.

Background Art

[0002] Semiconductor devices such as insulated-gate bipolar transistors (IGBTs), metal-insulating-semiconductor field-effect transistors (MISFETs), or metal-oxide-semiconductor field-effect transistors (MOSFETs) are well known in the art. IGBTs, MISFETs, or MOSFETs are three-terminal power semiconductor devices mainly used as electronic switches that were developed to have both high efficiency and fast switching. However, over time, the characteristics of such MOSFETs or IGBTs can be affected by, for example, aging and / or electrical wear after many switching cycles.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Thus, the prior art leaves room for improvement in this regard. Therefore, it would be advantageous to improve, for example, semiconductor devices having insulated gates to have higher durability.

Means for Solving the Problems

[0004] As further described below, embodiments of the present disclosure address, in whole or in part, the above-mentioned shortcomings in the art, which are addressed at least in part by providing an improved insulated gate semiconductor device, a method for manufacturing an improved insulated gate semiconductor device, and a power module including such an insulated gate semiconductor device, according to the accompanying independent claims, which solve or mitigate the above-mentioned problems.

[0005] According to a first aspect, a semiconductor device, particularly a power semiconductor device, having an insulated gate includes a gate contact, the gate contact being formed as a trench gate structure, the semiconductor device further includes a semiconductor body on which the gate contact is disposed, and the gate contact is at least partially embedded in a nonlinear dielectric layer.

[0006] In at least one embodiment, the nonlinear dielectric layer exhibits a charge-voltage dependence that is not linear.

[0007] In at least one embodiment, the gate contact is electrically isolated from the semiconductor body by the nonlinear dielectric layer at least partially surrounding the gate contact.

[0008] An advantage of the semiconductor devices disclosed herein is that they reduce or eliminate the risk of hot carrier injection into the gate insulating layer, which can cause critical conditions for avalanche initiation in the semiconductor body of such semiconductor devices to be met, such as can occur in semiconductor devices having conventional insulated gates during turn-off switching events characterized by high voltage drop (dV / dt) conditions and large currents.

[0009] The above-mentioned hot carrier injection can lead to oxide degradation effects in the gate insulating layer of conventional semiconductor devices. After repeated switching cycles, the hot carrier injection can affect the switching characteristics of the device itself.

[0010] A semiconductor device according to a first aspect can use a nonlinear dielectric in the semiconductor device to exploit the capacitance-voltage dielectric behavior of such a gate insulating layer in combination with a voltage gradient along the gate structure, thereby improving the reliability of such a semiconductor device.

[0011] Additionally, a further advantage is that problems associated with trench formation in such trench gate structures can also be alleviated or mitigated, resulting in more effective depletion and distribution of the electric field between trenches for narrow pitch devices.

[0012] The semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT), a metal-insulator-semiconductor field-effect transistor (MISFET), or a metal-oxide-semiconductor field-effect transistor (MOSFET). An IGBT having such a gate contact is also known as a trench IGBT. A MOSFET having such a gate contact is also known as a trench MOSFET. Such a trench gate structure has lateral sidewalls along which the gate contact penetrates the semiconductor body, and further has a bottom wall located at the end of the trench gate structure within the semiconductor body. The bottom wall may be substantially or completely perpendicular to the sidewalls. A nonlinear dielectric layer may be disposed along the sidewalls and bottom wall, at least partially insulating the gate contact from the semiconductor body and at least partially surrounding the gate contact.

[0013] The semiconductor body on which the gate contact is disposed includes the p-layer and n-layer of a semiconductor device, which layers may be disposed, for example, according to conventional semiconductor devices or any type of future semiconductor device to be developed.

[0014] The gate contact being at least partially embedded in the non-linear dielectric layer means that the non-linear dielectric layer covers the gate contact at least in part. The gate contact and the non-linear dielectric layer may be adjacent or may share a common surface. The non-linear dielectric layer may be arranged along the entire trench structure so that the gate contact does not directly contact the semiconductor body. Therefore, the gate contact can be separated from the semiconductor body by the non-linear dielectric layer.

[0015] In the non-linear dielectric layer, the electric dipole moment per unit volume may have a non-linear dependence on the electric field within the semiconductor device. In other words, the non-linear dielectric layer exhibits a non-linear charge-voltage dependence.

[0016] A semiconductor device having an insulated gate can be a silicon-based semiconductor device such as a silicon trench IGBT. However, a semiconductor device having an insulated gate may also be a silicon carbide (SiC) semiconductor device such as an SiC trench MOSFET or an SiC IGBT.

[0017] According to at least one embodiment, the non-linear dielectric layer may have higher capacitive coupling characteristics in the region of the sidewalls than in the region of the bottom wall of the trench gate structure. As used herein, the region of the sidewalls includes the portion of the non-linear dielectric layer located adjacent to the sidewalls, and the region of the bottom wall includes the portion of the non-linear dielectric layer located adjacent to the bottom wall.

[0018] A semiconductor device designed such that the non-linear dielectric layer has higher capacitive coupling characteristics in the region of the sidewalls than in the region of the bottom wall has the advantage that the characteristics of the non-linear dielectric layer are utilized in the semiconductor device.

[0019] In a semiconductor body, during the switching of a semiconductor device, a channel region is created adjacent to at least one side of the sidewall of the trench gate structure. The non-linear dielectric layer described herein provides a higher capacitive coupling in the region of the sidewall adjacent to this channel region in the semiconductor body than in the region of the bottom wall of the trench gate structure.

[0020] Generally, during the switching of a semiconductor device, a lower voltage drop occurs in the region of the sidewall than in the region of the bottom wall of the trench gate structure, respectively. This reduces the risk of hot carrier injection in the region of the bottom wall where a higher voltage drop occurs. In other words, a semiconductor device according to such an embodiment has self-limiting robustness against dynamic charge carrier balance in the region of the bottom wall, while at the same time having higher capacitive coupling characteristics in the region of the sidewall located adjacent to the channel region. Therefore, the gate capacitance required for electrostatic control in the region of the sidewall can be sufficiently provided without reducing the thickness of the insulating layer to such an extent that the insulating layer cannot be conveniently processed or is exposed to leakage current unacceptable to the insulating layer.

[0021] To improve those properties of the non-linear dielectric, the design of the semiconductor device and the gate dielectric material can be adapted accordingly. For example, the composition of the gate dielectric material, the operating temperature, the thickness of the non-linear dielectric layer, etc. can be adjusted.

[0022] According to at least one embodiment, the non-linear dielectric layer in which the gate contact is at least partially embedded contains a material doped with at least one additional material.

[0023] Thereby, the properties of the non-linear dielectric can be adjusted to exhibit ferroelectric behavior. Such a doped material of the non-linear dielectric layer is advantageous in that such a material as a dielectric layer can overcome problems caused by the thermodynamic incompatibility of other ferroelectric materials when used as a gate dielectric in a semiconductor device.

[0024] According to at least one embodiment, the Curie temperature of the nonlinear dielectric layer is lower than the operating temperature of the semiconductor device.

[0025] In this context, the Curie temperature of a nonlinear dielectric layer is the temperature at which a phase transition between ferroelectric and paraelectric occurs in the nonlinear dielectric layer. A material that has ferroelectric properties at lower temperatures will have paraelectric properties above its particular Curie temperature.

[0026] In this case, operating temperature refers to the operating temperature of the semiconductor device during its intended use, where the intended use refers to the use of the semiconductor device in an environment, such as a particular electronic device in which the semiconductor device is intended to be used, ambient temperature, etc. Furthermore, intended use in this context relates to the use of the semiconductor device in an environment (e.g., degree of switching) that is substantially normal for the intended use without incurring serious damage.

[0027] The advantage of having a Curie temperature of the nonlinear dielectric layer lower than the operating temperature of the semiconductor device is that the nonlinear dielectric layer exhibits paraelectric properties during such operation. Due to paraelectric properties, the dependence between induced polarization (P) and the external electric field (E) does not exhibit the hysteretic behavior of the P-E dependence of ferroelectric materials. Using an operating temperature at which the nonlinear dielectric layer exhibits paraelectric behavior (i.e., does not exhibit the hysteretic P-E dependence) has the advantage of reducing or overcoming problems arising from the time dependence of polarization in ferroelectric materials, such as threshold voltage drift over time, which can lead to long-term reliability issues, or problems that occur during switching of the semiconductor device.

[0028] According to a second aspect, a method for manufacturing a semiconductor device having an insulated gate includes the steps of: providing a semiconductor wafer for the semiconductor device; The method comprises a step of disposing a gate contact on the semiconductor wafer, the gate contact being formed as a trench gate structure and being at least partially embedded in a non-linear dielectric layer.

[0029] According to at least one embodiment, the method comprises forming a non-linear dielectric layer exhibiting a non-linear charge-voltage dependence with the doped material, in particular by doping the material with at least one further material to make it ferroelectric.

[0030] According to at least one embodiment, the gate contact is electrically insulated from the semiconductor body by the non-linear dielectric layer.

[0031] The embodiments and advantages disclosed and described with respect to the first aspect are equally applicable to the second aspect.

[0032] The advantage of the method according to the second aspect is that a semiconductor device having the above advantages can be formed in an efficient and straightforward manner. According to the above method, an oxide insulating layer, i.e., a non-linear dielectric layer, having a higher capacitive coupling in the region of the sidewalls of the trench and a self-limiting robustness against dynamic avalanche in the region of the bottom wall of the trench can be formed in a single processing step.

[0033] According to a third aspect, a power module includes at least one power semiconductor device having an insulated gate according to the first aspect.

[0034] The embodiments and advantages of the first and second aspects are equally applicable to the third aspect, and vice versa.

[0035] The semiconductor device in any of the above aspects may be, for example, an insulated gate bipolar transistor (IGBT), such as a silicon trench IGBT or a silicon carbide trench IGBT, or a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET).

[0036] Further embodiments and advantages are disclosed in the accompanying drawings and description. In the drawings, the present disclosure is described in detail with respect to an insulated gate bipolar transistor. However, this example does not limit the scope of the present disclosure. The disclosed features may be equally applicable to other types of semiconductor devices. [Brief explanation of the drawings]

[0037]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0038] Figure 1 is a schematic cross-sectional view of a part of an insulated gate bipolar transistor (IGBT) according to an embodiment of the present disclosure. The IGBT 1 includes a semiconductor body 2 having various layers. From bottom to top, the semiconductor body 2 includes a collector layer 3, an optional buffer layer 4 on the collector layer 3, and a drift layer 5 on the buffer layer 4. The drift layer 5 is significantly thicker than each of the collector layer 3 and the buffer layer 4. In the embodiment shown herein, the drift layer 5 is, for example, 5 to 10 times thicker than the buffer layer 4. On the drift layer 5, a p-well 6 is disposed that extends only along a part of the surface of the drift layer 5. An n-source region 14 is disposed on the p-well 6.

[0039] At the lower end of the semiconductor body 2, a collector contact 7 is disposed under the collector layer 3. At the upper end of the semiconductor body 2, an emitter contact 8 is disposed. The emitter contact 8 is in partial contact with the p-well 6.

[0040] A gate contact 9 is disposed between the drift layer 5 and the emitter contact 8. The gate contact 9 is embedded in a non-linear dielectric layer 10. The non-linear dielectric layer 10 surrounds the gate contact 9 such that the gate contact 9 is spatially separated and electrically insulated from any doped layer such as the emitter contact 8 and the drift layer 5. The non-linear dielectric layer 10 further spatially separates the gate contact 9 from the p-well 6 disposed adjacent to the non-linear dielectric layer 10. Thereby, the non-linear dielectric layer 10 electrically insulates the gate contact 9 from the semiconductor body 2 and the emitter contact 8.

[0041] The gate contact 9 is formed as a trench gate structure 11. This means that the gate contact 9 has a first portion that extends parallel to the major extension plane of the drift layer 5 in this embodiment. Further, the gate contact 9 has a second portion that penetrates the semiconductor body 2 in which the gate contact 9 is disposed. In the embodiment shown in FIG. 1, the first and second portions of the gate contact 9 are perpendicular to each other. Such an IGBT1 is also referred to as a trench IGBT.

[0042] The trench gate structure 11 has side walls 12, along which the trench gate structure 11 penetrates into the semiconductor body 2, and the trench gate structure 11 further has a bottom wall 13 located at the end of the trench gate structure 11 within the semiconductor body 2. In this embodiment, the bottom wall 13 is perpendicular to the side walls 12. The bottom wall 13 in this case is parallel to the major extension area of the semiconductor body 2, and the side walls 12 in this case are perpendicular to the major extension area of the semiconductor body 2. During the switching of the IGBT1, in the semiconductor body 2, a channel region is created on the side of the side walls 12 facing the emitter contact 8. Alternatively or additionally, there may be an emitter contact on the other side of the trench gate structure 11, in which case, during switching, an alternative or additional channel region will be created in the semiconductor body 2 on the other side of the trench gate structure 11. By disposing the non-linear dielectric layer 10 along the entire side walls 12 and the bottom wall 13 of the trench gate structure 11, the gate contact 9 is insulated from the semiconductor body 2.

[0043] In this case, the non-linear dielectric layer 10 is made of a material having non-linear dielectric properties. The electric dipole moment per unit volume in this material has a non-linear dependence on the electric field present in the IGBT1. Such behavior is shown, for example, by the curve in the right-hand figure of FIG. 2. This figure shows the capacitance-voltage curve of the non-linear dielectric. The capacitance of the material changes with the external electric field. In comparison, the left-hand figure of FIG. 2 shows the capacitance characteristics of a linear dielectric material with a straight charge-voltage (Q-V) curve. The slope of this curve indicates the capacitance of the material.

[0044] Such S-shaped non-linear dielectric behavior is typical of ferroelectric and normal dielectric materials, and their permittivity dependence is shown in the figure of FIG. 3. The left-hand figure shows the dielectric dependence on the external electric field of a ferroelectric non-linear dielectric material, and the right-hand figure of FIG. 3 shows the dielectric dependence on the external electric field of a normal dielectric non-linear dielectric material.

[0045] As can be seen from both curves in FIG. 3, the permittivity changes with the electric field. This behavior is advantageous for the non-linear dielectric layer 10 of the IGBT1 in FIG. 1. This is because a lower capacitive coupling is achieved in the region of the trench gate structure 11 where a higher electric field is generated, that is, in the region having a higher voltage drop. This can reduce or avoid the risk of hot carrier injection during the switching of an IGBT such as the IGBT1 in FIG. 1. By reducing or avoiding the risk of hot carrier injection in the IGBT1 using the non-linear dielectric layer 10, the durability of the IGBT1 is improved. This is because it reduces the influence of the oxide degradation of the conventional insulating layer that can occur after repeated switching cycles. Since the influence of such degradation can affect the switching characteristics of the IGBT, avoiding them improves the durability.

[0046] Some characteristics of a conventional IGBT during a switching event are shown in Figure 4. The left diagram of Figure 4 shows an example of a turn-off waveform of a conventional IGBT device under normal switching conditions. A first curve 100 shows the collector-emitter voltage over time during such turn-off switching, and a second curve 200 shows carrier avalanche over time during such turn-off switching, caused by the high voltage drop (dV / dt) of the collector-emitter voltage of the first curve 100. As can be seen from the diagram, significant avalanche occurred in this case.

[0047] The region of avalanche generation is depicted in the right-hand diagram of Figure 4, which shows a portion of a conventional IGBT 20. The right-hand diagram of Figure 4 shows the semiconductor body 21, passivation layer 22, trench gate structure 23, and insulating layer 24 of the conventional IGBT 20.

[0048] Furthermore, the impact ionization in the semiconductor body 21 during the peak 210 of the avalanche initiation (i.e., the second curve 200 in the left diagram of FIG. 4) is depicted in this right diagram of FIG. 4. As can be seen, there is a first region 25 with the highest impact ionization, a second region 26 with high impact ionization, a third region 27 with average impact ionization, and the remaining region 28 in the semiconductor body 21 with low impact ionization. This regional depiction of impact ionization is obviously simplified for ease of explanation. What can be learned from this diagram is that the highest impact ionization, i.e., the avalanche initiation, occurs in the region of the bottom wall 29 of the trench gate structure 23.

[0049] Figure 5 illustrates the characteristics of an IGBT 30 according to one embodiment of the present disclosure during turn-off switching. The left diagram of Figure 5 shows a portion of the IGBT 30 to facilitate comparison with the conventional IGBT 20 of Figure 4. The IGBT 30 according to Figure 5 also shows the semiconductor body 31, passivation layer 32, trench gate structure 33, and in this case the nonlinear dielectric layer 34 of the IGBT 30. The layout shown here differs slightly from that of the IGBT 1 shown in Figure 1, but the features of the present disclosure may be interchangeable.

[0050] The left diagram in Figure 5 shows the distribution of electrostatic potential in the IGBT 30. The first region 35 has the lowest electrostatic potential, the second region 36 has a low electrostatic potential, the third region 37 has an average electrostatic potential, and the remaining region 38 has a high electrostatic potential. As can be seen, a high electrostatic potential, i.e., a high voltage drop, occurs in the region of the bottom wall 39 of the trench gate structure 33. The lowest electrostatic potential, i.e., the lowest voltage drop, occurs in a portion of the region of the side wall 40.

[0051] As can be further seen from the diagram on the right of FIG. 5, which shows the dielectric dependence on voltage potential in the nonlinear dielectric layer 34, the dielectric constant tuning via the electric field along the trench gate structure 33 results in higher capacitive coupling in areas with the lowest voltage drop and less coupling in areas with higher voltage drop.

[0052] This reduces the risk of hot carrier injection in the region of the bottom wall 39 where high voltage drops occur. In other words, IGBT 30 according to such embodiments has self-limiting robustness against dynamic charge carrier avalanche in the region of the bottom wall 39, but at the same time has higher capacitive coupling characteristics in the region of the lateral sidewall 40 where the voltage drop is lowest.

[0053] To improve those properties of the nonlinear dielectric layer 10, 34, the design of the IGBT and the gate dielectric material can be adapted accordingly. For example, the composition of the gate dielectric material, the operating temperature, the thickness of the nonlinear dielectric layer, etc. can be adjusted.

[0054] The thickness of the nonlinear dielectric layer 10, 34 can be, for example, between 1 and 500 nanometers. A thinner dielectric layer may be advantageous for scaling rules regarding gate capacitance. A thicker dielectric layer may be easier and / or cheaper to manufacture and may reduce losses associated with gate-emitter leakage.

[0055] A first material having substantially linear dielectric behavior may be used as the material for the nonlinear dielectric layer 10, 34 in which the gate contact 9 is at least partially embedded, and this first material is doped with at least one second material to make it ferroelectric. For example, a completed device (e.g., IGBT 1, 30) may include a layer including the first material as the base or bulk material and the second material as an impurity contained therein.

[0056] An example is shown in Figure 6, which shows the polarization hysteresis loop in an applied electric field and the dielectric constant depending on the applied electric field for a thin film of the hafnium dioxide (HfO2)-zirconium dioxide (ZrO2) system. HfO2 has substantially linear dielectric behavior. Ferroelectric behavior is achieved by doping HfO2 with ZrO2. Alternatively, HfO2 may be doped with silicon (Si). Such a material overcomes the problems caused by the thermodynamic incompatibility of other ferroelectric materials when used as a gate dielectric in semiconductor devices.

[0057] A further improvement of the non-linear dielectric layers 10, 34 can be achieved by designing the IGBTs 1, 30 to have a non-linear dielectric layer 10 with a Curie temperature lower than the operating temperature of the semiconductor device. For example, the operating temperature may be the operating temperature of the IGBTs 1, 30 within a range of predefined operating conditions such as within one or more of the rated voltage, current, or temperature ratings.

[0058] At the Curie temperature of the non-linear dielectric layers 10, 34, a phase transition between ferroelectricity and paraelectricity occurs. Materials having ferroelectric properties at lower temperatures have paraelectric properties above the above-mentioned Curie temperature.

[0059] In such an operation, the non-linear dielectric layer has paraelectric properties. Due to the paraelectric properties, the dependence between the induced polarization (P) and the external electric field (E) does not have the hysteresis behavior of the P-E dependence of ferroelectric materials. Using an operating temperature at which the non-linear dielectric layer has paraelectric behavior (i.e., does not have hysteretic P-E dependence) has the advantage that it can overcome or reduce the obstacles arising from the time dependence of polarization in ferroelectric materials during the switching of the IGBT. The Curie temperature of the material can be adjusted within a specific range by changing the composition of the material. The addition of a buffer oxide layer can also affect such parameters.

[0060] FIG. 7 is a diagram showing a flowchart of a method for manufacturing an IGBT according to an embodiment of the present disclosure. In a first step 70, a semiconductor wafer for an IGBT is provided. In a second step 71, a material having a linear dielectric behavior is doped with at least one additional material, and a nonlinear dielectric layer is formed of the doped material. In a third step 72, a gate contact is disposed on the semiconductor wafer, and the gate contact is formed as a trench gate structure and is at least partially embedded in the nonlinear dielectric layer. The semiconductor wafer may be processed according to known processing steps immediately after the first step 70, or after either the second step 71 or the third step 72, to obtain a semiconductor body for the IGBT. By the above method, for example, the IGBT1 or IGBT30 according to FIG. 1 or FIG. 5 can be manufactured.

[0061] FIG. 8 is a diagram showing a power module 80 having a plurality of IGBTs 81 according to an embodiment of the present disclosure. The IGBTs 81 are, for example, those disclosed and described with respect to FIG. 1. Of course, such a power module 80 may include additional elements, such as power semiconductor diodes, which may correspond to known additional elements of such a power module 80 although not illustrated or further described herein. The power module 80 may be designed to be used at voltages of 0.5 kilovolts or more.

[0062] The IGBTs 1, 30, 81 shown herein are examples. The nonlinear dielectric layers 10, 34 that at least partially insulate the gate contacts 9 from the semiconductor bodies 2, 31 can also be applied to other types of IGBTs or other transistors.

Description of Reference Numerals

[0063] 1, 30, 81 Insulated Gate Bipolar Transistor (IGBT) 2, 21, 31 Semiconductor body 3 Collector layer 4 Buffer layer 5 Drift layer 6 p-well 7 Collector contact 8 Emitter contact 9 Gate contact 10,34 Nonlinear dielectric layer 11,23,33 Trench gate structure 12,40 Sidewall 13,29,39 Bottom wall 14 n-source region 20 Conventional IGBT 22,32 Passivation layer 24 Insulating layer 25,35 First region 26,36 Second region 27,37 Third region 28,38 Remaining region 70~72 Steps 80 Power module 100 First curve 200 Second curve 210 Peak of the second curve

Claims

1. A power semiconductor device having an insulating gate, comprising a gate contact (9), the gate contact (9) being formed as a trench gate structure (11, 33), and the power semiconductor device further comprising a semiconductor body (2, 31), on which the gate contact (9) is disposed, the gate contact (9) being at least partially embedded in a non-linear dielectric layer (10, 34) exhibiting a non-linear charge-voltage dependence that is not linear, the gate contact (9) being electrically insulated from the semiconductor body (2, 31) by the non-linear dielectric layer (10, 34) that at least partially surrounds the gate contact (9), the non-linear dielectric layer (10, 34) comprising a material doped with at least one additional material to make the non-linear dielectric layer (10, 34) ferroelectric, a power semiconductor device having an insulating gate.

2. In the non-linear dielectric layer (10, 34), the electric dipole moment per unit volume has a non-linear dependence on the electric field, the power semiconductor device having an insulating gate according to Claim 1.

3. The trench gate structure (11, 33) has side walls (12, 40), along which the gate contact (9) penetrates into the semiconductor body (2, 31), and the trench gate structure (11, 33) further has a bottom wall (13, 39) located at an end of the trench gate structure (11, 33) within the semiconductor body (2, 31), the non-linear dielectric layer (10, 34) having a higher capacitive coupling property in the region of the side walls (12, 40) than in the region of the bottom wall (13, 39), the power semiconductor device having an insulating gate according to any one of Claims 1 or 2.

4. The non-linear dielectric layer (10, 34) is hafnium dioxide (HfO ２ ) doped with zirconium dioxide (ZrO ２ ) and / or silicon (Si), and the power semiconductor device having an insulated gate according to any one of claims 1 to 3.

5. The Curie temperature of the non-linear dielectric layer (10, 34) is lower than the operating temperature of the power semiconductor device, the power semiconductor device having an insulating gate according to any one of Claims 1 to 4.

6. The thickness of the non-linear dielectric layer (10, 34) is between 1 nanometer and 100 nanometers, the power semiconductor device having an insulating gate according to any one of Claims 1 to 5.

7. The power semiconductor device according to any one of claims 1 to 6, wherein the power semiconductor device is a silicon trench insulated gate bipolar transistor (IGBT) (1, 30, 81), a silicon carbide trench IGBT, or a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET).

8. A method for manufacturing a power semiconductor device having an insulated gate, comprising: providing a semiconductor wafer for the power semiconductor device (70); forming a non-linear dielectric layer (10, 34) exhibiting non-linear charge-voltage dependence with the material doped with at least one additional material to make the material ferroelectric (71); disposing a gate contact (9) on the semiconductor wafer (72), the gate contact (9) being formed as a trench gate structure (11, 33), the power semiconductor device comprising a semiconductor body (2, 31), the gate contact (9) being at least partially embedded in the non-linear dielectric layer (10, 34) and electrically insulated from the semiconductor body (2, 31) by the non-linear dielectric layer (10, 34), the method for manufacturing a power semiconductor device having an insulated gate.

9. The method for manufacturing a power semiconductor device having an insulated gate according to claim 8, wherein in the doping step (71), the material having linear dielectric behavior is doped with the at least one additional material to make the material ferroelectric.

10. In the step (71) of doping, hafnium dioxide (HfO ２ ) is doped with zirconium dioxide (ZrO ２ ) and / or silicon (Si), and the non-linear dielectric layer (10, 34) is formed of the doped HfO ２ . A method for manufacturing a power semiconductor device having an insulated gate according to claim 9

11. A power module (80) comprising at least one power semiconductor device having an insulated gate according to any one of claims 1 to 7.

Images