Multilayer Substrate, Semiconductor Package, and Method of Manufacturing Semiconductor Package

Abstract

To achieve high-precision chip mounting and efficient manufacturing.SOLUTION: There is disclosed a multi-layered board on which a chip is flip-chip mounted. First upper conductor parts each include a first pad part exposed from a hole of an upper insulator layer, and second upper conductor parts each include a second pad part exposed from a hole of the upper insulator layer. At least a part of the first pad part is in direct contact with a first lower conductor part within a hole of a lower insulator layer. The second pad part is located outside the hole of the lower insulator layer. A top surface of the second pad part is higher than a top surface of the first pad part.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present disclosure relates to a laminated substrate, a semiconductor package, and a method of manufacturing a semiconductor package.

Background Art

[0002] In recent years, in the flip-chip mounting of semiconductor packages, with the miniaturization and multifunctionalization of chips, multi-bumping (also called area bumping) in which bumps are provided over the entire chip surface and narrow pitch have advanced.

[0003] On the other hand, since the bump pitch of the chip is small, it has become difficult to directly mount the chip on a printed circuit board-based main substrate. Therefore, in order to perform scale conversion between the chip and the main substrate and to integrate a plurality of chips having different functions into one package, a package having a Fan-out structure has been developed.

[0004] The Fan-out structure is a means for SiP (System in Package), and uses a redistribution layer (RDL) capable of fine laminated wiring as an intermediate layer to route the wiring outside the chip.

[0005] In the flip-chip mounting of a Fan-out package, generally, solder connection is used. In the fine laminated wiring within the RDL layer, it fans out from the connection pads with the chip-side bumps. Thereby, scale conversion of the mounting pitch is performed so that the chip can be connected to the main substrate.

[0006] In reflow solder connection, a self-alignment effect on the pads due to the surface tension during solder melting is known. Even if the placement position is deviated, if the pads and bumps can exhibit the self-alignment effect within the deviation range, the placement position is automatically corrected, and the pads and bumps are joined with higher accuracy than at the time of placement.

[0007] Japanese Patent Application Laid-Open No. 9-307022 discloses a method for realizing high-precision mounting by utilizing the self-alignment effect of solder in flip-chip bonding using solder bumps. Specifically, bumps are formed on four pads located at the corners of the placement area of the semiconductor package on the printed circuit board. The thickness of these four pads is larger than that of the other pads.

[0008] The configuration of Japanese Patent Application Laid-Open No. 9-307022 is that the semiconductor package is placed on the pads located at the corners via the bumps, and the self-alignment effect absorbs the load caused by the thermal expansion difference between the printed wiring board and the package body during reflow. As a result, the soldering reliability at the other pads is improved, as disclosed.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] However, the configuration of Japanese Patent Application Laid-Open No. 9-307022 thickens the pads at the corners by additionally forming a solder layer, which complicates the manufacturing process. Therefore, a technology that can achieve high-precision chip mounting and efficient manufacturing is desired.

Means for Solving the Problems

[0011] One aspect of the present disclosure is a laminated substrate including a redistribution layer in which a chip is flip-chip mounted. The laminated substrate includes an upper insulator layer, a lower conductor layer located below the upper insulator layer and including a plurality of first lower conductor portions, an upper conductor layer located between the lower conductor layer and the upper insulator layer and including a plurality of first upper conductor portions and a plurality of second upper conductor portions, and a lower insulator layer located between the lower conductor layer and the upper conductor layer. Each of the first upper conductor portions includes a first pad portion exposed from a hole in the upper insulator layer. Each of the second upper conductor portions includes a second pad portion exposed from a hole in the upper insulator layer. At least a part of the first pad portion is in direct contact with the first lower conductor portion in a hole of the lower insulator layer. The second pad portion is located outside the hole of the lower insulator layer. A surface height of the second pad portion is higher than a surface height of the first pad portion.

[0012] A method of manufacturing a semiconductor package according to another aspect of the present disclosure includes manufacturing a stacked substrate including a plurality of first pad portions and a plurality of second pad portions, preparing a chip including a plurality of first solder bumps and a plurality of second solder bumps, melting the plurality of second solder bumps in a state where the plurality of second solder bumps are in contact with the plurality of second pad portions, melting the plurality of first solder bumps in a state where the plurality of first solder bumps are in contact with the plurality of first pads after melting the plurality of second solder bumps, joining the plurality of first solder bumps and the first pad portions, and joining the plurality of second solder bumps and the second pad portions. The manufacturing of the stacked substrate includes forming a lower conductor layer, forming a lower insulator layer on the lower conductor layer, forming an upper conductor layer on the lower insulator layer, and forming an upper insulator layer on the upper conductor layer. The lower conductor layer includes a plurality of first lower conductor portions. The upper conductor layer includes a plurality of first upper conductor portions and a plurality of second upper conductor portions. Each of the first upper conductor portions includes the first pad portion exposed from a hole in the upper insulator layer. Each of the second upper conductor portions includes the second pad portion exposed from a hole in the upper insulator layer. At least a part of the first pad portion is in direct contact with the first lower conductor portion in a hole in the lower insulator layer. The second pad portion is located outside the hole in the lower insulator layer. The lowest position of the surface height of the second pad portion is higher than the lowest position of the surface height of the first pad portion.

Effect of the Invention

[0013] According to one aspect of the present disclosure, high-precision chip mounting and efficient manufacturing can be achieved.

Brief Description of the Drawings

[0014]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 5G

Figure 5H

Figure 5I

Figure 5J

Figure 5K

Figure 6

Figure 7

Figure 8A

Figure 8B

Figure 8C

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Figure 8E

Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure. For the sake of clarity in the description, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0016] [Schematic] Hereinafter, a laminated substrate on which a semiconductor chip (also simply referred to as a chip) is mounted is disclosed. The pad portion of the laminated substrate and the solder bumps of the chip are joined by reflow soldering. The reflow solder connection exhibits a self-alignment effect on the pad portion due to the surface tension during solder melting. Even if the placement position is displaced, if the pad portion and the bumps can exhibit the self-alignment effect within the displacement range, the placement position of the chip with respect to the laminated substrate is automatically corrected, and the pad portion and the bumps are joined with higher precision as a result than at the initial placement of the chip.

[0017] To make the self-alignment work more effectively, the laminated substrate disclosed below includes a first pad portion and a second pad portion with different surface heights. The surface height of the second pad portion is higher than that of the first pad portion.

[0018] More specifically, the laminated substrate includes a lower insulator layer and an upper insulator layer. The first pad portion and the second pad portion are located between the upper insulator layer and the lower insulator layer and are exposed from the holes in the upper insulator layer. At least a part of the first pad portion is in direct contact with the lower conductor portion within the hole of the lower insulator layer. The second pad portion is located outside the hole of the lower insulator layer. The surface height of the second pad portion is higher than that of the first pad portion.

[0019] The solder bumps of the chip first melt on the second pad portion, and the self-alignment function acts due to its surface tension, automatically correcting the placement position of the chip relative to the laminated substrate. Thereafter, the solder bumps of the chip also melt on the first pad portion for fine automatic position correction. Thereafter, the solder bumps solidify, and the pad portion and the bumps are soldered together.

[0020] [Structure of the laminated substrate] FIG. 1A is a plan view schematically showing a configuration example of a laminated substrate according to an embodiment of the present specification. The laminated substrate 10 includes a redistribution layer with a Fan-out structure for scale conversion between a semiconductor chip and a main substrate or for integrating a plurality of chips with different functions into one package. That is, the pitch of the pad portion on the surface opposite to the surface on which the semiconductor chip is mounted is larger than the pitch of the pad portion on the surface on which the semiconductor chip is mounted.

[0021] The Fan-out structure is a means for SiP (System in Package). Using a redistribution layer (Redistribution Layer: RDL) capable of fine laminated wiring as an intermediate layer, the wiring is routed outside the chip.

[0022] The laminated substrate 10 includes a redistribution layer (RDL) composed of a plurality of conductor layers and a plurality of insulator layers. Each conductor layer is sandwiched by insulator layers. In the configuration example shown in FIG. 1A, the outer shape of the laminated substrate 10 is rectangular, but its shape is arbitrary.

[0023] FIG. 1A shows the upper surface of the laminated substrate 10, on which a semiconductor chip (not shown in FIG. 1A) including a bump array is mounted (flip chip mounting). The semiconductor package includes the laminated substrate 10 and the semiconductor chip mounted on the laminated substrate 10. Typically, the semiconductor chip is further packaged together with the laminated substrate 10 by a molding resin.

[0024] The laminated substrate 10 includes a plurality of pads to which the bumps of the semiconductor chip are soldered. In the configuration example of FIG. 1A, the laminated substrate 10 includes a plurality of second pad portions 103 and a plurality of first pad portions 101. In FIG. 1A, four second pad portions 103 are shown, and one of them is indicated by reference numeral 103 as an example. Also, 16 first pad portions 101 are shown, and one of them is indicated by reference numeral 101 as an example. The dashed rectangle 104 indicates the outer shape of the semiconductor chip to be mounted. The pad portions 101 and 103 are located inside the outer shape 104.

[0025] The pad portions 101 and 103 are exposed from the surface of the insulator layer. The material used for the pad portions 101 and 103 is arbitrary. For example, it can be formed of copper whose exposed surface is covered with gold. The material of the insulator layer is arbitrary, and typically polyimide is used. In the configuration example of FIG. 1A, the pad portions 101 and 103 are circular, but they may have other shapes.

[0026] In the arrays of the second pad portions 103 and the first pad portions 101, the second pad portions 103 are arranged at the outer ends (outer peripheral ends). Along the virtual line from the center of gravity of the array to the center of gravity of the second pad portion at the outer end, there are no pad portions outside the second pad portion. In the configuration example of FIG. 1A, the distance from the center of gravity position of the array of the second pad portions 103 and the first pad portions 101 to the center of gravity position of each of the second pad portions 103 is greater than the distance from the center of gravity of the array to the center of gravity position of any of the first pad portions 101. Thereby, in the reflow of the solder bumps of the chip described later, the position of the chip can be effectively self-aligned. The distance from the center of gravity position of the array to the center of gravity position of the second pad portion 103 may be the same as the maximum distance to the first pad portion 101.

[0027] In the configuration example of FIG. 1A, the second pad portions 103 are arranged at point-symmetrical positions. With this arrangement, in the reflow of the solder bumps of the chip described later, the position of the chip can be effectively self-aligned. The number of the second pad portions 103 in the configuration example of FIG. 1A is 4, but the number is arbitrary. For example, for example, 2, 3, or 5 or more second pad portions may be included in the multilayer substrate 10. For example, the second pad portions may be arranged at at least two diagonal positions, or the second pad portions may be arranged at the four corners of the first pad portion group.

[0028] In the configuration example of FIG. 1A, the area of the second pad portions 103 is larger than the area of the first pad portions 101. Thereby, in the reflow of the solder bumps of the chip described later, the position of the chip can be effectively self-aligned. The pad portions can have any shape. The minimum value of the length between the two intersection points of the virtual line passing through the center of gravity of the second pad portion and its outer shape is larger than the minimum value of the length of the first pad portion. The second pad portions 103 may have a planar shape different from that of the first pad portions 101.

[0029] In the configuration example shown in FIG. 1A, the first pad portion 101 is connected to a lower-layer lower conductor portion 111 shown by a broken line and located below the uppermost insulator layer. The second pad portion 103 is a part of the conductor portion 105. The other part of the conductor portion 105 shown by a broken line exists below the uppermost insulator layer. Further, the conductor portion 105 is connected to a lower conductor portion 112. The lower conductor portion 112 is a conductor portion of the lower layer located below the uppermost insulator layer and shown by a broken line.

[0030] FIG. 1B schematically shows a cross-sectional structure along the cutting line IB-IB shown in FIG. 1A. FIG. 1B shows a cross-sectional structure of the stacked substrate 10 on the support substrate 150. The support substrate 150 is, for example, a glass substrate. The stacked substrate 10 is peeled off from the support substrate 150 after mounting the semiconductor chip.

[0031] In the configuration example shown in FIG. 1B, the stacked substrate 10 includes a lower conductor layer 110, a lower insulator layer 120, an upper conductor layer 100, and an upper insulator layer 130, which are stacked from the lower layer side (support substrate 150 side). Note that a release layer (not shown in FIG. 1B) exists between the lower conductor layer 110 and the support substrate 150. For the configuration example of FIG. 1B, an additional lower insulator layer and conductor layer may exist between the lower conductor layer 110 and the support substrate 150. The materials used for the conductor layer and the insulator layer are arbitrary. For example, copper can be used as the conductor material and polyimide can be used as the insulator material.

[0032] The lower conductor layer 110 includes a plurality of first lower conductor portions 111 and a plurality of second lower conductor portions 112. In the configuration example of FIG. 1B, the conductor portions 111 and 112 are spaced apart. The lower insulator layer 120 exists in direct contact with the lower conductor layer 110 and covering a part of the lower conductor layer 110. The lower insulator layer 120 fills the space between the lower Lead body portions.

[0033] The lower insulator layer 120 has a plurality of holes (openings). A part of the first lower conductor portion 111 is present in those holes in a plan view (as viewed in the stacking direction). That is, a part of the first lower conductor portion 111 is exposed from the lower insulator layer 120 in the holes. As will be described later, in the holes of the lower insulator layer 120, the first lower conductor portion 111 is completely covered by the first pad portion 101.

[0034] The upper conductor layer 100 includes a first pad portion 101 and a second pad portion 103. The upper insulator layer 130 is in direct contact with the upper conductor layer 100 and exists so as to cover the upper conductor layer 100 (a part thereof). As shown in FIG. 1A, the pad portion is a portion of the upper conductor portion that is exposed in the holes of the upper insulator layer 130. A part of the upper insulator layer 130 is in direct contact with the lower insulator layer 120.

[0035] A via portion 132, which is a part of the first pad portion 101, is formed in the lower insulator layer 120 and exists in the hole, and is in direct contact with the first lower conductor portion 111 in the hole. Thus, the first pad portion 101 is electrically connected to the first lower conductor portion 111 directly below it. In the example of FIG. 1B, a part of the first pad portion 101 exists on the lower insulator layer 120, but the first pad portion may be composed only of the via portion.

[0036] In a plan view, the holes of the upper insulator layer 130 where the first pad portion 101 is exposed and the holes of the lower insulator layer 120 where a part of the first lower conductor portion 111 exists overlap at least partially. A part of the first lower conductor portion 111 exists directly below the first pad portion 101 and is in direct contact with the via portion 132.

[0037] At least a part of the second lower conductor portion 112 exists directly below the second pad portion 103. The lower insulator layer 120 exists between the second lower conductor portion 112 and the second pad portion 103, and the second pad portion 103 and the second lower conductor portion 112 are spaced apart in the stacking direction.

[0038] In the configuration example shown in FIG. 1B, the first pad portion 101 exists on the first lower conductor portion 111 in the hole of the lower insulator layer 120, and the second pad portion 103 exists on the lower insulator layer 120. The thickness of the upper conductor layer 100 is substantially uniform. The surface height of the first pad portion 101 is lower than the surface height of the second pad portion 103.

[0039] The surface height of the pad portion is defined as the height of the center of gravity of the pad portion. FIG. 1B shows these height differences ΔH. In the configuration example of FIG. 1B, the lowest position on the surface of the first pad portion 101 is lower than the lowest position on the surface of the second pad portion 103. As will be described later, the fact that the surface height of the first pad portion 101 is lower than the surface height of the second pad portion 103 enables appropriate self-alignment in the reflow of the solder bumps of the semiconductor chip.

[0040] As in the configuration example of FIG. 1B, when the second lower conductor portion 112 exists directly below the second pad portion 103, that is, in a plan view, the second lower conductor portion 112 overlaps the second pad portion 103, the necessary height difference ΔH can be easily obtained. In other configuration examples, when the lower insulator layer 120 can form the necessary height difference ΔH, the conductor portion of the lower conductor layer 110 does not have to exist directly below the second pad portion 103.

[0041] In the configuration examples of FIGS. 1A and 1B, the width W2 of the second pad portion 103 is larger than the width W1 of the first pad portion 101. In this configuration example, the pad portions 101 and 103 are circular, and their widths are diameters.

[0042] FIG. 1C schematically shows the cross-sectional structure along the IC-IC cutting line shown in FIG. 1A. The first pad portion 101 is the first upper conductor portion of the upper conductor layer or a part thereof. As described with reference to FIG. 1B, the first pad portion 101 includes a via portion 132. The first lower conductor portion 111 exists directly below the first pad portion 101, and the via portion 132 is in direct contact (direct connection) with the first lower conductor portion 111. The first lower conductor portion 111 extends outward from the contact portion with the via portion 132.

[0043] FIG. 1D schematically shows a cross-sectional structure along the ID-ID cut line shown in FIG. 1A. The second pad portion 103 is a part of the second upper conductor portion 105 of the upper conductor layer. The second upper conductor portion 105 includes a via portion 133 at a position different from the pad portion 103. The via portion 133 penetrates through the hole of the lower insulator layer 120 shown in FIG. 1B and is in direct contact with the second lower conductor portion 112. The second lower conductor portion 112 extends outward from the contact portion with the via portion 133.

[0044] FIG. 2 is a cross-sectional view schematically showing a chip 20 soldered to a multilayer substrate 10. The chip 20 and the multilayer substrate 10 are joined by a bump array. The bumps are formed of solder. As will be described later, a solder bump array is disposed on the surface of the chip 20, and the bump array of the chip 20 is reflow-joined to the pad portions 101 and 103 of the multilayer substrate 10.

[0045] In the configuration example shown in FIG. 2, the first pad portion 101 is joined to a bump 211 (first solder bump), and the second pad portion 103 is joined to a bump 212 (second solder bump). In FIG. 2, one of the bumps joined to each of the first pad portions 101 is indicated by reference numeral 211 as an example. Also, one of the bumps joined to each of the second pad portions 103 is indicated by reference numeral 212 as an example.

[0046] After reflow, the height D2 of the bump 212 is smaller than the height D1 of the bump 211. The height of the bump is the distance from the pad surface to the main surface of the chip 20. This difference in height is caused by the height difference between the surface heights of the first pad portion 101 and the second pad portion 103. In this configuration example, the shapes (including sizes) of the bumps 211 and 212 before reflow are common. Thus, by having common bump shapes before reflow, a bump array can be efficiently formed on the chip 20.

[0047] In the configuration example shown in FIG. 2, the bumps 211 and 212 are composed of only solder. In other configuration examples, the bump may include a pillar and a solder portion at the tip of the pillar. The pillar is typically formed of copper. Also, in other configuration examples, the bump 211 and the bump 212 may have different shapes. For example, the width of the bump 212 may be larger than the width of the bump 211. When the width of the bump is not constant, the minimum value may be used as a reference.

[0048] [Solder reflow] Self-alignment of the chip mounting position due to reflow of the solder bumps will be described. FIGS. 3A, 3B, and 3C are schematic diagrams for explaining chip self-alignment by reflow of the solder bumps. Note that one of a plurality of components of the same type is indicated by a reference numeral as an example.

[0049] Reflow soldering exhibits a self-alignment effect between the pad and the bump due to the surface tension during solder melting. Even if the initial placement position of the chip with respect to the stacked substrate is misaligned, if the pad and the bump are within a specific misalignment range and the self-alignment effect is obtained, the chip mounting position is automatically corrected. As a result, the chip 20 is joined to the stacked substrate 10 with higher accuracy than at the initial placement.

[0050] FIG. 3A schematically shows the chip 20 at the initial value placement position with respect to the stacked substrate 10 and the surface tension due to solder bump reflow. Roll Bumps 211 and 212 are pre-arranged on one surface of the chip 20. The chip 20 is placed on the stacked substrate 10 such that the surface on which the bumps 211 and 212 are arranged faces the surface on which the pad portions 101 and 103 of the stacked substrate 10 are present.

[0051] In FIG. 3A, the chip 20 is displaced to the left from the proper position with respect to the stacked substrate 10. The surface height of the second pad portion 103 is higher than the surface height of the first pad portion 101. Therefore, when the chip 20 is placed on the stacked substrate 10, the bump group 212 contacts the surface of the second pad portion group 103 first. At this time, the bump group 211 has not yet contacted the first pad portion group 101.

[0052] Heated, the bump group 212 Melting and surface tension is generated. Even if the initial position of the bump group 212 is displaced with respect to the second pad portion group 103, Melting due to the surface tension of the heated bump group 212, the position of the chip 20 with respect to the stacked substrate 10 is corrected. In the example of FIG. 3A, the surface straight force acts so as to shift the chip 20 from the left side to the right side.

[0053] In addition, in FIG. 3A, although the end portions of the first pad portion 101 appear to be in contact with the bumps, in reality, they are separated or, even if in contact, the area is very small, so the solder does not spread on the first pad portion 101.

[0054] FIG. 3B shows the chip 20 at the corrected position by self-alignment. Due to the self-alignment effect in the second pad portion group 103, the position of the bump group 211 corresponding to the first pad portion group 101 is also corrected. Further, due to the melting of the solder bumps 212 in the second pad portion group 103, the chip 20 sinks downward, and the first pad portion group 101 also comes into contact with the solder bump group 211.

[0055] FIG. 3C schematically shows the stacked substrate 10 and the chip 20 after the reflow is completed. By continuing the reflow heating, the solder spreads on the pads with the bumps corresponding to the first 1 pad group also in the state of having been position-corrected, and the reflow solder connection is completed.

[0056] As described above, due to the surface tension of the molten bump group 212 on the second pad portion group 103, the chip 20 is self-aligned with respect to the stacked substrate 10. Since the self-alignment force is generated on the second pad portion group 103 that is appropriately arranged with respect to the self-alignment, the chip 20 can be appropriately aligned with the stacked substrate 10 without requiring a high-precision initial arrangement. In addition, the bump group 212 joined to the second pad portion group 103 can absorb the load due to the difference in thermal expansion between the stacked substrate 10 and the chip 20, and can improve the connection reliability of the solder bumps.

[0057]

[0058]

[0059] [Manufacture of Multilayer Substrate]

[0060]

[0061]

[0062] Next, referring to FIG. 4C, an upper conductor layer including a first pad portion 101 and a second pad portion 103 is formed. The first pad portion 101 is all or part of the first upper conductor portion, and the second pad portion 103 is all or part of the second upper conductor portion. In the configuration example shown in FIG. 1D, the second pad portion 103 is part of the second upper conductor portion. The formation of the upper conductor layer can form the first upper conductor portion group and the second upper conductor portion group, for example, by using plating on the pattern of the seed layer.

[0063] The first pad portion 101 is in direct contact with the first lower conductor portion 111 in the hole 123 of the lower insulator layer 120. The main portion other than the outer peripheral end portion of the first pad portion 101 is formed in the hole 123. The second pad portion 103 is formed on the lower insulator layer 120. As a result, the surface height of the first pad portion 101 is lower than the surface height of the second pad portion 103.

[0064] Next, referring to FIG. 4D, an upper insulator film 135 is formed so as to cover the entire support substrate 150 including the upper conductor layer. Next, referring to FIG. 4E, exposure and development are performed on the upper insulator film 135 through a mask to form holes including holes 136 and 137, thereby forming an upper insulator layer 130. The hole 136 is a hole for exposing the first pad portion 101, and the hole 137 is a hole for exposing the second pad portion 103. In FIG. 4E, one hole for exposing the first pad portion 101 is indicated by reference numeral 136 as an example. Also, one hole for exposing the second pad portion 103 is indicated by reference numeral 137 as an example.

[0065] Next, the method for forming the insulator layer and the conductor layer of the stacked substrate 10 will be described in more detail. FIGS. 5A to 5K each show steps in the manufacture of the stacked substrate 10. Referring to FIG. 5A, a release layer 201 is slit-coated and fired on a support substrate 150 formed of glass. The purpose is to peel the semiconductor package from the support substrate 150 after the completion of the semiconductor package.

[0066] Next, referring to FIG. 5B, a copper seed layer 203 is deposited by sputtering on the entire surface of the release layer 201 (support substrate 150) for subsequent copper plating. Next, referring to FIG. 5C, for subsequent copper plating, a photosensitive resist is applied, exposed through a mask, and then developed. As a result, a resist pattern 205 is formed.

[0067] Next, referring to FIG. 5D, copper is electroplated Below Partial plating portions 251 and 252 are formed on the seed layer 203 within the holes of the resist pattern 205. Next, referring to FIG. 5E, the resist pattern 205 is removed. As a result, the seed layer 203 is exposed only through the holes from which the resist pattern 205 has been removed.

[0068] Next, referring to FIG. 5F, regions other than the plated regions of the seed layer 203 are removed by etching. For example, wet etching using an etching solution is selected. As a result, only the portions of the seed layer 203 under the lower plating portions 251 and 252 remain. The lower plating portion 251 and the seed layer immediately below it, as well as the lower plating portion 252 and the seed layer immediately below it, each constitute a lower conductor portion.

[0069] Next, referring to FIG. 5G, an insulator is applied to the entire surface of the release layer 201 (support substrate 150) and fired to form a lower insulator film 221. The insulating material is, for example, polyimide. Depending on the shape of the lower plating portions 251 and 252, the lower insulator film 221 is formed slightly raised on the lower plating portions 251 and 252.

[0070] Therefore, as described with reference to FIG. 1B, the second lower conductor portion 112 raises the position of the lower surface of the second pad portion 103 via the lower insulator layer 120. As a result, a height difference in the surface heights of the second pad portion 103 and the first pad portion 101 is effectively formed. In the following description of the manufacturing process, this raising is omitted.

[0071] Next, referring to FIG. 5H, the lower insulator film 221 is exposed and developed through a mask to form a plurality of holes including holes 223. As a result, a lower insulator layer 225 having a plurality of holes is formed. A part of the lower plating portion 252 is exposed to the outside through the holes 223. A part of the lower plating portion 251 may be exposed to the outside through holes (not shown).

[0072] Next, refer to FIG. 5I. As described with reference to FIGS. 5B, 5C, and 5D, after forming the seed layer 231, a plating resist pattern 235 is formed, and further, upper plating portions 241 and 242 are formed by electrolytic plating in the holes of the resist pattern 235. The upper plating portion 241 and the seed layer 231 directly thereunder constitute an upper conductor portion. A part of the upper plating portion 241 and the seed layer 231 directly thereunder constitute the second pad portion 103 shown in FIG. 1B.

[0073] The upper plating portion 242 and the seed layer 231 directly thereunder constitute an upper conductor portion. A part of the upper plating portion 242 and the seed layer 231 directly thereunder constitute the first pad portion 101 shown in FIG. 1B. The portions of the seed layer 231 and the upper plating portion 242 within the holes 223 of the lower insulator layer 225 correspond to the via portion 132 for conducting with the lower conductor portion 111 shown in FIG. 1B.

[0074] Electrolytic plating deposits copper substantially evenly in film thickness along the unevenness of the base. Therefore, in FIG. 5I, the surface of the upper plating portion 242 pad portion is lower than the surface of the upper plating portion 241, and a height difference ΔH occurs. This corresponds to the height difference ΔH between the first pad portion 101 and the second pad portion 103 described with reference to FIG. 1B.

[0075] Next, refer to FIG. 5J. As described with reference to FIGS. 5E and 5F, the resist pattern 235 is peeled off, and the regions other than the plated regions of the seed layer 231 are removed by etching.

[0076] Next, refer to FIG. 5K. As described with reference to FIGS. 5G and 5H, an insulator is applied to the entire surface of the support substrate 150 and fired to form an upper insulator film. Further, the upper insulator film is exposed and developed through a mask to form a plurality of holes including holes 243 and 244. Thereby, a lower insulator layer 245 having a plurality of holes is formed. The portion of the upper conductor part exposed from hole 243 corresponds to the first pad part 101, and the portion of the upper conductor part exposed from hole 244 corresponds to the second pad part 103.

[0077] Chip mounting arranges the semiconductor chip 20 on the multilayer substrate 10 and completes the solder bonding by reflow. In order to obtain a self-alignment effect according to the height difference provided between the first pad part and the second pad part, in manufacturing the multilayer substrate 10, as shown in FIG. 1B, a via part is not provided directly under the second pad part 103, and a via part 132 is formed directly under the first pad part 101.

[0078] [Structural Example of Multilayer Substrate] Hereinafter, a more specific structure of the multilayer substrate 10 will be described. FIG. 6 shows the height G of the solder bump and the height difference ΔH between the surfaces of the first pad part 101 and the second pad part 103. In the configuration example of FIG. 6, the solder bump 211 is joined to the surface of the chip 20 without passing through a pillar. Therefore, the distance from the surface of the chip 20 to the tip of the solder bump 211 corresponds to the height of the solder bump. When the solder bump is joined to the tip of the pillar, the distance from the tip of the pillar to the tip of the solder bump corresponds to the solder bump height.

[0079] In one embodiment of this specification, the height difference ΔH is greater than 0 and equal to or less than 0.3G (0 < ΔH ≦ 0.3G). Thereby, the solder bump 211 can be properly joined by the first pad part 101. When the pad part height difference ΔH is too large with respect to the bump height G, it becomes impossible to perform reflow solder bonding of the bump 211 to the first pad part 101. Therefore, in one example, the pad part height difference ΔH is equal to or less than 0.2G. Also, in order to perform more appropriate self-alignment, the pad part height difference ΔH may be set to 0.1G or more.

[0080] FIG. 7 shows the relationship between the thickness t of the first pad portion 101 and the opening width (inner diameter of the hole) W of the lower insulator layer 120. The hole in the lower insulator layer 120 has a depth h. Since the thickness of the seed layer is extremely small compared to the plating thickness, the thickness t of the first pad portion 101 is substantially the plating thickness. In one embodiment of the present specification, the opening width W is not less than twice the pad thickness t (W ≧ 2t). With this relationship, the height difference ΔH between the first pad portion 101 and the second pad portion 103 can be formed more appropriately.

[0081] As described above, by satisfying the predetermined relationships among the solder bumps, the pad portions, and the holes in the lower insulator layer, the height difference between the pads is actively created, and the self-alignment by reflow soldering in the first pad portion and the second pad portion works with a time difference.

[0082] Hereinafter, specific numerical values of the multilayer substrate 10 that satisfy the above conditions are shown as examples. FIG. 8A shows an example of the specific sizes of the lower conductor portions 111 and 112 and the lower insulator layer 120 formed on the support substrate 150. In one example, the plating thickness t of each layer is 5 μm, and the thickness of the insulator layer is 8 μm. The depth h of the hole in the lower insulator layer 120 where the first lower conductor portion 111 is exposed is 3 μm.

[0083] In the manufacture of the multilayer substrate 10, the second lower conductor portion 112 of the lower conductor layer has a diameter of φ50 μm, the first lower conductor portion 111 has a diameter of φ30 μm, and they are formed by plating at a pitch of 50 μm, covered with the lower insulator layer 120, and via holes are provided in the lower insulator layer 120 on the first lower conductor portion 111 with a diameter of φ14 μm. FIG. 8A indicates only one hole as reference numeral 301 as an example. Note that the pitches of the first lower conductor portion 111 and the second lower conductor portion 112 do not have to be the same. For example, the pitch of the second lower conductor portion 112 may be larger than the pitch of the first lower conductor portion 111.

[0084] As shown in FIG. 8B, the manufacturing of the laminated substrate 10 forms a first upper conductor part including a first pad part 101 and a second upper conductor part including a second pad part 103 in the same process using plating. In the example of FIG. 8B, the widths of the laminated upper conductor part and the lower conductor part are the same, but they may be different.

[0085] The opening width W of the holes in the lower insulator layer 120 satisfies W≧2t (plating thickness t). Since the first pad part 101 is formed following the hole depth (step) h of the lower insulator layer 120, at this time, the height difference between the surfaces of the first pad part 101 and the second pad part 103 is 3 μm (equivalent to the hole depth h).

[0086] As shown in FIG. 8C, the manufacturing of the laminated substrate 10 forms an upper insulator layer 130 having a plurality of holes. The opening width W of the holes where the first pad part 101 is exposed is 20 μm, and the opening width W of the holes where the second pad part 103 is exposed is 40 μm.

[0087] FIG. 8D shows the chip 20 disposed on the laminated substrate 10 for solder bonding. The height G of the solder bump is 15 μm. There is a height difference ΔH of about 3 μm between the first pad part 101 and the second pad part 103. Also, with respect to the solder height G = 15 μm, the height difference ΔH = 3 μm, Δ H≦0.3G is satisfied.

[0088] Therefore, even if the position where the chip 20 is disposed on the laminated substrate 10 is displaced, first, the solder bump 212 contacts the second pad part 103, and the solder bump 211 does not contact the first pad part 101. Solder wets and spreads only on the second pad part 103, and its surface tension functions as a self-alignment function.

[0089] FIG. 8E shows the details of the portion surrounded by the dashed circle E in FIG. 8D. In the previous figures, the structure has been described for convenience, so at the edge of the hole in the upper insulator layer 130, the solder bump 211 is in contact with the first pad portion 101. However, as shown in FIG. 8E, actually, the first pad portion 101 has a tapered shape, and the solder bump 211 does not contact the first pad portion 101, or even if it contacts, the area is small, so the solder does not spread.

[0090] When the solder spreads on the second pad portion 103, the position of the chip 20 with respect to the stacked substrate 10 is corrected by self-alignment. For the height difference ΔH = 3 μm between the first pad portion 101 and the second pad portion 103, the allowable height difference for the solder to spread is designed with the solder bump height G = 15 μm. Therefore, Δ H ≤ 0.3G (= 4.5 μm) is satisfied. Thus, even if there is a height difference, the solder bump 211 contacts and collapses at the first pad portion 101, so the solder spreads. Finally, the solder also spreads at the first pad portion 101, and the misaligned position is self-aligned near the center, and the reflow soldering joint is completed.

[0091] As described above, the embodiments of the present disclosure have been described, but the present disclosure is not limited to the above embodiments. Those skilled in the art can easily change, add, and convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

Description of Reference Numerals

[0092] 10 Stacked substrate 20 Semiconductor chip 100 Upper conductor layer 101 First pad portion 103 Second pad portion 111 First lower conductor portion 112 Second lower conductor portion 120 Lower insulator layer 130 Upper insulator layer Via portions 132 and 133 Seed layer 203 Solder bumps 211 and 212 Upper plating portions 241 and 242 Lower plating portions 251 and 252 W Opening width t Pad thickness ΔH Pad portion height difference W1 Width of the first pad portion W2 Width of the second pad portion h Hole depth

Claims

1. A laminated substrate including a rewiring layer in which a chip is flip-chip mounted, comprising: an upper insulator layer; a lower conductor layer positioned below the upper insulator layer and including a plurality of first lower conductor portions and a plurality of second lower conductor portions; an upper conductor layer positioned between the lower conductor layer and the upper insulator layer and including a plurality of first upper conductor portions and a plurality of second upper conductor portions; a lower insulator layer positioned between the lower conductor layer and the upper conductor layer; wherein each of the first upper conductor portions includes a first pad portion exposed from a hole in the upper insulator layer; each of the second upper conductor portions includes a second pad portion exposed from a hole in the upper insulator layer; at least a part of the first pad portion is in direct contact with the first lower conductor portion within a hole in the lower insulator layer; the second pad portion is disposed in direct contact with the lower insulator layer outside the hole in the lower insulator layer; the second pad portion is spaced apart from the second lower conductor portion by the lower insulator layer intervening between the second pad portion and the second lower conductor portion in a thickness direction of the second pad portion; a surface height of the second pad portion is higher than a surface height of at least a part of the first pad portion; a laminated substrate.

2. The laminated substrate according to claim 1, wherein an area of the second pad portion is larger than an area of the first pad portion; a laminated substrate.

3. The laminated substrate according to claim 1, wherein the second pad portion is located at an outer peripheral end of an array including the first pad portion and the second pad portion; a laminated substrate.

4. The laminated substrate according to claim 1, wherein a portion extending from each of the second pad portions of the plurality of second upper conductor portions is covered by the upper insulator layer and contacts the second lower conductor portion within a hole in the lower insulator layer; a laminated substrate.

5. The laminated substrate according to claim 1, wherein a width of the hole in the lower insulator layer is equal to or more than twice a thickness of the first pad portion; a laminated substrate.

6. a semiconductor chip; the laminated substrate according to claim 1; solder bumps joining a surface of the semiconductor chip to the first pad portion and the second pad portion; a semiconductor package including the above.

7. A method of manufacturing a semiconductor package, comprising: manufacturing a laminated substrate including a plurality of first pad portions and a plurality of second pad portions; preparing a chip including a plurality of first solder bumps and a plurality of second solder bumps; With the plurality of first pad portions and the plurality of first solder bumps being in a separated state, the plurality of molten second solder bumps are spread on the plurality of second pad portions, including spreading the plurality of molten second solder bumps on the plurality of second pad portions and then spreading the plurality of molten first solder bumps on the plurality of first pad portions, The manufacturing of the laminated substrate forms a lower conductor layer, forms a lower insulator layer on the lower conductor layer, forms an upper conductor layer on the lower insulator layer, forms an upper insulator layer on the upper conductor layer, including The lower conductor layer includes a plurality of first lower conductor portions and a plurality of second lower conductor portions, The upper conductor layer includes a plurality of first upper conductor portions and a plurality of second upper conductor portions, Each of the first upper conductor portions includes the first pad portion exposed from the hole of the upper insulator layer, Each of the second upper conductor portions includes the second pad portion exposed from the hole of the upper insulator layer, At least a part of the first pad portion is in direct contact with the first lower conductor portion within the hole of the lower insulator layer, The second pad portion is disposed in direct contact with the lower insulator layer outside the hole of the lower insulator layer, The second pad portion is separated from the second lower conductor portion by the lower insulator layer interposed between the second pad portion and the second lower conductor portion in the thickness direction of the second pad portion, The surface height of the second pad portion is higher than the surface height of at least a part of the first pad portion, Manufacturing method.

8. A method for manufacturing a semiconductor package according to claim 7, wherein the height difference ΔH between the surfaces of the first pad portion and the second pad portion and the height G of the first solder bump satisfy the following relationship: 0 < ΔH ≤ 0.3G Method for manufacturing a semiconductor package.

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