MOSFET Device and Method for Manufacturing the Same

Abstract

The present invention provides a MOSFET device and a manufacturing method thereof, which includes first implanting first ions through a patterned mask to form a well region that is difficult to diffuse, then implanting second ions through the patterned mask and its sidewalls to self-align with the source region, and forming a semi-super junction at the bottom of the well region and in contact with the bottom of the well region due to the second ions being more diffusive than the first ions, which effectively expands the junction depth of the well region, thereby improving the breakdown voltage of the device and realizing high conductivity of the device, while shifting the peak of the electric field strength below the gate oxide layer to the bottom of the well region, effectively reducing and making the electric field strength below the gate oxide layer more uniform, and further improving the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of MOSFET device manufacturing, and particularly to MOSFET devices and manufacturing methods thereof.

Background Art

[0002] Silicon carbide (SiC) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices have advantages such as fast switching speed and low on-resistance, and can achieve a high breakdown voltage level with a small drift layer thickness, reducing the volume of power switch modules and reducing power consumption, and have high superiority in application fields such as power switches and converters.

[0003] Since aluminum (Al) has low diffusivity in SiC by ion implantation, in the conventional planar gate SiC MOSFET process, a P-well with a certain depth is often obtained by means of several Al ion implantations. However, the diffusion effect of Al in SiC is low, and a deeper junction depth cannot be obtained by the diffusion process, so the breakdown voltage of the SiC has not been able to reach the ideal value conventionally. In addition, an electric field spike always exists under the gate oxide layer, and the reliability of SiC MOSFET devices is always threatened.

[0004] The above problems also exist in other planar MOSFET processes that form a P-well by several Al ion implantations.

Summary of the Invention

[0005] An object of the present invention is to provide a MOSFET device and a manufacturing method thereof that can reduce the electric field peak at the bottom of the gate oxide layer and improve the breakdown voltage and reliability of the device.

[0006] To achieve the above object, the present invention Prepare a substrate, form a patterned mask layer on the substrate, use the patterned mask layer as a mask, and implant first ions of a first conductivity type into the surface layer of the substrate to form a well region. Form sidewalls on the sidewalls of the patterned mask layer, use the patterned mask layer and the sidewalls as a mask, and implant ions of a second conductivity type into the surface layer of the well region to form a source region. Use the patterned mask layer and the sidewalls as a mask, and implant second ions of the first conductivity type, which diffuse more easily in the substrate than the first ions, into the substrate below the well region to form a semi-superjunction that contacts the bottom of the well region and is self-aligned with the source region. Provide a method for manufacturing a MOSFET device, including forming a gate oxide layer and a gate sequentially stacked on the substrate, and using a region overlapping the gate in the well region as a channel of the MOSFET device.

[0007] Optionally, the prepared substrate includes a second-conductivity-type base material, a second-conductivity-type buffer layer, and a second-conductivity-type drift layer stacked in sequence, the drift layer is a silicon carbide layer, and both the well region and the semi-superjunction are formed in the drift layer.

[0008] Optionally, after implanting the first ions of the first conductivity type into the substrate below the well region, annealing activation is performed. The second ions diffuse more easily in the substrate than the first ions during annealing activation, and the semi-superjunction is formed after the second ions diffuse in the substrate.

[0009] Optionally, before forming the semi-superjunction by performing annealing activation after implanting the second ions, the manufacturing method includes removing the patterned mask layer and the sidewalls. Forming a body contact region of a first conductivity type and a junction implantation region of a second conductivity type by corresponding ion implantation, wherein the body contact region is formed in the source region and deeply penetrates into a part of the well region to short-circuit the source region and the well region, and the junction implantation region is at the bottom of the gate and between the well regions on both sides of the gate, further comprising the steps of.

[0010] Optionally, the first ion contains aluminum ions, and the second ion contains boron ions and / or boron fluoride ions.

[0011] Optionally, the implantation process parameters of the first ion include an implantation energy of 50 keV to 800 keV and an implantation dose of 1E12 / cm 2 ~9E13 / cm 2 And / or the implantation process parameters of the second ion include an implantation energy of 100 keV to 2 MeV and an implantation dose of 1E12 / cm 2 ~5E14 / cm 2 Including.

[0012] Optionally, the process conditions for annealing activation include an annealing temperature of 1500 °C to 1900 °C and an annealing time of 2 min to 200 min.

[0013] [[ID=2X]]Optionally, the manufacturing method further includes Forming an interlayer dielectric layer on the substrate, in which the gate is embedded and a part of the source region is exposed; Forming a source metal layer electrically connected to the source region on the interlayer dielectric layer; Forming a drain metal layer on the bottom surface of the substrate.

[0014] Based on the same inventive concept, the present invention further provides A substrate having a well region of a first conductivity type, a semi-superjunction, and a source region of a second conductivity type formed therein, wherein the well region is formed in a surface layer of a partial region of the substrate, the source region is formed in a surface layer of the well region, the semi-superjunction is formed in the substrate below the well region, and a substrate that is self-aligned with the source region and contacts the bottom of the well region, A gate oxide layer and a gate sequentially stacked on the substrate, wherein the gate has an overlap with the source region, and the well region on one side of the source region and at the bottom of the gate forms a MOSFET device channel, including a gate oxide layer and a gate, further providing a MOSFET device.

[0015] Optionally, the MOSFET device includes a second conductivity type base material, a second conductivity type buffer layer, and a second conductivity type drift layer sequentially stacked, the drift layer is a silicon carbide layer, and both the well region and the semi-superjunction are formed in the drift layer. The first conductivity type ions doped in the well region include aluminum ions, and the first conductivity type ions doped in the semi-superjunction include boron ions and / or boron fluoride ions.

[0016] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects.

[0017] 1. First, perform the implantation of the first ions through a patterned mask to form a well region that is difficult to diffuse. Next, perform the implantation of the second ions so as to be self-aligned with the source region by the patterned mask and the sidewalls on its sidewalls. Further, due to the property that the second ions are more likely to diffuse compared to the first ions, form a semi-superjunction at the bottom of the well region and in contact with the bottom of the well region. The semi-superjunction plays a role in effectively expanding the junction depth of the well region, enabling the improvement of the device breakdown voltage and realizing the high conductivity of the device. On the other hand, it can shift the peak of the electric field strength below the gate oxide layer to below the well region, effectively reducing the electric field strength below the gate oxide layer to be more uniform, and further improving the reliability of the device.

[0018] 2. The process is easy to implement and can achieve the desired structure without requiring multi-layer lithography.

Brief Description of the Drawings

[0019] Those skilled in the art can understand that the provided drawings are for better understanding of the present invention and do not limit the scope of the present invention in any way. The description of the drawings is as follows.

Figure 1

Figure 2

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Figure 4

Modes for Carrying Out the Invention

[0020] In the following description, numerous specific details are provided in order to understand the present invention more thoroughly. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, some technical features known in the art are not described in order to avoid confusion with the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments provided herein. Rather, by providing these embodiments, the disclosure is thorough and complete, and the scope of the present invention is fully conveyed to those skilled in the art. In the figures, the size and relative size of layers and regions may be exaggerated for clarity purposes. The same reference numerals indicate the same elements throughout the drawings. It should be understood that when an element or layer is described as being "on" another element or layer, "connected to" another element or layer, it may be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. Conversely, when an element is described as being "directly on" another element or layer, "directly connected to" another element or layer, no intervening elements or layers are present. The terms first, second, etc. may be used to describe various elements, members, regions, layers, and / or portions, but these elements, members, regions, layers, and / or portions should not be limited to these terms. These terms are merely for distinguishing one element, member, region, layer, or portion from another. Thus, a first element, member, region, layer, or portion discussed below without departing from the teachings of the present invention can be denoted as a second element, member, region, layer, or portion. Spatial relationship terms such as "under," "below," "beneath," "over," "above," etc. are used herein for convenience of description to explain the relationship of one element or feature shown in the figure to another. It should be understood that the spatial relationship terms are intended to encompass various orientations of the device during use and operation in addition to the orientation shown in the figure. For example, if the device in the figure is inverted, an element or feature described as "under," "below," or "beneath" will be oriented "above" another element or feature.The device may have other orientations (90-degree rotation or other orientations), and the spatial descriptors used herein are interpreted accordingly. The terms used herein are merely for the purpose of describing specific embodiments and do not limit the present invention. In use, the singular forms "a", "one", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Also, the term "comprising" is for identifying the presence of features, steps, operations, elements, and / or components, but should not be understood to exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0021] In the following, the technical solutions proposed in the present invention will be described in more detail in association with the drawings and specific embodiments. Through the following description, the advantages and features of the present invention will become clearer. It should be noted that all the drawings are in a very simplified scale with little requirement for accuracy and are merely for the purpose of facilitating and clearly explaining the embodiments of the present invention.

[0022] Referring to FIG. 1, an embodiment of the present invention includes preparing a substrate, forming a patterned mask layer on the substrate, using the patterned mask layer as a mask, and implanting first ions of a first conductivity type into the surface layer of the substrate to form a well region, step S1; forming sidewalls on the sidewalls of the patterned mask layer, using the patterned mask layer and the sidewalls as a mask, and implanting ions of a second conductivity type into the surface layer of the well region to form a source region, step S2; using the patterned mask layer and the sidewalls as a mask, and implanting second ions of a first conductivity type that are more diffusible in the substrate than the first ions into the substrate below the well region to form a semi-superjunction that contacts the bottom of the well region and is self-aligned with the source region, step S3; A method for manufacturing a MOSFET device is provided, including step S4 of forming a gate oxide layer and a gate sequentially stacked on the substrate, and using a region overlapping the gate in the well region as a channel of the MOSFET device.

[0023] Hereinafter, with an example where the first conductivity type is P-type and the second conductivity type is N, the technical solution of this embodiment will be described in detail in association with FIG. 2. Naturally, in other embodiments of the present invention, the first conductivity type may be N-type and the second conductivity type may be P-type.

[0024] Specifically, referring to (A) in FIG. 2, in step S1, an arbitrary suitable semiconductor material such as silicon carbide or silicon may be prepared to form the substrate 100. For example, the prepared substrate 100 is an N-type substrate, and an N+ substrate 100a, an N buffer layer 100b, and an N-drift layer 100c are sequentially stacked from bottom to top. Among the N+ substrate 100a, the N buffer layer 100b, and the N-drift layer 100c, at least the layer of the N-drift layer 100c is a silicon carbide layer. Also, the doping concentration of N-type ions in the N-drift layer 100c is lower than the doping concentration of N-type ions in the N+ substrate 100a.

[0025] Referring to (A) in FIG. 2, in step S1, first, the surface of the substrate 100 may be cleaned and dried, and then a mask layer material is deposited on the N-drift layer 100c. For example, one or more selected from polycrystalline silicon (poly Si), single-crystalline silicon (Si), silica (SiO2), silicon nitride (SiN), etc. may be deposited, a single-layer film may be deposited, or films of various materials may be stacked. Lithography and etching are performed on the mask layer material to form a patterned mask layer 200 for defining the P well to be formed. In this example, injection windows (not shown) of the P well to be formed are defined on both sides of the patterned mask layer 200. Therefore, parameters such as the shape and line width of the patterned mask layer 200 need to be designed according to the well region 101 to be formed, and the present invention does not specifically limit it.

[0026] Continuing to refer to (A) in FIG. 2, in step S1, next, using the patterned mask layer 200 as a mask, P-type first ions are implanted into the surface layer of the N-drift layer 100c to form well regions 101 in the surface layers of the N-drift layer 100c on both sides of the patterned mask layer 200. The first ions selected in this step are ions that can form holes in the N-drift layer 100c and are less diffusible than the subsequent second ions and source ions at high temperatures.

[0027] As an example, the first ions include elemental ions such as aluminum (Al) ions that cannot diffuse in SiC. The implantation direction may be perpendicular to the surface of the N-drift layer 100c or may form a certain inclination angle with respect to the surface of the N-drift layer 100c. The implantation temperature is 400°C to 1000°C (for example, 500°C, 800°C, etc.), the implantation energy is 50 keV to 800 keV (for example, 100 keV, 200 keV, 400 keV, 500 keV, 600 keV, 700 keV, etc.), and the implantation dose is 1E12 / cm 2 ~9E13 / cm 2 (for example, 5E12 / cm 2 , 1E13 / cm 2 , etc.).

[0028] Referring to (B) in FIG. 2, in step S2, first, a sidewall material (not shown) that is the same as or different from the material of the patterned mask layer 200 is coated on the surfaces of the N-drift layer 100c and the patterned mask layer 200 by a process such as deposition or coating. Then, an extra sidewall material is removed by a sidewall self-alignment process (such as a wet etching or anisotropic dry etching process) that does not require a photomask, to form a sidewall 201 coated on the sidewalls of the patterned mask layer 200. As an example, when the patterned mask layer 200 is silicon nitride, the sidewall 201 may be silicon nitride, silicon oxide, polycrystalline silicon, or the like. Here, parameters such as the shape and line width of the sidewall need to be designed according to the requirements of the source region 102 to be formed, and the present invention does not specifically limit it.

[0029] Continuing to refer to (B) in FIG. 2, in step S2, next, using the patterned mask layer 200 and the sidewall 201 as a mask, N-type ions are vertically or obliquely implanted into the surface layer of the well region 101 to form source regions 102 on the surface layers of the well regions 101 on both sides of the patterned mask layer 200. As an example, the N-type ions include at least one of phosphorus (P) ions, arsenic (As) ions, nitrogen (N) ions, etc., the implantation energy is 50 keV to 400 keV (such as 100 keV, 200 keV, etc.), and the implantation dose is 1E14 / cm 2 ~1E16 / cm 2 (such as 5E14 / cm 2 , 1E15 / cm 2 , 5E15 / cm 2 , etc.).

[0030] Continuing to refer to (C) in FIG. 2, in step S3, using the patterned mask layer 200 and the sidewall 201 as masks, P-type second ions are implanted into the N-drift layer 100c below the well region 101 to form a semi-superjunction 103 self-aligned with the source region 102 in the N-drift layer 100c below the well regions 101 on both sides of the patterned mask layer 200. Thus, the semi-superjunction 103 can form a junction deeper than the well region 101. Here, for the second ions, P-type ions that are more likely to diffuse in the N-drift layer 100c are selected. For example, the second ions include boron ions or boron fluoride ions or a combination of both. The implantation direction may be perpendicular to the surface of the N-drift layer 100c. The implantation energy is 100 keV to 2 MeV (such as 500 keV, 800 keV, 1 MeV, etc.), and the implantation dose is 1E12 / cm 2 ~5E14 / cm 2 (such as 5E12 / cm 2 , 1E13 / cm 2 , 5E13 / cm 2 , 1E14 / cm 2 etc.).

[0031] Note that since the semi-superjunction 103 has a junction depth that does not reach the bottom surface of the N-drift layer 100c, it should be noted that the junction depth is shallower than that of a normal superjunction. In this embodiment, the ratio of the depth to the width of the semi-superjunction 103 may be 5 or less. As an example, the junction depth of the semi-superjunction 103 (i.e., the distance from the top surface of the N-drift layer 100c) is 1 μm to 5 μm.

[0032] Referring to (D) in FIG. 2, in step S3, optionally, after injecting P-type second ions, first, the patterned mask layer 200 and the sidewall 201 may be removed. Further, P-type ions including at least one of boron ions, boron fluoride ions, and aluminum ions are injected into a part of the source region 102 to form the body contact region 104, and N-type ions such as nitrogen are injected into the surface layer of the N-drift layer 100c between the well regions 101 on both sides to form the junction injection region 105. Here, the body contact region 104 has its bottom deeply penetrating into a part of the well region 101 in order to short-circuit the source region 102 and the well region 101, and the doping concentration of its P-type ions is higher than that of the well region 101. As an example, the conditions of the ion implantation process in the formation of the body contact region 104 are an implantation energy of 50 keV to 300 keV (for example, 100 keV, 200 keV, etc.), an implantation dose of 1E13 / cm 2 ~1E16 / cm 2 (for example, 5E14 / cm 2 、1E15 / cm 2 、5E15 / cm 2 etc.).

[0033] Continuing to refer to (D) in FIG. 2, in step S3, after completing the corresponding ion implantation process, the substrate 100 is annealed by an annealing activation process to activate all the implanted ions. The annealing temperature is 1500 °C to 1900 °C (for example, 1650 °C, 1700 °C, 1800 °C, etc.), and the annealing time is 2 min to 200 min (for example, 10 min, 20 min, 50 min, 100 min, etc.). In this annealing activation process, the second ions in the semi-superjunction 103 are more likely to diffuse than the first ions in the well region 101. After diffusion, the semi-superjunction 103 is in the vertical direction with its top contacting the bottom of the well region 101 and its bottom diffusing to the required depth in the N-drift layer 100c, and in the horizontal direction, it expands to the junction width required for the device.

[0034] Referring to (E) in FIG. 2, in step S4, first, an appropriate gate oxidation process such as a thermal oxidation process or a chemical vapor deposition process may be used to form a gate oxide layer 301 on the surfaces of the body contact region 104, the source region 102, the well region 101, and the junction implantation region (JFET region) 105. Next, a gate material layer (such as doped polycrystalline silicon, etc.) is deposited on the surface of the gate oxide layer 301, and lithography and etching are performed on the deposited gate material layer and the gate oxide layer 301 to form a gate 302. The formed gate 302 overlaps both the well region 101 and the source region 102, and the overlapping region between the well region 101 and the gate 302 serves as the channel of the MOSFET device (the channel extends from the boundary of the source region 102 to the boundary of the junction implantation region 105).

[0035] Optionally, referring to (F) in FIG. 2, after forming the gate 302, first, an interlayer dielectric layer 400 is coated on the substrate 100 and the gate 302 by a chemical vapor deposition process or the like. The interlayer dielectric layer 400 may have a single-layer dielectric film structure or a laminated structure formed by multiple dielectric films. Next, lithography and etching are performed on the interlayer dielectric layer 400 to pattern the interlayer dielectric layer 400, and after patterning, the gate 302 can be embedded in the interlayer dielectric layer 400 to expose a part of the source region 102. Subsequently, a source metal layer 500 (such as one metal material or alloy of copper, aluminum, gold, etc.) is formed on the interlayer dielectric layer 400 by an appropriate process such as metal sputter deposition or evaporation. The source metal layer 500 is electrically connected to both the source region 102 and the body contact region 104. Thereafter, a drain metal layer (not shown) is formed on the back surface of the N+ substrate 100a.

[0036] Referring to (F) in FIG. 2, an embodiment of the present invention further provides a MOSFET device preferably manufactured using the manufacturing method of the MOSFET device of the present invention. The MOSFET device includes a substrate 100, a gate oxide layer 301, a gate 302, an interlayer dielectric layer 400, and a source metal layer 500.

[0037] The substrate 100 can be any suitable semiconductor material. For example, the substrate 100 is an N-type silicon carbide substrate, and from bottom to top, it consists of three layers: an N+ substrate 100a, an N buffer layer 100b, and an N-drift layer 100c in sequence. A P-type well region 101, an N-type source region 102, a P-type semi-superjunction 103, a P-type body contact region 104, and an N-type junction implantation region 105 are formed in the N-drift layer 100c. The well region 101 is formed in the surface layer of a partial region of the N-drift layer 100c, the source region 102 is formed in the surface layer of the well region 101, the semi-superjunction 103 is formed in the N-drift layer 100c below the bottom of the well region 101 and is self-aligned with the source region 102 and contacts the bottom of the well region 101. The P-type ions doped in the well region 101 include ions that are difficult to diffuse, such as aluminum ions, and the P-type ions doped in the semi-superjunction 103 include ions that are easy to diffuse, such as boron ions and / or boron fluoride ions. The body contact region 104 is formed in the source region 102 and shorts the source region 102 and the well region 101. The junction implantation region 105 is formed in the N-drift layer 100c between the well regions 101 on both sides of the bottom of the gate 302.

[0038] The gate oxide layer 301 and the gate 302 are sequentially stacked on the N-drift layer 100c, and the gate 302 overlaps with both the well region 101 and the source region 102. The overlapping region of the well region 101 and the gate 302 serves as the channel of the MOSFET device.

[0039] To better explain the effects of the MOSFET device manufactured in this embodiment, in this embodiment, simulation tests were further conducted on the MOSFET device of this embodiment and the MOSFET device of the prior art. Among them, the MOSFET device of the prior art is different from the MOSFET device of this embodiment only in that there is no semi-superjunction structure in the drift layer below the bottom of the well region, and other structures, manufacturing steps, process conditions, etc. are all the same as those of the MOSFET device of this embodiment. According to the test, in the MOSFET device of the prior art, an electric field spike 106 exists under the gate oxide layer 301, and the electric field spike 106 (that is, the peak of the electric field strength, abbreviated as the electric field peak) is close to the gate oxide layer 301 as shown in FIGS. 3A and 4, thereby constantly threatening the reliability of the device. In contrast, in the MOSFET device of this embodiment, the electric field peak near the gate oxide layer 301 is reduced by 40% compared with the prior art, and its effective reduction is obvious. And the electric field spike 106 (that is, the electric field peak) is shifted below the well region 101 as shown in FIGS. 3B and 4, specifically shifted to the bottom boundary region of the semi-superjunction 103, improving both the breakdown voltage and the reliability of the device.

[0040] From these, it can be seen that the semi-superjunction formed in the MOSFET device of this embodiment plays a role in effectively expanding the junction depth of the well region, enabling the improvement of the device breakdown voltage and realizing the high conductivity of the device. At the same time, it can shift the peak of the electric field strength below the gate oxide layer below the well region, effectively reducing and making more uniform the electric field strength below the gate oxide layer, and further improving the reliability of the device.

[0041] As described above, the method for manufacturing a MOSFET device according to the present invention first performs implantation of a first ion through a patterned mask to form a well region that is difficult to diffuse. Next, implantation of a second ion is performed so as to be self-aligned with the source region by the patterned mask and sidewalls on its sidewalls. Furthermore, due to the characteristic that the second ion diffuses more easily than the first ion, a semi-superjunction that is at the bottom of the well region and in contact with the bottom of the well region is formed. The semi-superjunction plays a role in effectively expanding the junction depth of the well region, enabling improvement of the device breakdown voltage and realizing high conductivity of the device. On the other hand, the peak of the electric field strength below the gate oxide layer is shifted below the well region, effectively reducing the electric field strength below the gate oxide layer and making it more uniform, and further improving the reliability of the device. Also, in the method for manufacturing a MOSFET device according to the present invention, the ion implantation windows for the source region and the semi-superjunction are realized by self-aligning and forming sidewalls on the sidewalls of a patterned mask layer for defining the ion implantation window of the well region. The process is easy to implement, does not require extra multi-layer lithography, and has low cost.

[0042] In addition, since the MOSFET device according to the present invention has a semi-superjunction structure at the bottom of its well region, the electric field strength below the gate oxide layer is effectively reduced and becomes more uniform, and both the device breakdown voltage and reliability are improved.

[0043] The above description is only for the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the technical solution of the present invention.

Claims

1. Prepare a substrate, form a patterned mask layer on the substrate, use the patterned mask layer as a mask, and implant first ions of a first conductivity type into the surface layer of the substrate to form a well region; Form sidewalls on the sidewalls of the patterned mask layer, use the patterned mask layer and the sidewalls as a mask, and implant ions of a second conductivity type into the surface layer of the well region to form a source region; Use the patterned mask layer and the sidewalls as a mask, and implant second ions of the first conductivity type, which are more likely to diffuse in the substrate than the first ions, into the substrate below the well region to form a semi-superjunction that contacts the bottom of the well region and is self-aligned with the source region; Form a gate oxide layer and a gate sequentially stacked on the substrate, and use the region overlapping the gate in the well region as the channel of the MOSFET device. A method for manufacturing a MOSFET device, characterized by comprising the above steps.

2. The prepared substrate includes a second-conductivity-type base material, a second-conductivity-type buffer layer, and a second-conductivity-type drift layer stacked in sequence. The drift layer is a silicon carbide layer, and both the well region and the semi-superjunction are formed in the drift layer. The manufacturing method according to Claim 1, characterized by this.

3. After implanting second ions of the first conductivity type into the substrate below the well region, perform annealing activation. The second ions are more likely to diffuse in the substrate than the first ions during annealing activation, and further, after the second ions diffuse in the substrate, the semi-superjunction is formed. The manufacturing method according to Claim 1, characterized by this.

4. Before forming the semi-superjunction by implanting the second ions and then performing annealing activation, Remove the patterned mask layer and the sidewalls; Forming a body contact region of a first conductivity type and a junction implantation region of a second conductivity type by corresponding ion implantation, wherein the body contact region is formed within the source region and deeply penetrates into a part of the well region to short-circuit the source region and the well region, and the junction implantation region is at the bottom of the gate and between the well regions on both sides of the gate. The manufacturing method according to claim 3, further comprising this step.

5. The manufacturing method according to claim 3, wherein the first ion contains aluminum ions, and the second ion contains boron ions and / or boron fluoride ions.

6. The implantation process parameters of the first ion include an implantation energy of 50 keV to 800 keV and an implantation dose of 1E12 / cm ２ to 9E13 / cm ２ and / or the implantation process parameters of the second ion include an implantation energy of 100 keV to 2 MeV and an implantation dose of 1E12 / cm ２ to 5E14 / cm ２ The manufacturing method according to claim 5, characterized by including the above.

7. The manufacturing method according to claim 5, wherein the process conditions of the annealing activation include an annealing temperature of 1500°C to 1900°C and an annealing time of 2 min to 200 min.

8. Forming an interlayer dielectric layer on the substrate, in which the gate is embedded and a part of the source region is exposed. Forming a source metal layer electrically connected to the source region on the interlayer dielectric layer. Forming a drain metal layer on the bottom surface of the substrate. The manufacturing method according to any one of claims 1 to 7, further comprising this step.

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