Substrate processing apparatus and substrate processing method

Abstract

This substrate-processing device comprises: a pick-up unit; a removal unit; and a mounting unit. The pick-up unit separates a chip from a tape in a state where a plurality of the chips are fitted to a frame via the tape and a protective film is formed on a first main surface of each of the chips on the side that is opposite from the tape. After the chip is separated from the tape by the pick-up unit, the removal unit removes the protective film from the chip. After the removal unit has removed the protective film, the mounting unit mounts the chip on a substrate with the first main surface of the chip facing the substrate.

Description

Technical Field

[0001] The present disclosure relates to a substrate processing apparatus and a substrate processing method.

Background Art

[0002] The chip mounting system described in Patent Document 1 includes a chip supply device, a bonding device, a surface treatment device, a loading / unloading unit, and a transfer unit (paragraph

[0225] of Patent Document 1). The chip supply device individually supplies chips to be bonded while holding a plurality of chips. The bonding device attaches the chips supplied from the chip supply device onto a substrate. The surface treatment device performs a surface activation treatment and a hydrophilic treatment on the bonding surfaces of the plurality of chips and the substrate. The loading / unloading unit loads chips and substrates to be bonded from outside the chip mounting system into the system, and unloads the substrate with the chips attached (a structure including the chips and the substrate) to the outside of the system. The transfer unit transfers a plurality of chips, substrates, and structures including chips and substrates between the loading / unloading unit, the chip supply device, the bonding device, and the surface treatment device. Inside the chip supply device, dicing processing is performed to generate a plurality of chips (paragraph

[0248] of Patent Document 1). Further, inside the chip supply device, the plurality of diced chips are placed on a dicing tape (paragraph

[0250] of Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One aspect of the present disclosure provides a technique for improving the quality of a substrate with chips.

Means for Solving the Problems

[0005] A substrate processing apparatus according to an aspect of the present disclosure includes a pickup unit, a removal unit, and a mounting unit. The pickup unit peels a chip from a tape in a state where a plurality of chips are mounted on a frame via the tape and a protective film is formed on a first main surface of the chip opposite to the tape. The removal unit removes the protective film from the chip after the pickup unit peels the chip from the tape. The mounting unit mounts the chip on the substrate with the first main surface of the chip facing the substrate after the removal unit removes the protective film.

Effect of the Invention

[0006] According to an aspect of the present disclosure, the quality of a substrate with chips can be improved.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each drawing, the same or corresponding components are denoted by the same reference numerals, and the description thereof may be omitted. In this specification, the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other. The X-axis direction and the Y-axis direction are horizontal directions, and the Z-axis direction is a vertical direction.

[0009] With reference to FIGS. 1 to 2, a substrate processing apparatus 1 according to an embodiment will be described. As shown in FIGS. 2(A) to 2(D), the substrate processing apparatus 1 manufactures a substrate CW1 with chips by bonding a plurality of chips CP1 to different bonding regions on the main surface W1c of a substrate W1. The bonding regions are preset.

[0010] The substrate CW1 with chips includes a substrate W1 and a plurality of chips CP1 bonded to the substrate W1. Although not shown, another chip may be further stacked on each chip CP1.

[0011] The substrate W1 is carried into the substrate processing apparatus 1 as shown in FIG. 2(A). The substrate W1 has a base substrate W1a and a plurality of devices W1b formed on the base substrate W1a. The base substrate W1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The devices W1b include semiconductor elements, circuits, or terminals, etc. The devices W1b are formed on the main surface W1c.

[0012] Further, a plurality of chips CP1 shown in FIG. 2(B) are loaded into the substrate processing apparatus 1. The plurality of chips CP1 are adhered to a tape TP1, and the outer periphery of the tape TP1 is attached to a frame FR1. The plurality of chips CP1 are arranged in the opening of the frame FR1. The plurality of chips CP1 can be obtained, for example, by dicing a substrate while the substrate is adhered to the tape TP1.

[0013] The chip CP1 has a base substrate CP1a and a device CP1b formed on the base substrate CP1a. The base substrate CP1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The device CP1b includes a semiconductor element, a circuit, or a terminal, etc. The device CP1b is arranged on the side opposite to the tape TP1 with respect to the base substrate CP1a.

[0014] As shown in FIG. 2(C), the pickup unit 53 peels the plurality of chips CP1 from the tape TP1 individually. After that, the chips CP1 are turned upside down and then bonded to the substrate W1 as shown in FIG. 2(D). The device W1b of the substrate W1 and the device CP1b of the chip CP1 are electrically connected. Thereby, a substrate with chips CW1 is obtained.

[0015] Note that, as shown in FIG. 17(A), the substrate W1 constituting the substrate with chips CW1 may not have the device W1b. That is, the substrate W1 may not have an electric circuit. For example, the substrate W1 may consist only of a silicon wafer, a compound semiconductor wafer, or a glass substrate. When the substrate W1 does not have the device W1b, as shown in FIG. 17(B), the substrate W1 and the substrate W2 are joined with the plurality of chips CP1 sandwiched therebetween. Next, as shown in FIG. 17(C), the plurality of chips CP1 and the substrate W1 are peeled off, and finally, as shown in FIG. 17(D), the substrate W2 and the substrate W3 are joined with the plurality of chips CP1 sandwiched therebetween. The substrate W3 has a base substrate W3a and a plurality of devices W3b formed on the base substrate W3a. The device W3b of the substrate W3 and the device CP1b of the chip CP1 are electrically connected.

[0016] As shown in FIG. 1, the substrate processing apparatus 1 includes a loading / unloading station 2, a first processing station 3, an interface block 4, a second processing station 5, and a control unit 9. The loading / unloading station 2, the first processing station 3, the interface block 4, and the second processing station 5 are arranged in this order from the negative X-axis direction side to the positive X-axis direction side.

[0017] The loading / unloading station 2 includes a mounting table 20. Cassettes C1 to C4 are mounted on the mounting table 20. Cassette C1 houses the substrate W1 shown in FIG. 2(A). Cassette C2 houses the substrate CW1 with chips shown in FIG. 2(D). Cassette C3 houses a plurality of chips CP1 together with the frame FR1 shown in FIG. 2(B). Cassette C4 houses the used frame FR1 (not shown). The used frame FR1 is the frame FR1 remaining after peeling a plurality of chips CP1 from the tape TP1. The used frame FR1 may have chips CP1 remaining on it.

[0018] The loading / unloading station 2 includes a transfer area 21, a third substrate transfer arm 22, and a third frame transfer arm 23. The transfer area 21 is adjacent to the mounting table 20. The third substrate transfer arm 22 holds and transfers the substrate W1 in the transfer area 21. The third frame transfer arm 23 holds and transfers the frame FR1 in the transfer area 21. The third substrate transfer arm 22 and the third frame transfer arm 23 are each capable of moving in the horizontal direction (both the X-axis direction and the Y-axis direction) and the vertical direction, and rotating about the vertical axis.

[0019] The loading / unloading station 2 has a driving unit (not shown) that moves or rotates the third substrate transfer arm 22 and the third frame transfer arm 23. The third substrate transfer arm 22 and the third frame transfer arm 23 may be mounted on the same Y-axis slider and moved simultaneously in the Y-axis direction, or may be mounted on different Y-axis sliders and moved independently in the Y-axis direction. When the third substrate transfer arm 22 and the third frame transfer arm 23 are mounted on the same Y-axis slider, they are stacked in the Z-axis direction. When the third substrate transfer arm 22 and the third frame transfer arm 23 are mounted on different Y-axis sliders, the plurality of Y-axis sliders are arranged with a shift in the Z-axis direction.

[0020] The third substrate transfer arm 22 takes out the substrate W1 before bonding the chip CP1 from the cassette C1 and transports it to the substrate placement portion 24. Further, the third substrate transfer arm 22 takes out the substrate CW1 with chips from the substrate placement portion 24 and stores it in the cassette C2. The third substrate transfer arm 22 for transporting the substrate W1 before bonding the chip CP1 and the third substrate transfer arm 22 for transporting the substrate CW1 with chips may be provided separately.

[0021] The third frame transfer arm 23 takes out a plurality of chips CP1 together with the frame FR1 from the cassette C3 and transports them to the frame placement portion 25. Further, the third frame transfer arm 23 takes out the used frame FR1 from the frame placement portion 25 and stores it in the cassette C4. The third frame transfer arm 23 for transporting a plurality of chips CP1 together with the frame FR1 and the third frame transfer arm 23 for transporting the used frame FR1 may be provided separately.

[0022] The loading / unloading station 2 includes a substrate placement portion 24 and a frame placement portion 25. The substrate placement portion 24 and the frame placement portion 25 are arranged between the transfer area 21 of the loading / unloading station 2 and the transfer area 30 of the first processing station 3 and are adjacent to both transfer areas 21 and 30. The substrate placement portion 24 and the frame placement portion 25 may be stacked in the vertical direction in order to reduce the footprint of the loading / unloading station 2.

[0023] On the substrate placement unit 24, the substrate W1 before bonding the chip CP1 is placed. The substrate with chips CW1 may be placed on the substrate placement unit 24. The substrate placement unit 24 on which the substrate W1 before bonding the chip CP1 is placed and the substrate placement unit 24 on which the substrate with chips CW1 is placed may be provided separately, or a plurality of each may be provided.

[0024] On the frame placement unit 25, a plurality of chips CP1 are placed together with the frame FR1. The used frame FR1 may be placed on the frame placement unit 25. The frame placement unit 25 on which a plurality of chips CP1 are placed together with the frame FR1 and the frame placement unit 25 on which the used frame FR1 is placed may be provided separately, or a plurality of each may be provided.

[0025] The first processing station 3 includes a transfer area 30, a first substrate transfer arm 31, and a first frame transfer arm 32. The transfer area 30 extends in the X-axis direction. The first substrate transfer arm 31 holds and transfers the substrate W1 in the transfer area 30. The first frame transfer arm 32 holds and transfers the frame FR1 in the transfer area 30. Each of the first substrate transfer arm 31 and the first frame transfer arm 32 is capable of moving in the horizontal direction (both the X-axis direction and the Y-axis direction) and the vertical direction, and rotating about the vertical axis.

[0026] The first processing station 3 has a drive unit (not shown) for moving or rotating the first substrate transfer arm 31 and the first frame transfer arm 32. The first substrate transfer arm 31 and the first frame transfer arm 32 may be mounted on the same X-axis slider and moved in the X-axis direction simultaneously, or may be mounted on different X-axis sliders and moved independently in the X-axis direction. When the first substrate transfer arm 31 and the first frame transfer arm 32 are mounted on the same X-axis slider, they are stacked in the Z-axis direction. When the first substrate transfer arm 31 and the first frame transfer arm 32 are mounted on different X-axis sliders, the plurality of X-axis sliders are arranged offset in the Z-axis direction.

[0027] The first substrate transfer arm 31 takes out the substrate W1 before bonding the chip CP1 from the substrate placement unit 24, and transfers it to the first buffer unit 41 of the interface block 4 via the surface modification unit 34 and the substrate cleaning unit 35. Also, the first substrate transfer arm 31 takes out the substrate CW1 with chips from the first buffer unit 41, and places it on the substrate placement unit 24 of the loading / unloading station 2 via the inspection unit 36 and the like. The first substrate transfer arm 31 for transferring the substrate W1 before bonding the chip CP1 and the first substrate transfer arm 31 for transferring the substrate CW1 with chips may be provided separately.

[0028] The first frame transfer arm 32 takes out a plurality of chips CP1 together with the frame FR1 from the frame placement unit 25, and transfers them to the second buffer unit 42 of the interface block 4 via the chip cleaning unit 33. Also, the first frame transfer arm 32 takes out the used frame FR1 from the second buffer unit 42, and places it on the frame placement unit 25 of the loading / unloading station 2. The first frame transfer arm 32 for transferring a plurality of chips CP1 together with the frame FR1 and the first frame transfer arm 32 for transferring the used frame FR1 may be provided separately.

[0029] The first processing station 3 includes a chip cleaning unit 33, a surface modification unit 34, a substrate cleaning unit 35, an inspection unit 36, a chip peeling unit 37, a rework unit 38, and an annealing unit 39. The chip cleaning unit 33, the surface modification unit 34, the substrate cleaning unit 35, the inspection unit 36, the chip peeling unit 37, the rework unit 38, and the annealing unit 39 are adjacent to the transfer area 30, and are arranged on the positive Y-axis side or the negative Y-axis side of the transfer area 30.

[0030] The chip cleaning unit 33 cleans the plurality of chips CP1 in a state where the plurality of chips CP1 are adhered to the tape TP1 and the outer periphery of the tape TP1 is attached to the frame FR1. After cleaning the chip CP1, by bonding the chip CP1 to the substrate W1, it is possible to suppress the intrusion of foreign matter. Details of the chip cleaning unit 33 will be described later.

[0031] The surface modification unit 34 performs plasma treatment on the main surface W1c of the substrate W1. In the surface modification unit 34, for example, oxygen gas, which is a processing gas, is excited and turned into plasma and ionized under reduced pressure. The main surface W1c is modified by irradiating the main surface W1c of the substrate W1 with oxygen ions. The processing gas is not limited to oxygen gas, and for example, nitrogen gas or the like may be used.

[0032] The substrate cleaning unit 35 cleans the main surface W1c of the substrate W1. For example, the substrate cleaning unit 35 supplies pure water (for example, deionized water) onto the substrate W1 while rotating the substrate W1 held by a spin chuck. The pure water spreads over the entire main surface W1c by centrifugal force and cleans the main surface W1c. The pure water imparts OH groups to the pre-modified main surface W1c. By utilizing the hydrogen bonds between the OH groups, the substrate W1 and the chip CP1 can be bonded together.

[0033] The inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions on the main surface W1c of the substrate W1 is good or bad. The inspection items include at least one of the presence or absence of foreign matters such as bubbles and the presence or absence of misalignment. For example, if there are bubbles at the interface between the substrate W1 and the chip CP1, the bubbles will burst when the chip-mounted substrate CW1 is subjected to vacuum treatment. Due to the bursting of the bubbles, problems may occur even with the chip CP1 with a good bonding state, or the vacuum chamber may be contaminated. Alternatively, if there are bubbles or particles at the interface between the substrate W1 and the chip CP1, the height of the chip CP1 will increase, chipping will occur during grinding or polishing, and problems may occur even with the chip CP1 with a good bonding state due to the impact. Details of the inspection unit 36 will be described later.

[0034] The chip peeling unit 37 peels off the chip CP1 with a poor bonding state from the substrate W1 in the inspection by the inspection unit 36. By peeling off the chip CP1 with a poor bonding state from the substrate W1, problems that occur when there are bubbles or particles at the interface between the substrate W1 and the chip CP1 can be solved, and the quality of the chip-mounted substrate CW1 can be improved. The chip CP1 peeled off from the substrate W1 may be reused or discarded. Details of the chip peeling unit 37 will be described later.

[0035] The rework unit 38 selectively processes the bonding region on the main surface W1c of the substrate W1 from which the chip CP1 has been peeled off by the chip peeling unit 37. The processing is a process of returning the bonding region from which the chip CP1 has been peeled off to the state immediately before bonding the chip CP1. For example, the rework unit 38 selectively supplies at least one of plasma and water to the bonding region from which the chip CP1 has been peeled off. Details of the rework unit 38 will be described later.

[0036] The annealing unit 39 heat-treats the substrate CW1 with chips. Before the heat treatment, the chip CP1 and the substrate W1 are bonded by hydrogen bonds between OH groups. By the heat treatment, a dehydration condensation reaction occurs, a covalent bond is formed, and the bonding strength between the chip CP1 and the substrate W1 is improved. Note that the peeling of the chip CP1 by the chip peeling unit 37 is performed before the heat treatment of the substrate CW1 with chips by the annealing unit 39.

[0037] The interface block 4 is adjacent to the transfer region 30 of the first processing station 3. The interface block 4 includes a first buffer unit 41, a second buffer unit 42, a second substrate transfer arm 43, and a second frame transfer arm 44. The first buffer unit 41 and the second buffer unit 42 are adjacent to the transfer region 30 of the first processing station 3. The first buffer unit 41 and the second buffer unit 42 may be stacked in the vertical direction in order to reduce the footprint of the interface block 4.

[0038] The first buffer unit 41 stores the substrate W1 before bonding the chip CP1. The first buffer unit 41 may store the substrate CW1 with chips. The first buffer unit 41 that stores the substrate W1 before bonding the chip CP1 and the first buffer unit 41 that stores the substrate CW1 with chips may be provided separately, and a plurality of each may be provided.

[0039] The second buffer unit 42 stores a plurality of chips CP1 together with the frame FR1. The second buffer unit 42 may store the used frame FR1. The second buffer unit 42 that stores a plurality of chips CP1 together with the frame FR1 and the second buffer unit 42 that stores the used frame FR1 may be provided separately, or a plurality of each may be provided.

[0040] The second substrate transfer arm 43 takes out the substrate W1 before bonding the chip CP1 from the first buffer unit 41 and transfers it to the substrate holding unit 51 of the second processing station 5. The second substrate transfer arm 43 may transfer the substrate CW1 with chips from the substrate holding unit 51 to the first buffer unit 41. The second substrate transfer arm 43 can move in the horizontal direction (both the X-axis direction and the Y-axis direction) and the vertical direction, and can rotate about the vertical axis. The second substrate transfer arm 43 that transfers the substrate W1 before bonding the chip CP1 and the second substrate transfer arm 43 that transfers the substrate CW1 with chips may be provided separately.

[0041] The second frame transfer arm 44 takes out a plurality of chips CP1 together with the frame FR1 from the second buffer unit 42 and transfers them to the chip holding unit 52 of the second processing station 5. The second frame transfer arm 44 may transfer the used frame FR1 from the chip holding unit 52 to the second buffer unit 42. The second frame transfer arm 44 can move in the horizontal direction (both the X-axis direction and the Y-axis direction) and the vertical direction, and can rotate about the vertical axis. The second frame transfer arm 44 that transfers a plurality of chips CP1 together with the frame FR1 and the second frame transfer arm 44 that transfers the used frame FR1 may be provided separately.

[0042] The interface block 4 has a drive unit (not shown) that moves or rotates the second substrate transfer arm 43 and the second frame transfer arm 44. The second substrate transfer arm 43 and the second frame transfer arm 44 may be moved simultaneously in a predetermined direction or may be moved independently in a predetermined direction. The second substrate transfer arm 43 and the second frame transfer arm 44 are not stacked in the Z-axis direction in FIGS. 1 and 2, but may be stacked in the Z-axis direction.

[0043] The interface block 4 stores the substrate W1 that has undergone pre-treatment (e.g., surface modification and cleaning) and a plurality of chips CP1 that have undergone pre-treatment (e.g., cleaning). Thereby, the operating rate of the second processing station 5 can be improved, and the production efficiency of the substrate CW1 with chips can be improved.

[0044] Note that the interface block 4 may be omitted, and the first processing station 3 and the second processing station 5 may be adjacent to each other. In this case, the first substrate transfer arm 31 of the first processing station 3 transports the substrate W1 before bonding the chip CP1 to the substrate holding portion 51 of the second processing station 5 and receives the substrate CW1 with chips from the substrate holding portion 51. Also, in this case, the first frame transfer arm 32 of the first processing station 3 transports a plurality of chips CP1 together with the frame FR1 to the chip holding portion 52 of the second processing station 5 and receives the used frame FR1 from the chip holding portion 52.

[0045] The second processing station 5 is arranged on the side opposite to the transfer area 30 of the first processing station 3 with respect to the interface block 4. The second processing station 5 includes a substrate holding unit 51, a chip holding unit 52, a pickup unit 53, and a mounting unit 54. The substrate holding unit 51 holds the substrate W1. The chip holding unit 52 holds a plurality of chips CP1 in a state where the plurality of chips CP1 are mounted on the frame FR1 via the tape TP1. The substrate holding unit 51 and the chip holding unit 52 are each capable of moving in both the horizontal directions (both the X-axis direction and the Y-axis direction) and rotating about the vertical axis. The pickup unit 53 peels the chip CP1 held by the chip holding unit 52 from the tape TP1. The mounting unit 54 mounts the chip CP1 peeled from the tape TP1 by the pickup unit 53 on the main surface W1c of the substrate W1. Details of the second processing station 5 will be described later.

[0046] The interface block 4 and the second processing station 5 constitute a chip bonding portion 6. The chip bonding portion 6 is adjacent to the transfer area 30 of the first processing station 3. As described above, the interface block 4 may be omitted, and the chip bonding portion 6 may be constituted by only the second processing station 5.

[0047] The control unit 9 is, for example, a computer and includes a CPU (Central Processing Unit) 91 and a storage medium 92 such as a memory. A program for controlling various processes executed in the substrate processing apparatus 1 is stored in the storage medium 92. The control unit 9 controls the operation of the substrate processing apparatus 1 by causing the CPU 91 to execute the program stored in the storage medium 92. A unit control unit for controlling the operation of each unit may be provided for each unit constituting the substrate processing apparatus 1, and a system control unit for comprehensively controlling a plurality of unit control units may be provided. The control unit 9 may be constituted by the unit control unit and the system control unit.

[0048] Next, with reference to FIG. 3, a substrate processing method according to an embodiment will be described. The processing in FIG. 3 is performed under the control of the control unit 9.

[0049] First, the third substrate transfer arm 22 of the loading / unloading station 2 takes out the substrate W1 from the cassette C1 and transfers it to the substrate placement unit 24. Next, the first substrate transfer arm 31 of the first processing station 3 takes out the substrate W1 from the substrate placement unit 24 and transfers it to the surface modification unit 34. Next, the surface modification unit 34 performs plasma treatment on the main surface W1c of the substrate W1 (step S101). After that, the first substrate transfer arm 31 takes out the substrate W1 from the surface modification unit 34 and transfers it to the substrate cleaning unit 35. Next, the substrate cleaning unit 35 cleans the main surface W1c of the substrate W1 (step S102). After that, the first substrate transfer arm 31 takes out the substrate W1 from the substrate cleaning unit 35 and transfers it to the first buffer unit 41 of the interface block 4. Next, the second substrate transfer arm 43 takes out the substrate W1 from the first buffer unit 41 and transfers it to the substrate holding unit 51 of the second processing station 5.

[0050] In parallel with the above processing, the following processing is performed. First, the third frame transfer arm 23 of the loading / unloading station 2 takes out a plurality of chips CP1 together with the frame FRl from the cassette C3 and transfers them to the frame placement unit 25. Next, the first frame transfer arm 32 of the first processing station 3 takes out a plurality of chips CP1 together with the frame FRl from the frame placement unit 25 and transfers them to the chip cleaning unit 33. Next, the chip cleaning unit 33 cleans the plurality of chips CP1 (step S103). After that, the first frame transfer arm 32 takes out a plurality of chips CP1 together with the frame FRl from the chip cleaning unit 33 and transfers them to the second buffer unit 42 of the interface block 4. Next, the second frame transfer arm 44 takes out a plurality of chips CP1 together with the frame FRl from the second buffer unit 42 and transfers them to the chip holding unit 52 of the second processing station 5.

[0051] Next, the chip bonding section 6 bonds a plurality of chips CP1 to different bonding regions on the main surface W1c of the substrate W1 (step S104). Thereby, the substrate CW1 with chips is obtained. Then, the second substrate transfer arm 43 takes out the substrate CW1 with chips from the substrate holding section 51 and transfers it to the first buffer section 41. Next, the first substrate transfer arm 31 of the first processing station 3 takes out the substrate CW1 with chips from the first buffer section 41 and transfers it to the inspection section 36.

[0052] Next, the inspection section 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions on the main surface W1c of the substrate W1 is good or bad (step S105). The inspection section 36 transmits the inspection result to the control section 9. The control section 9 checks for the presence or absence of defects (step S106). The control section 9 performs control to distribute the transfer destination of the substrate CW1 with chips to the annealing section 39 and the chip peeling section 37 according to the inspection result by the inspection section 36.

[0053] When there is a defect in the bonding state of the chip CP1 (step S106, NO), the transfer destination of the substrate CW1 with chips becomes the chip peeling section 37. The first substrate transfer arm 31 takes out the substrate CW1 with chips from the inspection section 36 and transfers it to the chip peeling section 37. Next, the chip peeling section 37 peels off the chip CP1 with a defective bonding state from the substrate W1 (step S107). Then, the first substrate transfer arm 31 takes out the substrate CW1 with chips from the chip peeling section 37 and transfers it to the rework section 38. Next, the rework section 38 selectively processes the bonding region from which the chip CP1 has been peeled off (step S108). Then, the first substrate transfer arm 31 takes out the substrate CW1 with chips from the rework section 38 and transfers it to the chip bonding section 6.

[0054] Next, the chip bonding unit 6 bonds the chip CP1 again to the bonding region from which the chip CP1 has been peeled, or bonds a dummy chip DC1 (see FIG. 8) prepared separately from the chip CP1 without bonding the chip CP1 again (step S109). Unlike the chip CP1, the dummy chip DC1 does not have a device, that is, an electric circuit. For example, the dummy chip DC1 consists only of a silicon wafer, a compound semiconductor wafer, or a glass substrate. Note that the chip bonding unit 6 does not have to bond either the chip CP1 or the dummy chip DC1 to the bonding region from which the chip CP1 has been peeled, and may not bond anything.

[0055] When the chip CP1 is peeled from the substrate W1, the device W1b of the substrate W1 may be damaged. Re-bonding the chip CP1 to the damaged device W1b is a waste of the chip CP1. If the chip CP1 is not bonded to the damaged device W1b, the waste of the chip CP1 can be prevented. This effect can also be obtained when nothing is bonded to the damaged device W1b.

[0056] Note that when the substrate W1 does not have the device W1b as shown in FIG. 17(A), it is preferable to bond the chip CP1 again to the bonding region from which the chip CP1 has been peeled. This is because if the chip CP1 is not bonded again (including the case where the dummy chip DC1 is bonded again without bonding the chip CP1 again), the device W3b of the substrate W3 shown in FIG. 17(D) will be wasted.

[0057] As described above, the chip bonding unit 6 bonds the chip CP1 again to the bonding region from which the chip CP1 has been peeled, or bonds the dummy chip DC1 (step S109). In this case, unlike the case where nothing is bonded to the bonding region from which the chip CP1 has been peeled, it is possible to prevent the chip-mounted substrate CW1 from being subjected to post-processing with the space where the chip CP1 is to be mounted remaining empty, and the quality of the post-processing can be improved. For example, uniform processing is possible during grinding or polishing.

[0058] After step S109, the first substrate transfer arm 31 of the first processing station 3 takes out the substrate CW1 with chips from the chip bonding section 6 and transfers it to the inspection section 36. Thereafter, the processes after step S105 are performed again. Note that after step S109, the first substrate transfer arm 31 may take out the substrate CW1 with chips from the chip bonding section 6 and transfer it to the annealing section 39. Thereafter, the processes after step S110 are performed.

[0059] On the other hand, when there is no defect in the bonding state of all the chips CP1 (step S106, YES), the transfer destination of the substrate CW1 with chips is the annealing section 39. The first substrate transfer arm 31 takes out the substrate CW1 with chips from the inspection section 36 and transfers it to the annealing section 39. Next, the annealing section 39 heat-treats the substrate CW1 with chips (step S110). By the heat treatment, the bonding strength between the chip CP1 and the substrate W1 is improved.

[0060] Thereafter, the first substrate transfer arm 31 takes out the substrate CW1 with chips from the annealing section 39 and places it on the substrate placement section 24 of the loading / unloading station 2. Finally, the third substrate transfer arm 22 of the loading / unloading station 2 takes out the substrate CW1 with chips from the substrate placement section 24 and stores it in the cassette C2. The substrate CW1 with chips is carried out of the substrate processing apparatus 1 in a state of being stored in the cassette C2.

[0061] Note that after step S104, the first frame transfer arm 32 of the first processing station 3 takes out the used frame FR1 from the chip bonding section 6 and places it on the frame placement section 25 of the loading / unloading station 2. Next, the third frame transfer arm 23 of the loading / unloading station 2 takes out the used frame FR1 from the frame placement section 25 and stores it in the cassette C4.

[0062] Next, with reference to FIG. 4, an example of the first frame transfer arm 32 of the first processing station 3 will be described. The first frame transfer arm 32 includes a pair of guide rails 321 on which the frame FR1 is placed, a gripping portion 322 that grips the frame FR1, and a drive portion 323 that moves the gripping portion 322 in the longitudinal direction of the pair of guide rails 321.

[0063] Note that the third frame transfer arm 23 of the loading / unloading station 2 and the second frame transfer arm 44 of the interface block 4 may also be configured in the same manner as the first frame transfer arm 32 of the first processing station 3, and may include a pair of guide rails on which the frame FR1 is placed, a gripping portion that grips the frame FR1, and a drive portion that moves the gripping portion in the longitudinal direction of the pair of guide rails.

[0064] Each of the pair of guide rails 321 has an L-shaped cross section and includes a horizontal plate 321a and a vertical plate 321b. When viewed from above, the pair of vertical plates 321b are arranged with the frame FR1 therebetween and restrict the movement of the frame FR1 in a direction orthogonal to the vertical plates 321b. The frame FR1 is placed on the pair of horizontal plates 321a.

[0065] By having the pair of guide rails 321 in addition to the gripping portion 322, the first frame transfer arm 32 can stably support the frame FR1. Further, by moving the gripping portion 322 in the longitudinal direction of the pair of guide rails 321, the drive portion 323 can smoothly transfer the frame FR1 to a desired device (for example, the chip cleaning unit 33).

[0066] As shown in FIG. 4, the chip cleaning unit 33 may have a pair of guide rails 338. By arranging the pair of guide rails 338 and the pair of guide rails 321 continuously, the frame FR1 can be smoothly transferred. The pair of guide rails 338 may be movable in the horizontal and vertical directions.

[0067] A pair of guide rails 338 each have an L-shaped cross section and include a horizontal plate 338a and a vertical plate 338b. When viewed from above, the pair of vertical plates 338b are arranged with the frame FR1 therebetween, and restrict movement of the frame FR1 in a direction orthogonal to the vertical plates 338b. The frame FR1 is placed on the pair of horizontal plates 338a.

[0068] The chip cleaning unit 33 may have an internal conveyance unit 339. As shown in FIG. 4(B), the internal conveyance unit 339 holds and conveys the frame FR1 from above inside the chip cleaning unit 33. The internal conveyance unit 339 conveys the frame FR1 between a pair of guide rails 338 and a frame holding unit 332 described later.

[0069] The internal conveyance unit 339 has, for example, a plurality of arms 339a. When viewed from above, the plurality of arms 339a each cross the opening of the frame FR1, and adsorb and convey the frame FR1 from above at both longitudinal ends. The internal conveyance unit 339 is capable of moving in both the horizontal direction (both the X-axis direction and the Y-axis direction) and the vertical direction.

[0070] Next, with reference to FIGS. 5 and 6, an example of the chip cleaning unit 33 will be described. The chip cleaning unit 33 has, for example, a chip holding unit 331 and a frame holding unit 332. The chip holding unit 331 horizontally holds a plurality of chips CP1 from below via a tape TP1. When an expand unit 333 described later radially expands the tape TP1, the chip holding unit 331 slidably places the tape TP1 thereon. Note that the chip holding unit 331 may have a vacuum chuck mechanism and fix the tape TP1.

[0071] The frame holding unit 332 horizontally holds the frame FR1 from below. The frame holding unit 332 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1. When a rotation drive unit 334 described later rotationally drives the frame holding unit 332, the plurality of chips CP1 rotate together with the frame FR1.

[0072] The chip cleaning unit 33 may have an expandable portion 333. As shown in FIG. 6, the expandable portion 333 expands the tape TP1 radially to increase the spacing between adjacent chips CP1. For example, the expandable portion 333 expands the tape TP1 radially by relatively raising the chip holding portion 331 with respect to the frame holding portion 332. By increasing the spacing between adjacent chips CP1, the sides of the chips CP1 can be efficiently cleaned.

[0073] The chip cleaning unit 33 may include a rotation driving unit 334, a nozzle 335, and a cup 336. The rotation driving unit 334 rotates the plurality of chips CP1 together with the frame FR1 by rotationally driving the frame holding portion 332. The rotation driving unit 334 also rotationally drives the chip holding portion 331 together with the frame holding portion 332. The nozzle 335 supplies a cleaning liquid to the plurality of chips CP1. The cleaning liquid is a chemical solution or a rinsing liquid, etc. The rinsing liquid is pure water such as DIW (deionized water). The nozzle 335 may move in a direction orthogonal to the rotation center line of the chip holding portion 331 or the like. The cup 336 collects the cleaning liquid.

[0074] The chip cleaning unit 33 may have a cleaning head 337. The cleaning head 337 is a brush or a sponge, etc., and scrub-cleans the plurality of chips CP1. The cleaning head 337 may apply ultrasonic waves to the liquid film formed between the plurality of chips CP1. The liquid film is formed by the nozzle 335 supplying the cleaning liquid.

[0075] Next, with reference to FIG. 7, an example of the second processing station 5 will be described. As described above, the second processing station 5 includes a substrate holding portion 51, a chip holding portion 52, a pickup portion 53, and a mount portion 54.

[0076] The substrate holding part 51 holds the substrate W1. The substrate holding part 51 holds the substrate W1 horizontally, for example, with the main surface W1c of the substrate W1 facing upward. The main surface W1c of the substrate W1 may have the devices W1b for each bonding region, and the substrate holding part 51 may hold the substrate W1 horizontally with the devices W1b facing upward.

[0077] The chip holding part 52 holds the plurality of chips CP1 in a state where the plurality of chips CP1 are mounted on the frame FR1 via the tape TP1. The chip holding part 52 holds the plurality of chips CP1 horizontally, for example, with the respective devices CP1b of the plurality of chips CP1 facing upward.

[0078] The pickup part 53 separates the plurality of chips CP1 from the tape TP1 individually. The pickup part 53 has the first suction head 531. The first suction head 531 sucks the chip CP1 from the side opposite to the tape TP1. For example, the first suction head 531 sucks the chip CP1 from above.

[0079] With the chip CP1 sucked, the first suction head 531 moves upward to separate the chip CP1 from the tape TP1. The first suction head 531 may be capable of being turned upside down. By turning the chip CP1 upside down, the chip CP1 can be mounted on the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1.

[0080] The chip holding part 52 may have the push-up pins 532. The push-up pins 532 push up the chips CP1 from below via the tape TP1. The first suction head 531 sucks the chips CP1 pushed up by the push-up pins 532. Thereby, it is possible to suppress the adjacent chips CP1 from rubbing against each other.

[0081] Although not shown, the pickup part 53 may have an expandable part, similar to the chip cleaning part 33. The expandable part expands the tape TP1 radially to widen the interval between the adjacent chips CP1. Thereby, it is possible to suppress the adjacent chips CP1 from rubbing against each other.

[0082] The mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1. The mounting unit 54 has a second suction head 541. The second suction head 541 sucks the chip CP1 that is upside down from above, and moves downward in that state to mount the chip CP1 on the main surface W1c of the substrate W1.

[0083] In this embodiment, the second suction head 541 of the mounting unit 54 directly receives the chip CP1 from the first suction head 531 of the pickup unit 53, but it may also be received via a transfer unit (not shown). The transfer unit transfers the chip CP1 from the pickup unit 53 to the mounting unit 54. The transfer unit may invert the chip CP1 upside down.

[0084] As shown in FIG. 7, when the main surface W1c of the substrate W1 has the device W1b for each bonding region, the control unit 9 may have an information acquisition unit 93. The information acquisition unit 93 acquires information indicating whether the state of the device W1b is good or bad for each bonding region. Whether the state of the device W1b is good or bad is inspected by an external inspection device. The inspection device performs, for example, an appearance inspection or an operation inspection of the device W1b, and transmits the inspection result to the control unit 9.

[0085] The chip bonding unit 6 bonds the chip CP1 to the device W1b with a good state and bonds the dummy chip DC1 (see FIG. 8) to the device W1b with a bad state under the control of the control unit 9. Note that the chip bonding unit 6 does not have to bond either the chip CP1 or the dummy chip DC1 to the device W1b with a bad state, and does not have to bond anything.

[0086] Bonding the chip CP1 to the device W1b with a bad state is a waste of the chip CP1. By not bonding the chip CP1 to the device W1b with a bad state, waste of the chip CP1 can be prevented. This effect can also be obtained when nothing is bonded to the device W1b with a bad state.

[0087] Further, if the dummy chip DC1 is bonded to the device W1b with a poor state without bonding the chip CP1, unlike the case where nothing is bonded, it is possible to prevent the substrate CW1 with the chip from being subjected to post-processing while leaving the space where the chip CP1 is to be mounted empty, and the quality of the post-processing can be improved.

[0088] Next, with reference to FIG. 9, an example of the inspection unit 36 will be described. The inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions on the main surface W1c of the substrate W1 is good or bad. The inspection items include at least one of the presence or absence of foreign matters such as air bubbles and the presence or absence of misalignment. The inspection unit 36 has, for example, a substrate holding unit 361 and an inspection head 362.

[0089] The substrate holding unit 361 holds the substrate CW1 with the chip. The substrate holding unit 361 is movable in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holding unit 361 may be rotatable about a vertical axis. By moving or rotating the substrate holding unit 361, the inspection position can be changed. The substrate holding unit 361 may be movable in the vertical direction.

[0090] The inspection head 362 has, for example, a CT scanner, an infrared scanner, a confocal laser scanner, or an ultrasonic scanner, etc., acquires an image of the interface between the chip CP1 and the substrate W1, and detects the presence or absence of air bubbles. Alternatively, the inspection head 362 may have a height measuring instrument such as a laser displacement meter, and detect the presence or absence of air bubbles by detecting the height of the chip CP1. If there are air bubbles, the height of the chip CP1 increases by the thickness of the air bubbles.

[0091] The inspection unit 36 may have a determination unit (not shown) that determines whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions on the main surface W1c of the substrate W1 is good or bad based on the information acquired by the inspection head 362. The determination unit is configured by a computer. The determination unit may be a part of the control unit 9.

[0092] Next, with reference to FIG. 10, an example of the chip peeling unit 37 will be described. The chip peeling unit 37 peels off the chip CP1 with a defective bonding state in the inspection by the inspection unit 36 from the substrate W1. The chip peeling unit 37 includes, for example, a substrate holding unit 371, a peeling head 372, and a collection box 373.

[0093] The substrate holding unit 371 holds the substrate CW1 with chips. The substrate holding unit 371 is movable in the horizontal directions (both the X-axis direction and the Y-axis direction). The substrate holding unit 371 may be rotatable about a vertical axis. The peeling position can be changed by the movement or rotation of the substrate holding unit 371. The substrate holding unit 371 may be movable in the vertical direction.

[0094] The peeling head 372 includes, for example, a suction head 372a. The suction head 372a sucks the chip CP1 from above and moves upward in that state to peel the chip CP1 from the substrate W1. The first suction head 531 may be movable not only in the vertical direction but also in the horizontal direction. The suction head 372a drops the chip CP1 peeled from the substrate W1 into the collection box 373.

[0095] Next, with reference to FIGS. 11 and 12, a modified example of the chip peeling unit 37 will be described. As shown in FIG. 11(A), the peeling head 372 may include a blade 372b in addition to the suction head 372a. The blade 372b is inserted into the interface between the chip CP1 and the substrate W1 to peel the chip CP1 from the substrate W1.

[0096] As shown in FIG. 11(B), the peeling head 372 may include a heater 372c and a cooler 372d in addition to the suction head 372a. The heater 372c and the cooler 372d are provided inside the suction head 372a to form a temperature gradient in the chip CP1 and peel the chip CP1 from the substrate W1 by thermal stress.

[0097] The cooler 372d is arranged so as to surround the heater 372c. Thereby, it is possible to suppress the lateral leakage of the heat of the heater 372c and suppress the heating of the chip CP1 that is not the object to be peeled off. Even if the arrangements of the cooler 372d and the heater 372c are reversed, it is possible to peel the chip CP1 from the substrate W1 due to thermal stress. The cooler 372d may be provided in the substrate holding portion 371 (see FIG. 10) instead of being provided inside the suction head 372a.

[0098] As shown in FIG. 12(A), the peeling head 372 may include, in addition to the suction head 372a, a tubular seal 372e and a nozzle 372f. The seal 372e stores a peeling liquid that reduces the bonding strength between the chip CP1 and the substrate W1 around the chip CP1 to be peeled off. The nozzle 372f discharges the peeling liquid inside the seal 372e.

[0099] The peeling liquid penetrates into the interface between the chip CP1 to be peeled off and the substrate W1, reducing the bonding strength between the chip CP1 and the substrate W1. The peeling liquid contains, for example, pure water such as DIW. The pure water reduces the bonding strength between the chip CP1 and the substrate W1 by hydrolysis. The peeling liquid may contain pure water and components other than pure water.

[0100] The seal 372e is pressed against the main surface W1c of the substrate W1. The material of the seal 372e is, for example, resin or rubber. The inner peripheral surface of the seal 372e may be a tapered surface that tapers downward. The tapered surface can guide the peeling liquid inward.

[0101] The nozzle 372f may suck up the peeling liquid stored inside the seal 372e before separating the seal 372e from the substrate W1. The nozzle 372f for discharging the peeling liquid and the nozzle 372f for sucking up the peeling liquid may be provided separately.

[0102] As shown in FIG. 12(B), the chip peeling portion 37 may have a plurality of push-up pins 374 inside the substrate holding portion 371. The plurality of push-up pins 374 can be individually raised and lowered. In a state where the substrate holding portion 371 adsorbs the substrate CW1 with chips, the push-up pins 374 locally lift the substrate W1, so that the substrate W1 is locally bent and deformed, and the chip CP1 is peeled from the substrate W1.

[0103] Next, with reference to FIG. 13, an example of the rework portion 38 will be described. The rework portion 38 selectively processes the bonding region on the main surface W1c of the substrate W1 from which the chip CP1 has been peeled by the chip peeling portion 37. The rework portion 38 has, for example, a substrate holding portion 381 and a processing head 382.

[0104] The substrate holding portion 381 holds the substrate CW1 with chips. The substrate holding portion 381 can move in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holding portion 381 may be rotatable about the vertical axis. The processing position can be changed by the movement or rotation of the substrate holding portion 381. The substrate holding portion 381 may be movable in the vertical direction.

[0105] The processing head 382 has, for example, a plasma head, and selectively supplies plasma to the bonding region from which the chip CP1 has been peeled from the plasma head. The processing head 382 may have a cover surrounding the plasma head in order to narrow the plasma supply region, and the inside of the cover may be depressurized.

[0106] The processing head 382 may have a cleaning head, and selectively supplies water from the cleaning head to the bonding region from which the chip CP1 has been peeled. The cleaning head may supply water in either a liquid state or a gas state, but preferably in a gas state. The processing head 382 may have a cover surrounding the cleaning head in order to narrow the water supply region, and the inside of the cover may be depressurized.

[0107] The processing head 382 may be movable in the horizontal direction (both the X-axis direction and the Y-axis direction). By moving the processing head 382, the processing position can be changed. The processing head 382 may also be movable in the vertical direction.

[0108] Next, with reference to FIG. 14, the differences between the substrate processing apparatus 1 according to the first modification example and the above-described embodiment will be mainly described. Instead of the first processing station 3, the second processing station 5 of the substrate processing apparatus 1 includes the inspection unit 36. It is also possible to simultaneously perform the bonding of the substrate W1 and the chip CP1 (step S104) and the inspection of the bonded state (step S105). Instead of the first processing station 3, the second processing station 5 may also include a chip peeling unit 37 in addition to the inspection unit 36.

[0109] Next, with reference to FIGS. 15 and 16, the differences between the substrate processing apparatus 1 according to the second modification example and the above-described embodiment and the above-described first modification example will be mainly described. As shown in FIGS. 16(A) to 16(D), the substrate processing apparatus 1 manufactures the chip-mounted substrate CW1 by bonding a second chip CP2 different from the chip CP1 to a second bonding region different from the bonding region of the main surface W1c of the substrate W1. The chip-mounted substrate CW1 includes the substrate W1, a plurality of chips CP1 bonded to the substrate W1, and a plurality of second chips CP2 bonded to the substrate W1.

[0110] A plurality of second chips CP2 shown in FIG. 16(B) are carried into the substrate processing apparatus 1. The plurality of second chips CP2 are adhered to the second tape TP2, and the outer periphery of the second tape TP2 is attached to the second frame FR2. A plurality of second chips CP2 are arranged in the opening of the second frame FR2. The plurality of second chips CP2 can be obtained, for example, by dicing the substrate in a state where the substrate is adhered to the second tape TP2.

[0111] The second chip CP2 has a lower base substrate CP2a and a device CP2b formed on the lower base substrate CP2a. The lower base substrate CP2a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The device CP2b includes semiconductor elements, circuits, terminals, and the like. The device CP2b is disposed on the side opposite to the second tape TP2 with respect to the lower base substrate CP2a.

[0112] As shown in FIG. 16(C), the pickup unit 53 individually peels a plurality of second chips CP2 from the second tape TP2. Thereafter, the second chip CP2 is turned upside down and then bonded to the substrate W1 as shown in FIG. 16(D). The device W1b on the substrate W1, the device CP1b of the chip CP1, and the device CP2b of the second chip CP2 are electrically connected. Thereby, a substrate with chips CW1 is obtained.

[0113] As shown in FIG. 15, the interface block 4 may include a third buffer unit 45. The third buffer unit 45 is adjacent to the transfer area 30 of the first processing station 3. The first buffer unit 41, the second buffer unit 42, and the third buffer unit 45 may be stacked in the vertical direction so as to reduce the footprint of the interface block 4.

[0114] The third buffer unit 45 stores a plurality of second chips CP2 together with the second frame FR2. The third buffer unit 45 stores a plurality of second chips CP2 that have undergone pre-processing (for example, cleaning). Thereby, the operating rate of the second processing station 5 can be improved, and the production efficiency of the substrate with chips CW1 can be improved.

[0115] Note that the transfer and cleaning of the second chip CP2 are performed in the same manner as the transfer and cleaning of the chip CP1, and thus the description thereof is omitted. The apparatus used for the transfer and cleaning of the second chip CP2 and the apparatus used for the transfer and cleaning of the chip CP1 may be a common apparatus or may be separately provided apparatuses.

[0116] In addition, since the pickup and mounting of the second chip CP2 are performed in the same manner as those of the chip CP1, the description thereof will be omitted. The apparatus used for the pickup and mounting of the second chip CP2 and the apparatus used for the pickup and mounting of the chip CP1 may be a common apparatus or may be separately provided apparatuses.

[0117] Next, with reference to FIGS. 18 to 22, the substrate processing apparatus 1 according to the third modification will be mainly described in terms of differences from the above-described embodiment, the first modification, and the second modification. As shown in FIGS. 19(A) to 19(C), the substrate processing apparatus 1 peels the chip CP1 protected by the protective film PF1 from the tape TP1, and then mounts the chip CP1 on the substrate W1. During this process, the substrate processing apparatus 1 removes the protective film PF1 from the chip CP1.

[0118] As shown in FIG. 20, the second processing station 5 includes a substrate holding unit 51, a chip holding unit 52, a pickup unit 53, and a mount unit 54. The second processing station 5 also includes a removal unit 55 (see FIG. 18). Hereinafter, the pickup unit 53, the mount unit 54, and the removal unit 55 will be described in this order.

[0119] The pickup unit 53 peels the chip CP1 from the tape TP1 in a state where a plurality of chips CP1 are mounted on the frame FR1 via the tape TP1 and the protective film PF1 is formed on the first main surface CP1c on the side opposite to the tape TP1 of the chip CP1. The protective film PF1 covers the first main surface CP1c of the chip CP1.

[0120] The pickup unit 53 has a first suction head 531. The first suction head 531 sucks the chip CP1 through the protective film PF1. The protective film PF1 suppresses damage to the device CP1b by preventing contact between the first suction head 531 and the device CP1b of the chip CP1.

[0121] The first suction head 531 moves upward while sucking the chip CP1, thereby peeling the chip CP1 from the tape TP1. At this time, the protective film PF1 is torn and divided. Note that the protective film PF1 may be divided in advance by laser processing or blade processing or the like.

[0122] The first suction head 531 may be capable of being turned upside down. The chip CP1 can be turned upside down, and the first main surface CP1c of the chip CP1 can be directed toward the substrate W1. As described above, a conveying unit (not shown) may convey the chip CP1 from the pickup unit 53 to the mounting unit 54, and the conveying unit may turn the chip CP1 upside down during the conveyance.

[0123] The mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the first main surface CP1c of the chip CP1 directed toward the substrate W1. The mounting unit 54 has a second suction head 541. The second suction head 541 sucks the second main surface CP1d of the chip CP1. The second main surface CP1d is a surface opposite to the first main surface CP1c and is the surface peeled from the tape TP1.

[0124] The second suction head 541 sucks the chip CP1 from above and moves downward in that state, thereby mounting the chip CP1 on the main surface W1c of the substrate W1. The protective film PF1 is removed in advance so that the chip CP1 and the substrate W1 come into contact with each other. The device CP1b of the chip CP1 and the device W1b of the substrate W1 are electrically connected.

[0125] According to this modification, the pickup unit 53 peels the chip CP1 from the tape TP1 with the protective film PF1 covering the first main surface CP1c of the chip CP1. Therefore, contact between the pickup unit 53 and the chip CP1 can be prevented, and damage to the chip CP1 can be suppressed. This is particularly effective when the first main surface CP1c of the chip CP1 has the device CP1b.

[0126] Thereafter, after removing the protective film PF1, the chip CP1 is bonded to the substrate W1 with the first main surface CP1c of the chip CP1 facing the substrate W1. By removing the protective film PF1 in advance, the chip CP1 can be brought into contact with the substrate W1, and the device CP1b of the chip CP1 and the device W1b of the substrate W1 can be electrically connected.

[0127] Next, with reference to FIG. 21, an example of the removal portion 55 will be described. As shown in FIG. 21(A), the protective film PF1 may cover not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1. The protective film PF1 is formed, although details will be described later, by applying a liquid material of the protective film PF1 onto a plurality of chips CP1 previously divided by dicing and solidifying it, and is also formed in the gaps between adjacent chips CP1.

[0128] As shown in FIG. 21(B), the removal portion 55 may include a first supply portion 551. The first supply portion 551 supplies a release liquid L1 for peeling the protective film PF1 from the chip CP1 to the protective film PF1. The release liquid L1 peels the protective film PF1 from the chip CP1 without dissolving the protective film PF1, for example. The protective film PF1 can be peeled from the chip CP1 while remaining in the form of a film.

[0129] For example, the first supply portion 551 has a storage tank for storing the release liquid L1, and the protective film PF1 together with the chip CP1 is immersed in the release liquid L1 stored in the storage tank. At this time, for example, the second suction head 541 of the mounting portion 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the release liquid L1. Note that the suction head for holding the chip CP1 is not limited to the second suction head 541 of the mounting portion 54.

[0130] As shown in FIG. 21(C), when the release liquid L1 penetrates into the protective film PF1 and reaches the interface between the protective film PF1 and the chip CP1, the protective film PF1 is peeled from the chip CP1. As a result, the particles PC adhering to the chip CP1 before the formation of the protective film PF1 are peeled from the chip CP1 together with the protective film PF1.

[0131] The protective film PF1 preferably covers not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1 in order to improve the removal efficiency of the particles PC. The particles PC attached to the side surface CP1e of the chip CP1 can also be peeled off from the chip CP1.

[0132] The stripping liquid L1 is appropriately selected according to the material of the protective film PF1, and is, for example, pure water such as DIW. The protective film PF1 is, for example, an organic film. Pure water can penetrate into the organic film. The material of the organic film is not particularly limited, and is, for example, an acrylic resin or an epoxy resin, preferably an acrylic resin. The pure water may be heated in order to improve the peelability between the protective film PF1 and the chip CP1.

[0133] As shown in FIG. 21(D), the removing section 55 may have a second supply section 552. After the first supply section 551 supplies the stripping liquid L1 to the protective film PF1, the second supply section 552 supplies a dissolving liquid L2 that dissolves the protective film PF1.

[0134] For example, the second supply section 552 has a storage tank for storing the dissolving liquid L2, and the protective film PF1 and the chip CP1 are immersed in the dissolving liquid L2 stored in the storage tank. At this time, for example, the second suction head 541 of the mounting section 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the dissolving liquid L2. Note that the suction head that holds the chip CP1 is not limited to the second suction head 541 of the mounting section 54.

[0135] As the dissolving liquid L2, for example, an alkaline developer is used. When an alkaline developer is used, a zeta potential of the same polarity can be generated in the chip CP1 and the particles PC, and reattachment of the particles PC to the chip CP1 can be suppressed. When an alkaline developer is used as the dissolving liquid L2, an alkaline developer having a lower concentration than the dissolving liquid L2 may be used as the stripping liquid L1.

[0136] Note that the storage tank for storing the dissolution liquid L2 and the storage tank for storing the peeling liquid L1 may be common. Further, although the removal unit 55 has both the first supply unit 551 and the second supply unit 552, it may have only the first supply unit 551 or only the second supply unit 552. The removal unit 55 may have a drying unit for drying the chip CP1. When the removal unit 55 does not use a liquid such as the peeling liquid L1 or the dissolution liquid L2, the drying unit is unnecessary.

[0137] Next, with reference to FIGS. 18 and 22, an example of the coating unit 70 will be described. As shown in FIG. 18, the coating unit 70 is provided in the first processing station 3. The coating unit 70 is adjacent to the transfer area 30. After the plurality of chips CP1 are cleaned by the chip cleaning unit 33, they are processed by the coating unit 70 and then transferred to the chip bonding unit 6 by the first frame transfer arm 32. In this modification, the coating unit 70 and the chip cleaning unit 33 are provided separately, but the coating unit 70 may have the function of the chip cleaning unit 33.

[0138] As shown in FIG. 22, the coating unit 70 has, for example, a chip holding unit 701 and a frame holding unit 702. The chip holding unit 701 horizontally holds a plurality of chips CP1 from below via the tape TP1. The chip holding unit 701 slidably mounts the tape TP1. Note that the chip holding unit 701 may have a vacuum chuck mechanism and fix the tape TP1.

[0139] The frame holding unit 702 horizontally holds the frame FR1 from below. The frame holding unit 702 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1. By the rotation drive unit 704, which will be described later, rotating the frame holding unit 702, the plurality of chips CP1 rotate together with the frame FR1.

[0140] The coating unit 70 includes a rotation driving unit 704, a nozzle 705, and a cup 706. The rotation driving unit 704 rotates a plurality of chips CP1 together with the frame FR1 by rotationally driving the frame holding unit 702. The rotation driving unit 704 also rotationally drives the chip holding unit 701 together with the frame holding unit 702. The nozzle 705 supplies the liquid material L3 of the protective film PF1 to the plurality of chips CP1. The cup 706 collects the liquid material L3.

[0141] The coating unit 70 forms the protective film PF1 by applying and solidifying the liquid material of the protective film PF1 on a plurality of chips CP1 that have been previously divided by dicing. The protective film PF1 can also be formed in the gaps between adjacent chips CP1 and on the side surfaces CP1e of the chips CP1. In this specification, "solidification" includes "curing". "Curing" means that molecules are linked to form a polymer (such as cross-linking or polymerization).

[0142] The coating unit 70 forms the protective film PF1 by applying and solidifying the liquid material L3 of the protective film PF1 to the chips CP1 from the side opposite to the tape TP1 with respect to the chips CP1 in a state where the plurality of chips CP1 are mounted on the frame FR1 via the tape TP1. Since the plurality of chips CP1 are adhered to the tape TP1, the handling property is good.

[0143] The liquid material L3 is supplied near the rotation center line of the plurality of chips CP1 and spreads radially in a direction away from the rotation center line by centrifugal force to form a liquid film. The protective film PF1 is formed by solidifying the liquid film of the liquid material L3. After the formation of the liquid film and before the solidification of the liquid film, the rotation of the chips CP1 may be stopped.

[0144] The liquid material L3 contains, for example, a volatile component and solidifies by the volatilization of the volatile component. By utilizing the volume shrinkage associated with the volatilization of the volatile component, the particles PC can be peeled off from the chips CP1. The liquid material L3 may contain an acrylic resin. The particles PC can also be peeled off from the chips CP1 by the curing shrinkage of the acrylic resin.

[0145] As described above, embodiments of the substrate processing apparatus and the substrate processing method according to the present disclosure have been explained. However, the present disclosure is not limited to the above embodiments. Within the scope described in the claims, various changes, modifications, substitutions, additions, deletions, and combinations are possible. Naturally, those also belong to the technical scope of the present disclosure.

[0146] This application claims priority based on Japanese Patent Application No. 2022-011239 filed with the Japan Patent Office on January 27, 2022, and incorporates the entire contents of Japanese Patent Application No. 2022-011239 into this application.

Explanation of Reference Numerals

[0147] 1 Substrate processing apparatus 6 Chip bonding part 53 Pickup part 54 Mounting part 55 Removal part CP1 Chip CP1c First main surface FR1 Frame TP1 Tape PF1 Protective film W1 Substrate W1c Main surface

Claims

1. A pickup unit that peels a chip from a tape with a plurality of chips mounted on a frame via the tape and a protective film formed on a first main surface of the chip opposite to the tape; A removal unit that removes the protective film from the chip after the chip is peeled from the tape by the pickup unit; A mount unit that mounts the chip on a substrate with the first main surface of the chip facing the substrate after the protective film is removed by the removal unit; A substrate processing apparatus comprising the same.

2. The pickup unit includes a first suction head that sucks the chip through the protective film, and the mount unit includes a second suction head that sucks a second main surface of the chip peeled from the tape. The substrate processing apparatus according to Claim 1.

3. The removal unit includes a first supply unit that supplies a peeling liquid for peeling the protective film from the chip to the protective film. The substrate processing apparatus according to Claim 1 or 2.

4. The substrate processing apparatus according to Claim 3, wherein the peeling liquid is pure water.

5. The removal unit includes a second supply unit that supplies a dissolving liquid for dissolving the protective film to the protective film after the peeling liquid is supplied to the protective film by the first supply unit. The substrate processing apparatus according to Claim 3.

6. A coating unit that forms the protective film by applying and solidifying a liquid material of the protective film on a plurality of the chips previously divided by dicing. The substrate processing apparatus according to Claim 1 or 2.

7. The coating unit forms the protective film by applying the liquid material of the protective film to the chips from a side opposite to the tape with respect to the chips in a state where the plurality of chips are mounted on the frame via the tape and then solidifying the applied material. The substrate processing apparatus according to Claim 6.

8. A chip bonding unit having the pickup unit, the removal unit, and the mount unit; A transport area adjacent to the coating unit and the chip bonding unit, and a first frame transport arm that holds the frame in the transport area and transports a plurality of the chips together with the frame. The first frame transport arm transports a plurality of the chips together with the frame from the coating unit to the chip bonding unit. The substrate processing apparatus according to Claim 6.

9. The chip bonding part includes an interface part adjacent to the conveyance area, and a second processing station arranged on the side opposite to the conveyance area with reference to the interface part. The second processing station includes a substrate holding part for holding the substrate, a chip holding part for holding a plurality of the chips in a state where the plurality of the chips are mounted on the frame via the tape, the pickup part, the removing part, and the mounting part. The interface part includes a first buffer part for storing the substrate, a second substrate transfer arm for transferring the substrate from the first buffer part to the substrate holding part, a second buffer part for storing a plurality of the chips transferred together with the frame by the first frame transfer arm, and a second frame transfer arm for transferring the plurality of the chips together with the frame from the second buffer part to the chip holding part. The substrate processing apparatus according to claim 8.

10. The second processing station includes an inspection part for inspecting whether the bonding state of each of a plurality of the chips bonded to different bonding areas on the main surface of the substrate is good or bad, and a chip peeling part for peeling off the chip whose bonding state is bad from the substrate in the inspection by the inspection part. The substrate processing apparatus according to claim 9.

11. An inspection part for inspecting whether the bonding state of each of a plurality of the chips bonded to different bonding areas on the main surface of the substrate is good or bad, and a chip peeling part for peeling off the chip whose bonding state is bad from the substrate in the inspection by the inspection part. The inspection part and the chip peeling part are adjacent to the conveyance area. The substrate processing apparatus according to claim 8.

12. Peeling the chip from the tape in a state where a plurality of chips are mounted on a frame via a tape and a protective film is formed on a first main surface of the chip opposite to the tape. After peeling the chip from the tape, removing the protective film from the chip. After removing the protective film, mounting the chip on the substrate with the first main surface of the chip facing the substrate. A substrate processing method having the above steps.

13. Removing the protective film includes supplying a peeling liquid for peeling the protective film from the chip to the protective film. The substrate processing method according to claim 12.

14. The substrate processing method according to claim 13, wherein the release liquid is pure water.

15. The substrate processing method according to claim 13 or 14, wherein removing the protective film includes supplying a release liquid to the protective film and then supplying a dissolving liquid that dissolves the protective film to the protective film.

16. The substrate processing method according to any one of claims 12 to 14, including forming the protective film by applying and solidifying a liquid material of the protective film on a plurality of the chips previously divided by dicing.

17. The substrate processing method according to claim 16, wherein forming the protective film includes applying the liquid material of the protective film to the chips and solidifying it from the side opposite to the tape with respect to the chips in a state where the plurality of chips are mounted on the frame via the tape.

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