Switch device

Abstract

To provide a switching device capable of improving resistance to an excess current.SOLUTION: A switching device comprises: an output transistor; an excessive current protection circuit that is constructed so as to execute an excessive current protection operation for limiting a magnitude of an objective current (IOUT) flowing in the output transistor to a predetermined upper limit current value or less; and a control circuit that can control a state of the output transistor, and is constructed so as to change the upper limit current value between a plurality of current values including a predetermined first current value (ILIM1) and a second predetermined current value (ILIM2) lower than the first current value. The control circuit is constructed so as to change the upper limit current value to a second current value after the excessive current protection operation that the magnitude of the objective current limit to the first current value or less is performed in response that the magnitude of the objective current achieves the first current value.SELECTED DRAWING: Figure 23

Description

Technical Field

[0001] The present disclosure relates to a switching device.

Background Art

[0002] There is a switching device having an output transistor and turning on and off a current flowing through the output transistor. In this type of switching device, an overcurrent protection function is provided, and when an overcurrent is detected, the magnitude of the current flowing through the output transistor is limited to a predetermined value or less.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a sky short circuit or a ground short circuit occurs, the overcurrent protection operation may be repeatedly executed. Temperature fluctuations of the output transistor occurring during the repetition of the overcurrent protection operation may have an undesirable influence on the structure of the switching device. The higher the resistance to overcurrent, the higher the reliability of the switching device.

[0005] An object of the present disclosure is to provide a switching device that contributes to improving resistance to overcurrent.

Means for Solving the Problems

[0006] The switch device according to the present disclosure includes an output transistor, an overcurrent protection circuit configured to be capable of performing an overcurrent protection operation for limiting the magnitude of a target current flowing through the output transistor to a predetermined upper limit current value or less, and a control circuit capable of controlling the state of the output transistor and configured to be capable of changing the upper limit current value among a plurality of current values including a predetermined first current value and a predetermined second current value lower than the first current value. After an overcurrent protection operation for limiting the magnitude of the target current to the first current value or less is performed in response to the magnitude of the target current reaching the first current value, the control circuit is configured to be capable of changing the upper limit current value to the second current value.

Advantages of the Invention

[0007] According to the present disclosure, it is possible to provide a switch device that contributes to improving the tolerance to overcurrent.

Brief Description of the Drawings

[0008]

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Figure 25

[0009] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are denoted by the same reference numerals, and redundant descriptions regarding the same parts are omitted in principle. In this specification, for the sake of simplicity of description, the name of information, signal, physical quantity, element, or part corresponding to a symbol or reference numeral may be omitted or abbreviated by writing the symbol or reference numeral for referring to the information, signal, physical quantity, element, or part. For example, the gate control circuit referred to by "1110" described later may be denoted as the gate control circuit 1110 (see FIG. 16), or may be abbreviated as the control circuit 1110 or the circuit 1110, but they all refer to the same thing.

[0010] <<First Embodiment>> The first embodiment of the present disclosure will be described. FIG. 1 is a perspective view of the semiconductor device 1 according to the first embodiment of the present disclosure as viewed from one direction. Hereinafter, a form example in which the semiconductor device 1 is a high-side switching device will be described, but the semiconductor device 1 is not limited to a high-side switching device. The semiconductor device 1 can also be provided as a low-side switching device by adjusting the electrical connection form and function of various structures.

[0011] Referring to FIG. 1, the semiconductor device 1 includes a semiconductor layer 2. The semiconductor layer 2 contains silicon. The semiconductor layer 2 is formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4.

[0012] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") as viewed from the normal direction Z thereof. The side surface 5A and the side surface 5C extend along the first direction X and face each other in the second direction Y intersecting the first direction X. The side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.

[0013] An output region 6 and an input region 7 are set in the semiconductor layer 2. The output region 6 is set in the region on the side surface 5C side. The input region 7 is set in the region on the side surface 5A side. In a plan view, the area SOUT of the output region 6 is equal to or larger than the area SIN of the input region 7 (SIN≦SOUT).

[0014] The ratio SOUT / SIN of the area SOUT to the area SIN may be 1 or more and 10 or less (1<SOUT / SIN≦10). The ratio SOUT / SIN may be 1 or more and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, or 8 or more and 10 or less. The planar shape of the input region 7 and the planar shape of the output region 6 are arbitrary and are not limited to a specific shape. Of course, the ratio SOUT / SIN may be more than 0 and less than 1.

[0015] The output region 6 includes a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) 9 as an example of an insulated gate type transistor. The power MISFET 9 includes a gate, a drain, and a source.

[0016] The input region 7 includes a control IC (Integrated Circuit) 10 as an example of a control circuit. The control IC 10 includes a plurality of types of functional circuits that implement various functions. The plurality of types of functional circuits includes a circuit that generates a gate control signal for driving and controlling the power MISFET 9 based on an electrical signal from the outside. The control IC 10 forms a so-called IPD (Intelligent Power Device) together with the power MISFET 9. Note that the IPD is also referred to as an IPM (Intelligent Power Module).

[0017] The input region 7 is electrically insulated from the output region 6 by the region separation structure 8. In FIG. 1, the region separation structure 8 is indicated by hatching. Although specific description is omitted, the region separation structure 8 may have a trench insulation structure in which an insulator is embedded in a trench.

[0018] On the semiconductor layer 2, a plurality (here, six) of electrodes 11, 12, 13, 14, 15, and 16 are formed. In FIG. 1, the plurality of electrodes 11 to 16 are indicated by hatching. The plurality of electrodes 11 to 16 are formed as terminal electrodes that are externally connected by a conducting wire (for example, a bonding wire) or the like. The number, arrangement, and planar shape of the plurality of electrodes 11 to 16 are arbitrary and are not limited to the form shown in FIG. 1.

[0019] The number, arrangement, and planar shape of the plurality of electrodes 11 to 16 are adjusted according to the specifications of the power MISFET 9 and the control IC 10. In this form, the plurality of electrodes 11 to 16 include a drain electrode 11 (power supply electrode), a source electrode 12 (output electrode), an input electrode 13, a reference voltage electrode 14, an ENABLE electrode 15, and a SENSE electrode 16.

[0020] The drain electrode 11 is formed on the second main surface 4 of the semiconductor layer 2. The drain electrode 11 is electrically connected to the second main surface 4 of the semiconductor layer 2. The drain electrode 11 transmits the power supply voltage VB to the drain of the power MISFET 9 and various circuits of the control IC 10.

[0021] The drain electrode 11 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The drain electrode 11 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The drain electrode 11 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are laminated in an arbitrary manner.

[0022] The source electrode 12 is formed on the output region 6 on the first main surface 3. The source electrode 12 is electrically connected to the source of the power MISFET 9. The source electrode 12 transmits the electrical signal generated by the power MISFET 9 to the outside.

[0023] The input electrode 13, the reference voltage electrode 14, the ENABLE electrode 15, and the SENSE electrode 16 are respectively formed on the input region 7 on the first main surface 3. The input electrode 13 transmits the input voltage for driving the control IC 10.

[0024] The reference voltage electrode 14 transmits a reference voltage (for example, a ground voltage) to the control IC 10. The ENABLE electrode 15 transmits an electrical signal for enabling or disabling some or all of the functions of the control IC 10. The SENSE electrode 16 transmits an electrical signal for detecting an abnormality of the control IC 10.

[0025] On the semiconductor layer 2, a gate control wiring 17 as an example of a control wiring is further formed. The gate control wiring 17 is selectively routed to the output region 6 and the input region 7. The gate control wiring 17 is electrically connected to the gate of the power MISFET 9 in the output region 6 and is electrically connected to the control IC 10 in the input region 7.

[0026] The gate control wiring 17 transmits the gate control signal generated by the control IC 10 to the gate of the power MISFET 9. The gate control signal includes an on signal Von and an off signal Voff, and controls the on state and off state of the power MISFET 9.

[0027] The on signal Von is higher than the gate threshold voltage Vth of the power MISFET 9 (Vth < Von). The off signal Voff is lower than the gate threshold voltage Vth of the power MISFET 9 (Voff < Vth). The off signal Voff may be a reference voltage (e.g., ground voltage).

[0028] In this form, the gate control wiring 17 includes a first gate control wiring 17A, a second gate control wiring 17B, and a third gate control wiring 17C. The first gate control wiring 17A, the second gate control wiring 17B, and the third gate control wiring 17C are electrically insulated from each other.

[0029] In this form, two first gate control wirings 17A are routed to different regions. Also, two second gate control wirings 17B are routed to different regions. Also, two third gate control wirings 17C are routed to different regions.

[0030] The first gate control wiring 17A, the second gate control wiring 17B, and the third gate control wiring 17C transmit the same or different gate control signals to the gate of the power MISFET 9. The number, arrangement, shape, etc. of the gate control wiring 17 are arbitrary and are adjusted according to the transmission distance of the gate control signal and the number of gate control signals to be transmitted.

[0031] The source electrode 12, the input electrode 13, the reference voltage electrode 14, the ENABLE electrode 15, the SENSE electrode 16, and the gate control wiring 17 may each contain at least one of nickel, palladium, aluminum, copper, aluminum alloy, and copper alloy.

[0032] The source electrode 12, input electrode 13, reference voltage electrode 14, ENABLE electrode 15, SENSE electrode 16, and gate control wiring 17 may each contain at least one of an Al-Si-Cu (aluminum-silicon-copper) alloy, an Al-Si (aluminum-silicon) alloy, and an Al-Cu (aluminum-copper) alloy.

[0033] The source electrode 12, input electrode 13, reference voltage electrode 14, ENABLE electrode 15, SENSE electrode 16, and gate control wiring 17 may contain the same type of electrode material, or may contain different electrode materials from each other.

[0034] FIG. 2 is a block circuit diagram showing the electrical structure of the semiconductor device 1 shown in FIG. 1. Hereinafter, the case where the semiconductor device 1 is mounted on a vehicle will be described as an example.

[0035] The semiconductor device 1 includes a drain electrode 11, a source electrode 12, an input electrode 13, a reference voltage electrode 14, an ENABLE electrode 15, a SENSE electrode 16, gate control wiring 17, a power MISFET 9, and a control IC 10.

[0036] The drain electrode 11 is connected to a power supply. The drain electrode 11 provides a power supply voltage VB to the power MISFET 9 and the control IC 10. The power supply voltage VB may be 10V or more and 20V or less. The source electrode 12 is connected to a load.

[0037] The input electrode 13 may be connected to an MCU (Micro Controller Unit), a DC / DC converter, an LDO (Low Drop Out), etc. The input electrode 13 provides an input voltage to the control IC 10. The input voltage may be 1V or more and 10V or less. The reference voltage electrode 14 is connected to a reference voltage wiring. The reference voltage electrode 14 provides a reference voltage to the power MISFET 9 and the control IC 10.

[0038] The ENABLE electrode 15 may be connected to the MCU. An electrical signal for enabling or disabling some or all of the functions of the control IC 10 is input to the ENABLE electrode 15. The SENSE electrode 16 may be connected to a resistor.

[0039] The gate of the power MISFET 9 is connected to the control IC 10 (gate control circuit 25 described later) via the gate control wiring 17. The drain of the power MISFET 9 is connected to the drain electrode 11. The source of the power MISFET 9 is connected to the control IC 10 (current detection circuit 27 described later) and the source electrode 12.

[0040] The control IC 10 includes a sensor MISFET 21, an input circuit 22, a current / voltage control circuit 23, a protection circuit 24, a gate control circuit 25, an active clamp circuit 26, a current detection circuit 27, a power reverse connection protection circuit 28, and an abnormality detection circuit 29.

[0041] The gate of the sensor MISFET 21 is connected to the gate control circuit 25. The drain of the sensor MISFET 21 is connected to the drain electrode 11. The source of the sensor MISFET 21 is connected to the current detection circuit 27.

[0042] The input circuit 22 is connected to the input electrode 13 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0043] The current / voltage control circuit 23 is connected to the protection circuit 24, the gate control circuit 25, the power reverse connection protection circuit 28, and the abnormality detection circuit 29. The current / voltage control circuit 23 may include a logic circuit.

[0044] The current / voltage control circuit 23 generates various voltages according to the electrical signals from the input circuit 22 and the electrical signals from the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage / reference current generation circuit 33.

[0045] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 30 may generate a drive voltage of 5 V or more and 15 V or less obtained by subtracting 5 V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0046] The first constant voltage generation circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generation circuit 31 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be 1 V or more and 5 V or less. The first constant voltage is input to the protection circuit 24 (more specifically, a load open detection circuit 35 or the like described later).

[0047] The second constant voltage generation circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generation circuit 32 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be 1 V or more and 5 V or less. The second constant voltage is input to the protection circuit 24 (more specifically, a thermal protection circuit 36 or a low voltage malfunction suppression circuit 37 described later).

[0048] The reference voltage / reference current generation circuit 33 generates a reference voltage and a reference current for various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to various circuits. When various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0049] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The protection circuit 24 includes an overcurrent protection circuit 34, a load open detection circuit 35, an overheat protection circuit 36, and a low voltage malfunction suppression circuit 37.

[0050] The overcurrent protection circuit 34 protects the power MISFET 9 from overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25 and the source of the sensor MISFET 21. The overcurrent protection circuit 34 may include a current monitor circuit. The signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, the drive signal output circuit 40 described later).

[0051] The load open detection circuit 35 detects the short state or open state of the power MISFET 9. The load open detection circuit 35 is connected to the current / voltage control circuit 23 and the source of the power MISFET 9. The signal generated by the load open detection circuit 35 is input to the current / voltage control circuit 23.

[0052] The overheat protection circuit 36 monitors the temperature of the power MISFET 9 and protects the power MISFET 9 from excessive temperature rise. The overheat protection circuit 36 is connected to the current / voltage control circuit 23. The overheat protection circuit 36 may include a temperature sensing device such as a temperature sensing diode or a thermistor. The signal generated by the overheat protection circuit 36 is input to the current / voltage control circuit 23.

[0053] The low voltage malfunction suppression circuit 37 suppresses the malfunction of the power MISFET 9 when the power supply voltage VB is less than a predetermined value. The low voltage malfunction suppression circuit 37 is connected to the current / voltage control circuit 23. The signal generated by the low voltage malfunction suppression circuit 37 is input to the current / voltage control circuit 23.

[0054] The gate control circuit 25 controls the on-state and off-state of the power MISFET 9, as well as the on-state and off-state of the sensor MISFET 21. The gate control circuit 25 is connected to the current-voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0055] The gate control circuit 25 generates a plurality of types of gate control signals corresponding to the number of gate control wirings 17 according to the electrical signal from the current-voltage control circuit 23 and the electrical signal from the protection circuit 24. The plurality of types of gate control signals are respectively input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17.

[0056] More specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates according to the electrical signal from the current-voltage control circuit 23 and generates a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 boosts the electrical signal from the oscillation circuit 38. The electrical signal boosted by the charge pump circuit 39 is input to the drive signal output circuit 40.

[0057] The drive signal output circuit 40 generates a plurality of types of gate control signals according to the electrical signal from the charge pump circuit 39 and the electrical signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). The plurality of types of gate control signals are input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. The sensor MISFET 21 and the power MISFET 9 are simultaneously controlled by the gate control circuit 25.

[0058] The active clamp circuit 26 protects the power MISFET 9 from the back electromotive force. The active clamp circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamp circuit 26 may include a plurality of diodes.

[0059] The active clamp circuit 26 may include a plurality of diodes connected in forward bias to each other. The active clamp circuit 26 may include a plurality of diodes connected in reverse bias to each other. The active clamp circuit 26 may include a plurality of diodes connected in forward bias to each other and a plurality of diodes connected in reverse bias to each other.

[0060] The plurality of diodes may include pn junction diodes, or Zener diodes, or pn junction diodes and Zener diodes. The active clamp circuit 26 may include a plurality of Zener diodes connected in bias to each other. The active clamp circuit 26 may include a Zener diode and a pn junction diode connected in reverse bias to each other.

[0061] The current detection circuit 27 detects the current flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal according to the electrical signal generated by the power MISFET 9 and the electrical signal generated by the sensor MISFET 21. The current detection signal is input to the abnormality detection circuit 29.

[0062] The power reverse connection protection circuit 28 protects the current-voltage control circuit 23, the power MISFET 9, etc. from the reverse voltage when the power supply is reversely connected. The power reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current-voltage control circuit 23.

[0063] The abnormality detection circuit 29 monitors the voltage of the protection circuit 24. The abnormality detection circuit 29 is connected to the current / voltage control circuit 23, the protection circuit 24, and the current detection circuit 27. When an abnormality (such as voltage fluctuation) occurs in any of the overcurrent protection circuit 34, the load open detection circuit 35, the overheat protection circuit 36, and the low voltage malfunction suppression circuit 37, the abnormality detection circuit 29 generates an abnormality detection signal corresponding to the voltage of the protection circuit 24 and outputs it externally.

[0064] More specifically, the abnormality detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two input parts, one output part, and one selection control input part. The protection circuit 24 and the current detection circuit 27 are respectively connected to the input parts of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output part of the first multiplexer circuit 41. The current / voltage control circuit 23 is connected to the selection control input part of the first multiplexer circuit 41.

[0065] The first multiplexer circuit 41 generates an abnormality detection signal according to the electrical signal from the current / voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0066] The second multiplexer circuit 42 includes two input parts and one output part. The output part of the second multiplexer circuit 42 and the ENABLE electrode 15 are respectively connected to the input parts of the second multiplexer circuit 42. The SENSE electrode 16 is connected to the output part of the second multiplexer circuit 42.

[0067] When an MCU is connected to the ENABLE electrode 15 and a resistor is connected to the SENSE electrode 16, an on-signal is input from the MCU to the ENABLE electrode 15, and an abnormality detection signal is taken out from the SENSE electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to the SENSE electrode 16. The state abnormality of the semiconductor device 1 is detected based on this electrical signal.

[0068] FIG. 3 is a circuit diagram for explaining the active clamp operation of the semiconductor device 1 shown in FIG. 1. FIG. 4 is a waveform diagram of main electrical signals of the circuit diagram shown in FIG. 3.

[0069] Here, the normal operation and the active clamp operation of the semiconductor device 1 will be explained using a circuit example in which an inductive load L is connected to the power MISFET 9. Devices using windings (coils) such as solenoids, motors, transformers, and relays are exemplified as the inductive load L. The inductive load L is also referred to as an L load.

[0070] Referring to FIG. 3, the source of the power MISFET 9 is connected to the inductive load L. The drain of the power MISFET 9 is electrically connected to the drain electrode 11. The gate and drain of the power MISFET 9 are connected to the active clamp circuit 26. In this circuit example, the active clamp circuit 26 includes m (m is a natural number) Zener diodes DZ and n (n is a natural number) pn junction diodes D. The pn junction diode D is connected in reverse bias to the Zener diode DZ.

[0071] Referring to FIGS. 3 and 4, when an on-signal Von is input to the gate of the off-state power MISFET 9, the power MISFET 9 switches from the off state to the on state (normal operation). The on-signal Von has a voltage equal to or higher than the gate threshold voltage Vth (Vth ≦ Von). The power MISFET 9 is maintained in the on state for a predetermined on-time TON.

[0072] When the power MISFET 9 switches to the on state, the drain current ID starts to flow from the drain to the source of the power MISFET 9. The drain current ID increases from zero to a predetermined value and saturates. The inductive load L accumulates inductive energy due to the increase in the drain current ID.

[0073] When an off signal Voff is input to the gate of the power MISFET 9, the power MISFET 9 switches from the on state to the off state. The off signal Voff has a voltage less than the gate threshold voltage Vth (Voff < Vth). The off signal Voff may be a reference voltage (for example, the ground voltage).

[0074] At the transition when the power MISFET 9 switches from the on state to the off state, the inductive energy of the inductive load L is applied to the power MISFET 9 as a back electromotive force. As a result, the power MISFET 9 enters the active clamp state (active clamp operation). When the power MISFET 9 enters the active clamp state, the source voltage VSS rapidly drops to a negative voltage less than the reference voltage (ground voltage).

[0075] At this time, the source voltage VSS is limited to a voltage equal to or higher than the voltage obtained by subtracting the limit voltage VL and the clamp - on voltage VCLP from the power supply voltage VB due to the operation of the active clamp circuit 26 (VSS ≧ VB - VL - VCLP).

[0076] In other words, when the power MISFET 9 enters the active clamp state, the drain - source voltage VDS across the power MISFET 9 rapidly rises to the clamp voltage VDSSCL. The clamp voltage VDSSCL is limited to a voltage equal to or lower than the voltage obtained by adding the clamp - on voltage VCLP and the limit voltage VL by the power MISFET 9 and the active clamp circuit 26 (VDS ≦ VCLP + VL).

[0077] The clamping voltage VL is, in this form, the sum of the voltage VZ across the terminals of the Zener diode DZ and the voltage VF across the terminals of the pn junction diode in the active clamp circuit 26 (VL = m·VZ + n·VF).

[0078] The clamp-on voltage VCLP is the positive voltage applied between the gate and source of the power MISFET 9 (i.e., the gate voltage VGS). The clamp-on voltage VCLP is equal to or higher than the gate threshold voltage Vth (Vth ≤ VCLP). Therefore, the power MISFET 9 maintains the on state in the active clamp state.

[0079] When the clamp voltage VDSSCL exceeds the maximum rated drain voltage VDSS (VDSS < VDSSCL), the power MISFET 9 will be damaged. The power MISFET 9 is designed such that the clamp voltage VDSSCL is equal to or lower than the maximum rated drain voltage VDSS (VDSSCL ≤ VDSS).

[0080] When the clamp voltage VDSSCL is equal to or lower than the maximum rated drain voltage VDSS (VDSSCL ≤ VDSS), the drain current ID continues to flow from the drain to the source of the power MISFET 9, and the inductive energy of the inductive load L is consumed (absorbed) by the power MISFET 9.

[0081] The drain current ID decreases from the peak value IAV just before the power MISFET 9 turns off to zero after passing through the active clamp time TAV. As a result, the gate voltage VGS becomes the reference voltage (e.g., the ground voltage), and the power MISFET 9 switches from the on state to the off state.

[0082] The active clamp tolerance Eac of the power MISFET 9 is defined by the tolerance of the power MISFET 9 during the active clamp operation. More specifically, the active clamp tolerance Eac is defined by the tolerance of the power MISFET 9 with respect to the back electromotive force generated due to the inductive energy of the inductive load L during the transition of the power MISFET 9 from the on state to the off state.

[0083] The active clamp tolerance Eac is more specifically defined by the tolerance of the power MISFET9 with respect to the energy generated due to the clamp voltage VDSSCL. For example, the active clamp tolerance Eac is expressed by the formula Eac = (VL + VCLP) × ID × TAV using the limit voltage VL, the clamp-on voltage VCLP, the drain current ID, and the active clamp time TAV.

[0084] FIG. 5 is a cross-sectional perspective view of region V shown in FIG. 1. FIG. 6 is a cross-sectional perspective view with the source electrode 12 and the gate control wiring 17 removed from FIG. 5. FIG. 7 is a cross-sectional perspective view with the interlayer insulating layer 142 removed from FIG. 6, and is a cross-sectional perspective view showing a form including the channel structure according to the first exemplary embodiment.

[0085] FIG. 8 is a plan view of FIG. 7. FIG. 9 is an enlarged cross-sectional view of a region including the first trench gate structure 60 (first gate structure) and the second trench gate structure 70 (second gate structure) shown in FIG. 5. FIG. 10 is an enlarged cross-sectional view of the first trench gate structure 60 shown in FIG. 5. FIG. 11 is an enlarged cross-sectional view of the second trench gate structure 70 shown in FIG. 5.

[0086] Referring to FIGS. 5 to 11, in this form, the semiconductor layer 2 has a stacked structure including an n + -type semiconductor substrate 51 and an n-type epitaxial layer 52. The second main surface 4 of the semiconductor layer 2 is formed by the semiconductor substrate 51. The first main surface 3 of the semiconductor layer 2 is formed by the epitaxial layer 52. The side surfaces 5A to 5D of the semiconductor layer 2 are formed by the semiconductor substrate 51 and the epitaxial layer 52.

[0087] The epitaxial layer 52 has an n-type impurity concentration lower than the n-type impurity concentration of the semiconductor substrate 51. The n-type impurity concentration of the semiconductor substrate 51 may be 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. The n-type impurity concentration of the epitaxial layer 52 is 1×10 15 cm-3 The above 1×10 18 cm -3 may be below.

[0088] The epitaxial layer 52 has a thickness Tepi (Tepi < Tsub) less than the thickness Tsub of the semiconductor substrate 51. The thickness Tsub may be 50 μm or more and 450 μm or less. The thickness Tsub may be 50 μm or more and 150 μm or less, 150 μm or more and 250 μm or less, 250 μm or more and 350 μm or less, or 350 μm or more and 450 μm or less.

[0089] By reducing the thickness Tsub, the resistance value can be reduced. The thickness Tsub is adjusted by grinding. In this case, the second main surface 4 of the semiconductor layer 2 may be a ground surface having grinding marks.

[0090] The thickness Tepi of the epitaxial layer 52 is preferably 1 / 10 or less of the thickness Tsub. The thickness Tepi may be 5 μm or more and 20 μm or less. The thickness Tepi may be 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less. The thickness Tepi is preferably 5 μm or more and 15 μm or less.

[0091] The semiconductor substrate 51 is formed on the second main surface 4 side of the semiconductor layer 2 as a drain region 53. The epitaxial layer 52 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 as a drift region 54 (drain drift region). The bottom of the drift region 54 is formed by the boundary between the semiconductor substrate 51 and the epitaxial layer 52. Hereinafter, the epitaxial layer 52 is referred to as the drift region 54.

[0092] In the output region 6, a p-type body region 55 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. The body region 55 is a region that serves as the basis of the power MISFET 9. The p-type impurity concentration of the body region 55 is 1×10 16 cm -3 The above 1×10 18 cm -3 may be below.

[0093] The body region 55 is formed in the surface layer portion of the drift region 54. The bottom of the body region 55 is formed in the region on the first main surface 3 side with respect to the bottom of the drift region 54. The thickness of the body region 55 may be 0.5 μm or more and 2 μm or less. The thickness of the body region 55 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0094] The power MISFET 9 includes a first MISFET 56 (first transistor) and a second MISFET 57 (second transistor). The first MISFET 56 is electrically separated from the second MISFET 57 and is independently controlled. The second MISFET 57 is electrically separated from the first MISFET 56 and is independently controlled.

[0095] That is, the power MISFET 9 is configured to be driven when both the first MISFET 56 and the second MISFET 57 are in the on state (Full-ON control). Also, the power MISFET 9 is configured to be driven when the first MISFET 56 is in the on state while the second MISFET 57 is in the off state (first Half-ON control). Further, the power MISFET 9 is configured to be driven when the first MISFET 56 is in the off state while the second MISFET 57 is in the on state (second Half-ON control).

[0096] In the case of Full-ON control, the power MISFET 9 is driven with all current paths released. Therefore, the on-resistance in the semiconductor layer 2 relatively decreases. On the other hand, in the case of the first Half-ON control or the second Half-ON control, the power MISFET 9 is driven with some current paths blocked. Therefore, the on-resistance in the semiconductor layer 2 relatively increases.

[0097] The first MISFET 56 specifically includes a plurality of first FET (Field Effect Transistor) structures 58. The plurality of first FET structures 58 are arranged at intervals along a first direction X in a plan view, and each extends in a strip shape along a second direction Y. The plurality of first FET structures 58 are formed in a stripe shape as a whole in a plan view.

[0098] In FIGS. 5 to 8, a region on one end side of the first FET structure 58 is illustrated, and illustration of a region on the other end side of the first FET structure 58 is omitted. Note that the structure of the region on the other end side of the first FET structure 58 is substantially the same as the structure of the region on one end side of the first FET structure 58. Hereinafter, the structure of the region on one end side of the first FET structure 58 will be described as an example, and description of the structure of the region on the other end side of the first FET structure 58 will be omitted.

[0099] Each first FET structure 58 includes a first trench gate structure 60 in this form. The first width WT1 of the first trench gate structure 60 may be 0.5 μm or more and 5 μm or less. The first width WT1 is the width in a direction (first direction X) orthogonal to the direction (second direction Y) in which the first trench gate structure 60 extends.

[0100] Note that the first width WT1 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less. The first width WT1 is preferably 0.8 μm or more and 1.2 μm or less.

[0101] The first trench gate structure 60 penetrates the body region 55 and reaches the drift region 54. The first depth DT1 of the first trench gate structure 60 may be 1 μm or more and 10 μm or less. The first depth DT1 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The first depth DT1 is preferably 2 μm or more and 6 μm or less.

[0102] The first trench gate structure 60 includes a first sidewall 61 on one side, a second sidewall 62 on the other side, and a bottom wall 63 connecting the first sidewall 61 and the second sidewall 62. Hereinafter, the first sidewall 61, the second sidewall 62, and the bottom wall 63 may be collectively referred to as the "inner wall" or the "outer wall".

[0103] The absolute value of the angle (taper angle) formed between the first sidewall 61 and the first main surface 3 within the semiconductor layer 2 may be greater than 90° and less than or equal to 95° (for example, about 91°). The absolute value of the angle (taper angle) formed between the second sidewall 62 and the first main surface 3 within the semiconductor layer 2 may be greater than 90° and less than or equal to 95° (for example, about 91°). The first trench gate structure 60 may be formed in a tapered shape (taper shape) in which the first width WT1 narrows from the first main surface 3 side toward the bottom wall 63 side in a cross-sectional view.

[0104] The bottom wall 63 of the first trench gate structure 60 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54. The bottom wall 63 of the first trench gate structure 60 is formed in a convex curved shape (U-shaped) toward the bottom of the drift region 54.

[0105] The bottom wall 63 of the first trench gate structure 60 is located in a region on the first main surface 3 side with a first interval IT1 of 1 μm or more and 10 μm or less from the bottom of the drift region 54. The first interval IT1 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The first interval IT1 is preferably 1 μm or more and 5 μm or less.

[0106] In this form, the second MISFET 57 includes a plurality of second FET structures 68. The plurality of second FET structures 68 are arranged at intervals along the first direction X in a plan view and each extend in a strip shape along the second direction Y.

[0107] The plurality of second FET structures 68 extend along the same direction as the plurality of first FET structures 58. The plurality of second FET structures 68 are formed in a stripe shape as a whole in a plan view. In this form, the plurality of second FET structures 68 are alternately arranged with the plurality of first FET structures 58 in a manner of sandwiching one first FET structure 58.

[0108] In FIGS. 5 to 8, the region on one end side of the second FET structure 68 is illustrated, and the illustration of the region on the other end side of the second FET structure 68 is omitted. Note that the structure of the region on the other end side of the second FET structure 68 is substantially the same as the structure of the region on one end side of the second FET structure 68. Hereinafter, the structure of the region on one end side of the second FET structure 68 will be described as an example, and the description of the structure of the region on the other end side of the second FET structure 68 will be omitted.

[0109] Each second FET structure 68 includes a second trench gate structure 70 in this form. The second width WT2 of the second trench gate structure 70 may be 0.5 μm or more and 5 μm or less. The second width WT2 is the width in the direction (first direction X) orthogonal to the direction (second direction Y) in which the second trench gate structure 70 extends.

[0110] Note that the second width WT2 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less. The second width WT2 is preferably 0.8 μm or more and 1.2 μm or less.

[0111] The second width WT2 of the second trench gate structure 70 may be equal to or greater than the first width WT1 of the first trench gate structure 60 (WT1 ≤ WT2). The second width WT2 may be equal to or less than the first width WT1 (WT1 ≥ WT2). The second width WT2 is preferably equal to the first width WT1 (WT1 = WT2).

[0112] The second trench gate structure 70 penetrates the body region 55 and reaches the drift region 54. The second depth DT2 of the second trench gate structure 70 may be 1 μm or more and 10 μm or less. The second depth DT2 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The second depth DT2 is preferably 2 μm or more and 6 μm or less.

[0113] The second depth DT2 of the second trench gate structure 70 may be equal to or greater than the first depth DT1 of the first trench gate structure 60 (DT1 ≤ DT2). The second depth DT2 may be equal to or less than the first depth DT1 (DT1 ≥ DT2). Note that the second depth DT2 is preferably equal to the first depth DT1 (DT1 = DT2).

[0114] The second trench gate structure 70 includes a first side wall 71 on one side, a second side wall 72 on the other side, and a bottom wall 73 connecting the first side wall 71 and the second side wall 72. Hereinafter, the first side wall 71, the second side wall 72, and the bottom wall 73 may be collectively referred to as the "inner wall" or the "outer wall".

[0115] The absolute value of the angle (taper angle) formed between the first side wall 71 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and 95° or less (for example, about 91°). The absolute value of the angle (taper angle) formed between the second side wall 72 and the first main surface 3 in the semiconductor layer 2 may be more than 90° and 95° or less (for example, about 91°). The second trench gate structure 70 may be formed in a tapered shape (taper shape) in which the second width WT2 narrows from the first main surface 3 side toward the bottom wall 73 side in a cross-sectional view.

[0116] The bottom wall 73 of the second trench gate structure 70 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54. The bottom wall 73 of the second trench gate structure 70 is formed in a convexly curved (U-shaped) shape toward the bottom of the drift region 54.

[0117] The bottom wall 73 of the second trench gate structure 70 is located in the region on the side of the first main surface 3 with a second interval IT2 of 1 μm or more and 10 μm or less from the bottom of the drift region 54. The second interval IT2 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The second interval IT2 is preferably 1 μm or more and 5 μm or less.

[0118] Cell regions 75 are respectively partitioned in the regions between the plurality of first trench gate structures 60 and the plurality of second trench gate structures 70. The plurality of cell regions 75 are arranged at intervals along the first direction X in a plan view, and each extends in a strip shape along the second direction Y. The plurality of cell regions 75 extend along the same direction as the first trench gate structure 60 and the second trench gate structure 70. The plurality of cell regions 75 are formed in a stripe shape as a whole in a plan view.

[0119] From the outer wall of the first trench gate structure 60, a first depletion layer extends into the drift region 54. The first depletion layer extends from the outer wall of the first trench gate structure 60 in the direction along the first main surface 3 and in the normal direction Z. Similarly, from the outer wall of the second trench gate structure 70, a second depletion layer extends into the drift region 54. The second depletion layer extends from the outer wall of the second trench gate structure 70 in the direction along the first main surface 3 and in the normal direction Z.

[0120] The second trench gate structure 70 is arranged at an interval from the first trench gate structure 60 in such a manner that the second depletion layer overlaps the first depletion layer. That is, the second depletion layer overlaps the first depletion layer in the region on the side of the first main surface 3 with respect to the bottom wall 73 of the second trench gate structure 70 in the cell region 75. According to such a structure, it is possible to suppress the concentration of the electric field in the first trench gate structure 60 and the second trench gate structure 70, and thus it is possible to suppress the decrease in the breakdown voltage.

[0121] The second depletion layer preferably overlaps the first depletion layer in a region on the bottom side of the drift region 54 with respect to the bottom wall 73 of the second trench gate structure 70. According to such a structure, since the concentration of the electric field in the bottom wall 63 of the first trench gate structure 60 and the bottom wall 73 of the second trench gate structure 70 can be suppressed, a decrease in the breakdown voltage can be appropriately suppressed.

[0122] The pitch PS between the side walls of the first trench gate structure 60 and the second trench gate structure 70 may be 0.2 μm or more and 2 μm or less. The pitch PS is the distance in the direction (first direction X) orthogonal to the direction (second direction Y) in which the first trench gate structure 60 and the second trench gate structure 70 extend, between the first side wall 61 (second side wall 62) of the first trench gate structure 60 and the second side wall 72 (first side wall 71) of the second trench gate structure 70.

[0123] The pitch PS may be 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1.0 μm or less, 1.0 μm or more and 1.2 μm or less, 1.2 μm or more and 1.4 μm or less, 1.4 μm or more and 1.6 μm or less, 1.6 μm or more and 1.8 μm or less, or 1.8 μm or more and 2.0 μm or less. The pitch PS is preferably 0.3 μm or more and 1.5 μm or less.

[0124] The pitch PC between the central portions of the first trench gate structure 60 and the second trench gate structure 70 may be 1 μm or more and 7 μm or less. The pitch PC is the distance in the direction (first direction X) orthogonal to the direction (second direction Y) in which the first trench gate structure 60 and the second trench gate structure 70 extend, between the central portion of the first trench gate structure 60 and the central portion of the second trench gate structure 70.

[0125] Incidentally, the pitch PC may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, or 6 μm or more and 7 μm or less. The pitch PC is preferably 1 μm or more and 3 μm or less.

[0126] Referring to FIGS. 9 and 10, the first trench gate structure 60 more specifically includes a first gate trench 81, a first insulating layer 82, and a first electrode 83. The first gate trench 81 is formed by digging down from the first main surface 3 toward the second main surface 4.

[0127] The first gate trench 81 demarcates a first side wall 61, a second side wall 62, and a bottom wall 63 of the first trench gate structure 60. Hereinafter, the first side wall 61, the second side wall 62, and the bottom wall 63 of the first trench gate structure 60 will also be referred to as the first side wall 61, the second side wall 62, and the bottom wall 63 of the first gate trench 81.

[0128] The first insulating layer 82 is formed in a film shape along the inner wall of the first gate trench 81. The first insulating layer 82 demarcates a concave space within the first gate trench 81. The portion of the first insulating layer 82 that covers the bottom wall 63 of the first gate trench 81 is formed following the shape of the bottom wall 63 of the first gate trench 81. Thereby, the first insulating layer 82 demarcates a U-shaped space that is recessed in a U-shape within the first gate trench 81.

[0129] The first insulating layer 82 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0130] The first insulating layer 82 may have a stacked structure including a SiN layer and a SiO2 layer stacked in this order from the semiconductor layer 2 side. The first insulating layer 82 may have a stacked structure including a SiO2 layer and a SiN layer stacked in this order from the semiconductor layer 2 side. The first insulating layer 82 may have a single-layer structure composed of a SiO2 layer or a SiN layer. In this form, the first insulating layer 82 has a single-layer structure composed of a SiO2 layer.

[0131] The first insulating layer 82 includes a first bottom-side insulating layer 84 and a first opening-side insulating layer 85 formed in this order from the bottom wall 63 side of the first gate trench 81 toward the first main surface 3 side.

[0132] The first bottom-side insulating layer 84 covers the inner wall on the bottom wall 63 side of the first gate trench 81. More specifically, the first bottom-side insulating layer 84 covers the inner wall on the bottom wall 63 side of the first gate trench 81 with respect to the bottom of the body region 55. The first bottom-side insulating layer 84 demarcates a U-shaped space on the bottom wall 63 side of the first gate trench 81. The first bottom-side insulating layer 84 has a smooth inner wall surface that demarcates the U-shaped space. The first bottom-side insulating layer 84 is in contact with the drift region 54. A part of the first bottom-side insulating layer 84 may be in contact with the body region 55.

[0133] The first opening-side insulating layer 85 covers the inner wall on the opening side of the first gate trench 81. More specifically, the first opening-side insulating layer 85 covers the first side wall 61 and the second side wall 62 of the first gate trench 81 in the region on the opening side of the first gate trench 81 with respect to the bottom of the body region 55. The first opening-side insulating layer 85 is in contact with the body region 55. A part of the first opening-side insulating layer 85 may be in contact with the drift region 54.

[0134] The first bottom-side insulating layer 84 has a first thickness T1. The first opening-side insulating layer 85 has a second thickness T2 (T2 < T1) less than the first thickness T1. The first thickness T1 is the thickness along the normal direction of the inner wall of the first gate trench 81 in the first bottom-side insulating layer 84. The second thickness T2 is the thickness along the normal direction of the inner wall of the first gate trench 81 in the first opening-side insulating layer 85.

[0135] Incidentally, the first ratio T1 / WT1 of the first thickness T1 to the first width WT1 of the first gate trench 81 may be 0.1 or more and 0.4 or less. Also, the first ratio T1 / WT1 may be 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less. The first ratio T1 / WT1 is preferably 0.25 or more and 0.35 or less.

[0136] Incidentally, the first thickness T1 of the first bottom-side insulating layer 84 may be 1500 Å or more and 4000 Å or less. The first thickness T1 may be 1500 Å or more and 2000 Å or less, 2000 Å or more and 2500 Å or less, 2500 Å or more and 3000 Å or less, 3000 Å or more and 3500 Å or less, or 3500 Å or more and 4000 Å or less. The first thickness T1 is preferably 1800 Å or more and 3500 Å or less.

[0137] The first thickness T1 may be adjusted to 4000 Å or more and 12000 Å or less according to the first width WT1 of the first gate trench 81. The first thickness T1 may be 4000 Å or more and 5000 Å or less, 5000 Å or more and 6000 Å or less, 6000 Å or more and 7000 Å or less, 7000 Å or more and 8000 Å or less, 8000 Å or more and 9000 Å or less, 9000 Å or more and 10000 Å or less, 10000 Å or more and 11000 Å or less, or 11000 Å or more and 12000 Å or less. In this case, the breakdown voltage of the semiconductor device 1 can be increased by thickening the first bottom-side insulating layer 84.

[0138] The second thickness T2 of the first opening-side insulating layer 85 may be 1 / 100 or more and 1 / 10 or less of the first thickness T1 of the first bottom-side insulating layer 84. The second thickness T2 may be 100 Å or more and 500 Å or less. The second thickness T2 may be 100 Å or more and 200 Å or less, 200 Å or more and 300 Å or less, 300 Å or more and 400 Å or less, or 400 Å or more and 500 Å or less. The second thickness T2 is preferably 200 Å or more and 400 Å or less.

[0139] The first bottom-side insulating layer 84 is formed in such a manner that the first thickness T1 decreases from the portion covering the first sidewall 61 and the second sidewall 62 of the first gate trench 81 toward the portion covering the bottom wall 63 of the first gate trench 81.

[0140] The thickness of the portion of the first bottom-side insulating layer 84 that covers the bottom wall 63 of the first gate trench 81 is smaller than the thickness of the portion of the first bottom-side insulating layer 84 that covers the first sidewall 61 and the second sidewall 62 of the first gate trench 81. The opening width on the bottom wall side of the U-shaped space partitioned by the first bottom-side insulating layer 84 is expanded by the amount of decrease in the first thickness T1. As a result, the taper of the U-shaped space is suppressed. Such a U-shaped space is formed, for example, by an etching method (e.g., a wet etching method) with respect to the inner wall of the first bottom-side insulating layer 84.

[0141] The first electrode 83 is embedded in the first gate trench 81 with the first insulating layer 82 interposed therebetween. A first gate control signal (first control signal) including an on signal Von and an off signal Voff is applied to the first electrode 83. In this form, the first electrode 83 has an insulated-separated split electrode structure including a first bottom-side electrode 86, a first opening-side electrode 87, and a first intermediate insulating layer 88.

[0142] The first bottom-side electrode 86 is embedded on the bottom wall 63 side of the first gate trench 81 with the first insulating layer 82 interposed therebetween. More specifically, the first bottom-side electrode 86 is embedded on the bottom wall 63 side of the first gate trench 81 with the first bottom-side insulating layer 84 interposed therebetween. The first bottom-side electrode 86 faces the drift region 54 with the first bottom-side insulating layer 84 interposed therebetween. A part of the first bottom-side electrode 86 may face the body region 55 with the first bottom-side insulating layer 84 interposed therebetween.

[0143] The first bottom-side electrode 86 includes a first upper end portion 86A, a first lower end portion 86B, and a first wall portion 86C. The first upper end portion 86A is located on the opening side of the first gate trench 81. The first lower end portion 86B is located on the bottom wall 63 side of the first gate trench 81. The first wall portion 86C connects the first upper end portion 86A and the first lower end portion 86B and extends in a wall shape along the inner wall of the first gate trench 81.

[0144] The first upper end portion 86A is exposed from the first bottom-side insulating layer 84. The first upper end portion 86A protrudes toward the first main surface 3 with respect to the first bottom-side insulating layer 84. As a result, the first bottom-side electrode 86 partitions a recess having an inversely concave shape in a cross-sectional view between the first bottom-side insulating layer 84 and the first opening-side insulating layer 85 on the opening side of the first gate trench 81. The width of the first upper end portion 86A is less than the width of the first wall portion 86C.

[0145] The first lower end portion 86B is formed in a convexly curved shape toward the bottom wall 63 of the first gate trench 81. More specifically, the first lower end portion 86B is formed following the bottom wall of the U-shaped space partitioned by the first bottom-side insulating layer 84 and is formed in a smooth convexly curved shape toward the bottom wall 63 of the first gate trench 81.

[0146] According to such a structure, local electric field concentration on the first bottom-side electrode 86 can be suppressed, so that a decrease in breakdown voltage can be suppressed. In particular, by embedding the first bottom-side electrode 86 in the expanded U-shaped space of the first bottom-side insulating layer 84, it is possible to appropriately suppress the first bottom-side electrode 86 from becoming tapered from the first upper end portion 86A toward the first lower end portion 86B. Thereby, local electric field concentration on the first lower end portion 86B of the first bottom-side electrode 86 can be appropriately suppressed.

[0147] The first bottom-side electrode 86 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy. In this form, the first bottom-side electrode 86 contains conductive polysilicon. The conductive polysilicon may contain an n-type impurity or a p-type impurity. Note that the conductive polysilicon preferably contains an n-type impurity.

[0148] The first opening-side electrode 87 is embedded on the opening side of the first gate trench 81 with the first insulating layer 82 interposed therebetween. More specifically, the first opening-side electrode 87 is embedded in a reverse concave-shaped recess partitioned on the opening side of the first gate trench 81 with the first opening-side insulating layer 85 interposed therebetween. The first opening-side electrode 87 faces the body region 55 with the first opening-side insulating layer 85 interposed therebetween. A part of the first opening-side electrode 87 may face the drift region 54 with the first opening-side insulating layer 85 interposed therebetween.

[0149] The first opening-side electrode 87 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy. The first opening-side electrode 87 preferably contains the same type of conductive material as the first bottom-side electrode 86. In this form, the first opening-side electrode 87 contains conductive polysilicon. The conductive polysilicon may contain an n-type impurity or a p-type impurity. The conductive polysilicon preferably contains an n-type impurity.

[0150] The first intermediate insulating layer 88 is interposed between the first bottom-side electrode 86 and the first opening-side electrode 87 and electrically insulates the first bottom-side electrode 86 and the first opening-side electrode 87. More specifically, the first intermediate insulating layer 88 covers the first bottom-side electrode 86 exposed from the first bottom-side insulating layer 84 in the region between the first bottom-side electrode 86 and the first opening-side electrode 87. The first intermediate insulating layer 88 covers the first upper end portion 86A (more specifically, the protruding portion) of the first bottom-side electrode 86. The first intermediate insulating layer 88 is continuous with the first insulating layer 82 (the first bottom-side insulating layer 84).

[0151] The first intermediate insulating layer 88 has a third thickness T3. The third thickness T3 is less than the first thickness T1 of the first bottom-side insulating layer 84 (T3 < T1). The third thickness T3 may be not less than 1 / 100 and not more than 1 / 10 of the first thickness T1. The third thickness T3 may be not less than 100 Å and not more than 500 Å. The third thickness T3 may be not less than 100 Å and not more than 200 Å, not less than 200 Å and not more than 300 Å, not less than 300 Å and not more than 400 Å, or not less than 400 Å and not more than 500 Å. Preferably, the third thickness T3 is not less than 200 Å and not more than 400 Å.

[0152] The first intermediate insulating layer 88 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3). In this form, the first intermediate insulating layer 88 has a single-layer structure composed of an SiO2 layer.

[0153] In the first opening-side electrode 87, the exposed portion exposed from the first gate trench 81 is, in this form, located on the bottom-wall 63 side of the first gate trench 81 with respect to the first main surface 3. The exposed portion of the first opening-side electrode 87 is formed in a curved shape toward the bottom wall 63 of the first gate trench 81.

[0154] The exposed portion of the first opening-side electrode 87 is covered by a first cap insulating layer 89 formed in a film shape. The first cap insulating layer 89 is continuous with the first insulating layer 82 (first opening-side insulating layer 85) within the first gate trench 81. The first cap insulating layer 89 may contain silicon oxide (SiO2).

[0155] Each first FET structure 58 further includes a p-type first channel region 91 (first channel). The first channel region 91 is formed in a region of the body region 55 that faces the first electrode 83 (first opening-side electrode 87) with the first insulating layer 82 (first opening-side insulating layer 85) interposed therebetween.

[0156] The first channel region 91 is formed along the first side wall 61 or the second side wall 62 of the first trench gate structure 60, or along both the first side wall 61 and the second side wall 62. In this form, the first channel region 91 is formed along the first side wall 61 and the second side wall 62 of the first trench gate structure 60.

[0157] Each first FET structure 58 further includes an n-type first source region 92 formed in the surface layer portion of the body region 55. + The first source region 92 defines the first channel region 91 within the body region 55 between it and the drift region 54. The n-type impurity concentration of the first source region 92 exceeds that of the drift region 54. The n-type impurity concentration of the first source region 92 may be 1×10 19 cm -3 or more and 1×10 21 cm -3 or less.

[0158] In this form, each first FET structure 58 includes a plurality of first source regions 92. The plurality of first source regions 92 are formed at intervals along the first trench gate structure 60 in the surface layer portion of the body region 55. More specifically, the plurality of first source regions 92 are formed along the first side wall 61 or the second side wall 62 of the first trench gate structure 60, or along both the first side wall 61 and the second side wall 62. In this form, the plurality of first source regions 92 are formed at intervals along the first side wall 61 and the second side wall 62 of the first trench gate structure 60.

[0159] The bottoms of the plurality of first source regions 92 are located in the region on the first main surface 3 side with respect to the bottom of the body region 55. Thereby, the plurality of first source regions 92 face the first electrode 83 (first opening side electrode 87) with the first insulating layer 82 (first opening side insulating layer 85) interposed therebetween. In this way, the first channel region 91 of the first MISFET 56 is formed in the region of the body region 55 sandwiched between the plurality of first source regions 92 and the drift region 54.

[0160] Each first FET structure 58 further includes a p-type first contact region 93 formed in the surface layer portion of the body region 55. The p-type impurity concentration of the first contact region 93 exceeds the p-type impurity concentration of the body region 55. The p-type impurity concentration of the first contact region 93 may be, for example, 1×10 + cm 19 or more and 1×10 -3 cm 21 or less. -3

[0161] In this form, each first FET structure 58 includes a plurality of first contact regions 93. The plurality of first contact regions 93 are formed at intervals along the first trench gate structure 60 in the surface layer portion of the body region 55. More specifically, the plurality of first contact regions 93 are formed along the first side wall 61 or the second side wall 62 of the first trench gate structure 60, or along the first side wall 61 and the second side wall 62.

[0162] In this form, the plurality of first contact regions 93 are formed at intervals along the first side wall 61 and the second side wall 62 of the first trench gate structure 60. More specifically, the plurality of first contact regions 93 are formed in the surface layer portion of the body region 55 in an alternating arrangement with respect to the plurality of first source regions 92. The bottom portions of the plurality of first contact regions 93 are located in a region on the first main surface 3 side with respect to the bottom portion of the body region 55.

[0163] Referring to FIGS. 9 and 11, the second trench gate structure 70 includes a second gate trench 101, a second insulating layer 102, and a second electrode 103. The second gate trench 101 is formed by digging down the first main surface 3 toward the second main surface 4 side.

[0164] The second gate trench 101 demarcates a first side wall 71, a second side wall 72, and a bottom wall 73 of the second trench gate structure 70. Hereinafter, the first side wall 71, the second side wall 72, and the bottom wall 73 of the second trench gate structure 70 are also referred to as the first side wall 71, the second side wall 72, and the bottom wall 73 of the second gate trench 101.

[0165] The second insulating layer 102 is formed in a film shape along the inner wall of the second gate trench 101. The second insulating layer 102 partitions a concave space in the second gate trench 101. The portion of the second insulating layer 102 that covers the bottom wall 73 of the second gate trench 101 is formed following the bottom wall 73 of the second gate trench 101. Thereby, the second insulating layer 102 partitions a U-shaped space that is recessed in a U shape in the second gate trench 101.

[0166] The second insulating layer 102 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0167] The second insulating layer 102 may have a stacked structure including a SiN layer and a SiO2 layer stacked in this order from the semiconductor layer 2 side. The second insulating layer 102 may have a stacked structure including a SiO2 layer and a SiN layer stacked in this order from the semiconductor layer 2 side. The second insulating layer 102 may have a single-layer structure composed of a SiO2 layer or a SiN layer. In this form, the second insulating layer 102 has a single-layer structure composed of a SiO2 layer.

[0168] The second insulating layer 102 includes a second bottom-side insulating layer 104 and a second opening-side insulating layer 105 formed in this order from the bottom wall 73 side of the second gate trench 101 toward the first main surface 3 side.

[0169] The second bottom-side insulating layer 104 covers the inner wall on the bottom wall 73 side of the second gate trench 101. More specifically, the second bottom-side insulating layer 104 covers the inner wall on the bottom wall 73 side of the second gate trench 101 with respect to the bottom of the body region 55. The second bottom-side insulating layer 104 partitions a U-shaped space on the bottom wall 73 side of the second gate trench 101. The second bottom-side insulating layer 104 has a smooth inner wall surface that partitions the U-shaped space. The second bottom-side insulating layer 104 is in contact with the drift region 54. A part of the second bottom-side insulating layer 104 may be in contact with the body region 55.

[0170] The second opening-side insulating layer 105 covers the inner wall of the opening side of the second gate trench 101. More specifically, the second opening-side insulating layer 105 covers the first side wall 71 and the second side wall 72 of the second gate trench 101 in the region of the opening side of the second gate trench 101 with respect to the bottom of the body region 55. The second opening-side insulating layer 105 is in contact with the body region 55. A part of the second opening-side insulating layer 105 may be in contact with the drift region 54.

[0171] The second bottom-side insulating layer 104 has a fourth thickness T4. The second opening-side insulating layer 105 has a fifth thickness T5 (T5 < T4) less than the fourth thickness T4. The fourth thickness T4 is the thickness along the normal direction of the inner wall of the second gate trench 101 in the second bottom-side insulating layer 104. The fifth thickness T5 is the thickness along the normal direction of the inner wall of the second gate trench 101 in the second opening-side insulating layer 105.

[0172] The second ratio T4 / WT2 of the fourth thickness T4 to the second width WT2 of the second gate trench 101 may be 0.1 or more and 0.4 or less. For example, the second ratio T4 / WT2 may be 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less, or 0.35 or more and 0.4 or less. The second ratio T4 / WT2 is preferably 0.25 or more and 0.35 or less.

[0173] The second ratio T4 / WT2 may be less than or equal to the first ratio T1 / WT1 (T4 / WT2 ≤ T1 / WT1). The second ratio T4 / WT2 may be greater than or equal to the first ratio T1 / WT1 (T4 / WT2 ≥ T1 / WT1). Also, the second ratio T4 / WT2 may be equal to the first ratio T1 / WT1 (T4 / WT2 = T1 / WT1).

[0174] The fourth thickness T4 of the second bottom-side insulating layer 104 may be 1500 Å or more and 4000 Å or less. The fourth thickness T4 may be 1500 Å or more and 2000 Å or less, 2000 Å or more and 2500 Å or less, 2500 Å or more and 3000 Å or less, 3000 Å or more and 3500 Å or less, or 3500 Å or more and 4000 Å or less. The fourth thickness T4 is preferably 1800 Å or more and 3500 Å or less.

[0175] The fourth thickness T4 may be 4000 Å or more and 12000 Å or less according to the second width WT2 of the second gate trench 101. The fourth thickness T4 may be 4000 Å or more and 5000 Å or less, 5000 Å or more and 6000 Å or less, 6000 Å or more and 7000 Å or less, 7000 Å or more and 8000 Å or less, 8000 Å or more and 9000 Å or less, 9000 Å or more and 10000 Å or less, 10000 Å or more and 11000 Å or less, or 11000 Å or more and 12000 Å or less. In this case, the breakdown voltage of the semiconductor device 1 can be increased by thickening the second bottom-side insulating layer 104.

[0176] The fourth thickness T4 may be less than or equal to the first thickness T1 (T4 ≦ T1). The fourth thickness T4 may be greater than or equal to the first thickness T1 (T4 ≧ T1). The fourth thickness T4 may be equal to the first thickness T1 (T4 = T1).

[0177] The fifth thickness T5 of the second opening-side insulating layer 105 is less than the fourth thickness T4 of the second bottom-side insulating layer 104 (T5 < T4). The fifth thickness T5 may be 1 / 100 or more and 1 / 10 or less of the fourth thickness T4. It may be 100 Å or more and 500 Å or less. The fifth thickness T5 may be 100 Å or more and 200 Å or less, 200 Å or more and 300 Å or less, 300 Å or more and 400 Å or less, or 400 Å or more and 500 Å or less. The fifth thickness T5 is preferably 200 Å or more and 400 Å or less.

[0178] The fifth thickness T5 may be less than or equal to the second thickness T2 (T5 ≦ T2). The fifth thickness T5 may be greater than or equal to the second thickness T2 (T5 ≧ T2). The fifth thickness T5 may be equal to the second thickness T2 (T5 = T2).

[0179] The second bottom-side insulating layer 104 is formed in such a manner that the fourth thickness T4 decreases from the portion covering the first sidewall 71 and the second sidewall 72 of the second gate trench 101 toward the portion covering the bottom wall 73 of the second gate trench 101.

[0180] The thickness of the portion of the second bottom-side insulating layer 104 that covers the bottom wall 73 of the second gate trench 101 is smaller than the thickness of the portion of the second bottom-side insulating layer 104 that covers the first sidewall 71 and the second sidewall 72 of the second gate trench 101. The opening width on the bottom wall side of the U-shaped space partitioned by the second bottom-side insulating layer 104 is expanded by the amount of decrease in the fourth thickness T4. As a result, the tapering of the U-shaped space is suppressed. Such a U-shaped space is formed, for example, by an etching method (such as a wet etching method) for the inner wall of the second bottom-side insulating layer 104.

[0181] The second electrode 103 is embedded in the second gate trench 101 with the second insulating layer 102 interposed therebetween. A predetermined second gate control signal (second control signal) including an on signal Von and an off signal Voff is applied to the second electrode 103.

[0182] In this form, the second electrode 103 has an insulating separation type split electrode structure including a second bottom-side electrode 106, a second opening-side electrode 107, and a second intermediate insulating layer 108. In this form, the second bottom-side electrode 106 is electrically connected to the first bottom-side electrode 86. The second opening-side electrode 107 is electrically insulated from the first opening-side electrode 87.

[0183] The second bottom-side electrode 106 is embedded on the bottom wall 73 side of the second gate trench 101 with the second insulating layer 102 interposed therebetween. More specifically, the second bottom-side electrode 106 is embedded on the bottom wall 73 side of the second gate trench 101 with the second bottom-side insulating layer 104 interposed therebetween. The second bottom-side electrode 106 faces the drift region 54 with the second bottom-side insulating layer 104 interposed therebetween. A part of the second bottom-side electrode 106 may face the body region 55 with the second bottom-side insulating layer 104 interposed therebetween.

[0184] The second bottom-side electrode 106 includes a second upper end portion 106A, a second lower end portion 106B, and a second wall portion 106C. The second upper end portion 106A is located on the opening side of the second gate trench 101. The second lower end portion 106B is located on the bottom wall 73 side of the second gate trench 101. The second wall portion 106C connects the second upper end portion 106A and the second lower end portion 106B and extends in a wall shape along the inner wall of the second gate trench 101.

[0185] The second upper end portion 106A is exposed from the second bottom-side insulating layer 104. The second upper end portion 106A protrudes toward the first main surface 3 side with respect to the second bottom-side insulating layer 104. Thereby, the second bottom-side electrode 106 partitions a recess having a reverse concave shape in a cross-sectional view between the second bottom-side insulating layer 104 and the second opening-side insulating layer 105 on the opening side of the second gate trench 101. The width of the second upper end portion 106A is less than the width of the second wall portion 106C.

[0186] The second lower end portion 106B is formed in a convex curved shape toward the bottom wall 73 of the second gate trench 101. More specifically, the second lower end portion 106B is formed following the bottom wall of the U-shaped space partitioned by the second bottom-side insulating layer 104 and is formed in a smooth convex curved shape toward the bottom wall 73 of the second gate trench 101.

[0187] According to such a structure, local electric field concentration on the second bottom-side electrode 106 can be suppressed, so that a decrease in the breakdown voltage can be suppressed. In particular, by embedding the second bottom-side electrode 106 in the expanded U-shaped space of the second bottom-side insulating layer 104, it is possible to appropriately suppress the second bottom-side electrode 106 from becoming a tapered shape from the second upper end portion 106A toward the second lower end portion 106B. Thereby, local electric field concentration on the second lower end portion 106B of the second bottom-side electrode 106 can be appropriately suppressed.

[0188] The second bottom-side electrode 106 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy. In this form, the second bottom-side electrode 106 contains conductive polysilicon. The conductive polysilicon may contain an n-type impurity or a p-type impurity. The conductive polysilicon preferably contains an n-type impurity.

[0189] The second opening-side electrode 107 is embedded on the opening side of the second gate trench 101 with the second insulating layer 102 interposed therebetween. More specifically, the second opening-side electrode 107 is embedded in a reverse concave-shaped recess partitioned on the opening side of the second gate trench 101 with the second opening-side insulating layer 105 interposed therebetween. The second opening-side electrode 107 faces the body region 55 with the second opening-side insulating layer 105 interposed therebetween. A part of the second opening-side electrode 107 may face the drift region 54 with the second opening-side insulating layer 105 interposed therebetween.

[0190] The second opening-side electrode 107 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy. The second opening-side electrode 107 preferably contains the same type of conductive material as the second bottom-side electrode 106. In this form, the second opening-side electrode 107 contains conductive polysilicon. The conductive polysilicon may contain an n-type impurity or a p-type impurity. The conductive polysilicon preferably contains an n-type impurity.

[0191] The second intermediate insulating layer 108 is interposed between the second bottom-side electrode 106 and the second opening-side electrode 107, and electrically insulates the second bottom-side electrode 106 and the second opening-side electrode 107. More specifically, the second intermediate insulating layer 108 covers the second bottom-side electrode 106 exposed from the second bottom-side insulating layer 104 in the region between the second bottom-side electrode 106 and the second opening-side electrode 107. The second intermediate insulating layer 108 covers the second upper end portion 106A (more specifically, the protruding portion) of the second bottom-side electrode 106. The second intermediate insulating layer 108 is continuous with the second insulating layer 102 (the second bottom-side insulating layer 104).

[0192] The second intermediate insulating layer 108 has a sixth thickness T6. The sixth thickness T6 is less than the fourth thickness T4 of the second bottom insulating layer 104 (T6 < T4). The sixth thickness T6 may be 1 / 100 or more and 1 / 10 or less of the fourth thickness T4. The sixth thickness T6 may be 100 Å or more and 500 Å or less. The sixth thickness T6 may be 100 Å or more and 200 Å or less, 200 Å or more and 300 Å or less, 300 Å or more and 400 Å or less, or 400 Å or more and 500 Å or less. Preferably, the sixth thickness T6 is 200 Å or more and 400 Å or less.

[0193] The sixth thickness T6 may be less than or equal to the third thickness T3 (T6 ≤ T3). The sixth thickness T6 may be greater than or equal to the third thickness T3 (T6 ≥ T3). The sixth thickness T6 may be equal to the third thickness T3 (T6 = T3).

[0194] The second intermediate insulating layer 108 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3). In this form, the second intermediate insulating layer 108 has a single-layer structure composed of an SiO2 layer.

[0195] In the second opening-side electrode 107, the exposed portion exposed from the second gate trench 101 is located on the bottom wall 73 side of the second gate trench 101 with respect to the first main surface 3 in this form. The exposed portion of the second opening-side electrode 107 is formed in a curved shape toward the bottom wall 73 of the second gate trench 101.

[0196] The exposed portion of the second opening-side electrode 107 is covered by a second cap insulating layer 109 formed in a film shape. The second cap insulating layer 109 is continuous with the second insulating layer 102 (second opening-side insulating layer 105) in the second gate trench 101. The second cap insulating layer 109 may contain silicon oxide (SiO2).

[0197] Each second FET structure 68 further includes a p-type second channel region 111 (second channel). More specifically, the second channel region 111 is formed in a region of the body region 55 that faces the second electrode 103 (second opening side electrode 107) with the second insulating layer 102 (second opening side insulating layer 105) interposed therebetween.

[0198] More specifically, the second channel region 111 is formed along the first sidewall 71 or the second sidewall 72 of the second trench gate structure 70, or along both the first sidewall 71 and the second sidewall 72. In this form, the second channel region 111 is formed along the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70.

[0199] Each second FET structure 68 further includes an n + -type second source region 112 formed in the surface layer portion of the body region 55. The second source region 112 defines the second channel region 111 with the drift region 54 within the body region 55.

[0200] The n-type impurity concentration of the second source region 112 exceeds the n-type impurity concentration of the drift region 54. The n-type impurity concentration of the second source region 112 may be 1×10 19 cm -3 or more and 1×10 21 cm -3 or less. Preferably, the n-type impurity concentration of the second source region 112 is equal to the n-type impurity concentration of the first source region 92.

[0201] In this form, each second FET structure 68 includes a plurality of second source regions 112. The plurality of second source regions 112 are formed at intervals along the second trench gate structure 70 in the surface layer portion of the body region 55. More specifically, the plurality of second source regions 112 are formed along the first sidewall 71 or the second sidewall 72 of the second trench gate structure 70, or along both the first sidewall 71 and the second sidewall 72. In this form, the plurality of second source regions 112 are formed at intervals along the first sidewall 71 and the second sidewall 72 of the second trench gate structure 70.

[0202] In this form, each second source region 112 faces each first source region 92 along the first direction X. Also, each second source region 112 is integrated with each first source region 92. In FIGS. 7 and 8, the first source region 92 and the second source region 112 are shown separately by a boundary line, but there is actually no distinct boundary line in the region between the first source region 92 and the second source region 112.

[0203] Each second source region 112 may be formed by being displaced in the second direction Y from each first source region 92 so as not to face a part or all of each first source region 92 along the first direction X. That is, the plurality of first source regions 92 and the plurality of second source regions 112 may be arranged in a staggered pattern in a plan view.

[0204] The bottoms of the plurality of second source regions 112 are located in the region on the first main surface 3 side with respect to the bottom of the body region 55. As a result, the plurality of second source regions 112 face the second electrode 103 (second opening side electrode 107) with the second insulating layer 102 (second opening side insulating layer 105) interposed therebetween. In this way, the second channel region 111 of the second MISFET 57 is formed in the region of the body region 55 sandwiched between the plurality of second source regions 112 and the drift region 54.

[0205] Each second FET structure 68 further includes a p-type second contact region 113 formed in the surface layer portion of the body region 55. The p-type impurity concentration of the second contact region 113 exceeds the p-type impurity concentration of the body region 55. The p-type impurity concentration of the second contact region 113 may be 1×10 + cm 19 cm -3 or more and 1×10 21 cm -3 or less. The p-type impurity concentration of the second contact region 113 is preferably equal to the p-type impurity concentration of the first contact region 93.

[0206] In this form, each second FET structure 68 includes a plurality of second contact regions 113. The plurality of second contact regions 113 are formed at intervals along the second trench gate structure 70 in the surface layer portion of the body region 55. More specifically, the plurality of second contact regions 113 are formed along the first side wall 71 or the second side wall 72 of the second trench gate structure 70, or along both the first side wall 71 and the second side wall 72. The bottom portions of the plurality of second contact regions 113 are located in a region on the first main surface 3 side with respect to the bottom portion of the body region 55.

[0207] In this form, the plurality of second contact regions 113 are formed at intervals along the first side wall 71 and the second side wall 72 of the second trench gate structure 70. More specifically, the plurality of second contact regions 113 are formed in the surface layer portion of the body region 55 in an alternating arrangement with respect to the plurality of second source regions 112.

[0208] Referring to FIGS. 7 and 8, in this form, each second contact region 113 faces each first contact region 93 along the first direction X. Each second contact region 113 is integrated with each first contact region 93.

[0209] In FIG. 7, to distinguish the first contact region 93 and the second contact region 113 from the first source region 92 and the second source region 112, the first contact region 93 and the second contact region 113 are collectively indicated by the symbol "p" + In FIG. 8, the first contact region 93 and the second contact region 113 are shown separately by a boundary line, but there is actually no distinct boundary line in the region between the first contact region 93 and the second contact region 113.

[0210] Each second contact region 113 may be formed offset in the second direction Y from each first contact region 93 so as not to face a part or all of each first contact region 93 along the first direction X. That is, the plurality of first contact regions 93 and the plurality of second contact regions 113 may be arranged in a staggered pattern in a plan view.

[0211] Referring to FIGS. 7 and 8, in this embodiment, the body region 55 is exposed from the region between one end of the first trench gate structure 60 and one end of the second trench gate structure 70 on the first main surface 3 of the semiconductor layer 2. The first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 are not formed in the region sandwiched between one end of the first trench gate structure 60 and one end of the second trench gate structure 70 on the first main surface 3.

[0212] Similarly, although not shown, in this embodiment, the body region 55 is exposed from the region between the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70 on the first main surface 3 of the semiconductor layer 2. The first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 are not formed in the region sandwiched between the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70.

[0213] Referring to FIGS. 5 to 8, a plurality (here, two) of trench contact structures 120 are formed on the first main surface 3 of the semiconductor layer 2. The plurality of trench contact structures 120 includes a trench contact structure 120 on one side and a trench contact structure 120 on the other side.

[0214] The trench contact structure 120 on one side is located in the region on the side of one end of the first trench gate structure 60 and one end of the second trench gate structure 70. The trench contact structure 120 on the other side is located in the region on the side of the other end of the first trench gate structure 60 and the other end of the second trench gate structure 70.

[0215] The trench contact structure 120 on the other side has substantially the same structure as the trench contact structure 120 on one side. Hereinafter, the structure on the side of the trench contact structure 120 on one side will be described as an example, and the specific description of the structure on the side of the trench contact structure 120 on the other side will be omitted.

[0216] The trench contact structure 120 is connected to one end of the first trench gate structure 60 and one end of the second trench gate structure 70. In this form, the trench contact structure 120 extends in a strip shape along the first direction X in a plan view.

[0217] The width WTC of the trench contact structure 120 may be 0.5 μm or more and 5 μm or less. The width WTC is the width in the direction (the second direction Y) orthogonal to the direction (the first direction X) in which the trench contact structure 120 extends.

[0218] The width WTC may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, or 4.5 μm or more and 5 μm or less. The width WTC is preferably 0.8 μm or more and 1.2 μm or less.

[0219] The width WTC is preferably equal to the first width WT1 of the first trench gate structure 60 (WTC = WT1). The width WTC is preferably equal to the second width WT2 of the second trench gate structure 70 (WTC = WT2).

[0220] The trench contact structure 120 penetrates the body region 55 and reaches the drift region 54. The depth DTC of the trench contact structure 120 may be 1 μm or more and 10 μm or less. The depth DTC may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The depth DTC is preferably 2 μm or more and 6 μm or less.

[0221] The depth DTC is preferably equal to the first depth DT1 of the first trench gate structure 60 (DTC = DT1). The depth DTC is preferably equal to the second depth DT2 of the second trench gate structure 70 (DTC = DT2).

[0222] The trench contact structure 120 includes a first sidewall 121 on one side, a second sidewall 122 on the other side, and a bottom wall 123 connecting the first sidewall 121 and the second sidewall 122. Hereinafter, the first sidewall 121, the second sidewall 122, and the bottom wall 123 may be collectively referred to as the "inner wall". The first sidewall 121 is a connection surface connected to the first trench gate structure 60 and the second trench gate structure 70.

[0223] The first sidewall 121, the second sidewall 122, and the bottom wall 123 are located within the drift region 54. The first sidewall 121 and the second sidewall 122 extend along the normal direction Z. The first sidewall 121 and the second sidewall 122 may be formed perpendicular to the first main surface 3.

[0224] The absolute value of the angle (taper angle) formed between the first sidewall 121 and the first main surface 3 within the semiconductor layer 2 may be greater than 90° and less than or equal to 95° (for example, about 91°). The absolute value of the angle (taper angle) formed between the second sidewall 122 and the first main surface 3 within the semiconductor layer 2 may be greater than 90° and less than or equal to 95° (for example, about 91°). The trench contact structure 120 may be formed in a tapered shape (taper shape) in which the width WTC narrows from the first main surface 3 side to the bottom wall 123 side in a cross-sectional view.

[0225] The bottom wall 123 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54. The bottom wall 123 is formed in a convexly curved shape toward the bottom of the drift region 54. The bottom wall 123 is located in a region on the first main surface 3 side with a gap ITC of 1 μm or more and 10 μm or less with respect to the bottom of the drift region 54. The gap ITC may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The gap ITC is preferably 1 μm or more and 5 μm or less.

[0226] The interval ITC is preferably equal to the first interval IT1 of the first trench gate structure 60 (ITC = IT1). The interval ITC is preferably equal to the second interval IT2 of the second trench gate structure 70 (ITC = IT2).

[0227] The trench contact structure 120 includes a contact trench 131, a contact insulating layer 132, and a contact electrode 133. The contact trench 131 is formed by digging down the first main surface 3 of the semiconductor layer 2 toward the second main surface 4.

[0228] The contact trench 131 demarcates the first sidewall 121, the second sidewall 122, and the bottom wall 123 of the trench contact structure 120. Hereinafter, the first sidewall 121, the second sidewall 122, and the bottom wall 123 of the trench contact structure 120 are also referred to as the first sidewall 121, the second sidewall 122, and the bottom wall 123 of the contact trench 131.

[0229] The first sidewall 121 of the contact trench 131 communicates with the first sidewall 61 and the second sidewall 62 of the first gate trench 81. The first sidewall 121 of the contact trench 131 communicates with the first sidewall 71 and the second sidewall 72 of the second gate trench 101. The contact trench 131 forms one trench between the first gate trench 81 and the second gate trench 101.

[0230] The contact insulating layer 132 is formed in a film shape along the inner wall of the contact trench 131. The contact insulating layer 132 demarcates a concave space within the contact trench 131. The portion of the contact insulating layer 132 covering the bottom wall 123 of the contact trench 131 is formed following the bottom wall 123 of the contact trench 131.

[0231] The contact insulating layer 132 demarcates a U-shaped space that is recessed in a U-shape within the contact trench 131 in the same manner as the first bottom insulating layer 84 (the second bottom insulating layer 104). That is, the contact insulating layer 132 demarcates a U-shaped space in which the region on the bottom wall 123 side of the contact trench 131 is expanded and the tapering is suppressed. Such a U-shaped space is formed, for example, by an etching method (such as a wet etching method) for the inner wall of the contact insulating layer 132.

[0232] The contact insulating layer 132 has a seventh thickness T7. The seventh thickness T7 may be 1500 Å or more and 4000 Å or less. The seventh thickness T7 may be 1500 Å or more and 2000 Å or less, 2000 Å or more and 2500 Å or less, 2500 Å or more and 3000 Å or less, 3000 Å or more and 3500 Å or less, or 3500 Å or more and 4000 Å or less. Preferably, the seventh thickness T7 is 1800 Å or more and 3500 Å or less.

[0233] The seventh thickness T7 may be 4000 Å or more and 12000 Å or less according to the width WTC of the trench contact structure 120. The seventh thickness T7 may be 4000 Å or more and 5000 Å or less, 5000 Å or more and 6000 Å or less, 6000 Å or more and 7000 Å or less, 7000 Å or more and 8000 Å or less, 8000 Å or more and 9000 Å or less, 9000 Å or more and 10000 Å or less, 10000 Å or more and 11000 Å or less, or 11000 Å or more and 12000 Å or less. In this case, the breakdown voltage of the semiconductor device 1 can be increased by thickening the contact insulating layer 132.

[0234] Preferably, the seventh thickness T7 is equal to the first thickness T1 of the first bottom insulating layer 84 (T7 = T1). Preferably, the seventh thickness T7 is equal to the fourth thickness T4 of the second bottom insulating layer 104 (T7 = T4).

[0235] The contact insulating layer 132 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0236] The contact insulating layer 132 may have a laminated structure including a SiN layer and a SiO2 layer laminated in this order from the semiconductor layer 2 side. The contact insulating layer 132 may have a laminated structure including a SiO2 layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The contact insulating layer 132 may have a single-layer structure composed of a SiO2 layer or a SiN layer. In this form, the contact insulating layer 132 has a single-layer structure composed of a SiO2 layer. The contact insulating layer 132 is preferably made of the same insulating material as the first insulating layer 82 (second insulating layer 102).

[0237] The contact insulating layer 132 is integrated with the first insulating layer 82 at the communication portion between the first gate trench 81 and the contact trench 131. The contact insulating layer 132 is integrated with the second insulating layer 102 at the communication portion between the second gate trench 101 and the contact trench 131.

[0238] In this form, the contact insulating layer 132 has an extended insulating layer 132A drawn out from one end of the first gate trench 81 and one end of the second gate trench 101. The extended insulating layer 132A covers the inner wall of one end of the first gate trench 81 across the communication portion. The extended insulating layer 132A covers the inner wall of one end of the second gate trench 101 across the communication portion.

[0239] The extended insulating layer 132A is integrated with the first bottom-side insulating layer 84 and the first opening-side insulating layer 85 in the first gate trench 81. The extended insulating layer 132A and the first bottom-side insulating layer 84 define a U-shaped space at the inner wall of one end of the first gate trench 81.

[0240] The extended insulating layer 132A is integrated with the second bottom-side insulating layer 104 and the second opening-side insulating layer 105 in the second gate trench 101. The extended insulating layer 132A and the second bottom-side insulating layer 104 define a U-shaped space at the inner wall of one end of the second gate trench 101.

[0241] The contact electrode 133 is embedded in the contact trench 131 with the contact insulating layer 132 interposed therebetween. Unlike the first electrode 83 and the second electrode 103, the contact electrode 133 is embedded in the contact trench 131 as an integral body. The contact electrode 133 has an upper end portion exposed from the contact trench 131 and a lower end portion in contact with the contact insulating layer 132.

[0242] The lower end portion of the contact electrode 133 is formed in a convexly curved shape toward the bottom wall 123 of the contact trench 131 in the same manner as the first bottom-side electrode 86 (the second bottom-side electrode 106). More specifically, the lower end portion of the contact electrode 133 is formed following the bottom wall of the U-shaped space partitioned by the contact insulating layer 132, and is formed in a smooth convexly curved shape toward the bottom wall 123.

[0243] According to such a structure, local electric field concentration on the contact electrode 133 can be suppressed, so that a decrease in breakdown voltage can be suppressed. In particular, by embedding the contact electrode 133 in the extended U-shaped space of the contact insulating layer 132, it is possible to appropriately suppress the contact electrode 133 from becoming tapered from the upper end portion to the lower end portion. Thereby, local electric field concentration on the lower end portion of the contact insulating layer 132 can be appropriately suppressed.

[0244] The contact electrode 133 is electrically connected to the first bottom-side electrode 86 at the connection portion between the first gate trench 81 and the contact trench 131. The contact electrode 133 is electrically connected to the second bottom-side electrode 106 at the connection portion between the second gate trench 101 and the contact trench 131. Thereby, the second bottom-side electrode 106 is electrically connected to the first bottom-side electrode 86.

[0245] The contact electrode 133 more specifically has a lead-out electrode 133A drawn out from one end of the first gate trench 81 and one end of the second gate trench 101. The lead-out electrode 133A is located in the first gate trench 81 across the communication portion between the first gate trench 81 and the contact trench 131. The lead-out electrode 133A is further located in the second gate trench 101 across the communication portion between the second gate trench 101 and the contact trench 131.

[0246] The lead-out electrode 133A is embedded in a U-shaped space partitioned by the contact insulating layer 132 in the first gate trench 81. The lead-out electrode 133A is integrated with the first bottom-side electrode 86 in the first gate trench 81. Thereby, the contact electrode 133 is electrically connected to the first bottom-side electrode 86.

[0247] A first intermediate insulating layer 88 is interposed between the contact electrode 133 and the first opening-side electrode 87 in the first gate trench 81. Thereby, the contact electrode 133 is electrically insulated from the first opening-side electrode 87 in the first gate trench 81.

[0248] The lead-out electrode 133A is embedded in a U-shaped space partitioned by the contact insulating layer 132 in the second gate trench 101. The lead-out electrode 133A is integrated with the second bottom-side electrode 106 in the second gate trench 101. Thereby, the contact electrode 133 is electrically connected to the second bottom-side electrode 106.

[0249] A second intermediate insulating layer 108 is interposed between the contact electrode 133 and the second opening-side electrode 107 in the second gate trench 101. Thereby, the contact electrode 133 is electrically insulated from the second opening-side electrode 107 in the second gate trench 101.

[0250] The contact electrode 133 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, and copper alloy. In this form, the contact electrode 133 contains conductive polysilicon. The conductive polysilicon may contain an n-type impurity or a p-type impurity. It is preferable that the conductive polysilicon contains an n-type impurity. The contact electrode 133 preferably contains the same conductive material as the first bottom electrode 86 and the second bottom electrode 106.

[0251] In the contact electrode 133, the exposed portion exposed from the contact trench 131 is located on the bottom wall 123 side of the contact trench 131 with respect to the first main surface 3 in this form. The exposed portion of the contact electrode 133 is formed in a curved shape toward the bottom wall 123 of the contact trench 131.

[0252] The exposed portion of the contact electrode 133 is covered by the third cap insulating layer 139 formed in a film shape. The third cap insulating layer 139 is continuous with the contact insulating layer 132 in the contact trench 131. The third cap insulating layer 139 may contain silicon oxide (SiO2).

[0253] Referring to FIGS. 5 to 11, a main surface insulating layer 141 is formed on the first main surface 3 of the semiconductor layer 2. The main surface insulating layer 141 selectively covers the first main surface 3. The main surface insulating layer 141 is continuous with the first insulating layer 82, the second insulating layer 102, and the contact insulating layer 132. The main surface insulating layer 141 contains at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0254] The main surface insulating layer 141 may have a stacked structure including a SiN layer and a SiO2 layer stacked in this order from the semiconductor layer 2 side. The main surface insulating layer 141 may have a stacked structure including a SiO2 layer and a SiN layer stacked in this order from the semiconductor layer 2 side. The main surface insulating layer 141 may have a single-layer structure made of a SiO2 layer or a SiN layer. In this form, the main surface insulating layer 141 has a single-layer structure made of a SiO2 layer. The main surface insulating layer 141 is preferably made of the same insulating material as the first insulating layer 82, the second insulating layer 102, and the contact insulating layer 132.

[0255] An interlayer insulating layer 142 is formed on the upper portion of the main surface insulating layer 141. The interlayer insulating layer 142 may have a thickness exceeding the thickness of the main surface insulating layer 141. The interlayer insulating layer 142 covers substantially the entire area of the main surface insulating layer 141. The interlayer insulating layer 142 contains, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), zirconium oxide (ZrO2), and tantalum oxide (Ta2O3).

[0256] Here, the interlayer insulating layer 142 includes a USG (Undoped Silica Glass) layer as an example of silicon oxide. The interlayer insulating layer 142 may have a single-layer structure made of a USG layer. The interlayer insulating layer 142 may have a planarized main surface. The main surface of the interlayer insulating layer 142 may be a ground surface ground by a CMP (Chemical Mechanical Polishing) method.

[0257] The interlayer insulating layer 142 may contain PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide. The interlayer insulating layer 142 may have a stacked structure including a PSG layer and a BPSG layer stacked in this order from the semiconductor layer 2 side. The interlayer insulating layer 142 may have a stacked structure including a BPSG layer and a PSG layer stacked in this order from the first main surface 3 side.

[0258] Referring to FIGS. 5 and 6, in the output region 6, the first plug electrode 143, the second plug electrode 144, the third plug electrode 145, and the fourth plug electrode 146 are embedded in the interlayer insulating layer 142. In this form, a plurality of first plug electrodes 143, a plurality of second plug electrodes 144, a plurality of third plug electrodes 145, and a plurality of fourth plug electrodes 146 are embedded in the interlayer insulating layer 142. The first plug electrode 143, the second plug electrode 144, the third plug electrode 145, and the fourth plug electrode 146 may each contain tungsten.

[0259] The plurality of first plug electrodes 143 are respectively embedded in the portion of the interlayer insulating layer 142 that covers the first opening side electrode 87 of the first trench gate structure 60. In this form, the plurality of first plug electrodes 143 penetrate the interlayer insulating layer 142 in the region on one end side of the first trench gate structure 60 and are connected to the plurality of first opening side electrodes 87 in a one-to-one correspondence.

[0260] Of course, a plurality of first plug electrodes 143 may be connected to one first opening side electrode 87. Although not shown, the plurality of first plug electrodes 143 are also embedded in the portion of the interlayer insulating layer 142 that covers the region on the other end side of the first trench gate structure 60 in the same manner as the region on the one end side.

[0261] In this form, the plurality of first plug electrodes 143 are arranged at intervals in a row along the first direction X. Each first plug electrode 143 may be formed in a polygonal shape such as a triangular shape, a square shape, a pentagonal shape, a hexagonal shape, etc., or a circular shape or an elliptical shape in a plan view. Here, each first plug electrode 143 is formed in a square shape in a plan view.

[0262] The plurality of second plug electrodes 144 are respectively embedded in portions of the interlayer insulating layer 142 that cover the second opening-side electrodes 107 of the second trench gate structure 70. In this form, the plurality of second plug electrodes 144 penetrate the interlayer insulating layer 142 in a region on one end side of the second trench gate structure 70 and are connected to the plurality of second opening-side electrodes 107 in a one-to-one correspondence relationship.

[0263] Of course, a plurality of second plug electrodes 144 may be connected to one second opening-side electrode 107. Although not shown, the plurality of second plug electrodes 144 are also embedded in portions of the interlayer insulating layer 142 that cover the region on the other end side of the second trench gate structure 70 in a manner similar to the region on one end side.

[0264] In this form, the plurality of second plug electrodes 144 are arranged at intervals in a row along the first direction X. Each second plug electrode 144 may be formed in a polygonal shape such as a triangular shape, a square shape, a pentagonal shape, or a hexagonal shape, or a circular shape or an elliptical shape in a plan view. Here, each second plug electrode 144 is formed in a square shape in a plan view.

[0265] The plurality of third plug electrodes 145 are respectively embedded in portions of the interlayer insulating layer 142 that cover the contact electrodes 133. The plurality of third plug electrodes 145 penetrate the interlayer insulating layer 142 and are connected to the contact electrodes 133.

[0266] Although not shown, the plurality of third plug electrodes 145 are also embedded in portions of the interlayer insulating layer 142 that cover the contact electrodes 133 of the other trench contact structure 120 in a manner similar to the region on one end side.

[0267] In this form, the plurality of third plug electrodes 145 are arranged at intervals in a row along the first direction X. Each third plug electrode 145 may be formed in a polygonal shape such as a triangular shape, a square shape, a pentagonal shape, a hexagonal shape, etc., or a circular shape or an elliptical shape in a plan view. Here, each third plug electrode 145 is formed in a square shape in a plan view.

[0268] The plurality of fourth plug electrodes 146 are respectively embedded in portions of the interlayer insulating layer 142 that cover the plurality of cell regions 75. Each fourth plug electrode 146 penetrates the interlayer insulating layer 142 and is respectively connected to each cell region 75. More specifically, each fourth plug electrode 146 is electrically connected to the first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 in each cell region 75.

[0269] Each fourth plug electrode 146 is formed in a strip shape extending along each cell region 75 in a plan view. The length of each fourth plug electrode 146 in the second direction Y may be less than the length of each cell region 75 in the second direction Y.

[0270] Of course, a plurality of fourth plug electrodes 146 may be connected to each cell region 75. In this case, the plurality of fourth plug electrodes 146 are formed at intervals along each cell region 75. Further, each fourth plug electrode 146 may be formed in a polygonal shape such as a triangular shape, a square shape, a pentagonal shape, a hexagonal shape, etc., or a circular shape or an elliptical shape in a plan view.

[0271] On the interlayer insulating layer 142 in the output region 6, the aforementioned source electrode 12 and gate control wiring 17 are formed. The source electrode 12 is electrically connected to the plurality of fourth plug electrodes 146 collectively on the interlayer insulating layer 142. A reference voltage (for example, a ground voltage) is applied to the source electrode 12. The reference voltage is transmitted to the first source region 92, the first contact region 93, the second source region 112, and the second contact region 113 via the plurality of fourth plug electrodes 146.

[0272] Of the gate control wirings 17, the first gate control wiring 17A is electrically connected to a plurality of first plug electrodes 143 on the interlayer insulating layer 142. A gate control signal from the control IC 10 is input to the first gate control wiring 17A. The gate control signal is transmitted to the first opening side electrode 87 via the first gate control wiring 17A and the plurality of first plug electrodes 143.

[0273] Of the gate control wirings 17, the second gate control wiring 17B is electrically connected to a plurality of second plug electrodes 144 on the interlayer insulating layer 142. A gate control signal from the control IC 10 is input to the second gate control wiring 17B. The gate control signal is transmitted to the second opening side electrode 107 via the second gate control wiring 17B and the plurality of second plug electrodes 144.

[0274] Of the gate control wirings 17, the third gate control wiring 17C is electrically connected to a plurality of third plug electrodes 145 on the interlayer insulating layer 142. A gate control signal from the control IC 10 is input to the third gate control wiring 17C. The gate control signal is transmitted to the contact electrode 133 via the third gate control wiring 17C and the plurality of third plug electrodes 145. That is, the gate control signal from the control IC 10 is transmitted to the first bottom side electrode 86 and the second bottom side electrode 106 via the contact electrode 133.

[0275] When both the first MISFET 56 (first trench gate structure 60) and the second MISFET 57 (second trench gate structure 70) are controlled to be in the off state, both the first channel region 91 and the second channel region 111 are controlled to be in the off state.

[0276] When both the first MISFET 56 and the second MISFET 57 are controlled to be in the on state, both the first channel region 91 and the second channel region 111 are controlled to be in the on state (Full-ON control).

[0277] When the first MISFET 56 is controlled to be in the on state while the second MISFET 57 is controlled to be in the off state, the first channel region 91 is controlled to be in the on state and the second channel region 111 is controlled to be in the off state (first Half-ON control).

[0278] When the first MISFET 56 is controlled to be in the off state while the second MISFET 57 is controlled to be in the on state, the first channel region 91 is controlled to be in the off state and the second channel region 111 is controlled to be in the on state (second Half-ON control).

[0279] In this way, in the power MISFET 9, a plurality of types of controls including Full-ON control, first Half-ON control, and second Half-ON control are realized by using the first MISFET 56 and the second MISFET 57 formed in one output region 6.

[0280] When driving the first MISFET 56 (that is, during on control of the gate), an on signal Von may be applied to the first bottom electrode 86 and an on signal Von may be applied to the first opening-side electrode 87. In this case, the first bottom electrode 86 and the first opening-side electrode 87 function as gate electrodes.

[0281] Thereby, the voltage drop between the first bottom electrode 86 and the first opening-side electrode 87 can be suppressed, so that the electric field concentration between the first bottom electrode 86 and the first opening-side electrode 87 can be suppressed. Also, the on-resistance of the semiconductor layer 2 can be reduced, so that power consumption can be reduced.

[0282] When driving the first MISFET 56 (that is, during on control of the gate), an off signal Voff (for example, a reference voltage) may be applied to the first bottom electrode 86 and an on signal Von may be applied to the first opening-side electrode 87. In this case, the first bottom electrode 86 functions as a field electrode while the first opening-side electrode 87 functions as a gate electrode. Thereby, the parasitic capacitance can be reduced, so that the switching speed can be improved.

[0283] When driving the second MISFET 57 (i.e., during gate on-control), an on-signal Von may be applied to the second bottom electrode 106 and the on-signal Von may also be applied to the second opening-side electrode 107. In this case, the second bottom electrode 106 and the second opening-side electrode 107 function as gate electrodes.

[0284] Thereby, since the voltage drop between the second bottom electrode 106 and the second opening-side electrode 107 can be suppressed, the electric field concentration between the second bottom electrode 106 and the second opening-side electrode 107 can be suppressed. Also, since the on-resistance of the semiconductor layer 2 can be reduced, power consumption can be reduced.

[0285] When driving the second MISFET 57 (i.e., during gate on-control), an off-signal Voff (reference voltage) may be applied to the second bottom electrode 106 and the on-signal Von may be applied to the second opening-side electrode 107. In this case, while the second bottom electrode 106 functions as a field electrode, the second opening-side electrode 107 functions as a gate electrode. Thereby, since the parasitic capacitance can be reduced, the switching speed can be improved.

[0286] Referring to FIGS. 7 and 8, the first channel region 91 is formed with a first channel area S1 in each cell region 75. The first channel area S1 is defined by the total planar area of a plurality of first source regions 92 formed in each cell region 75.

[0287] The first channel region 91 is formed with a first channel ratio R1 (first ratio) in each cell region 75. The first channel ratio R1 is the ratio that the first channel area S1 occupies in each cell region 75 when the planar area of each cell region 75 is 100%.

[0288] The first channel ratio R1 is adjusted within a range of 0% or more and 50% or less. The first channel ratio R1 may be 0% or more and 5% or less, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, 20% or more and 25% or less, 25% or more and 30% or less, 30% or more and 35% or less, 35% or more and 40% or less, 40% or more and 45% or less, or 45% or more and 50% or less. The first channel ratio R1 is preferably 10% or more and 35% or less.

[0289] When the first channel ratio R1 is 50%, the first source region 92 is formed in substantially the entire area of the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. In this case, the first contact region 93 is not formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. The first channel ratio R1 is preferably less than 50%.

[0290] When the first channel ratio R1 is 0%, the first source region 92 is not formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. In this case, only the body region 55 and / or the first contact region 93 are formed on the first sidewall 61 and the second sidewall 62 of the first trench gate structure 60. The first channel ratio R1 is preferably more than 0%. In this form, an example where the first channel ratio R1 is 25% is shown.

[0291] The second channel region 111 is formed with a second channel area S2 in each cell region 75. The second channel area S2 is defined by the total planar area of a plurality of second source regions 112 formed in each cell region 75.

[0292] The second channel region 111 is formed in each cell region 75 with a second channel ratio R2 (second ratio). The second channel ratio R2 is the ratio that the second channel area S2 occupies in each cell region 75 when the planar area of each cell region 75 is taken as 100%.

[0293] The second channel ratio R2 is adjusted within a range of 0% or more and 50% or less. The second channel ratio R2 may be 0% or more and 5% or less, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, 20% or more and 25% or less, 25% or more and 30% or less, 30% or more and 35% or less, 35% or more and 40% or less, 40% or more and 45% or less, or 45% or more and 50% or less. The second channel ratio R2 is preferably 10% or more and 35% or less.

[0294] When the second channel ratio R2 is 50%, the second source region 112 is formed in substantially the entire area of the first side wall 71 and the second side wall 72 of the second trench gate structure 70. In this case, the second contact region 113 is not formed on the first side wall 71 and the second side wall 72 of the second trench gate structure 70. The second channel ratio R2 is preferably less than 50%.

[0295] When the second channel ratio R2 is 0%, the second source region 112 is not formed on the first side wall 71 and the second side wall 72 of the second trench gate structure 70. In this case, only the body region 55 and / or the second contact region 113 are formed on the first side wall 71 and the second side wall 72 of the second trench gate structure 70. The second channel ratio R2 is preferably greater than 0%. In this form, an example where the second channel ratio R2 is 25% is shown.

[0296] Thus, the first channel region 91 and the second channel region 111 are formed in each cell region 75 with a total channel ratio RT (RT = R1 + R2) of 0% or more and 100% or less (preferably greater than 0% and less than 100%).

[0297] The total channel ratio RT in each cell region 75 is 50% in this form. In this form, all the total channel ratios RT are set to equal values. Therefore, the average channel ratio RAV in the output region 6 (per unit area) is 50%. The average channel ratio RAV is obtained by dividing the sum of all the total channel ratios RT by the total number of the total channel ratios RT.

[0298] Next, FIGS. 12A and 12B show exemplary forms when the average channel ratio RAV is adjusted. FIG. 12A is a cross-sectional perspective view of a region corresponding to FIG. 7, and is a cross-sectional perspective view showing a form including a channel structure according to the second exemplary form. FIG. 12B is a cross-sectional perspective view of a region corresponding to FIG. 7, and is a cross-sectional perspective view showing a form including a channel structure according to the third exemplary form.

[0299] In FIG. 12A, an exemplary form when the average channel ratio RAV is adjusted to about 66% is shown. The total channel ratio RT of each cell region 75 is about 66%. In FIG. 12B, an exemplary form when the average channel ratio RAV is adjusted to 33% is shown. The total channel ratio RT of each cell region 75 is 33%.

[0300] The total channel ratio RT may be adjusted for each cell region 75. That is, a plurality of total channel ratios RT having different values may be applied for each cell region 75. The total channel ratio RT is related to the temperature rise of the semiconductor layer 2. For example, when the total channel ratio RT is increased, the temperature of the semiconductor layer 2 is likely to rise. On the other hand, when the total channel ratio RT is decreased, the temperature of the semiconductor layer 2 is less likely to rise.

[0301] Utilizing this, the total channel ratio RT may be adjusted according to the temperature distribution of the semiconductor layer 2. For example, the total channel ratio RT in a region where the temperature is likely to increase in the semiconductor layer 2 may be made relatively small, and the total channel ratio RT in a region where the temperature is less likely to increase in the semiconductor layer 2 may be made relatively large.

[0302] As a region where the temperature is likely to increase in the semiconductor layer 2, the central portion of the output region 6 can be exemplified. As a region where the temperature is less likely to increase in the semiconductor layer 2, the peripheral portion of the output region 6 can be exemplified. Of course, while adjusting the total channel ratio RT according to the temperature distribution of the semiconductor layer 2, the average channel ratio RAV may also be adjusted.

[0303] Cell regions 75 having a total channel ratio RT of 20% or more and 40% or less (for example, 25%) may be aggregated in a plurality in a region where the temperature is likely to increase (for example, the central part). Cell regions 75 having a total channel ratio RT of 60% or more and 80% or less (for example, 75%) may be aggregated in a plurality in a region where the temperature is less likely to increase (for example, the peripheral part). Cell regions 75 having a total channel ratio RT exceeding 40% and less than 60% (for example, 50%) may be aggregated in a plurality in a region between the region where the temperature is likely to increase and the region where the temperature is less likely to increase.

[0304] Furthermore, a total channel ratio RT of 20% or more and 40% or less, a total channel ratio RT of 40% or more and 60% or less, and a total channel ratio RT of 60% or more and 80% or less may be applied to a plurality of cell regions 75 in a regular arrangement.

[0305] As an example, three types of total channel ratios RT that repeat in the order of 25% (low) → 50% (middle) → 75% (high) may be applied to a plurality of cell regions 75. In this case, the average channel ratio RAV may be adjusted to 50%. In the case of such a structure, with a relatively simple design, it is possible to suppress the formation of a bias in the temperature distribution of the semiconductor layer 2. A specific form to which such a structure is applied is shown in the following embodiments.

[0306] FIG. 13 is a graph obtained by actually measuring the relationship between the active clamp tolerance Eac and the sheet resistivity Ron·A. The graph of FIG. 13 shows the characteristics when the first MISFET 56 and the second MISFET 57 are simultaneously controlled to be in the on state and the off state.

[0307] In FIG. 13, the vertical axis represents the active clamp tolerance Eac [mJ / mm 2 , and the horizontal axis represents the sheet resistivity Ron·A [mΩ·mm 2 . The active clamp tolerance Eac is the tolerance against the back electromotive force as described in FIG. 3. The sheet resistivity Ron·A represents the on-resistance in the semiconductor layer 2 during normal operation.

[0308] FIG. 13 shows a first plot point P1, a second plot point P2, a third plot point P3, and a fourth plot point P4. The first plot point P1, the second plot point P2, the third plot point P3, and the fourth plot point P4 respectively show characteristics when the average channel ratio RAV (that is, the total channel ratio RT in each cell region 75) is adjusted to 66%, 50%, 33%, and 25%.

[0309] When the average channel ratio RAV was increased, the sheet resistivity Ron·A decreased during normal operation, and the active clamp tolerance Eac decreased during active clamp operation. On the contrary, when the average channel ratio RAV was decreased, the sheet resistivity Ron·A increased during normal operation, and the active clamp tolerance Eac improved during active clamp operation.

[0310] In view of the sheet resistivity Ron·A, the average channel ratio RAV is preferably 33% or more (more specifically, 33% or more and less than 100%). In view of the active clamp tolerance Eac, the average channel ratio RAV is preferably less than 33% (more specifically, more than 0% and less than 33%).

[0311] The decrease in the sheet resistivity Ron·A due to the increase in the average channel ratio RAV is because the current path increased. Also, the decrease in the active clamp tolerance Eac due to the increase in the average channel ratio RAV is because a rapid temperature rise caused by the back electromotive force was induced.

[0312] In particular, when the average channel ratio RAV (total channel ratio RT) is relatively large, the possibility of a local and rapid temperature rise occurring in the region between the adjacent first trench gate structure 60 and second trench gate structure 70 increases. The active clamp tolerance Eac is considered to have decreased due to this type of temperature rise.

[0313] On the one hand, the reason why the sheet resistivity Ron·A increases due to the decrease in the average channel ratio RAV is that the current path is narrowed. It is considered that the improvement in the active clamp tolerance Eac due to the decrease in the average channel ratio RAV is because the average channel ratio RAV (total channel ratio RT) becomes relatively small, suppressing local and rapid temperature rise.

[0314] From the results of the graph in FIG. 13, since there is a trade-off relationship in the adjustment method based on the average channel ratio RAV (total channel ratio RT), it can be seen that it is difficult to achieve both excellent sheet resistivity Ron·A and excellent active clamp tolerance Eac while separating from this trade-off relationship.

[0315] On the other hand, from the results of the graph in FIG. 13, in the power MISFET 9, by operating close to the first plot point P1 (RAV = 66%) during normal operation and close to the fourth plot point P4 (RAV = 25%) during active clamp operation, it can be seen that both excellent sheet resistivity Ron·A and excellent active clamp tolerance Eac can be achieved. Therefore, in this form, the following control is implemented.

[0316] FIG. 14A is a cross-sectional perspective view for explaining the normal operation according to the first control example of the semiconductor device 1 shown in FIG. 1. FIG. 14B is a cross-sectional perspective view for explaining the active clamp operation according to the first control example of the semiconductor device 1 shown in FIG. 1. In FIGS. 14A and 14B, for convenience of explanation, the structure above the first main surface 3 is omitted and the gate control wiring 17 is simplified.

[0317] Referring to FIG. 14A, during the normal operation of the power MISFET 9, the first on-signal Von1 is input to the first gate control wiring 17A, the second on-signal Von2 is input to the second gate control wiring 17B, and the third on-signal Von3 is input to the third gate control wiring 17C.

[0318] The first on-signal Von1, the second on-signal Von2, and the third on-signal Von3 are respectively input from the control IC10. The first on-signal Von1, the second on-signal Von2, and the third on-signal Von3 each have a voltage equal to or higher than the gate threshold voltage Vth. The first on-signal Von1, the second on-signal Von2, and the third on-signal Von3 may each have the same voltage.

[0319] In this case, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 are each turned on. That is, the first opening-side electrode 87, the second opening-side electrode 107, the first bottom-side electrode 86, and the second bottom-side electrode 106 each function as a gate electrode.

[0320] As a result, both the first channel region 91 and the second channel region 111 are controlled to be in the on state. In FIG. 14A, the on-state first channel region 91 and second channel region 111 are indicated by dot-like hatching.

[0321] As a result, both the first MISFET 56 and the second MISFET 57 are driven (Full-ON control). The channel utilization rate RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. The channel utilization rate RU is the ratio of the first channel region 91 and the second channel region 111 that are controlled to be in the on state among the first channel region 91 and the second channel region 111.

[0322] Note that the characteristic channel ratio RC is a value obtained by multiplying the average channel ratio RAV by the channel utilization rate RU (RC = RAV × RU). The characteristics (on-resistance area Ron·A and active clamp tolerance Eac) of the power MISFET 9 are determined based on the characteristic channel ratio RC. As a result, the on-resistance area Ron·A approaches the on-resistance area Ron·A indicated by the second plot point P2 in the graph of FIG. 13.

[0323] On the other hand, referring to FIG. 14B, during the active clamp operation of the power MISFET 9, an off signal Voff is input to the first gate control wiring 17A, a first clamp-on signal VCon1 is input to the second gate control wiring 17B, and a second clamp-on signal VCon2 is input to the third gate control wiring 17C.

[0324] The off signal Voff, the first clamp-on signal VCon1, and the second clamp-on signal VCon2 are respectively input from the control IC 10. The off signal Voff has a voltage (for example, a reference voltage) less than the gate threshold voltage Vth. The first clamp-on signal VCon1 and the second clamp-on signal VCon2 each have a voltage equal to or higher than the gate threshold voltage Vth. The first clamp-on signal VCon1 and the second clamp-on signal VCon2 may each have the same voltage. The first clamp-on signal VCon1 and the second clamp-on signal VCon2 may have a voltage equal to or less than the voltage during normal operation.

[0325] In this case, the first opening-side electrode 87 is turned off, and the first bottom-side electrode 86, the second bottom-side electrode 106, and the second opening-side electrode 107 are each turned on. As a result, the first channel region 91 is controlled to be off and the second channel region 111 is controlled to be on. In FIG. 14B, the off first channel region 91 is shown by shaded hatching, and the on second channel region 111 is shown by dotted hatching.

[0326] As a result, the first MISFET 56 is controlled to be off while the second MISFET 57 is controlled to be on (second Half-ON control). Thereby, the channel utilization rate RU during the active clamp operation becomes less than the channel utilization rate RU during normal operation and exceeds zero.

[0327] The channel utilization rate RU during the active clamp operation is 50%. Also, the characteristic channel ratio RC during the active clamp operation is 25%. As a result, the active clamp tolerance Eac approaches the active clamp tolerance Eac indicated by the fourth plot point P4 in the graph of FIG. 13.

[0328] In the first control example, an example in which the second Half-ON control is applied during the active clamp operation was described. However, the first Half-ON control may be applied during the active clamp operation.

[0329] FIG. 15A is a cross-sectional perspective view for explaining the normal operation according to the second control example of the semiconductor device 1 shown in FIG. 1. FIG. 15B is a cross-sectional perspective view for explaining the active clamp operation according to the second control example of the semiconductor device 1 shown in FIG. 1. In FIGS. 15A and 15B, for convenience of explanation, the structure above the first main surface 3 is omitted and the gate control wiring 17 is simplified.

[0330] Referring to FIG. 15A, during the normal operation of the power MISFET 9, a first on signal Von1 is input to the first gate control wiring 17A, a second on signal Von2 is input to the second gate control wiring 17B, and an off signal Voff is input to the third gate control wiring 17C.

[0331] The first on signal Von1, the second on signal Von2, and the off signal Voff are respectively input from the control IC 10. The first on signal Von1 and the second on signal Von2 each have a voltage equal to or higher than the gate threshold voltage Vth. The first on signal Von1 and the second on signal Von2 may each have the same voltage. The off signal Voff has a voltage (for example, a reference voltage) less than the gate threshold voltage Vth.

[0332] In this case, the first opening-side electrode 87 and the second opening-side electrode 107 are each in an on state, and the first bottom-side electrode 86 and the second bottom-side electrode 106 are each in an off state. That is, while the first opening-side electrode 87 and the second opening-side electrode 107 function as gate electrodes, the first bottom-side electrode 86 and the second bottom-side electrode 106 function as field electrodes.

[0333] As a result, both the first channel region 91 and the second channel region 111 are controlled to be in an on state. In FIG. 15A, the on-state first channel region 91 and second channel region 111 are indicated by dot-shaped hatching.

[0334] As a result, both the first MISFET 56 and the second MISFET 57 are driven (Full-ON control). The channel utilization rate RU during normal operation is 100%. The characteristic channel ratio RC during normal operation is 50%. As a result, the sheet resistivity Ron·A approaches the sheet resistivity Ron·A indicated by the second plot point P2 in the graph of FIG. 13.

[0335] On the other hand, referring to FIG. 15B, during the active clamp operation of the power MISFET 9, a first off signal Voff1 is input to the first gate control wiring 17A, a clamp-on signal VCon is input to the second gate control wiring 17B, and a second off signal Voff2 is input to the third gate control wiring 17C.

[0336] The first off signal Voff1, the clamp-on signal VCon, and the second off signal Voff2 are input from the control IC 10, respectively. The first off signal Voff1 has a voltage (e.g., a reference voltage) less than the gate threshold voltage Vth. The clamp-on signal VCon has a voltage equal to or higher than the gate threshold voltage Vth. The clamp-on signal VCon may have a voltage equal to or less than the voltage during normal operation. The second off signal Voff2 has a voltage value (e.g., a reference voltage) less than the gate threshold voltage Vth.

[0337] In this case, the first opening-side electrode 87, the first bottom-side electrode 86, and the second bottom-side electrode 106 are each in an off state, and the second opening-side electrode 107 is in an on state. As a result, the first channel region 91 is controlled to be in an off state and the second channel region 111 is controlled to be in an on state. In FIG. 15B, the off-state first channel region 91 is shown by shaded hatching, and the on-state second channel region 111 is shown by dotted hatching.

[0338] As a result, the first MISFET 56 is controlled to be in an off state while the second MISFET 57 is controlled to be in an on state (second Half-ON control). Thereby, the channel utilization rate RU during the active clamp operation becomes less than the channel utilization rate RU during the normal operation and exceeds zero.

[0339] The channel utilization rate RU during the active clamp operation is 50%. Also, the characteristic channel ratio RC during the active clamp operation is 25%. Thereby, the active clamp tolerance Eac approaches the active clamp tolerance Eac indicated by the fourth plot point P4 in the graph of FIG. 13.

[0340] In the second control example, an example in which the second Half-ON control is applied during the active clamp operation has been described. However, the first Half-ON control may be applied during the active clamp operation.

[0341] As described above, the semiconductor device 1 includes an IPD (Intelligent Power Device) formed in the semiconductor layer 2. The IPD includes a power MISFET 9 and a control IC 10 that controls the power MISFET 9. The power MISFET 9 more specifically includes a first MISFET 56 and a second MISFET 57. The control IC 10 individually controls the first MISFET 56 and the second MISFET 57.

[0342] More specifically, during normal operation, the control IC 10 controls the first MISFET 56 and the second MISFET 57 to be in the on state, and during active clamp operation, controls the first MISFET 56 to be in the off state and the second MISFET 57 to be in the on state.

[0343] Therefore, during normal operation, currents can be passed using the first MISFET 56 and the second MISFET 57. As a result, the on-resistance Ron·A (area resistivity) can be reduced.

[0344] On the other hand, during active clamp operation, since currents can be passed using the second MISFET 57 with the first MISFET 56 stopped, the second MISFET 57 can consume (absorb) the back electromotive force. As a result, a rapid temperature rise due to the back electromotive force can be suppressed, and thus the active clamp tolerance Eac can be improved.

[0345] More specifically, the semiconductor device 1 has a first MISFET 56 including a first FET structure 58 and a second MISFET 57 including a second FET structure 68. The first FET structure 58 includes a first trench gate structure 60 and a first channel region 91. The second FET structure 68 includes a second trench gate structure 70 and a second channel region 111.

[0346] In this case, the control IC 10 controls the first MISFET 56 and the second MISFET 57 so that different characteristic channel ratios RC (channel area) are applied between normal operation and active clamp operation. More specifically, the control IC 10 controls the first MISFET 56 and the second MISFET 57 so that the channel utilization rate RU during active clamp operation exceeds zero and is less than the channel utilization rate RU during normal operation.

[0347] Therefore, during normal operation, the characteristic channel ratio RC increases relatively. As a result, since the current path increases relatively, it is possible to reduce the sheet resistivity Ron·A (on-resistance). On the other hand, during active clamp operation, the characteristic channel ratio RC decreases relatively. As a result, since a rapid temperature rise due to the back electromotive force can be suppressed, it is possible to improve the active clamp tolerance Eac.

[0348] Therefore, it is possible to provide a semiconductor device 1 that can achieve both an excellent sheet resistivity Ron·A and an excellent active clamp tolerance Eac, separated from the trade-off relationship shown in FIG. 13.

[0349] <<Second Embodiment>> The second embodiment of the present disclosure will be described. First, some terms used in the description of the second embodiment will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive part having a reference potential of 0V (zero volts) or the 0V potential itself. The reference conductive part is formed of a conductor such as metal. The 0V potential may also be referred to as the ground potential. In the second embodiment, a voltage shown without particularly setting a reference represents a potential viewed from the ground.

[0350] A level refers to the level of a potential. For any signal or voltage of interest, the high level has a higher potential than the low level. For any signal or voltage of interest, when the signal or voltage is at the high level, it strictly means that the level of the signal or voltage is at the high level, and when the signal or voltage is at the low level, it strictly means that the level of the signal or voltage is at the low level. The level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level. In any signal or voltage of interest, the transition from the low level to the high level is called an up edge (or rising edge), and the transition from the high level to the low level is called a down edge (or falling edge).

[0351] For any transistor configured as a FET (Field Effect Transistor) including a MISFET (Metal Insulator Semiconductor Field Effect Transistor), the on-state refers to the state where the drain and source of the transistor are conducting, and the off-state refers to the state where the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MISFET is understood to be an enhancement-type MISFET.

[0352] For any transistor, the switching from the off-state to the on-state is expressed as turn-on, and the switching from the on-state to the off-state is expressed as turn-off. The same applies to any switch such as an analog switch. Hereinafter, for any transistor or switch, the on-state and off-state may also be simply expressed as on and off.

[0353] Also, for any transistor or switch, the section in which the transistor or switch is in the on-state may be referred to as the on-section, and the section in which the transistor or switch is in the off-state may be referred to as the off-section. For any signal taking a high-level or low-level signal level, the section in which the level of the signal is high is referred to as the high-level section, and the section in which the level of the signal is low is referred to as the low-level section. The same applies to any voltage taking a high-level or low-level voltage level. Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring (line), node, etc., may be understood to refer to an electrical connection.

[0354] FIG. 16 shows a configuration block diagram of a switch device 1000 according to the second embodiment. Here, as an example, it is assumed that the switch device 1000 is configured as a low-side switching device.

[0355] The switch device 1000 includes an input terminal 1001, an output terminal 1002, a ground terminal 1003, and a self-diagnosis terminal 1004, and further includes an output transistor 1010, a gate control circuit 1110, a low-voltage protection circuit 1120, an overcurrent protection circuit 1130, a first temperature protection circuit 1140, a second temperature protection circuit 1150, an active clamp circuit 1160, and a self-diagnosis circuit 1170, and still further includes a transistor 1172, and Zener diodes 1174 and 1176.

[0356] The switch device 1000 is a semiconductor device (electronic component) including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing to the outside of the switch device 1000. The semiconductor device is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Each circuit element constituting the switch device 1000, including the output transistor 1010, circuits 1110 to 1170, the transistor 1172, and the Zener diodes 1174 and 1176, is included in the semiconductor integrated circuit. In FIG. 16, only the terminals 1001 to 1004 are shown as the external terminals provided in the switch device 1000, but other external terminals may also be provided in the switch device 1000.

[0357] An input voltage V IN is supplied from an upper system (not shown) provided outside to the input terminal 1001, and the input voltage V IN is applied to the input terminal 1001. The input voltage V IN is a voltage for designating the state of the output transistor 1010 to be either an on state or an off state. The input voltage V IN may function as a power supply voltage for the circuits 1120 to 1150. In this case, the circuits 1120 to 1150 are driven based on the input voltage V IN . The circuits 1110 and 1170 may also be driven based on the input voltage V IN . However, all or any part of the circuits 1110 to 1170 may be driven based on a power supply voltage (not shown) supplied to the switch device 1000 separately from the input voltage V IN .

[0358] A voltage V is applied to a terminal BB provided outside the switch device 1000. BB The voltage V BB has a positive DC voltage value. For example, when the switch device 1000 is provided in a vehicle such as an automobile, the output voltage of a battery mounted on the vehicle is applied to the terminal BB as the voltage V. BB A load LD is inserted between the terminal BB and the output terminal 1002 outside the switch device 1000. The load LD may include an inductive load. Examples of the inductive load include windings (coils) such as a solenoid, a motor, a transformer, and a relay. The load LD may include at least one of a resistive load and a capacitive load in addition to or instead of the inductive load.

[0359] The voltage applied to the output terminal 1002 is referred to as an output voltage V OUT . Also, the current flowing from the terminal BB to the output terminal 1002 is referred to as an output current I OUT . Unless a so-called short circuit occurs, the output current I OUT flows from the terminal BB through the load LD to the output terminal 1002.

[0360] The ground terminal 1003 is connected to the ground. Therefore, in the second embodiment, that any part is connected to the ground is equivalent to that the part is connected to the ground terminal 1003. The self-diagnosis terminal 1004 is connected to a terminal to which a predetermined positive DC voltage V PU is applied via a pull-up resistor R DD outside the switch terminal 1000. The voltage applied to the self-diagnosis terminal 1004 is referred to as a self-diagnosis voltage V ST .

[0361] The output transistor 1010 is configured as an N-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor). The output transistor 1010 has a drain, a source, and a gate. In the output transistor 1010, the drain is connected to the output terminal 1002, and the source is connected to the ground terminal 1003. Therefore, when the output transistor 1010 is in the on state, the output current I OUT flows from the output terminal 1002 toward the ground terminal 1003 through the channel of the output transistor 1010 (the channel between the drain and the source).

[0362] The gate control circuit 1110 controls the on / off state of the output transistor 1010 (i.e., drives the output transistor 1010) by controlling the gate potential of the output transistor 1010. The gate control circuit 1110 controls the gate potential of the output transistor 1010 according to the input voltage V IN and the output signals of the circuits 1120 to 1150.

[0363] The low voltage protection circuit 1120 generates and outputs a signal S IN corresponding to the input voltage V UVLO . The signal S UVLO is input to the gate control circuit 1110. The low voltage protection circuit 1120 generates the signal S IN so that the output transistor 1010 can be controlled to be in the on state only when the input voltage V UVLO has a voltage value equal to or higher than a certain value. The signal S UVLO is a binary signal taking a high level or a low level signal level. The high level signal S UVLO has one of the values (logical values) of "0" and "1", and the low level signal S UVLO has the other value of the values (logical values) of "0" and "1".

[0364] Fig. 17 shows the relationship between the input voltage V IN and the signal S UVLO . The input voltage V IN including the case where the input voltage V is 0VIN In a state where it is sufficiently low, signal S UVLO has a low level. Starting from the state where signal S UVLO is at a low level, as the input voltage V IN rises, when it switches from the state where “V IN <V UVLO _H” holds to the state where “V IN ≧V UVLO _H” holds, the level of signal S UVLO changes from a low level to a high level. Then, as the input voltage V IN decreases, when it switches from the state where “V IN ≧V UVLO _L” holds to the state where “V IN <V UVLO _L” holds, the level of signal S UVLO changes from a high level to a low level. Here, V UVLO _H and V UVLO _L have positive DC voltage values that satisfy “V UVLO _H>V UVLO _L>0”.

[0365] The overcurrent protection circuit 1130 has a function of detecting the magnitude of the output current I OUT flowing through the output transistor 1010. When the magnitude of the detected output current I OUT reaches a predetermined upper limit current value I LIM , the overcurrent protection circuit 1130 executes an overcurrent protection operation to limit the magnitude of the output current I OUT flowing through the output transistor 1010 to be equal to or lower than the upper limit current value I LIM . “I LIM >0” is satisfied. In the overcurrent protection operation, while keeping the output transistor 1010 in the on state, the gate potential of the output transistor 1010 is controlled so that the magnitude of the output current I OUT does not exceed the upper limit current value I LIM .

[0366] FIG. 18 shows the waveform of the output current I OUT when the overcurrent protection operation is performed. Due to the occurrence of a short circuit or the like in the load LD, the output current I OUTWhen [the value] becomes excessive, overcurrent protection operation is performed to protect the output transistor 1010 and the switch device 1000. The short circuit of the load LD means that the terminal BB is short-circuited to the output terminal 1002 and the voltage V BB is directly applied to the output terminal 1002.

[0367] The first temperature protection circuit 1140 detects the temperature to be measured. Hereinafter, the temperature to be measured is referred to as temperature Tj. The temperature Tj is the temperature of the output transistor 1010. More specifically, the temperature Tj is the temperature of a predetermined location of the semiconductor constituting the output transistor 1010 and corresponds to the junction temperature of the output transistor 1010. However, the temperature Tj may be the temperature of an arbitrary predetermined location within the switch device 1000, which is different from the temperature of the output transistor 1010. The first temperature protection circuit 1140 generates and outputs a signal S TSD corresponding to the detected temperature Tj. The signal S TSD corresponds to the first temperature protection signal and is input to the gate control circuit 1110. The signal S TSD is a binary signal having a high-level or low-level signal level. The high-level signal S TSD has one of the values (logical values) of "0" and "1", and the low-level signal S TSD has the other of the values (logical values) of "0" and "1".

[0368] Fig. 19 shows the relationship between the temperature Tj and the signal S TSD . When the temperature Tj is sufficiently low, the signal S TSD has a low level. Starting from the state where the signal S TSD is at a low level, as the temperature Tj rises and switches from the state where "Tj < T TSD _H" holds to the state where "Tj ≥ T TSD _H" holds, the level of the signal S TSD changes from low level to high level. Then, as the temperature Tj decreases and switches from the state where "Tj ≥ T TSD _L" holds to the state where "Tj < T TSD _L" holds, the level of the signal S TSD changes from high level to low level. Here, TTSD _H and T TSD _L respectively represent a predetermined protection temperature (protection start temperature) and a protection release temperature. The protection temperature T TSD _H is the protection release temperature T TSD _L is higher. For example, the protection temperature T TSD _H and the protection release temperature T TSD _L are 175°C and 155°C respectively.

[0369] When the temperature Tj of the output transistor 1010 reaches the predetermined protection temperature T TSD _H, the first temperature protection circuit 1140 is configured to switch the value of the signal S TSD from the first logical value to the second logical value as the first temperature protection signal. Here, the first logical value (for example, "0") is associated with the low-level signal S TSD , and the second logical value (for example, "1") is associated with the high-level signal S TSD .

[0370] The second temperature protection circuit 1150 has a function of detecting a temperature Tcnt different from the temperature Tj, and generates and outputs a signal S ΔT corresponding to the temperature difference between the temperature Tj and Tcnt. The signal S ΔT corresponds to the second temperature protection signal and is input to the gate control circuit 1110. The temperature Tcnt is the temperature at a predetermined temperature measurement location within the switch device 1000. The temperature measurement location is a location away from the output transistor 1010. For example, the temperature Tcnt may be the temperature of the gate control circuit 1110. The temperature difference between the temperature Tj and Tcnt is hereinafter referred to as the temperature difference ΔT. However, the temperature difference ΔT represents the height of the temperature Tj as seen from the temperature Tcnt, and thus the temperature difference ΔT is expressed as "ΔT = Tj - Tcnt". The signal S ΔT is a binary signal taking a high-level or low-level signal level. The high-level signal S ΔT has one of the values (logical values) of "0" and "1", and the low-level signal S ΔT has the other of the values (logical values) of "0" and "1".

[0371] In FIG. 20, the temperature difference ΔT and the signal SΔT shows the relationship with. In a state where the temperature difference ΔT is sufficiently small, the signal S ΔT has a low level. Starting from the state where the signal S ΔT is at a low level, when the temperature difference ΔT increases and switches from the state where "ΔT < ΔT_H" holds to the state where "ΔT ≧ ΔT_H" holds, the signal S ΔT changes from a low level to a high level. Then, when the temperature difference ΔT decreases and switches from the state where "ΔT ≧ ΔT_L" holds to the state where "ΔT < ΔT_L" holds, the signal S ΔT changes from a high level to a low level. Here, ΔT_H and ΔT_L represent a predetermined protection temperature difference (protection start temperature difference) and a protection release temperature difference, respectively. The protection temperature difference ΔT_H is larger than the protection release temperature difference ΔT_L. For example, the protection temperature difference ΔT_H and the protection release temperature difference ΔT_L are 80°C and 45°C, respectively.

[0372] The second temperature protection circuit 1150 is configured to switch the value of the signal S ΔT as the second temperature protection signal from the first logical value to the second logical value when the temperature difference ΔT reaches the predetermined protection temperature difference ΔT_H. Here, the first logical value (for example, "0") is associated with the signal S ΔT at a low level, and the second logical value (for example, "1") is associated with the signal S ΔT at a high level.

[0373] The active clamp circuit 1160 protects the output transistor 1010 from the back electromotive force generated in the inductive load when the load LD includes an inductive load. The active clamp circuit 1160 is configured to include, for example, a plurality of diodes, and realizes the protection by limiting the voltage between the drain and the source of the output transistor 1010 to be below a predetermined clamp voltage.

[0374] The self-diagnosis circuit 1170 self-diagnoses whether the switch device 1000 is operating normally and outputs the result of the self-diagnosis from the self-diagnosis terminal 1004 using the transistor 1172. In the configuration example of FIG. 16, the transistor 1172 is formed of an N-channel type MISFET, and the drain and source of the transistor 1172 are connected to the self-diagnosis terminal 1004 and the ground, respectively. Then, the self-diagnosis circuit 1170 controls the on / off state of the transistor 1172 according to the signal S TSD to output the result of the self-diagnosis from the self-diagnosis terminal 1004. The voltage V ST at the self-diagnosis terminal 1004 becomes a low level when the transistor 1172 is in the on state and a high level when the transistor 1172 is in the off state.

[0375] The Zener diodes 1174 and 1176 are elements for protecting the internal circuit of the switch device 1000 from high voltages (such as static electricity) that may be applied to the terminals 1004 and 1001. The cathodes of the Zener diodes 1174 and 1176 are connected to the terminals 1004 and 1001, respectively. The anodes of the Zener diodes 1174 and 1176 are connected to the ground terminal 1003.

[0376] FIG. 21 shows the relationships of some voltages and signals in the switch device 1000. In FIG. 21, the waveforms of the input voltage V IN , the signal S UVLO , the state of the output transistor 1010, the waveform of the signal S ΔT , the waveform of the signal S TSD , and the waveform of the voltage V ST are shown from top to bottom in this order. For any natural number i, it is assumed that the time t i+1 is a time later than the time t i .

[0377] At time t1, the voltage value of the input voltage V IN rises from 0V to a predetermined positive voltage value, and as a result, an up edge occurs in the signal S UVLO . After that, at time t6, the voltage value of the input voltage V IN returns to 0V, and the signal S UVLOA down edge occurs. In the example of FIG. 21, the signal S ΔT is basically at a low level, but the signal S ΔT becomes high level only in the interval from time t2 to time t3. In the example of FIG. 21, the signal S TSD is basically at a low level, but the signal S TSD becomes high level only in the interval from time t4 to time t5.

[0378] The gate control circuit 1110 basically controls the output transistor 1010 to be in an on state or an off state based on the input voltage V IN . That is, the gate control circuit 1110 basically controls the output transistor 1010 to be in an on state in the high level interval of the signal S UVLO (that is, the interval in which the input voltage V UVLO is high to the extent that the signal S IN becomes high level), while controlling the output transistor 1010 to be in an off state in the low level interval of the signal S UVLO (that is, the interval in which the input voltage V UVLO is low to the extent that the signal S IN becomes low level). Hereinafter, the high level interval of the signal S UVLO is referred to as the on-designated interval, and the low level interval of the signal S UVLO is referred to as the off-designated interval. In the example of FIG. 21, the interval from time t1 to time t6 is the on-designated interval, and the intervals before time t1 and after time t6 are off-designated intervals.

[0379] The off-designated interval is an interval in which the state of the output transistor 1010 is designated to be in an off state based on the input voltage V IN . The gate control circuit 1110 controls the output transistor 1010 to be in an off state regardless of the signals S ΔT and S TSD in the off-designated interval.

[0380] On the other hand, the on-designated interval is the input voltage V INThis is the section where the state of the output transistor 1010 is specified to be in the on state based on [conditions]. However, the gate control circuit 1110, while generally controlling the output transistor 1010 to be in the on state during the on-designated section, may control the output transistor 1010 to be in the off state according to signal S ΔT or S TSD . Specifically, the gate control circuit 1110, even within the on-designated section (i.e., even when signal S UVLO is at a high level), will control the output transistor 1010 to be in the off state if at least one of signal S ΔT and S TSD is at a high level. The gate control circuit 1110 will control the output transistor 1010 to be in the on state if both of signal S ΔT and S TSD are at a low level and signal S UVLO is at a high level.

[0381] Therefore, in the example of Fig. 21, the output transistor 1010 turns on, turns off, turns on, turns off, turns on, and turns off at times t1, t2, t3, t4, t5, and t6 respectively. That is, the output transistor 1010 is in the on state between times t1 and t2, between times t3 and t4, and between times t5 and t6, and the output transistor 1010 is in the off state between times t2 and t4 and between times t4 and t5. Before time t1 and after time t6, the output transistor 1010 is in the off state.

[0382] During the high-level section of signal S TSD , the gate control circuit 1110 executes the first temperature protection operation based on signal S TSD . In the example of Fig. 21, the change of signal S TSD from a low level to a high level at time t4 (signal S TSDUpon receiving the switching from the first logical value to the second logical value of the value), the gate control circuit 1110 executes the first temperature protection operation. In the first temperature protection operation, the gate control circuit 1110 switches the output transistor 1010 from the on state to the off state, and thereafter maintains the output transistor 1010 in the off state until a predetermined first temperature protection release condition is satisfied. The first temperature protection release condition is established by the establishment of "Tj < T TSD _L" (see FIG. 19), and in the example of FIG. 21, the first temperature protection release condition is established at time t B5 .

[0383] Signal S ΔT In the high-level section of, the second temperature protection operation is executed by the gate control circuit 1110 based on signal S ΔT . In the example of FIG. 21, upon receiving the switching of signal S ΔT from the low level to the high level at time t2 (the switching of the value of signal S ΔT from the first logical value to the second logical value), the gate control circuit 1110 executes the second temperature protection operation. In the second temperature protection operation, the gate control circuit 1110 switches the output transistor 1010 from the on state to the off state, and thereafter maintains the output transistor 1010 in the off state until a predetermined second temperature protection release condition is satisfied. The second temperature protection release condition is established by the establishment of "ΔT < ΔT_L" (see FIG. 20), and in the example of FIG. 21, the second temperature protection release condition is established at time t B3 .

[0384] The self-diagnosis circuit 1170 controls the transistor 1172 so that an up edge occurs in the voltage V UVLO synchronized with the up edge of signal S at time t1. Thereafter, when an up edge occurs in signal S ST , the self-diagnosis circuit 1170 turns on the transistor 1172 to cause a down edge in the voltage V TSD , and thereafter maintains the on state of the transistor 1172 (i.e., maintains the voltage V ST at the low level) until a predetermined latch release condition is satisfied. Therefore, in the example of FIG. 21, at time t4, the voltage V ST ... STA down edge occurs. The switch device 1000 is provided with a function of monitoring the output voltage V OUT . For example, after a down edge occurs in the voltage V ST , when the source (not shown) of the voltage V BB is removed from the terminal BB and the output voltage V OUT becomes equal to or lower than a predetermined voltage, the latch release condition is satisfied. Alternatively, for example, after a down edge occurs in the voltage V ST , when the signal S UVLO is at a low level and the output voltage V OUT becomes equal to or lower than a predetermined voltage, the latch release condition is satisfied. However, the content of the latch release condition can be changed in various ways.

[0385] <<Reference Example>> A reference example for comparison with the subsequent Example EX2_1 etc. will be described. In the switch device 1000 according to the reference example, in the overcurrent protection operation, the upper limit current value I LIM is fixed to a predetermined current value I LIM1 .

[0386] Fig. 22 shows the timing chart in the reference example. In Fig. 22, waveforms 3211 to 3218 according to the reference example are shown. The waveforms 3211 to 3218 are the waveforms of the input voltage V IN , the signal S UVLO , the output current I OUT , the output voltage V OUT , the temperature Tj, the temperature Tcnt, the signal S ΔT , and the signal S TSD according to the reference example, respectively. In addition, in Fig. 22, it is assumed that after the temperature Tcnt represented by the broken-line waveform 3216 reaches the temperature Tj represented by the solid-line waveform 3215, the temperature Tj and the temperature Tcnt coincide, and the explicit indication of the waveform 3216 after the temperature Tcnt reaches the temperature Tj is omitted. For any natural number i, it is assumed that the time t Ai+1 is a time later than the time t Ai .

[0387] At the time t A1 , the input voltage V INThe voltage value rises from 0V to a predetermined positive voltage value, whereby signal S UVLO has an up edge, and after that, at time t A9 the input voltage V IN returns to 0V, causing a down edge in signal S UVLO . Therefore, the period between time t A1 and t A9 corresponds to the on-designated period. Immediately after time t A1 and time t A1 , there is no short circuit, but it is assumed that a short circuit occurs at time t A2 . Then, with time t A2 as the boundary, the output current I OUT rises steeply, but due to the overcurrent protection operation, the magnitude of the output current I OUT is limited to be equal to or less than the current value I LIM1 . Immediately after the start of the overcurrent protection operation, the magnitude of the output current I OUT may transiently exceed the upper limit current value I LIM (here, the current value I LIM1 ), and in FIG. 22, the state of its transient response is schematically shown.

[0388] After time t A2 , as a large output current I OUT flows and the temperature Tj rises rapidly, when the temperature difference ΔT rises and reaches the protection temperature difference ΔT_H (see FIG. 20), an up edge occurs in signal S ΔT and the second temperature protection operation (see FIG. 21) is executed. In the example of FIG. 22, at times t A3 , t A4 , t A5 , t A6 , up edges, down edges, up edges, and down edges occur in signal S ΔT , respectively. Therefore, from time t A2 to time t A7 , the output current I LIM (here, the current value I LIM1 ) near the upper limit current value I OUTThe increase in the temperature Tj due to the current flowing through the output transistor 1010 and the decrease in the temperature Tj due to the output transistor 1010 being maintained in the off state in the second temperature protection operation occur alternately.

[0389] After that, at time t A7 the temperature Tj rises to the protection temperature T TSD _H (see FIG. 19). Then, thereafter, until the short circuit is eliminated, the temperature Tj fluctuates between the protection temperature T TSD _H and the protection release temperature T TSD _L. In the example of FIG. 22, the short circuit is eliminated immediately before time t A7 after time t A8 . From time t A7 to time t A8 , the increase in the temperature Tj due to the output current I LIM (here the current value I LIM1 ) near the upper limit current value I OUT flowing through the output transistor 1010 and the decrease in the temperature Tj due to the output transistor 1010 being maintained in the off state in the first temperature protection operation occur alternately.

[0390] At the time t A8 after the short circuit is eliminated, when the temperature Tj falls below the temperature T TSD _L (protection release temperature) and a falling edge occurs in the signal S TSD , the output transistor 1010 is turned on, but the magnitude of the output current I OUT at this time is sufficiently lower than the upper limit current value I LIM (here the current value I LIM1 ). Thereafter, when the input voltage V A9 is set to 0V at time t IN , the output transistor 1010 is turned off and the output current I OUT becomes zero.

[0391] As described above, in the switch device 1000 according to the reference embodiment, in the overcurrent protection operation, the upper limit current value I LIM is fixed to a predetermined current value I LIM1 . For this reason, at time t A2After an open circuit occurs and before the open circuit is eliminated, the upper limit current value I LIM (Here, the current value I LIM1 ) near the output current I OUT flows through the output transistor 1010, causing an increasing interval of the temperature Tj, and the output transistor 1010 is maintained in the off state by the first or second temperature protection operation, causing a decreasing interval of the temperature Tj, and these intervals occur alternately.

[0392] By the way, the drain and source of the output transistor 1010 are connected to corresponding electrode pads by wire bonding. That is, the drain of the output transistor 1010 is connected to the first electrode pad corresponding to the output terminal 1002 through the first wire, and the source of the output transistor 1010 is connected to the second electrode pad corresponding to the ground terminal 1003 through the second wire. When the increasing interval of the temperature Tj accompanied by the overcurrent protection operation and the decreasing interval of the temperature Tj due to the first or second temperature protection operation occur alternately as shown in FIG. 22, due to the difference in the thermal expansion coefficients between the electrode pad and the wire, a thermal stress is generated at the joint between the electrode pad and the wire. The repeatedly generated thermal stress may cause cracks at the joint between the electrode pad and the wire, resulting in a decrease in the wire bonding strength and, consequently, the possibility of wire breakage.

[0393] <<Example EX2_1>> The example EX2_1 belonging to the second embodiment will be described. In the section where an open circuit occurs, if the steep heat generation can be reduced, the possibility of the occurrence of the above cracks due to thermal stress is reduced, and wire breakage is less likely to occur, thereby enhancing the reliability of the switch device 1000. In the example EX2_1, the configuration of the switch device 1000 that contributes to reducing the steep heat generation will be described. Except for the reference example, the matters described in the second embodiment are applied to the example EX2_1.

[0394] FIG. 23 shows the timing chart in the example EX2_1. In FIG. 23, the waveforms 3311 to 3318 according to the example EX2_1 are shown. The waveforms 3311 to 3318 are, respectively, the input voltage V according to the example EX2_1 IN , the signal SUVLO , output current I OUT , output voltage V OUT , temperature Tj, temperature Tcnt, signal S ΔT , signal S TSD is the waveform of. In FIG. 23, it is assumed that after the temperature Tcnt represented by the broken line waveform 3316 reaches the temperature Tj represented by the solid line waveform 3315, the temperature Tj and the temperature Tcnt coincide, and the waveform 3316 after the temperature Tcnt reaches the temperature Tj is omitted. For any natural number i, the time t Bi+1 is a time after the time t Bi .

[0395] The switch device 1000 according to Embodiment EX2_1 has an upper limit current value I in the overcurrent protection operation LIM to a predetermined current value I LIM1 and I LIM2 is configured to be changeable among a plurality of current values including. The plurality of current values may include three or more current values, but here, only the current values I LIM1 and I LIM2 are noted. Both the current values I LIM1 and I LIM2 have positive predetermined current values, but the current value I LIM2 is smaller than the current value I LIM1 . It is conceivable that the overcurrent protection circuit 1130 changes the upper limit current value I LIM among a plurality of current values, or it is conceivable that the gate control circuit 1110 changes the upper limit current value I LIM among a plurality of current values. Here, it is considered that the gate control circuit 1110 changes the upper limit current value I LIM among the above plurality of current values.

[0396] The gate control circuit 1110 sets the initial value of the upper limit current value I LIM to the current value I LIM1 . Then, when the magnitude of the output current I OUT reaches the current value I LIM1 , the first overcurrent protection operation is performed, and thereafter, when the second and subsequent overcurrent protection operations are performed, the gate control circuit 1110 sets the upper limit current value I LIM to the current value I LIM2Cause each overcurrent protection operation after the second time to be performed in the set state. The operation including the variable setting of such an upper limit current value I LIM will be described with reference to FIG. 23.

[0397] At time t B1 when the voltage value of the input voltage V IN rises from 0V to a predetermined positive voltage value, and as a result, an up edge occurs in the signal S UVLO after that, at time t B9 when the voltage value of the input voltage V IN returns to 0V, a down edge occurs in the signal S UVLO . Therefore, the period between time t B1 and t B9 corresponds to the on-designated section. Immediately after time t B1 and time t B1 , there is no short circuit, but it is assumed that a short circuit occurs at time t B2 . Then, with time t B2 as the boundary, the output current I OUT rises steeply, but due to the overcurrent protection operation, the magnitude of the output current I OUT is limited to be equal to or less than the current value I LIM1 . Note that immediately after the start of the overcurrent protection operation, the magnitude of the output current I OUT may transiently exceed the upper limit current value I LIM (in the first overcurrent protection operation, the current value I LIM1 ), and in FIG. 23, the state of its transient response is schematically shown.

[0398] At time t B2 and later, in the process where a large output current I OUT flows and the temperature Tj rises rapidly, when the temperature difference ΔT rises and reaches the protection temperature difference ΔT_H (see FIG. 20), an up edge occurs in the signal S ΔT and the second temperature protection operation (see FIG. 21) is executed. In the example of FIG. 23, at time t B3 , t B4 , t B5 , t B6 , an up edge, a down edge, an up edge, and a down edge occur in the signal S ΔT , respectively. Therefore, from time t B2 to time tB7 Up to the upper limit current value I LIM The output current I in the vicinity OUT flows through the output transistor 1010, causing the temperature Tj to rise, and the output transistor 1010 is maintained in the off state in the second temperature protection operation, causing the temperature Tj to drop alternately. It should be noted that at time t B3 The upper limit current value I of the overcurrent protection operation executed after LIM is the current value I LIM2 is.

[0399] Time t B7 At, the temperature Tj reaches the protection temperature T TSD _H (see Fig. 19). Then, hereafter, until the short circuit is eliminated, the temperature Tj fluctuates between the protection temperature T TSD _H and the protection release temperature T TSD _L. In the example of Fig. 23, the short circuit is eliminated immediately before time t B7 after. B8 From time t B7 to time t B8 Up to, the upper limit current value I LIM (here the current value I LIM2 ) The output current I in the vicinity of OUT flows through the output transistor 1010, causing the temperature Tj to rise, and the output transistor 1010 is maintained in the off state in the first temperature protection operation, causing the temperature Tj to drop alternately.

[0400] At the time t after the short circuit is eliminated B8 When the temperature Tj drops below the temperature T TSD _L (protection release temperature), causing a down edge in the signal S TSD , the output transistor 1010 is turned on, but the magnitude of the output current I OUT at this time is much lower than the upper limit current value I LIM (here the current value I LIM2 ). Thereafter, at time t B9 when the input voltage V IN is set to 0V, the output transistor 1010 is turned off, and the output current I OUT becomes zero.

[0401] In the example of FIG. 23, at time t B2 and t B3 the first overcurrent protection operation is performed over the entire interval therebetween, and at time t B4 and t B5 the second overcurrent protection operation is performed over the entire interval therebetween, and at time t B6 and t B7 the third overcurrent protection operation is performed over the entire interval therebetween. Thereafter, in the interval between time t B7 and t B8 the high-level intervals and low-level intervals of signal S TSD alternately and repeatedly occur, and each overcurrent protection operation after the fourth is performed in each high-level interval of signal S TSD In the interval between time t TSD and t B4 and the interval between time t B5 and t B6 and t B7 the output transistor 1010 is maintained in the off state by the second temperature protection operation, and in each high-level interval of signal S B7 and t B8 belonging to the interval between time t TSD the output transistor 1010 is maintained in the off state by the first temperature protection operation.

[0402] Then, the first overcurrent protection operation is an overcurrent protection operation (hereinafter referred to as overcurrent protection operation OCP_1) that limits the magnitude of the output current I OUT to be equal to or less than the current value I LIM1 and each overcurrent protection operation after the second is an overcurrent protection operation (hereinafter referred to as overcurrent protection operation OCP_2) that limits the magnitude of the output current I OUT to be equal to or less than the current value I LIM2

[0403] In overcurrent protection operation OCP_1, while allowing the magnitude of the output current I OUT to exceed the current value I LIM2 the magnitude of the output current I OUT is limited to be equal to or less than the current value I LIM1 ​Restrict as follows. The overcurrent protection operation OCP_1 controls the gate potential of the output transistor 1010 while keeping the output transistor 1010 in the on state so that the magnitude of the output current I OUT does not exceed the current value I LIM1 . If the overcurrent protection operation OCP_1 is executed during the continuation of the sky connection, the magnitude of the output current I OUT is maintained in the vicinity of the current value I LIM1 (except for the transient state). The overcurrent protection operation OCP_2 controls the gate potential of the output transistor 1010 while keeping the output transistor 1010 in the on state so that the magnitude of the output current I OUT does not exceed the current value I LIM2 . If the overcurrent protection operation OCP_2 is executed during the continuation of the sky connection, the magnitude of the output current I OUT is maintained in the vicinity of the current value I LIM2 (except for the transient state).

[0404] Similar to the above reference embodiment, also in the embodiment EX2_1, during the continuation of the sky connection, an increasing section of the temperature Tj due to the output current I LIM flowing through the output transistor 1010 in the vicinity of the upper limit current value I OUT , and a decreasing section of the temperature Tj due to the output transistor 1010 being maintained in the off state by the first or second temperature protection operation, occur alternately. However, in the embodiment EX2_1, the upper limit current value I LIM in the overcurrent protection operation is decreased to the current value I LIM2 in each overcurrent protection operation after the second time. Therefore, the inclination of the increase of the temperature Tj in the repetition of the increase and decrease of the temperature Tj becomes smaller than that of the reference embodiment. As a result, the possibility of the occurrence of the above cracks due to thermal stress is reduced and wire breakage is less likely to occur, thereby enhancing the reliability of the switch device 1000 (enhancing the resistance to overcurrent).

[0405] Next, the circuit configuration of Example EX2_1 will be described. The output transistor 1010 according to Example EX2_1 is a gate-split type FET. The gate-split type FET is a MISFET having the structure described in detail in the first embodiment, and the MISFET 9 of the first embodiment belongs to the gate-split type FET. The gate-split type FET has first to nth gates insulated from each other, and receives first to nth gate signals at the first to nth gates, respectively. n is an arbitrary integer of 2 or more. And the gate-split type FET has first to nth channel regions that are independently controlled to be in an on state or an off state based on the first to nth gate signals. In Example EX2_1, it is assumed that the MISFET 9 of the first embodiment is used as the output transistor 1010 (therefore, "n = 2" is assumed here).

[0406] Then, as shown in FIG. 24, the output transistor 1010 can be considered equivalent to a parallel connection circuit of transistors 1011 and 1012. The transistors 1011 and 1012 respectively correspond to the first MISFET 56 and the second MISFET 57 in the first embodiment. The gate signal G1 is propagated on the gate line GL1, and the gate signal G1 is applied to the gate of the transistor 1011. The gate signal G2 is propagated on the gate line GL2, and the gate signal G2 is applied to the gate of the transistor 1012. The gates of the transistors 1011 and 1012 correspond to the first and second gates of the output transistor 1010. The drains of the transistors 1011 and 1012 are commonly connected to form the drain of the output transistor 1010, and the sources of the transistors 1011 and 1012 are commonly connected to form the source of the output transistor 1010.

[0407] The channel region between the drain and source of transistor 1011 corresponds to the first channel region of output transistor 1010, and the channel region between the drain and source of transistor 1012 corresponds to the second channel region of output transistor 1010. When MISFET 9 of the first embodiment is used as output transistor 1010, the first channel region of output transistor 1010 is formed by channel region 91 described in the first embodiment, and the second channel region of output transistor 1010 is formed by channel region 111 described in the first embodiment. In output transistor 1010, the first and second channel regions are electrically separated. Therefore, in output transistor 1010, the first channel region is controlled to be in an on state or an off state independently of the second channel region based on gate signal G1, and the second channel region is controlled to be in an on state or an off state independently of the first channel region based on gate signal G2.

[0408] The state of output transistor 1010 becomes any one of a plurality of states including a full-on state, a first half-on state, a second half-on state, and a full-off state according to gate signals G1 and G2. The on state of output transistor 1010 in the above description corresponds to the full-on state, the first half-on state, or the second half-on state. The off state of output transistor 1010 in the above description corresponds to the full-off state. In the full-on state, both the first and second channel regions are in the on state. In the first half-on state, the first channel region is in the on state and the second channel region is in the off state. In the second half-on state, the first channel region is in the off state and the second channel region is in the on state. In the full-off state, both the first and second channel regions are in the off state.

[0409] The full-on state, the first half-on state, and the second half-on state respectively correspond to the Full-ON control, the first Half-ON control, and the second Half-ON control in the first embodiment. The on state and the off state of the first channel region respectively correspond to the on state and the off state of transistor 1011, and the on state and the off state of the second channel region respectively correspond to the on state and the off state of transistor 1012. For any integer i, the on state of the i-th channel region means that the i-th channel region is in a conductive state, and when the i-th channel region is in the on state, an output current I OUT flows through the i-th channel region. For any integer i, the off state of the i-th channel region means that the i-th channel region is in a cut-off state (non-conductive state), and when the i-th channel region is in the off state, there is no flow of the output current I OUT through the i-th channel region (the flow is cut off).

[0410] When the first or second temperature protection operation is executed, the output transistor 1010 is set to the full-off state. In the overcurrent protection operation, the output transistor 1010 is driven in the full-on state or the first half-on state (details will be described later).

[0411] FIG. 25 shows a partial circuit diagram of the switch device 1000 according to the embodiment EX2_1. The switch device 1000 according to the embodiment EX2_1 includes, in addition to the output transistor 1010 which is a gate-split type FET, an overcurrent protection circuit 1200, an active clamp circuit 1300, and a control signal generation circuit 1400, and further includes transistors 1401 to 1403 which are N-channel type MISFETs, resistors 1404 to 1407, 1410, and 1411, and switches 1408 and 1409 which are analog switches. The overcurrent protection circuit 1200 and the active clamp circuit 1300 are respectively examples of the overcurrent protection circuit 1130 and the active clamp circuit 1160 shown in FIG. 16. Each circuit element referred to by the control signal generation circuit 1400 and the reference numerals 1401 to 1404 is included in the components of the gate control circuit 1110. It may also be understood that each circuit element referred to by the reference numerals 1405 to 1411 is included in the components of the gate control circuit 1110.

[0412] The circuit configuration of FIG. 25 will be described. The drain of the output transistor 1010 is connected to the output terminal 1002, and the source of the output transistor 1010 is connected to the ground. The first gate and the second gate of the output transistor 1010 are connected to the gate line GL1 to which the gate signal G1 is applied and the gate line GL2 to which the gate signal G2 is applied, respectively.

[0413] The overcurrent protection circuit 1200 includes a sense transistor 1201, constant current circuits 1202 and 1203, transistors 1204, 1205, 1209, 1210 and 1211 which are N-channel type MISFETs, resistors 1206, 1207, 1208 and 1212, and a capacitor 1213. The transistors 1210 and 1211 are depletion type MISFETs. A phase compensation circuit is formed by the resistor 1212 and the capacitor 1213.

[0414] The sense transistor 1201 is a gate-divided type FET having the same structure as the output transistor 1010, and thus has first and second gates. The first and second gates of the sense transistor 1201 are connected to the gate lines GL1 and GL2, respectively. The drain of the sense transistor 1201 is connected to the drain of the output transistor 1010, and the source of the sense transistor 1201 is connected to one end of the resistor 1206 at the node 1221. The other end of the resistor 1206 is connected to the ground. The current flowing between the drain and the source of the sense transistor 1201 is defined as the sense current I SNS which is referred to as. The sense current I SNS is proportional to the output current I OUT flowing between the drain and the source of the output transistor 1010. That is, "I SNS :I OUT=1: Make the structure of the sense transistor 1201 similar to that of the output transistor 1010 so that "α” holds (where α has a value considerably larger than 1). When the output transistor 1010 is controlled to be in the full-on state, the first half-on state, the second half-on state, and the full-off state, the sense transistor 1201 will also be controlled to be in the full-on state, the first half-on state, the second half-on state, and the full-off state, respectively.

[0415] The constant current circuit 1202 is provided between the internal power supply terminal to which the internal power supply voltage Vreg is applied and the node 1223, and supplies a predetermined constant current from the internal power supply terminal to the node 1223. The constant current circuit 1203 is provided between the internal power supply terminal to which the internal power supply voltage Vreg is applied and the node 1224, and supplies a predetermined constant current from the internal power supply terminal to the node 1224. The internal power supply voltage Vreg has a positive DC voltage value. The switch device 1000 can generate the internal power supply voltage Vreg based on the voltage supplied from the outside.

[0416] The drain and source of the transistor 1204 are connected to the nodes 1223 and 1221, respectively. With respect to the node 1224, the drain and gate of the transistor 1205 and the gate of the transistor 1204 are commonly connected. The source of the transistor 1205 is connected to the node 1222 via the resistor 1207, and the node 1222 is connected to the ground via the resistor 1208.

[0417] The node 1223 is connected to the gates of the transistors 1209 and 1401 and one end of the resistor 1212. The other end of the resistor 1212 is connected to the node 1225 via the capacitor 1213. The drains of the transistor 1209 and the sources of the transistors 1210 and 1211 are commonly connected to each other at the node 1225. The source of the transistor 1209 is connected to the ground. The drain and gate of the transistor 1210 are short-circuited and connected to the gate line GL1, and the drain and gate of the transistor 1211 are short-circuited and connected to the gate line GL2.

[0418] The active clamp circuit 1300 includes transistors 1301 to 1303 which are N-channel type MISFETs, diodes 1304 and 1305, and a resistor 1306. Transistor 1303 is a depletion type MISFET.

[0419] The drain of transistor 1301 and the cathode of diode 1304 are connected to the drain of output transistor 1010. The anodes of diodes 1304 and 1305 are connected to each other, and the cathode of diode 1305 is connected to the gate of transistor 1301 and one end of resistor 1306. The other end of resistor 1306 is connected to the gate of transistor 1302 and the drain of transistor 1303. In transistor 1302, the drain is connected to gate line GL2, and the source is connected to ground. The gate and source of transistor 1303 are connected to ground. The source of transistor 1301 is connected to gate line GL1.

[0420] The drain of transistor 1401 is connected to an internal power supply terminal to which an internal power supply voltage Vreg is applied via resistor 1404. The source of transistor 1401 is connected to ground. For the control signal generation circuit 1400, a signal S having the drain voltage of transistor 1401 OCP and signal S ΔT and S TSD are input. The control signal generation circuit 1400 generates and outputs a control signal CNT1 based on these input signals. The control signal CNT1 is input to the gates of transistors 1402 and 1403. In transistor 1402, the drain is connected to node 1222, and the source is connected to ground. In transistor 1403, the drain is connected to gate line GL2, and the source is connected to ground.

[0421] The input terminal 1001 is connected to one end of a resistor 1407, and the other end of the resistor 1407 is connected to one end of each of switches 1408 and 1409. The other end of the switch 1408 is connected to a line GL1' via a resistor 1405. The other end of the switch 1409 is connected to a line GL2' via a resistor 1406. The line GL1' is connected to the gate line GL1 via a resistor 1410. The line GL2' is connected to the gate line GL2 via a resistor 1411.

[0422] The function and operation of the circuit shown in Fig. 25 will be described. The control terminals of the switches 1408 and 1409 are connected to a signal S UVLO is input. Signal S UVLO During the high level period of the signal S UVLO During the low level period of the input voltage V IN In the ON designated section based on (see Figure 21), the input voltage V IN is applied to lines GL1' and GL2', and if there is no charge being drawn from gate lines GL1 and GL2 by transistors 1210, 1211, 1302, or 1403, etc., then the input voltage V IN 25, the gate control circuit 1110 (FIG. 16) includes a circuit that quickly pulls down the gate signals G1 and G2 to a sufficiently low potential (for example, ground potential) when the output transistor 1010 should be turned off, or that keeps the gate signals G1 and G2 at a sufficiently low potential (for example, ground potential), thereby maintaining the output transistor 1010 in an off state (fully off state) during the off designation interval and the interval during which the first or second temperature protection operation is performed.

[0423] The active clamp circuit 1300 protects the output transistor 1010 from the back electromotive force generated in the inductive load when the load LD (see FIG. 16) includes an inductive load. The active clamp circuit 1300 limits the voltage between the drain and source of the output transistor 1010 to a predetermined clamp voltage or less by an operation similar to the active clamp operation described in the first embodiment, thereby protecting the output transistor 1010 from the back electromotive force.

[0424] The control signal generation circuit 1400 outputs a control signal CNT1 of a low level or a high level. In the low level section of the control signal CNT1, the transistors 1402 and 1403 are in an off state, and in the high level section of the control signal CNT1, the transistors 1402 and 1403 are in an on state. The control signal generation circuit 1400 sets the control signal CNT1 to a low level at the time when the input voltage V IN switches from a low level to a high level (i.e., the time when the up edge of the signal S UVLO occurs), but then switches the control signal CNT1 to a high level under a predetermined condition.

[0425] Assuming that the transistor 1403 is maintained in an off state, the overcurrent protection operation of the overcurrent protection circuit 1200 will be described. In a section where the output current I OUT and the sense current I SNS are sufficiently low, the voltage of the node 1223 is sufficiently low, and the transistors 1209 and 1401 are kept in an off state. As the output current I OUT increases from zero, the sense current I SNS also increases from zero. Then, when the magnitude of the output current I OUT increases to the upper limit current value I LIM , the transistors 1209 and 1401 switch from an off state to an on state through the potential rise of the node 1221 and the potential rise of the node 1223. In the on section of the transistor 1209, charges are drawn from the gate lines GL1 and GL2 through the transistors 1210 and 1211, so the potentials of the gate signals G1 and G2 decrease compared to the off section of the transistor 1209. As a result, the output current I OUTdecreases. Output current I OUT As the sense current I SNS decreases in conjunction with the decrease in the output current I OUT , the potential of node 1223 decreases, so the drain currents of transistors 1210 and 1211 also decrease, and the potentials of gate signals G1 and G2 increase. The increase in the potentials of gate signals G1 and G2 results in an increase in the output current I SNS , and the potential of node 1223 is increased through the increase in the sense current I OUT . During the continuation of the crowbar, the magnitude of the output current I LIM is maintained below the upper limit current value I LIM and kept in the vicinity of the upper limit current value I

[0426] The lower limit value of the sense current I SNS required to turn on transistors 1209 and 1401 is referred to as the sense boundary current value. In the on interval of transistor 1402, since both ends of resistor 1208 are short-circuited by transistor 1402, the sense boundary current value is lower than that in the off interval of transistor 1402. That is, the product obtained by multiplying the sense boundary current value in the off interval of transistor 1402 by a predetermined proportionality coefficient α corresponds to the current value I LIM1 , and the product obtained by multiplying the sense boundary current value in the on interval of transistor 1402 by a predetermined proportionality coefficient α corresponds to the current value I LIM2 . Therefore, by turning transistor 1402 on / off, the upper limit current value I LIM can be switched between the current values I LIM1 and I LIM2 .

[0427] In relation to the timing chart of FIG. 23, the operations of the overcurrent protection circuit 1200, the control signal generation circuit 1400, etc. will be described. The initial level of the control signal CNT1 in the on-designated interval is a low level. Therefore, the control signal generation circuit 1400 sets the control signal CNT1 to a low level at the time t IN when the input voltage V B1 switches from a low level to a high level (i.e., the time t UVLO at which an up edge occurs in signal S B1 ).

[0428] time t B2 The first overcurrent protection operation is performed when a short circuit to the power supply occurs at I LIM =I LIM1 If the transistor 1401 is in an off state, the signal S OCP has a high level, and when the transistor 1401 is in an on state, the signal S OCP Therefore, the signal S is at a low level during the period in which the first overcurrent protection operation is performed. OCP is input to the control signal generating circuit 1400. OCP The information indicating that the signal has become low level is latched in the control signal generating circuit 1400 as overcurrent detection information indicating that the overcurrent protection operation has been performed. B2 and t B3 During the interval during which the overcurrent protection operation OCP_1 is continuously executed, the control signal CNT1 is maintained at a low level.

[0429] After that, while the overcurrent detection information is latched, the signal S ΔT or S TSD When a rising edge occurs in the signal S, the control signal generating circuit 1400 switches the level of the control signal CNT1 from low to high, and thereafter maintains the level of the control signal CNT1 at high until a predetermined reset condition is met. ΔT and S TSD Among them, signal S ΔT Since the rising edge occurs first at signal S ΔT The level of the control signal CNT1 is switched to high level at the rising edge of the signal S TSD If a rising edge occurs first in signal S TSD The rising edge of this signal causes the level of the control signal CNT1 to be switched to high level.

[0430] The reset condition is signal S UVLO is established by the occurrence of the down edge of (hence, time tB9 (established at). However, the reset condition is not limited to this. Also, the switching timing of the level of the control signal CNT1 can be modified. In any case, in one on-designated section, in the section where the first overcurrent protection operation is executed, the control signal CNT1 is set to the low level, and in the section where each subsequent overcurrent protection operation is executed, the control signal CNT1 may be set to the high level. Thus, in one on-designated section, the first overcurrent protection operation becomes the overcurrent protection operation OCP_1, and each subsequent overcurrent protection operation becomes the overcurrent protection operation OCP_2.

[0431] Also, when the control signal CNT1 is set to the high level and the transistor 1403 is turned on, the gate signal G2 becomes sufficiently low and the second channel region of the output transistor 1010 is turned off. That is, in the section during the on-designated section and in the section where the output transistor 1010 is not controlled to be in the off state by the first or second temperature protection operation, if the control signal CNT1 is at the low level, the output current I flows through the first and second channel regions of the output transistor 1010 (in other words, the output transistor 1010 is driven in the full-on state), and if the control signal CNT1 is at the high level, the output current I flows only through the first channel region of the output transistor 1010 (in other words, the output transistor 1010 is driven in the first half-on state). OUT flows (in other words, the output transistor 1010 is driven in the full-on state), and if the control signal CNT1 is at the high level, the output current I OUT flows (in other words, the output transistor 1010 is driven in the first half-on state).

[0432] Therefore, in the overcurrent protection operation OCP_1, the output current I flows through the first and second channel regions of the output transistor 1010 OUT and in the overcurrent protection operation OCP_2, the output current I OUT flows only through the first channel region of the output transistor 1010.

[0433] Thus, in the second overcurrent protection operation, the output current I OUT ​By thinning out the channel regions through which current flows, the heat-generating sites will be thinned out. As a result, compared with the case where no thinning is performed (i.e., compared with the method of always setting all channel regions to the on state in a plurality of overcurrent protection operations that are repeatedly executed), the amount of heat generation is suppressed and the influence of thermal stress is reduced. As a result, the possibility of occurrence of the above-mentioned cracks due to thermal stress is reduced, wire breakage is less likely to occur, and thus the reliability of the switch device 1000 (the resistance to overcurrent is increased) is enhanced.

[0434] <<Example EX2_2>> An example EX2_2 belonging to the second embodiment will be described. In example EX2_2, supplementary matters, modified techniques, applied techniques, etc. for the matters described above in the second embodiment will be described.

[0435] In Example EX2_1, the configuration in which the output transistor 1010 is a gate-divided type FET was described. However, the output transistor 1010 does not have to be a gate-divided type FET. That is, the output transistor 1010 may be a MISFET having a single gate and being turned on or off according to a gate signal applied to the single gate.

[0436] The second temperature protection circuit 1150 may be deleted from the switch device 1000. In this case, the temperature protection operation that can be performed by the switch device 1000 is only the first temperature protection operation by the first temperature protection circuit 1140.

[0437] Assuming that the switch device 1000 is configured as a low-side switching device, the configuration and operation of the switch device 1000 have been described above. However, the switch device 1000 may be configured as a high-side switching device. In this case, by directly connecting the terminal BB (see FIG. 16) to the terminal 1002, the voltage V BB is applied to the drain of the output transistor 1010, and the source of the output transistor 1010 is connected to the ground via the load LD.

[0438] Regarding any signal or voltage, the relationship between their high level and low level can be reversed in a form that does not impair the above-mentioned gist.

[0439] The type of the channel of the FET (field effect transistor) shown in each embodiment is an exemplification, and the configuration of the circuit including the FET can be modified such that the N-channel type FET is changed to a P-channel type FET, or the P-channel type FET is changed to an N-channel type FET.

[0440] The switch device 1000 may be installed in a vehicle such as an automobile, and the switch device 1000 may be applied to any load LD in the vehicle. However, the use of the switch device 1000 is not limited to in-vehicle use and is arbitrary.

[0441] The embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each constituent element are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely exemplifications, and as a matter of course, they can be changed to various numerical values.

[0442] <<Supplementary Note>> A supplementary note is provided for the present disclosure in which specific configuration examples are shown in the above embodiments.

[0443] A switch device (1000; see the second embodiment) according to one aspect of the present disclosure includes an output transistor (1010), and an overcurrent protection circuit (1130, 1200) configured to be able to execute an overcurrent protection operation for limiting the magnitude of the target current (I OUT ) flowing through the output transistor to be equal to or less than a predetermined upper limit current value (I LIM ), and is capable of controlling the state of the output transistor, and the upper limit current value is a predetermined first current value (I LIM1 ) and a predetermined second current value (I LIM2 which is lower than the first current valueA control circuit (1110) configured to be changeable among a plurality of current values including (), and the control circuit (see FIG. 23) is configured such that after an overcurrent protection operation for limiting the magnitude of the target current to be equal to or less than the first current value is performed in response to the magnitude of the target current reaching the first current value, the upper limit current value can be changed to the second current value (a first configuration).

[0444] The overcurrent protection operation may be repeatedly executed due to, for example, a short circuit to the sky or the ground. When the overcurrent protection operation is repeatedly executed, temperature fluctuations occur in the output transistor. If the rate of increase in the temperature of the output transistor is too large during such repeated overcurrent protection operations, a large thermal stress may act on the joint between the electrode pad and the wire, causing a crack in the connection part. According to the first configuration, the possibility of the occurrence of the crack due to the thermal stress is reduced, and wire breakage is less likely to occur, thereby enhancing the reliability of the switch device (enhancing the resistance to overcurrent).

[0445] In the switch device according to the first configuration, an input terminal (1001), and a temperature protection circuit (1140, 1150) capable of outputting a temperature protection signal (S TSD , S ΔT ) having a predetermined first or second logic value according to the temperature of the output transistor, and the control circuit is configured such that the input voltage (V IN) is configured to be able to control the output transistor to be in an on state or an off state according thereto. The control circuit, when the value of the temperature protection signal switches from the first logic value to the second logic value in an on-designated section where the state of the output transistor is designated to be in the on state based on the input voltage, switches the output transistor from the on state to the off state and is configured to be able to execute a temperature protection operation of keeping the output transistor in the off state until a predetermined temperature protection release condition is satisfied. In the on-designated section, the control circuit is configured such that when an overcurrent protection operation (OCP_1) of limiting the magnitude of the target current to be equal to or less than the first current value is performed in response to the magnitude of the target current reaching the first current value, and then when another overcurrent protection operation (OCP_2) is performed after going through the temperature protection operation, the upper limit current value in the other overcurrent protection operation can be set to the second upper limit value (a second configuration).

[0446] When the overcurrent protection operation is repeatedly executed with the temperature protection operation of keeping the output transistor in the off state in between, temperature fluctuations occur in the output transistor. If the rate of temperature rise of the output transistor is too large during such repeated overcurrent protection operations, there is a risk that a large thermal stress acts on the joint between the electrode pad and the wire, causing a crack in the connection part. According to the second configuration described above, the possibility of the occurrence of the crack due to the thermal stress is reduced, making it less likely for wire disconnection to occur, thereby enhancing the reliability of the switch device (enhancing the resistance to overcurrent).

[0447] In the switch device according to the second configuration, the temperature protection circuit (1140) may be configured such that when the temperature (Tj) of the output transistor reaches a predetermined protection temperature, the value of the temperature protection signal is switched from the first logic value to the second logic value (a third configuration).

[0448] In the switch device according to the second configuration, the temperature protection circuit (1150) may be configured (a fourth configuration) to switch the value of the temperature protection signal from the first logical value to the second logical value when a temperature difference (ΔT) between the temperature (Tj) of the output transistor and another temperature (Tcnt) within the switch device reaches a predetermined protection temperature difference.

[0449] In the switch device according to any one of the first to fourth configurations (see FIGS. 24 and 25), the output transistor is a field effect transistor having a plurality of channel regions that are independently controlled to be in an on state or an off state based on a plurality of gate signals (G1, G2), and the control circuit is configured to allow the target current to flow through the plurality of channel regions in an overcurrent protection operation for limiting the magnitude of the target current to the first current value or less, and to allow the target current to flow through only a part of the plurality of channel regions in an overcurrent protection operation for limiting the magnitude of the target current to the second current value or less, so as to be able to generate the plurality of gate signals (a fifth configuration).

[0450] Thereby, when an overcurrent protection operation for limiting the magnitude of the target current to the second current value or less is executed, the channel regions through which the target current flows are thinned out, and the heat generating sites are thinned out. Then, the amount of heat generation is suppressed, and the influence of thermal stress is reduced. As a result, the possibility of occurrence of the crack due to thermal stress is reduced, wire breakage is less likely to occur, and thus the reliability of the switch device (the resistance to overcurrent is increased) is enhanced.

Explanation of Reference Numerals

[0451] 1 Semiconductor device 9 Power MISFET 10 Control IC 11 Drain electrode 12 Source electrode 21 Sensor MISFET 25 Gate control circuit 26 Active clamp circuit 34 Overcurrent protection circuit 36 Overheat protection circuit 56 First MISFET 57 Second MISFET 91 First channel region 111 Second channel region 1000 Switch device 1001 Input terminal 1002 Output terminal 1003 Ground terminal 1004 Self-diagnosis terminal 1010 Output transistor 1110 Gate control circuit 1120 Low voltage protection circuit 1130 Overcurrent protection circuit 1140 First temperature protection circuit 1150 Second temperature protection circuit 1160 Active clamp circuit 1170 Self-diagnosis circuit 1200 Overcurrent protection circuit 1300 Active clamp circuit 1400 Control signal generation circuit

Claims

1. An output transistor, an overcurrent protection circuit configured to be capable of performing an overcurrent protection operation for limiting the magnitude of a target current flowing through the output transistor to a predetermined upper limit current value or less, an input terminal, a control circuit capable of controlling the output transistor to be in an on state or an off state according to an input voltage at the input terminal, and configured to be capable of changing the upper limit current value among a plurality of current values including a predetermined first current value and a predetermined second current value lower than the first current value, a temperature protection circuit capable of outputting a temperature protection signal having a predetermined first or second logic value according to the temperature of the output transistor, and comprising: when the value of the temperature protection signal switches from the first logic value to the second logic value in an on-designated section where the state of the output transistor is designated to be in the on state based on the input voltage, the control circuit is configured to be capable of performing a temperature protection operation of switching the output transistor from the on state to the off state and maintaining the output transistor in the off state until a predetermined temperature protection release condition is satisfied, in the on-designated section, after an overcurrent protection operation for limiting the magnitude of the target current to the first current value or less in response to the magnitude of the target current reaching the first current value is performed, and after the temperature protection operation, when another overcurrent protection operation is performed, the control circuit is configured to be capable of setting the upper limit current value in the another overcurrent protection operation to the second current value , a switch device.

2. The temperature protection circuit is configured to switch the value of the temperature protection signal from the first logic value to the second logic value when the temperature of the output transistor reaches a predetermined protection temperature. The switch device according to Claim 1.

3. The temperature protection circuit is configured to switch the value of the temperature protection signal from the first logic value to the second logic value when a temperature difference between the temperature of the output transistor and another temperature within the switch device reaches a predetermined protection temperature difference. The switch device according to Claim 1.

4. The output transistor is a field effect transistor having a plurality of channel regions controlled to be in an on state or an off state independently of each other based on a plurality of gate signals, The control circuit is configured to be able to generate the plurality of gate signals such that the target current flows through the plurality of channel regions in an overcurrent protection operation that limits the magnitude of the target current to be equal to or less than the first current value, and such that the target current flows through only a part of the plurality of channel regions in an overcurrent protection operation that limits the magnitude of the target current to be equal to or less than the second current value. , The switch device according to any one of claims 1 to 3.

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